Semiconductor device

Abstract

To control the on / off state transition of a semiconductor element with a simple configuration.SOLUTION: A semiconductor device includes a second semiconductor element connected in parallel to a first semiconductor element, a source semiconductor element, a sink semiconductor element, a source-sink connection semiconductor element connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element, and a control circuit for controlling the on / off state transitions of the source semiconductor element, the sink semiconductor element, and the source-sink connection semiconductor element such that the first semiconductor element and then the second semiconductor element transition to the on state, and the second semiconductor element and then the first semiconductor element transition to the off state.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in the present specification relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, insulated gate bipolar transistors (IGBTs) or metal oxide semiconductor field effect transistors (MOSFETs) made of inexpensive silicon (Si) have been commonly used as power elements for inverter devices and the like for driving motors.

[0003] Meanwhile, in recent years, the use of high-efficiency power elements made of wide-bandgap semiconductors such as SiC (silicon carbide) or GaN (gallium nitride) has been increasing. Wide-bandgap semiconductors generally refer to semiconductors with a forbidden band width of approximately 2 eV or more, and known examples include Group 3 nitrides such as gallium nitride (GaN), Group 2 oxides such as zinc oxide (ZnO), Group 2 chalcogenides such as zinc selenide (ZnSe), diamond, and silicon carbide.

[0004] However, wide bandgap semiconductors are expensive, and therefore have not been widely adopted in consumer electronics, where cost is a priority. Therefore, for applications requiring long periods of low-current operation, such as drive motors for compressors in home air conditioners, it has been proposed to use a parallel circuit consisting of a small-sized SiC-MOSFET and a Si-IGBT connected in parallel in a product (see, for example, Patent Document 1). Such products are expected to reduce costs due to the small size of the SiC-MOSFET, and improve efficiency (i.e., reduce losses) due to the SiC-MOSFET's excellent DC characteristics at low currents. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6919292 Summary of the Invention [Problem to be solved by the invention]

[0006] To achieve both improved efficiency and reduced costs, it is necessary to reduce the element size of the SiC-MOSFET. However, as the element size of the SiC-MOSFET decreases, the amount of current that can flow (allowable current) decreases. Therefore, to prevent a large current from flowing only through the SiC-MOSFET and causing destruction, it is necessary to control the gate drive circuit in an appropriate order so that only the SiC-MOSFET is not turned on.

[0007] On the other hand, the above control requires a gate drive circuit for each element and a logic circuit to control the on / off state transitions of each element at individual timing, which raises concerns that the circuit size will increase and that the complicated timing control of the on / off state transitions will lead to system malfunction.

[0008] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for controlling the on / off state transition of a semiconductor element with a simple configuration and preventing the semiconductor element from being destroyed. [Means for solving the problem]

[0009] A semiconductor device that is a first aspect of the technology disclosed in the present specification comprises a first semiconductor element, a second semiconductor element connected in parallel with the first semiconductor element, a first source semiconductor element connected between a first power supply potential and a gate terminal of the first semiconductor element, a first sink semiconductor element connected between a reference potential and a gate terminal of the second semiconductor element, a source-sink connection semiconductor element connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element, and a control circuit for controlling the on / off state transitions of the first source semiconductor element, the first sink semiconductor element, and the source-sink connection semiconductor element so that the first semiconductor element and the second semiconductor element transition to the on state in that order, and the second semiconductor element and the first semiconductor element transition to the off state in that order. [Effects of the Invention]

[0010] According to at least the first aspect of the technology disclosed in the present specification, a simple circuit configuration including semiconductor elements for source-sink connection can control the transition of the on / off state of each semiconductor element, thereby preventing the semiconductor elements from being destroyed.

[0011] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0012] [Figure 1] 1A and 1B are diagrams illustrating an example of the operation of a Si element and an example of the operation of a SiC element. [Figure 2] FIG. 1 is a diagram illustrating an example of a drive circuit for driving a Si element and a SiC element. [Figure 3] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating an example of the operation of a Si device and an example of the operation of a SiC device according to an embodiment. [Figure 5]FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 6] FIG. 10 is a diagram showing an example of an increase in the gate voltage of a SiC-MOSFET and a decrease in the gate-source voltage VGS of a source-sink connection MOSFET. [Figure 7] 10A and 10B are diagrams conceptually showing modified examples of the circuit configuration of the semiconductor device according to the embodiment; [Figure 8] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 9] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating an example of the operation of a Si device and an example of the operation of a SiC device according to an embodiment. [Figure 11] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating an example of the operation of a Si device and an example of the operation of a SiC device according to an embodiment. [Figure 13] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 14] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 15] FIG. 1 is a diagram illustrating an example of DC characteristics of a MOSFET. [Figure 16] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 17] FIG. 1 is a diagram illustrating an example of the operation of a Si-IGBT and a SiC-MOSFET. [Figure 18] FIG. 1 is a diagram showing an example of a drive circuit having general parallel-connected circuits. [Figure 19] FIG. 1 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to an embodiment. [Figure 20] 1A to 1C are diagrams illustrating an example of the operation of a Si device and an example of the operation of a SiC device according to an embodiment. [Figure 21]FIG. 10 is a diagram showing an example of a configuration in which the gate of a SiC-MOSFET and a sink MOSFET are connected via a sink diode. [Figure 22] 1A to 1C are diagrams illustrating an example of the operation of a Si device and an example of the operation of a SiC device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0014] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0015] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0016] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0017] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0018] First Embodiment A semiconductor device according to this embodiment will be described below. For convenience of explanation, the configuration of a semiconductor device known to the inventor will be described first.

[0019] To improve efficiency and reduce costs at the same time, it is necessary to reduce the size of the SiC-MOSFET element. In this case, since the current that can flow decreases as the SiC-MOSFET element size decreases, it is necessary to control the gate drive circuit in an appropriate sequence so that only the SiC-MOSFET is not turned on, so that a large current does not flow only through the SiC-MOSFET and lead to destruction.

[0020] FIG. 1 is a diagram showing an example of the operation of a Si element and an example of the operation of a SiC element.

[0021] As shown in the example in Figure 1, the rise of the gate output of the SiC device relative to the input signal is delayed by time D1 relative to the gate output of the Si device, taking into account the timing (rise time) at which the Si device transitions to the on state. Also, the fall of the gate output of the Si device is delayed by time D2 relative to the gate output of the SiC device, taking into account the timing (fall time) at which the SiC device transitions to the off state.

[0022] Accordingly, the current in the Si element corresponds to the full current immediately after startup, then decreases as it is diverted to the SiC element, which starts up later, according to the element characteristics, and then again corresponds to the full current after the SiC element shuts down.

[0023] Such control requires a gate drive circuit for each element and a logic circuit for controlling the on / off of each element at individual timings.

[0024] Fig. 2 is a diagram showing an example of a drive circuit for driving Si elements and SiC elements. As shown in the example of Fig. 2, drive circuit 100 includes a control signal generation circuit 12 that receives an input signal, a gate drive circuit 14 that receives a control signal 12A from control signal generation circuit 12, and a gate drive circuit 16 that receives a control signal 12B from control signal generation circuit 12. Drive circuit 100 is connected to a Si-IGBT 20 that receives a gate signal at its gate terminal 20A from gate drive circuit 14, and a SiC-MOSFET 22 that receives a gate signal at its gate terminal 22A from gate drive circuit 16.

[0025] With a circuit structure such as that shown in Figure 2, the circuit scale increases and the timing control of the on / off state transitions becomes more complicated, which raises concerns about system malfunction.

[0026] <Configuration of semiconductor device> Fig. 3 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to this embodiment. As illustrated in Fig. 3, a drive circuit 100A in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of a Si-IGBT 20 (hereinafter also referred to as a Si element) as a first semiconductor element and a potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of a SiC-MOSFET 22 (hereinafter also referred to as a SiC element) as a second semiconductor element having a lower current capability than the first semiconductor element and a reference potential VNC, a source-sink connection MOSFET 28 connecting the gate terminals of both the Si element and the SiC element (i.e., connecting the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22), and a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) to transition between on and off states in a predetermined order. The drive circuit 100A is connected to a parallel connection circuit 200. The parallel connection circuit 200 is a circuit in which a Si-IGBT 20 as a first semiconductor element and a SiC-MOSFET 22 as a second semiconductor element having a lower current capability than the first semiconductor element are connected in parallel.

[0027] In the parallel connection circuit 200, the collector terminal of the Si-IGBT 20 and the drain terminal of the SiC-MOSFET 22 are connected, and the emitter terminal of the Si-IGBT 20 and the source terminal of the SiC-MOSFET 22 are connected.

[0028] The control circuit 30 is commonly connected to the gate terminal 24A of the source MOSFET 24 and the gate terminal 26A of the sink MOSFET 26, and is also connected to the gate terminal 28A of the source-sink connection MOSFET 28 and the reference potential VNC.

[0029] In order to prevent all the current from flowing through the small-sized SiC element and causing it to be destroyed, the on-operation (transition to the on state) of the semiconductor device by a control signal (input signal) from an external controller (not shown here) requires that the Si element that can pass a large current be turned on first, and then the small-sized SiC element be turned on after a predetermined time delay. In contrast, in order to prevent all the current from flowing through the small-sized SiC element and causing it to be destroyed, the off-operation (transition to the off state) of the semiconductor device by a control signal (input signal) from an external controller (not shown here) requires that the SiC element be turned off first. The detailed procedure will be described below.

[0030] FIG. 4 is a diagram showing an example of the operation of a Si device and an example of the operation of a SiC device according to this embodiment.

[0031] 4, when an input signal (ON signal) related to an ON operation is input to the control circuit 30, the control circuit 30 inputs an L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 for a predetermined time (time T1) to turn off the source-sink connection MOSFET 28 and cuts the connection between the gate terminal 20A for controlling the ON / OFF of the Si-IGBT 20 and the gate terminal 22A for controlling the ON / OFF of the SiC-MOSFET 22. The timing for inputting the L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 may be when the rising edge of the input signal (ON signal) is detected.

[0032] Thereafter, the source MOSFET 24 and the sink MOSFET 26, whose gate inputs are linked, perform transition operations opposite to each other. That is, the source MOSFET 24 transitions from off to on with a delay of time T2 when the signal input to the gate terminal 24A of the source MOSFET 24 changes from an L-level signal to an H-level signal, and the sink MOSFET 26 transitions from on to off with a delay of time T2 when the signal input to the gate terminal 26A of the sink MOSFET 26 changes from an H-level signal to an L-level signal.

[0033] As a result, the gate of Si-IGBT 20 is charged, and Si-IGBT 20 is turned on before SiC-MOSFET 22. On the other hand, since source-sink connection MOSFET 28 is turned off, the gate of SiC-MOSFET 22 is disconnected from the gate of Si-IGBT 20 and is not charged.

[0034] Thereafter, when an H-level signal is input to gate terminal 28A of source-sink connection MOSFET 28 to turn on source-sink connection MOSFET 28, gate terminal 20A for on / off control of Si-IGBT 20 is connected to gate terminal 22A for on / off control of SiC-MOSFET 22. This starts charging the gate of SiC-MOSFET 22, and SiC-MOSFET 22 turns on with a delay of time T3 from Si-IGBT 20.

[0035] Next, when an input signal (off signal) related to an off operation is input to the control circuit 30, the control circuit 30 inputs an L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 for a predetermined time (time T4) to turn off the source-sink connection MOSFET 28 and cuts the connection between the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22. The timing for inputting the L-level signal to the gate terminal 28A of the source-sink connection MOSFET 28 may be when the falling edge of the input signal (off signal) is detected.

[0036] Thereafter, the source MOSFET 24 and the sink MOSFET 26, whose gate inputs are linked, perform transition operations opposite to each other. That is, the source MOSFET 24 transitions from on to off with a delay of time T5 when the signal input to the gate terminal 24A of the source MOSFET 24 changes from an H-level signal to an L-level signal, and the sink MOSFET 26 transitions from off to on with a delay of time T5 when the signal input to the gate terminal 26A of the sink MOSFET 26 changes from an L-level signal to an H-level signal.

[0037] As a result, the gate of the SiC-MOSFET 22 is discharged, and the SiC-MOSFET 22 is turned off before the Si-IGBT 20. On the other hand, since the source-sink connection MOSFET 28 is turned off, the gate of the Si-IGBT 20 is disconnected from the gate of the SiC-MOSFET 22 and is not discharged.

[0038] Thereafter, when an H-level signal is input to gate terminal 28A of source-sink connection MOSFET 28 to turn on source-sink connection MOSFET 28, gate terminal 20A for on / off control of Si-IGBT 20 is connected to gate terminal 22A for on / off control of SiC-MOSFET 22. This starts discharging the gate of Si-IGBT 20, and Si-IGBT 20 turns off with a delay of time T6 from SiC-MOSFET 22.

[0039] As described above, it is possible to control the transition of the on / off states of the Si element and the SiC element with a simpler circuit configuration. Specifically, it is possible to control the transition of the on / off states of the Si element and the SiC element with a simple circuit configuration without providing a gate drive circuit for each of the Si element and the SiC element to cause a delay in the on / off operation.

[0040] <Second embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0041] <Configuration of semiconductor device> Fig. 5 is a diagram conceptually illustrating an example of the circuit configuration of a semiconductor device according to this embodiment. As illustrated in Fig. 5, a drive circuit 100A in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of the Si device and a potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of the SiC device and a reference potential VNC, a source-sink connection MOSFET 28 connecting the gate terminals of both the Si device and the SiC device (i.e., connecting the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22), and a control circuit 30 that transitions these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) between on and off states in a predetermined order. A parallel-connection circuit 200 is connected to the drive circuit 100A.

[0042] In the configuration shown in FIG. 5 , when an N-channel MOSFET is applied to the source-sink connection MOSFET 28, the control circuit 30 transitions the source-sink connection MOSFET 28 to the on state in order to charge the gate of the SiC-MOSFET 22.

[0043] At this time, the power supply voltage applied to the gate of source-sink connection MOSFET 28 to transition source-sink connection MOSFET 28 to the ON state is potential VCC. Because potential VCC is equivalent to the gate voltage of Si-IGBT 20, when source-sink connection MOSFET 28 transitions to the ON state and the gate voltage of SiC-MOSFET 22 increases, the gate-source voltage VGS of source-sink connection MOSFET 28 decreases as the gate voltage of SiC-MOSFET 22 increases. In order for a MOSFET to transition to the ON state, the gate-source voltage VGS must be equal to or greater than the gate threshold Vth. Therefore, in this case, source-sink connection MOSFET 28 transitions to the OFF state before the gate voltage of SiC-MOSFET 22 reaches potential VCC.

[0044] 6 is a diagram showing an example of an increase in the gate voltage of SiC-MOSFET 22 and a decrease in the gate-source voltage VGS of source-sink connection MOSFET 28. As shown in the example in FIG. 6, when the gate-source voltage VGS of source-sink connection MOSFET 28 falls below the gate threshold Vth, source-sink connection MOSFET 28 transitions to the off state. As a result, the increase in the gate voltage of SiC-MOSFET 22 is limited and does not rise to the potential VCC.

[0045] This may result in a decrease in the gate voltage of the SiC-MOSFET 22, leading to deterioration of the DC characteristics (and a decrease in the current carrying capacity, etc.).

[0046] 7 is a diagram conceptually illustrating a modified example of the circuit configuration of the semiconductor device according to the present embodiment. As illustrated in the example of FIG. 7, the semiconductor device includes a parallel connection circuit 200 in which an Si-IGBT 20 and an SiC-MOSFET 22 are connected in parallel, a source MOSFET 24 connected between a gate terminal 20A for controlling the on / off of the Si element and a potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for controlling the on / off of the SiC element and a reference potential VNC, and a source-sink connection MOSFET 27 that connects between the gate terminals of both the Si element and the SiC element (i.e., connects between the gate terminal 20A for controlling the on / off of the Si-IGBT 20 and the gate terminal 22A for controlling the on / off of the SiC-MOSFET 22). The drive circuit 100B includes a FET 28, a source MOSFET 32 connected between a gate terminal 28A for controlling the on / off of the source-sink connection MOSFET 28 and a potential VCC2, a sink MOSFET 34 connected between the gate terminal 28A for controlling the on / off of the source-sink connection MOSFET 28 and a reference potential VNC, a control circuit 30A that controls the on / off state transition of these MOSFETs (the source MOSFET 24, the sink MOSFET 26, the source-sink connection MOSFET 28, the source MOSFET 32, and the sink MOSFET 34) in a predetermined order, and an internal power supply circuit 50 that outputs potentials VCC and VCC2. A drive circuit 100B includes the source MOSFET 24, the sink MOSFET 26, the source-sink connection MOSFET 28, the source MOSFET 32, the sink MOSFET 34, the control circuit 30A, and the internal power supply circuit 50. Note that the potential VCC2 is assumed to be higher than the potential VCC. The source-sink connection MOSFET 28 is, for example, an N-channel MOSFET.

[0047] In the configuration shown in FIG. 7, the power supply voltage output from the internal power supply circuit 50 is divided into two systems, potential VCC and potential VCC2, and potential VCC2 is used as the power supply for a front-stage circuit (a circuit consisting of source MOSFET 32 and sink MOSFET 34) that applies a gate voltage to gate terminal 28A for on / off control of source-sink connection MOSFET 28.

[0048] With this circuit configuration, the source MOSFET 32 functions as an element that charges the gate of the source-sink connection MOSFET 28, and the sink MOSFET 34 functions as an element that discharges the gate of the source-sink connection MOSFET 28, thereby ensuring that the gate-source voltage VGS of the source-sink connection MOSFET 28 is equal to or higher than the threshold voltage even if the gate voltage of the SiC MOSFET 22 rises. This ensures that the gate of the SiC MOSFET 22 is sufficiently charged, preventing deterioration of the DC characteristics.

[0049] <Third embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0050] <Configuration of semiconductor device> Fig. 8 is a conceptual diagram illustrating an example of the circuit configuration of a semiconductor device according to this embodiment. As illustrated in Fig. 8, a drive circuit 100C in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of the Si device and a potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of the SiC device and a reference potential VNC, a source-sink connection MOSFET 128 connecting the gate terminals of both the Si device and the SiC device (i.e., connecting the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22), and a control circuit 30 that transitions these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 128) between on and off states in a predetermined order. A parallel-connection circuit 200 is connected to the drive circuit 100C.

[0051] 8, the source-sink connection MOSFET 128 is configured by connecting an N-channel MOSFET 128A and a P-channel MOSFET 128B in parallel. An inverter 128C is connected between the gate terminal of the N-channel MOSFET 128A and the gate terminal of the P-channel MOSFET 128B. The source-sink connection MOSFET 128 can apply a gate voltage so that both the SiC-MOSFET 22 and the Si-IGBT 20 are turned on or off (i.e., their on and off operations are synchronized).

[0052] With this configuration, even if N-channel MOSFET 128A of source-sink connection MOSFET 128 is turned off as the gate voltage of SiC-MOSFET 22 increases, P-channel MOSFET 128B can be turned on. Therefore, the gate voltage of SiC-MOSFET 22 can be sufficiently charged without using an additional power supply circuit, thereby suppressing deterioration of DC characteristics.

[0053] <Fourth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0054] <Configuration of semiconductor device> Fig. 9 is a diagram conceptually illustrating an example of the circuit configuration of a semiconductor device according to this embodiment. As illustrated in Fig. 9, a drive circuit 100D in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of the Si device and a potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of the SiC device and a reference potential VNC, a source-sink connection resistor 228 connecting the gate terminals of both the Si device and the SiC device (i.e., connecting the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22), and a control circuit 30 that transitions these MOSFETs (the source MOSFET 24 and the sink MOSFET 26) between on and off states in a predetermined order. A parallel-connection circuit 200 is connected to the drive circuit 100D.

[0055] In the configuration shown in FIG. 9, the gate input of the source MOSFET 24 and the gate input of the sink MOSFET 26 are not linked, and transitions from the off state to the on state and from the on state to the off state, respectively, at separate timings.

[0056] FIG. 10 is a diagram showing an example of the operation of a Si device and an example of the operation of a SiC device according to this embodiment.

[0057] 9, when an input signal (ON signal) related to an ON operation is input to the control circuit 30, the source MOSFET 24 transitions from OFF operation to ON operation as a result of the signal input to the gate terminal 24A of the source MOSFET 24 changing from an L level signal to an H level signal. Also, the sink MOSFET 26 transitions from ON operation to OFF operation with a delay of time T10 as a result of the signal input to the gate terminal 26A of the sink MOSFET 26 changing from an H level signal to an L level signal.

[0058] As a result, the gate of Si-IGBT 20 is charged, and Si-IGBT 20 turns on before SiC-MOSFET 22. Thereafter, charging of the gate of SiC-MOSFET 22 begins, and SiC-MOSFET 22 turns on with a delay of time T10 from Si-IGBT 20.

[0059] Next, when an input signal (off signal) related to an off operation is input to the control circuit 30, the sink MOSFET 26 transitions from an off operation to an on operation as a result of the signal input to the gate terminal 26A of the sink MOSFET 26 changing from an L level signal to an H level signal. Also, the source MOSFET 24 transitions from an on operation to an off operation with a delay of time T12 as a result of the signal input to the gate terminal 24A of the source MOSFET 24 changing from an H level signal to an L level signal.

[0060] As a result, the gate of the SiC-MOSFET 22 is discharged, and the SiC-MOSFET 22 is turned off before the Si-IGBT 20. Thereafter, the gate of the Si-IGBT 20 starts to discharge, and the Si-IGBT 20 is turned off later than the SiC-MOSFET 22 by time T12.

[0061] With such a configuration, a circuit for driving the source-sink connection MOSFET 28 is not required, and therefore the on / off control of the Si-IGBT 20 and the SiC-MOSFET 22 can be performed with a simple configuration.

[0062] <Fifth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0063] <Configuration of semiconductor device> Fig. 11 is a diagram conceptually illustrating an example of the circuit configuration of a semiconductor device according to this embodiment. As illustrated in Fig. 11, a drive circuit 100E in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of the Si element and a potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of the SiC element and a reference potential VNC, a source-sink connection MOSFET 28 connecting the gate terminals of both the Si element and the SiC element (i.e., connecting between the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22), a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) to transition between on and off states in a predetermined order, a Si-IGBT gate voltage monitor 40 that detects the gate voltage of the Si-IGBT 20, and a SiC-MOSFET gate voltage monitor 42 that detects the gate voltage of the SiC-MOSFET 22. A parallel connection circuit 200 is connected to the drive circuit 100E.

[0064] In the configuration shown in FIG. 11, the control circuit 30 can control the timing of the state transition of either the Si-IGBT 20 or the SiC-MOSFET 22 which will transition later (from the on state to the off state, or from the off state to the on state) based on the gate voltage of the Si-IGBT 20 detected by the Si-IGBT gate voltage monitor 40 and the gate voltage of the SiC-MOSFET 22 detected by the SiC-MOSFET gate voltage monitor 42.

[0065] In a circuit configuration other than this, for example, when in the on state, source-sink connection MOSFET 28 is turned off to charge the gate of Si-IGBT 20, and Si-IGBT 20 is turned on to start charging the gate of SiC-MOSFET 22. Therefore, the time until source-sink connection MOSFET 28 is turned on again is set with a certain margin secured so that SiC-MOSFET 22 does not turn on before Si-IGBT 20.

[0066] In this case, the time during which the SiC-MOSFET 22 is in the on state, which is effective for improving efficiency, may become shorter.

[0067] Therefore, the gate voltage of the Si-IGBT 20 is monitored by the Si-IGBT gate voltage monitor 40, and when the ON operation of the Si-IGBT 20 is confirmed, the source-sink connection MOSFET 28 is immediately transitioned to the ON state, thereby promptly starting gate charging of the SiC-MOSFET 22, thereby improving system efficiency.

[0068] FIG. 12 is a diagram showing an example of the operation of a Si device and an example of the operation of a SiC device according to this embodiment.

[0069] As shown in an example in FIG. 12, the gate voltage of the Si-IGBT 20 is monitored by the Si-IGBT gate voltage monitor 40, and when the ON operation of the Si-IGBT 20 is confirmed (X1), the source-sink connection MOSFET 28 is immediately transitioned to the ON state (i.e., the time difference between X1 and X2 is made as short as possible), thereby enabling gate charging (ON operation) of the SiC-MOSFET 22 to begin promptly.

[0070] Similarly, the gate voltage of the SiC-MOSFET 22 is monitored by the SiC-MOSFET gate voltage monitor 42, and when the off operation of the SiC-MOSFET 22 is confirmed (X3), the source-sink connection MOSFET 28 is immediately transitioned to the on state (i.e., the time difference between X3 and X4 is made as short as possible), thereby enabling the gate discharge (off operation) of the Si-IGBT 20 to be started promptly.

[0071] Sixth Embodiment A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0072] <Configuration of semiconductor device> 13 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to this embodiment. As illustrated in the example of FIG. 13, a drive circuit 100F in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of the Si element and a potential VCC2, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of the SiC element and a reference potential VNC, a source-sink connection MOSFET 28 connecting the gate terminals of both the Si element and the SiC element (i.e., connecting between the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22), a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) to transition between on and off states in a predetermined order, and an internal power supply circuit 52 connected to the control circuit 30 and the source MOSFET 24 and inputting a potential VCC to the control circuit 30 and a potential VCC2 to the source MOSFET 24. However, the potential VCC2 is assumed to be a voltage higher than the potential VCC, and may be the same as or different from the potential VCC2 shown in Fig. 7. Furthermore, a parallel connection circuit 200 is connected to the drive circuit 100F.

[0073] 3, the gate voltage of the SiC-MOSFET 22 may be lower than the gate voltage of the Si-IGBT 20 because it is supplied via the source-sink connection MOSFET 28. This may result in a deterioration of the DC characteristics and a decrease in operating efficiency.

[0074] 13, the internal power supply circuit 52 boosts the potential VCC to a potential VCC2 higher than the potential VCC, and then supplies the potential to the source MOSFET 24, thereby increasing the gate voltage of the SiC-MOSFET 22. This makes it possible to suppress deterioration of the DC characteristics and maintain the operating efficiency.

[0075] Seventh Embodiment A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0076] <Configuration of semiconductor device> FIG. 14 is a diagram conceptually showing an example of the circuit configuration of a semiconductor device according to this embodiment. As shown in the example of FIG. 14, a drive circuit 100G in the semiconductor device includes: a source MOSFET 24 connected between a gate terminal 20A for on / off control of the Si element and a potential VCC2; a sink MOSFET 26 connected between a gate terminal 22A for on / off control of the SiC element and a reference potential VNC; a source-sink connection MOSFET 28 connecting the gate terminals of both the Si element and the SiC element (i.e., connecting between the gate terminal 20A for on / off control of the Si-IGBT 20 and the gate terminal 22A for on / off control of the SiC-MOSFET 22); a control circuit 30 that causes these MOSFETs (the source MOSFET 24, the sink MOSFET 26, and the source-sink connection MOSFET 28) to transition between on and off states in a predetermined order; an internal power supply circuit 52 connected to the control circuit 30 and the source MOSFET 24, and that inputs a potential VCC to the control circuit 30 and a potential VCC2 to the source MOSFET 24; and a current detection circuit 54 that detects a current value at the emitter terminal of the Si-IGBT 20. However, the potential VCC2 is assumed to be higher than the potential VCC. A parallel connection circuit 200 is connected to the drive circuit 100G.

[0077] The current detection circuit 54 feeds back the detected current value to the control circuit 30. Then, based on the magnitude of the current value input from the current detection circuit 54, the control circuit 30 may control whether or not to boost the potential VCC to a potential VCC2 in the internal power supply circuit 52 and input it to the source MOSFET 24. Specifically, the control circuit 30 may boost the potential VCC to a potential VCC2 in the internal power supply circuit 52 and input it to the source MOSFET 24 only when the magnitude of the current value input from the current detection circuit 54 is larger than a predetermined threshold value.

[0078] 15 is a diagram showing an example of the DC characteristics of a MOSFET. As shown in the example of FIG. 15, as the voltage value increases, the current value decreases significantly (deterioration of the DC characteristics becomes apparent).

[0079] With this configuration, it is possible to reduce the current consumption in the internal power supply circuit 52, while suppressing deterioration of the DC characteristics and maintaining the operating efficiency.

[0080] <Eighth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0081] <Configuration of semiconductor device> 16 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to this embodiment. The configuration shown in Fig. 16 is, for example, a circuit that uses an inverter to drive a motor for rotating an air conditioner compressor.

[0082] 16, in this circuit, two parallel connection circuits 200 are connected in series to a load 2000 such as a motor, and a plurality of parallel connection circuits 200 connected in series are further connected in parallel. A drive circuit 1000 that drives a gate is connected to each parallel connection circuit 200. The drive circuit 1000 may be, for example, drive circuit 100A, drive circuit 100B, drive circuit 100C, drive circuit 100D, drive circuit 100E, drive circuit 100F, drive circuit 100G, or the like.

[0083] In a circuit such as that shown in Fig. 16, as shown in Fig. 17, dv / dt occurs due to switching of one of the Si-IGBT 20 and the SiC-MOSFET 22, and this dv / dt may cause a current to flow through the parasitic capacitance between the CG or DG of a semiconductor element that is in the OFF state. This may cause the gate voltage of the semiconductor element that is in the OFF state to be charged, resulting in an unintended transition to the ON state and an abnormal state. Fig. 17 is a diagram showing an example of the operation of the Si-IGBT 20 and the SiC-MOSFET 22.

[0084] To prevent such malfunctions, a common method is to place an additional sink MOSFET to reduce the impedance between the gate and the reference potential and quickly draw this current, and to transition the additional sink MOSFET to the on state after the semiconductor device normally transitions to the off state.

[0085] Fig. 18 is a diagram showing an example of a drive circuit having a general parallel-connected circuit. As shown in the example in Fig. 18, drive circuit 100H includes control signal generation circuit 12 that receives an input signal, gate drive circuit 14 to which control signal 12A is input from control signal generation circuit 12, gate drive circuit 16 to which control signal 12B is input from control signal generation circuit 12, sink MOSFET 13 connected between gate terminal 20A and reference potential VNC, and sink MOSFET 15 connected between gate terminal 22A and reference potential VNC. Drive circuit 100H is connected to Si-IGBT 20 to which a gate signal is input from gate drive circuit 14 to gate terminal 20A, and SiC-MOSFET 22 to which a gate signal is input from gate drive circuit 16 to gate terminal 22A.

[0086] 18, the gate drive circuit 14 of the Si-IGBT 20 and the gate drive circuit 16 of the SiC-MOSFET 22 are separated, so two additional sink MOSFETs (sink MOSFET 13 and sink MOSFET 15) are required, which increases the circuit size.

[0087] 19 is a diagram conceptually illustrating an example of a circuit configuration of a semiconductor device according to this embodiment. As illustrated in the example of FIG. 19, a drive circuit 100J in the semiconductor device includes a source MOSFET 24 connected between a gate terminal 20A for on / off control of Si-IGBT 20 and potential VCC, a sink MOSFET 26 connected between a gate terminal 22A for on / off control of SiC-MOSFET 22 and reference potential VNC, a source-sink connection MOSFET 28 connecting between the gate terminals of both the Si element and the SiC element (i.e., connecting between gate terminal 20A for on / off control of Si-IGBT 20 and gate terminal 22A for on / off control of SiC-MOSFET 22), a sink MOSFET 13A connected between gate terminal 20A and reference potential VNC, and a control circuit 30 that causes these MOSFETs (source MOSFET 24, sink MOSFET 26, source-sink connection MOSFET 28, and sink MOSFET 13A) to transition between on and off states in a predetermined order. A parallel connection circuit 200 is connected to the drive circuit 100J.

[0088] According to the configuration shown in FIG. 19, the gate terminal 20A and the gate terminal 22A are connected by the source-sink MOSFET 28, and therefore, by placing one additional sink MOSFET 13A at either the gate of the Si-IGBT 20 or the gate of the SiC-MOSFET 22, it is possible to obtain the same effect as that of FIG. 18.

[0089] FIG. 20 is a diagram showing an example of the operation of a Si device and an example of the operation of a SiC device according to this embodiment.

[0090] 20, sink MOSFET 13A transitions to the OFF state when an input signal (ON signal) related to an ON operation is input to control circuit 30, and transitions to the ON state after an input signal (OFF signal) related to an OFF operation is input to control circuit 30 and after Si-IGBT 20 transitions to the OFF state. In this way, the gate potential of Si-IGBT 20 is held at reference potential VNC.

[0091] <Ninth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0092] <Configuration of semiconductor device> In the configuration shown in Fig. 19, sink MOSFET 13A is connected to the gate of Si-IGBT 20, which transitions to the on state first. In such a case, the gate of SiC-MOSFET 22 and sink MOSFET 13A may be connected via a sink diode. Fig. 21 is a diagram showing an example of a configuration in which the gate of SiC-MOSFET 22 and sink MOSFET 13A are connected via sink diode 113. In Fig. 21, the anode of sink diode 113 is located on the gate side of SiC-MOSFET 22.

[0093] If sink diode 113 is not provided, the sinking capability may be affected because source-sink connection MOSFET 28 is provided in the path from the gate of SiC-MOSFET 22 via sink MOSFET 13A.

[0094] Therefore, by providing sink diode 113 and sinking in two parallel paths, the sinking capability can be improved.

[0095] The reason for providing sink diode 113 without connecting by direct wiring is that, as shown in the example in Fig. 22, the gate of Si-IGBT 20, which is to be transitioned to the ON state first, is charged first, and at that time, the gate of SiC-MOSFET 22, which is to be transitioned to the ON state later, is prevented from being charged. If sink diode 113 is not provided, the gate of SiC-MOSFET 22 will be charged in state Y in Fig. 22. Note that Fig. 22 is a diagram showing an example of the operation of the Si element and the operation of the SiC element according to this embodiment.

[0096] <Effects Produced by the Multiple Embodiments Described Above> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0097] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0098] According to the embodiment described above, the semiconductor device includes a first semiconductor element, a second semiconductor element, a first source semiconductor element, a first sink semiconductor element, a source-sink connection semiconductor element, and a control circuit 30. Here, the first semiconductor element corresponds to, for example, the Si-IGBT 20. The second semiconductor element corresponds to, for example, the SiC-MOSFET 22. The first source semiconductor element corresponds to, for example, the source MOSFET 24. The first sink semiconductor element corresponds to, for example, the sink MOSFET 26. The source-sink connection semiconductor element corresponds to, for example, the source-sink connection MOSFET 28, the source-sink connection MOSFET 128, etc. The SiC-MOSFET 22 is connected in parallel with the Si-IGBT 20. The source MOSFET 24 is connected between a first power supply potential (for example, potential VCC) and the gate terminal 20A of the Si-IGBT 20. Sink MOSFET 26 is connected between reference potential VNC and gate terminal 22A of SiC MOSFET 22. Source-sink connection MOSFET 28 is connected between gate terminal 20A of Si-IGBT 20 and gate terminal 22A of SiC MOSFET 22. Control circuit 30 controls the on / off state transitions of source MOSFET 24, sink MOSFET 26, and source-sink connection MOSFET 28 so that Si-IGBT 20 and SiC MOSFET 22 transition to the on state in this order, and SiC MOSFET 22 and Si-IGBT 20 transition to the off state in this order.

[0099] According to this configuration, the transition of the on / off state of each of the Si element and the SiC element can be controlled by a simple circuit configuration including a semiconductor element for source-sink connection.

[0100] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0101] Furthermore, according to the embodiment described above, the control circuit 30 turns the source-sink connection MOSFET 28 off to transition the Si-IGBT 20 to the on state, and then turns the source-sink connection MOSFET 28 on to transition the SiC-MOSFET 22 to the on state. Furthermore, the control circuit 30 turns the source-sink connection MOSFET 28 off to transition the SiC-MOSFET 22 to the off state, and then turns the source-sink connection MOSFET 28 on to transition the SiC-MOSFET 22 to the off state. This configuration allows the on / off transitions of the Si element and the SiC element to be controlled by a simple circuit configuration including source-sink connection semiconductor elements. Specifically, it is possible to control the on / off delays of the Si element and the SiC element with a simple circuit configuration without providing gate drive circuits for generating a delay in the on / off operation for each of the Si element and the SiC element.

[0102] According to the above-described embodiment, the semiconductor device includes a second source semiconductor element and a second sink semiconductor element. The second source semiconductor element corresponds to, for example, the source MOSFET 32. The second sink semiconductor element corresponds to, for example, the sink MOSFET 34. The source MOSFET 32 is connected to the gate terminal 28A of the source-sink connection MOSFET 28. The source MOSFET 32 charges the gate of the source-sink connection MOSFET 28. The sink MOSFET 34 is connected to the gate terminal 28A of the source-sink connection MOSFET 28. The sink MOSFET 34 discharges the gate of the source-sink connection MOSFET 28. The source-sink connection MOSFET 28 is an N-channel MOSFET. The source-sink connection MOSFET 28 is connected to a potential VCC via the source MOSFET 24. The source-sink connection MOSFET 28 is connected to a second power supply potential (for example, a potential VCC2) higher than the potential VCC via the source MOSFET 32. According to this configuration, even when the semiconductor element for source-sink connection is an N-channel MOSFET, the gate voltage of the SiC-MOSFET 22 can be charged up to the potential VCC, thereby preventing the gate voltage of the SiC-MOSFET 22 from becoming insufficient and suppressing deterioration of the DC characteristics.

[0103] Furthermore, according to the embodiment described above, the source-sink connection MOSFET 128 is an element in which an N-channel MOSFET 128A and a P-channel MOSFET 128B are connected in parallel. The N-channel MOSFET 128A and the P-channel MOSFET 128B are connected between the gate terminal 20A of the Si-IGBT 20 and the gate terminal 22A of the SiC-MOSFET 22. The Si-IGBT 20 and the SiC-MOSFET 22 are synchronized in their ON and OFF states. With this configuration, even if the N-channel MOSFET 128A of the source-sink connection MOSFET 128 turns OFF as the gate voltage of the SiC-MOSFET 22 increases, the P-channel MOSFET 128B can be turned ON. Therefore, the gate voltage of the SiC-MOSFET 22 can be sufficiently charged without using an additional power supply circuit, thereby suppressing deterioration of DC characteristics.

[0104] According to the above-described embodiment, the semiconductor device includes a first gate voltage detector and a second gate voltage detector. The first gate voltage detector corresponds to, for example, the Si-IGBT gate voltage monitor 40. The second gate voltage detector corresponds to, for example, the SiC-MOSFET gate voltage monitor 42. The Si-IGBT gate voltage monitor 40 detects the gate voltage of the Si-IGBT 20 as a first gate voltage. The SiC-MOSFET gate voltage monitor 42 detects the gate voltage of the SiC-MOSFET 22 as a second gate voltage. The control circuit 30 controls the transition timing of either the Si-IGBT 20 or the SiC-MOSFET 22, whichever transitions between on and off states later, based on the first and second gate voltages. With this configuration, the source-sink connection MOSFET 28 is immediately transitioned to the on state when the on operation of the Si-IGBT 20 is confirmed (X1), thereby enabling gate charging of the SiC-MOSFET 22 to begin promptly. Furthermore, when the off operation of the SiC-MOSFET 22 is confirmed (X3), the source-sink connection MOSFET 28 is immediately transitioned to the on state, thereby enabling the gate discharge of the Si-IGBT 20 to start promptly.

[0105] Furthermore, according to the embodiment described above, the semiconductor device includes an internal power supply circuit 52 connected to potential VCC and capable of outputting potential VCC2 higher than potential VCC. Source MOSFET 24 is connected between internal power supply circuit 52 and gate terminal 20A of Si-IGBT 20. This configuration boosts the potential VCC2 higher than potential VCC in internal power supply circuit 52 and then supplies it to source MOSFET 24, thereby increasing the gate voltage of SiC-MOSFET 22. This makes it possible to suppress deterioration of DC characteristics and maintain operating efficiency.

[0106] Furthermore, according to the embodiment described above, the semiconductor device includes a current detection circuit 54 that detects a current flowing through a parallel-connection circuit 200 that includes an Si-IGBT 20 and an SiC-MOSFET 22. Then, a control circuit 30 controls whether to output a potential VCC or a potential VCC2 from the internal power supply circuit 52 to the source MOSFET 24, depending on the value of the current detected by the current detection circuit 54. With this configuration, it is possible to reduce the current consumption in the internal power supply circuit 52, while suppressing deterioration of DC characteristics and maintaining operating efficiency.

[0107] Furthermore, according to the embodiment described above, the semiconductor device includes a third sink semiconductor element connected between the gate terminal 20A of the Si-IGBT 20 and the reference potential VNC. Here, the third sink semiconductor element corresponds to, for example, the sink MOSFET 13A. Then, the control circuit 30 turns on the sink MOSFET 13A after the Si-IGBT 20 transitions to the off state, thereby maintaining the gate potential of the Si-IGBT 20 at the reference potential VNC. With this configuration, the number of semiconductor elements required to maintain the gate potential of the Si-IGBT 20 at the reference potential VNC can be reduced to one, thereby suppressing an increase in the circuit size.

[0108] Furthermore, according to the embodiment described above, the semiconductor device includes sink diode 113 connected between gate terminal 22A of SiC-MOSFET 22 and sink MOSFET 13A. Such a configuration can improve the sink capability for maintaining the off state.

[0109] Furthermore, according to the embodiment described above, a plurality of parallel-connection circuits 200, each of which has a Si-IGBT 20 and a SiC-MOSFET 22 connected in parallel, are connected in series and in parallel. A drive circuit 1000 including a source MOSFET 24, a sink MOSFET 26, a source-sink connection MOSFET 28, and a control circuit 30 is connected to each parallel-connection circuit 200. According to this configuration, in a semiconductor device including a plurality of parallel-connection circuits 200, the drive circuits 1000 corresponding to each parallel-connection circuit 200 have a simple circuit configuration including a source-sink connection semiconductor element, thereby enabling effective control of the transition of the on / off states of the Si elements and the SiC elements.

[0110] Furthermore, according to the embodiment described above, the semiconductor device includes the Si-IGBT 20, the SiC-MOSFET 22 connected in parallel with the Si-IGBT 20, the source MOSFET 24 connected between the potential VCC and the gate terminal 20A of the Si-IGBT 20, the sink MOSFET 26 connected between the reference potential VNC and the gate terminal 22A of the SiC-MOSFET 22, the source-sink connecting resistor 228 connected between the gate terminal 20A of the Si-IGBT 20 and the gate terminal 22A of the SiC-MOSFET 22, and a control circuit 30 that controls the on / off state transitions of the source MOSFET 24 and the sink MOSFET 26 so that the Si-IGBT 20 and the SiC-MOSFET 22 transition to the on state in this order, and the SiC-MOSFET 22 and the Si-IGBT 20 transition to the off state in this order.

[0111] According to this configuration, it is possible to control the transition of the on / off states of the Si element and the SiC element with a simple configuration, without controlling the gate drive of the semiconductor element for source-sink connection.

[0112] Furthermore, according to the embodiment described above, the gate terminal of source MOSFET 24 and the gate terminal of sink MOSFET 26 are connected to control circuit 30. With this configuration, the gate voltage of source MOSFET 24 and the gate voltage of sink MOSFET 26 can be controlled to control the transition of the on / off states of Si-IGBT 20 and SiC-MOSFET 22.

[0113] Furthermore, according to the embodiment described above, the SiC-MOSFET 22 is a semiconductor element made of a wide bandgap semiconductor. The allowable current of the SiC-MOSFET 22 is lower than that of the Si-IGBT 20. With this configuration, by using a semiconductor element made of a wide bandgap semiconductor, it is possible to reduce costs due to its small size and improve efficiency (i.e., reduce losses) due to its good DC characteristics at low currents.

[0114] <Modifications of the above-described embodiments> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0115] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0116] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0117] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may also be provided.

[0118] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0119] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0120] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0121] Various aspects of the present disclosure are summarized below as appendices.

[0122] (Appendix 1) a first semiconductor element; a second semiconductor element connected in parallel to the first semiconductor element; a first source semiconductor element connected between a first power supply potential and a gate terminal of the first semiconductor element; a first sink semiconductor element connected between a reference potential and a gate terminal of the second semiconductor element; a source-sink connecting semiconductor element connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; a control circuit for controlling the on / off state transitions of the first source semiconductor element, the first sink semiconductor element, and the source-sink connection semiconductor element so that the first semiconductor element and the second semiconductor element are transitioned to an on state in this order, and the second semiconductor element and the first semiconductor element are transitioned to an off state in this order; Semiconductor device.

[0123] (Appendix 2) 10. The semiconductor device according to claim 1, The control circuit turning the source-sink coupling semiconductor element into an OFF state to transition the first semiconductor element into an ON state, and then turning the source-sink coupling semiconductor element into an ON state to transition the second semiconductor element into an ON state; turning the source-sink coupling semiconductor element into an off state to transition the second semiconductor element into an off state, and then turning the source-sink coupling semiconductor element into an on state to transition the second semiconductor element into an off state; Semiconductor device.

[0124] (Appendix 3) 3. The semiconductor device according to claim 1, a second source semiconductor element connected to a gate terminal of the source-sink connection semiconductor element and charging the gate of the source-sink connection semiconductor element; a second sink semiconductor element connected to the gate terminal of the source-sink connection semiconductor element and discharging the gate of the source-sink connection semiconductor element, The source-sink connecting semiconductor element is It is an N-channel MOSFET, connected to the first power supply potential via the first source semiconductor element, connected to a second power supply potential that is a potential higher than the first power supply potential via the second source semiconductor element; Semiconductor device.

[0125] (Appendix 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, the source-sink connection semiconductor element is an element in which an N-channel MOSFET and a P-channel MOSFET are connected in parallel, the N-channel MOSFET and the P-channel MOSFET are connected between the gate terminal of the first semiconductor device and the gate terminal of the second semiconductor device; the first semiconductor element and the second semiconductor element are synchronized in on and off states with each other; Semiconductor device.

[0126] (Appendix 5) A semiconductor device according to any one of Supplementary Notes 1 to 4, a first gate voltage detector that detects a gate voltage of the first semiconductor element as a first gate voltage; a second gate voltage detector that detects a gate voltage of the second semiconductor element as a second gate voltage; the control circuit controls a transition timing of one of the first semiconductor element and the second semiconductor element which will transition to an on / off state later, based on the first gate voltage and the second gate voltage. Semiconductor device.

[0127] (Appendix 6) 6. The semiconductor device according to any one of claims 1 to 5, further comprising an internal power supply circuit connected to the first power supply potential and capable of outputting a second power supply potential higher than the first power supply potential; the first source semiconductor element is connected between the internal power supply circuit and the gate terminal of the first semiconductor element; Semiconductor device.

[0128] (Appendix 7) 7. The semiconductor device according to claim 6, further comprising a current detection circuit that detects a current flowing through a parallel connection circuit that includes the first semiconductor element and the second semiconductor element; the control circuit controls whether to output the first power supply potential or the second power supply potential from the internal power supply circuit to the first source semiconductor element, depending on the value of the current detected by the current detection circuit. Semiconductor device.

[0129] (Appendix 8) 8. The semiconductor device according to claim 1, further comprising a third sink semiconductor element connected between the gate terminal of the first semiconductor element and the reference potential; the control circuit turns on the third sink semiconductor element after the first semiconductor element has transitioned to an off state, thereby maintaining the gate potential of the first semiconductor element at the reference potential; Semiconductor device.

[0130] (Appendix 9) 9. The semiconductor device according to claim 8, further comprising a sinking diode connected between the gate terminal of the second semiconductor element and the third sinking semiconductor element; Semiconductor device.

[0131] (Appendix 10) 10. The semiconductor device according to any one of claims 1 to 9, a plurality of parallel connection circuits in which the first semiconductor element and the second semiconductor element are connected in parallel are connected in series and in parallel; a drive circuit including the first source semiconductor element, the first sink semiconductor element, the source-sink connection semiconductor element, and the control circuit is connected to each of the parallel connection circuits; Semiconductor device.

[0132] (Appendix 11) a first semiconductor element; a second semiconductor element connected in parallel to the first semiconductor element; a first source semiconductor element connected between a first power supply potential and a gate terminal of the first semiconductor element; a first sink semiconductor element connected between a reference potential and a gate terminal of the second semiconductor element; a source-sink connecting resistor connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; a control circuit that controls the on / off state transitions of the first semiconductor element for source and the first semiconductor element for sink so that the first semiconductor element and the second semiconductor element are transitioned to the on state in this order, and the second semiconductor element and the first semiconductor element are transitioned to the off state in this order; Semiconductor device.

[0133] (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, a gate terminal of the first source semiconductor element and a gate terminal of the first sink semiconductor element are connected to the control circuit; Semiconductor device.

[0134] (Appendix 13) 13. The semiconductor device according to any one of claims 1 to 12, the second semiconductor element is a semiconductor element made of a wide bandgap semiconductor, The allowable current amount of the second semiconductor element is lower than the allowable current amount of the first semiconductor element. Semiconductor device. [Explanation of symbols]

[0135] 12 control signal generation circuit, 12A control signal, 12B control signal, 13 sink MOSFET, 13A sink MOSFET, 15 sink MOSFET, 14 gate drive circuit, 16 gate drive circuit, 20 Si-IGBT, 20A gate terminal, 22 SiC-MOSFET, 22A gate terminal, 24 source MOSFET, 24A gate terminal, 26 sink MOSFET, 26A gate terminal, 28 source-sink connection MOSFET, 28A gate terminal, 30 control circuit, 30A control circuit, 32 source MOSFET, 34 sink MOSFET, 40 Si-IGBT gate voltage monitor, 42 SiC-MOSFET gate voltage monitor, 50 internal power supply circuit, 52 internal power supply circuit, 54 current detection circuit, 100 drive circuit, 100A drive circuit, 100B drive circuit, 100C drive circuit, 100D drive circuit, 100E drive circuit, 100F Driver circuit, 100G driver circuit, 100H driver circuit, 100J driver circuit, 113 sink diode, 128 source-sink connection MOSFET, 128A N-channel MOSFET, 128B P-channel MOSFET, 128C inverter, 200 parallel connection circuit, 228 source-sink connection resistor, 1000 driver circuit, 2000 load.

Claims

1. a first semiconductor element; a second semiconductor element connected in parallel to the first semiconductor element; a first source semiconductor element connected between a first power supply potential and a gate terminal of the first semiconductor element; a first sink semiconductor element connected between a reference potential and a gate terminal of the second semiconductor element; a source-sink connecting semiconductor element connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; a control circuit for controlling the on / off state transitions of the first source semiconductor element, the first sink semiconductor element, and the source-sink connection semiconductor element so that the first semiconductor element and the second semiconductor element are transitioned to the on state in this order, and the second semiconductor element and the first semiconductor element are transitioned to the off state in this order; Semiconductor device.

2. 2. The semiconductor device according to claim 1, The control circuit the first semiconductor element is transitioned to an on state by turning the source-sink coupling semiconductor element off, and then the second semiconductor element is transitioned to an on state by turning the source-sink coupling semiconductor element on; turning the source-sink connection semiconductor element into an off state to transition the second semiconductor element into an off state, and then turning the source-sink connection semiconductor element into an on state to transition the second semiconductor element into an off state; Semiconductor device.

3. 3. The semiconductor device according to claim 1, a second source semiconductor element connected to the gate terminal of the source-sink connection semiconductor element and charging the gate of the source-sink connection semiconductor element; a second sink semiconductor element connected to the gate terminal of the source-sink connection semiconductor element and discharging the gate of the source-sink connection semiconductor element, The source-sink connecting semiconductor element is an N-channel MOSFET, connected to the first power supply potential via the first source semiconductor element, connected to a second power supply potential that is higher than the first power supply potential via the second source semiconductor element; Semiconductor device.

4. 3. The semiconductor device according to claim 1, the source-sink connected semiconductor element is an element in which an N-channel MOSFET and a P-channel MOSFET are connected in parallel, the N-channel MOSFET and the P-channel MOSFET are connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; the first semiconductor element and the second semiconductor element are synchronized in on and off states; Semiconductor device.

5. 3. The semiconductor device according to claim 1, a first gate voltage detector that detects a gate voltage of the first semiconductor element as a first gate voltage; a second gate voltage detector that detects a gate voltage of the second semiconductor element as a second gate voltage; the control circuit controls a transition timing of one of the first semiconductor element and the second semiconductor element which will transition to an on / off state later, based on the first gate voltage and the second gate voltage; Semiconductor device.

6. 3. The semiconductor device according to claim 1, further comprising an internal power supply circuit connected to the first power supply potential and capable of outputting a second power supply potential higher than the first power supply potential; the first source semiconductor element is connected between the internal power supply circuit and the gate terminal of the first semiconductor element; Semiconductor device.

7. 7. The semiconductor device according to claim 6, a current detection circuit that detects a current flowing through a parallel-connected circuit that includes the first semiconductor element and the second semiconductor element; the control circuit controls whether to output the first power supply potential or the second power supply potential from the internal power supply circuit to the first source semiconductor element, depending on the value of the current detected by the current detection circuit. Semiconductor device.

8. 3. The semiconductor device according to claim 1, further comprising a third sink semiconductor element connected between the gate terminal of the first semiconductor element and the reference potential; the control circuit turns on the third sink semiconductor element after the first semiconductor element has transitioned to an off state, thereby maintaining the gate potential of the first semiconductor element at the reference potential; Semiconductor device.

9. 9. The semiconductor device according to claim 8, further comprising a sinking diode connected between the gate terminal of the second semiconductor element and the third sinking semiconductor element; Semiconductor device.

10. 3. The semiconductor device according to claim 1, a plurality of parallel connection circuits in which the first semiconductor element and the second semiconductor element are connected in parallel are connected in series and in parallel; a drive circuit including the first source semiconductor element, the first sink semiconductor element, the source-sink connection semiconductor element, and the control circuit is connected to each of the parallel connection circuits; Semiconductor device.

11. a first semiconductor element; a second semiconductor element connected in parallel to the first semiconductor element; a first source semiconductor element connected between a first power supply potential and a gate terminal of the first semiconductor element; a first sink semiconductor element connected between a reference potential and a gate terminal of the second semiconductor element; a source-sink connecting resistor connected between the gate terminal of the first semiconductor element and the gate terminal of the second semiconductor element; a control circuit that controls the on / off state transitions of the first semiconductor element for source and the first semiconductor element for sink so that the first semiconductor element and the second semiconductor element are transitioned to the on state in this order, and the second semiconductor element and the first semiconductor element are transitioned to the off state in this order; Semiconductor device.

12. 12. The semiconductor device according to claim 1, 2 or 11, a gate terminal of the first source semiconductor element and a gate terminal of the first sink semiconductor element are connected to the control circuit; Semiconductor device.

13. 12. The semiconductor device according to claim 1, 2 or 11, the second semiconductor element is a semiconductor element made of a wide bandgap semiconductor, an allowable current amount of the second semiconductor element is lower than an allowable current amount of the first semiconductor element; Semiconductor device.

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