Electrostatic chuck

Abstract

To provide an electrostatic chuck that can sufficiently make uniform the in-plane temperature distribution of a substrate during processing.SOLUTION: An electrostatic chuck 10 comprises a dielectric substrate 100, a plurality of seal rings 150, and a plurality of dots 113. The plurality of seal rings 150 includes a first seal ring 151 arranged on the most outer peripheral end, and a second seal ring 152 arranged inside the first seal ring 151. In a top view, an area between the first seal ring 151 and the second seal ring 152 includes a first area D1 on the side of the first seal ring 151, and a second area D2 on the side of the second seal ring 152. The ratio of the total area of all the dots 113 arranged in the first area D1 occupied in the first area D1 is higher than the ratio of the total area of all the dots 113 arranged in the second area D2 occupied in the second area D2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an electrostatic chuck. [Background technology]

[0002] For example, semiconductor manufacturing equipment such as an etching apparatus is provided with an electrostatic chuck as a device for attracting and holding a substrate, such as a silicon wafer, to be processed. As described in Patent Document 1 below, an electrostatic chuck includes a dielectric substrate provided with an attracting electrode and a base plate that supports the dielectric substrate, which are joined together. When a voltage is applied to the attracting electrode, an electrostatic force is generated, and a substrate placed on the dielectric substrate is attracted and held.

[0003] An inert gas for temperature control is supplied to the space between the dielectric substrates. The space is divided into multiple sections by multiple annular protrusions provided on the dielectric substrate. By individually adjusting the pressure of the inert gas in each section, it is possible to make the temperature distribution within the surface of the substrate uniform during processing. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-135851 Summary of the Invention [Problem to be solved by the invention]

[0005] During processing such as etching, the temperature of the substrate tends to rise, particularly in the outer peripheral portion. Depending on the degree of temperature rise, it may be difficult to sufficiently uniform the temperature distribution within the surface of the substrate by simply adjusting the pressure of the inert gas.

[0006] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an electrostatic chuck that can sufficiently uniform the temperature distribution within the surface of a substrate during processing. [Means for solving the problem]

[0007] To achieve the above object, the present invention provides an electrostatic chuck comprising: a dielectric substrate having a mounting surface on which an object to be attracted is placed; a plurality of seal rings, which are annular protrusions formed on the dielectric substrate and whose tip surfaces form part of the mounting surface; and a plurality of dots, which are protrusions formed on the dielectric substrate and whose tip surfaces form part of the mounting surface. The plurality of seal rings include a first seal ring disposed at the outermost edge of the mounting surface and a second seal ring disposed inside the first seal ring without any other seal rings sandwiched between the first seal ring and the second seal ring. When viewed perpendicularly to the mounting surface, the region between the first seal ring and the second seal ring includes a first region on the first seal ring side and a second region on the second seal ring side, and the proportion of the total area of all the dots disposed in the first region to the first region is higher than the proportion of the total area of all the dots disposed in the second region to the second region.

[0008] In an electrostatic chuck having such a configuration, heat transfer from the substrate due to solid contact is more likely to occur in the first region directly below the outer periphery of the substrate than in the second region located inside the first region. Therefore, the outer periphery of the substrate, which is likely to increase in temperature during processing, can be efficiently cooled by heat transfer due to solid contact. As a result, it is possible to sufficiently uniform the temperature distribution within the surface of the substrate during processing. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an electrostatic chuck that can sufficiently uniform the temperature distribution within the surface of a substrate during processing. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view schematically illustrating a configuration of an electrostatic chuck according to an embodiment of the present invention. [Figure 2] 2 is a diagram showing the configuration of the mounting surface side of a dielectric substrate provided in the electrostatic chuck of FIG. 1. FIG. [Figure 3] 10A and 10B are diagrams showing the configuration of the mounting surface side of a dielectric substrate according to a modified example. [Figure 4] 10A and 10B are diagrams showing the configuration of the mounting surface side of a dielectric substrate according to another modified example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0012] The electrostatic chuck 10 according to this embodiment is configured to electrostatically attract and hold a substrate W to be processed inside a semiconductor manufacturing apparatus (not shown), such as an etching apparatus. The substrate W to be attracted is, for example, a silicon wafer. The electrostatic chuck 10 may also be used in apparatuses other than semiconductor manufacturing apparatuses.

[0013] 1 is a schematic cross-sectional view showing the configuration of an electrostatic chuck 10 in a state where the electrostatic chuck 10 attracts and holds a substrate W. The electrostatic chuck 10 includes a dielectric substrate 100 and a base plate 200.

[0014] The dielectric substrate 100 is a substantially disk-shaped member made of a sintered ceramic body. The dielectric substrate 100 contains, for example, high-purity aluminum oxide (Al2O3), but may also contain other materials. The purity, type, and additives of the ceramics in the dielectric substrate 100 can be appropriately set in consideration of the plasma resistance and other properties required of the dielectric substrate 100 in semiconductor manufacturing equipment.

[0015] 1 of the dielectric substrate 100 is a "mounting surface" on which the substrate W is placed. Also, a lower surface 120 of the dielectric substrate 100 in FIG. 1 is a "bonded surface" that is bonded to the base plate 200 via a bonding layer 300. The viewpoint when the electrostatic chuck 10 is viewed from the side of the surface 110 along a direction perpendicular to the surface 110 will hereinafter also be referred to as a "top view."

[0016] An attraction electrode 130 is embedded inside the dielectric substrate 100. The attraction electrode 130 is a thin, flat layer made of a metal material such as tungsten, and is disposed parallel to the surface 110. The attraction electrode 130 may be made of a material other than tungsten, such as molybdenum, platinum, or palladium. When a voltage is applied to the attraction electrode 130 from the outside via a power supply path (not shown), an electrostatic force is generated between the surface 110 and the substrate W, thereby attracting and holding the substrate W. The power supply path may be configured in any of various well-known ways. The attraction electrode 130 may be provided as a single so-called "monopolar" electrode as in this embodiment, or as two so-called "bipolar" electrodes.

[0017] As shown in Fig. 1, a space SP is formed between the dielectric substrate 100 and the substrate W. When a process such as etching is performed in the semiconductor manufacturing equipment, helium gas for temperature adjustment is supplied to the space SP from the outside through a gas hole 114 (not shown in Fig. 1, see Fig. 2) described below. By providing helium gas between the dielectric substrate 100 and the substrate W, the thermal resistance between them is adjusted, thereby maintaining the temperature of the substrate W at an appropriate temperature. Note that the temperature adjustment gas supplied to the space SP may be a type of gas other than helium.

[0018] 2 is a top view of the dielectric substrate 100. As shown in the figure, a seal ring 150 and dots 113 are provided on the surface 110, which is the mounting surface, and the space SP is formed around these. Note that the dots 113 are not shown in FIG.

[0019] The seal ring 150 is an annular protrusion provided as a wall that divides the space SP. A plurality of seal rings 150 are provided, and are arranged in a substantially concentric pattern when viewed from above. The tip surface (the upper end surface in FIG. 1) of each seal ring 150 forms part of the surface 110 and abuts against the substrate W. In this embodiment, a total of two seal rings 150 are provided, thereby dividing the space SP into two. With this configuration, it is possible to individually adjust the pressure of the helium gas in each space SP and make the surface temperature distribution of the substrate W during processing more uniform.

[0020] The seal ring 150 disposed on the outside will also be referred to as the "first seal ring 151" below. The seal ring 150 disposed on the inside will also be referred to as the "second seal ring 152" below.

[0021] The first seal ring 151 is a seal ring 150 that is arranged at the outermost position of the surface 110, which is the mounting surface. The second seal ring 152 is a seal ring 150 that is arranged at a position inside the first seal ring 151, without another seal ring 150 being sandwiched between it and the first seal ring 151. An embodiment in which another seal ring 150 is further provided inside the second seal ring 152 may also be adopted.

[0022] 1 and 2, the portion designated by the reference numeral "116" is the bottom surface of the space SP. Hereinafter, this portion will also be referred to as the "bottom surface 116." The seal ring 150, together with the dots 113 described below, is formed by digging down a portion of the surface 110 to the position of the bottom surface 116.

[0023] The dots 113 are tiny protrusions that protrude from the bottom surface 116. When viewed from above, each dot 113 has a circular shape. As shown in FIG. 2, a plurality of dots 113 are provided and are dispersedly arranged on the mounting surface of the dielectric substrate 100. The upper end surface of each dot 113 forms part of the surface 110 and abuts against the substrate W. By providing a plurality of such dots 113, bending of the substrate W is suppressed. The plurality of dots 113 are dispersedly arranged so as to be distributed at a substantially uniform density when viewed from above, but there is a bias in the arrangement density of the dots 113 in some areas. "Arrangement density" refers to the number of dots 113 per unit area. The arrangement of the dots 113 will be explained later.

[0024] As shown in Fig. 2, a plurality of gas holes 114 are formed in the dielectric substrate 100. The gas holes 114 are not shown in Fig. 1. The gas holes 114 are holes for supplying helium gas to the space SP, and are through-holes formed to extend vertically from the surface 120 toward the surface 110. Helium gas supplied from the outside passes through a gas flow path (not shown) formed inside the base plate 200, and is then supplied to the space SP through the gas holes 114.

[0025] In this embodiment, a plurality of gas holes 114 are connected to each of the two divided spaces SP. A porous body made of, for example, alumina may be disposed inside the gas holes 114. With this configuration, it is possible to prevent dielectric breakdown in the path through the gas holes 114 while ensuring the flow of gas through the gas holes 114.

[0026] Grooves may be formed on the bottom surface 116 of the space SP in order to increase the in-plane diffusion rate of the helium gas.

[0027] Lift pin holes are formed in the dielectric substrate 100 and the base plate 200 so as to penetrate them in a straight line, but are not shown in Figures 1 and 2. A total of three lift pin holes are formed, and they are arranged at equal intervals of 120 degrees. Lift pins that move up and down through the lift pin holes are used to attach and detach the substrate W to and from the surface 110 of the dielectric substrate 100. A sealing surface may be formed around the lift pin holes to separate the interior of the lift pin holes from the space SP.

[0028] The base plate 200 is a substantially disk-shaped member that supports the dielectric substrate 100. The base plate 200 is formed of a metal material such as aluminum. An upper surface 210 of the base plate 200 in FIG. 1 is a "bonded surface" that is bonded to the dielectric substrate 100 via a bonding layer 300.

[0029] The bonding layer 300 is a layer provided between the dielectric substrate 100 and the base plate 200, and bonds them together. The bonding layer 300 is formed by curing an adhesive made of an insulating material. In this embodiment, a silicone adhesive is used as the adhesive. However, the bonding layer 300 may be formed by curing another type of adhesive. In either case, it is preferable to use a material with as high a thermal conductivity as possible as the material for the bonding layer 300 so as to reduce the thermal resistance between the dielectric substrate 100 and the base plate 200.

[0030] An insulating film may be formed on the surface of the base plate 200. For example, an alumina film formed by thermal spraying can be used as the insulating film. By covering the surface of the base plate 200 with an insulating film, the dielectric strength of the base plate 200 can be increased.

[0031] A coolant flow path 250 for passing a coolant is formed inside the base plate 200. When a process such as etching is performed in the semiconductor manufacturing equipment, a coolant is supplied to the coolant flow path 250 from the outside, thereby cooling the base plate 200. Heat generated in the substrate W during the process is transferred to the coolant via the helium gas in the space SP, the dielectric substrate 100, and the base plate 200, and is discharged to the outside together with the coolant.

[0032] The arrangement of the seal rings 150, dots 113, etc. on the dielectric substrate 100 will be described with reference to Fig. 2. The dotted line DL shown in Fig. 2 is an imaginary circle between the first seal ring 151 and the second seal ring 152. The center of the dotted line DL coincides with the centers of the first seal ring 151 and the second seal ring 152. The radius of the dotted line DL is, for example, the average of the radii of the first seal ring 151 and the second seal ring 152, but it does not have to be this large.

[0033] In the top view, of the region between the first seal ring 151 and the second seal ring 152, the region on the outer circumferential side of the dotted line DL in FIG. 2 will also be referred to as the "first region D1" hereinafter. Also, of the region between the first seal ring 151 and the second seal ring 152, the region on the inner circumferential side of the dotted line DL in FIG. 2 will also be referred to as the "second region D2" hereinafter. The first region D1 is a region adjacent to the first seal ring 151 from the inner circumferential side, and the second region D2 is a region adjacent to the second seal ring 152 from the outer circumferential side. In other words, the first region D1 is a region on the first seal ring 151 side (i.e., the outer circumferential side), and the second region D2 is a region on the second seal ring 152 side (i.e., the inner circumferential side).

[0034] In this embodiment, all of the dots 113 formed on the dielectric substrate 100 have the same shape, and therefore the areas of the dots 113 when viewed from above are equal to each other.

[0035] 2, the arrangement density of the dots 113 in the first region D1 is higher than the arrangement density of the dots 113 in the second region D2. As a result, the proportion of the total area occupied by all the dots 113 arranged in the first region D1 is higher than the proportion of the total area occupied by all the dots 113 arranged in the second region D2 in the first region D1.

[0036] The reason for adopting such a configuration will be explained below. In a semiconductor back-up device, when a process such as etching is performed on a substrate W, the temperature of the substrate W is likely to rise, particularly in the outer peripheral portion. Depending on the degree of temperature rise, it may be difficult to sufficiently uniform the in-plane temperature distribution of the substrate W simply by adjusting the pressure of the inert gas in each space SP.

[0037] Therefore, in the electrostatic chuck according to this embodiment, as described above, the arrangement density of the dots 113 in the first region D1 is increased, and the area ratio of the dots 113 in the first region D1 is increased. In this configuration, heat transfer from the substrate W due to solid contact is more likely to occur in the first region D1 directly below the outer periphery of the substrate W than in the second region D2. Therefore, the outer periphery of the substrate W, which is likely to increase in temperature during processing, can be efficiently cooled by heat transfer due to solid contact. As a result, it is possible to sufficiently uniform the in-plane temperature distribution of the substrate W during processing.

[0038] The surface roughness of the tip surface of the first seal ring 151 may be greater than the surface roughness of the tip surface of the second seal ring 152. Note that the "tip surfaces" of the first seal ring 151 and the second seal ring 152 refer to the surfaces that are part of the surface 110, which is the mounting surface. Hereinafter, the surface roughness of the tip surface of the first seal ring 151 will be simply referred to as "the surface roughness of the first seal ring 151." Similarly, hereinafter, the surface roughness of the tip surface of the second seal ring 152 will be simply referred to as "the surface roughness of the second seal ring 152."

[0039] The surface roughness of the first seal ring 151 may be set to a value in the range of 0.10 μm to 0.20 μm in arithmetic mean roughness (Ra), for example, and the surface roughness of the second seal ring 152 may be set to a value in the range of 0.05 μm to 0.10 μm in arithmetic mean roughness (Ra), for example.

[0040] One method for making the surface roughness of the first seal ring 151 and the surface roughness of the second seal ring 152 different from each other is, for example, to simultaneously form the first seal ring 151 and the second seal ring 152 by processing such as sandblasting, and then, with the entire surface except for the first seal ring 151 masked, perform further blasting processing, etching processing, etc. only on the tip surface of the first seal ring 151.

[0041] In conventional electrostatic chucks, the tip surface of the outermost seal ring is gradually eroded from the outer periphery as plasma reaches it, gradually increasing its surface roughness. This change in surface roughness is undesirable because it can cause the amount of helium gas leakage to change over time. Therefore, by initially increasing the surface roughness of the first seal ring 151 as described above, it is possible to prevent the surface roughness from changing over time due to the arrival of plasma. As a result, it is expected that substrates W can be processed using semiconductor manufacturing equipment under the same conditions for a relatively long period of time.

[0042] If the surface roughness of the tip end surface of the first seal ring 151 is increased, the cooling performance (due to individual contact) of the first seal ring 151 will decrease. However, in this embodiment, as described above, the area ratio of the dots 113 is increased in the vicinity of the first seal ring 151. Therefore, the decrease in cooling performance due to the increase in the surface roughness of the tip end surface of the first seal ring 151 can be compensated for by the improvement in cooling performance via the dots 113.

[0043] The arrangement of the dots 113 is not limited to the example shown in Fig. 2, and various arrangements can be adopted. For example, in a modified example shown in Fig. 3, the dots 113 are arranged in the first region D1 with the same arrangement density as in this embodiment (Fig. 2), while no dots 113 are arranged in the second region D2. Even in this embodiment, the same effect as that described in this embodiment can be achieved. Note that the arrangement of the dots 113 and gas holes 114 in the region inside the second seal ring 152 is the same as the arrangement in Fig. 2, but these are omitted from Fig. 3. The same applies to Fig. 4, which will be described next.

[0044] In another modified example shown in FIG. 4, the arrangement density of the dots 113 in the first region D1 is approximately the same as the arrangement density of the dots 113 in the second region D2. However, in this modified example, the diameter of the dots 113 arranged in the first region D1 is larger than the diameter of the dots 113 arranged in the second region D2. As a result, in this modified example, the area ratio of the dots 113 in the first region D1 is higher than the area ratio of the dots 113 in the second region D2. In other words, the proportion of the total area of all the dots 113 arranged in the first region D1 in the first region D1 is higher than the proportion of the total area of all the dots 113 arranged in the second region D2 in the second region D2. This configuration can also achieve the same effects as those described in the present embodiment.

[0045] However, if the diameter of some of the dots 113 is increased as in this modified example, the contact area between the dots 113 and the substrate W becomes more likely to change due to bending of the substrate W, which may in turn affect the in-plane temperature distribution of the substrate W. Therefore, it is more preferable to have a configuration in which the area of all the dots 113 is small and the contact between the dots 113 and the substrate W is kept close to "point contact," as in this embodiment shown in Figure 2.

[0046] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Design modifications to these specific examples made by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of the above-described specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of the above-described specific examples can be combined in various ways as appropriate, as long as no technical contradictions arise. [Explanation of symbols]

[0047] 10: Electrostatic chuck 100: Dielectric substrate 113: Dot 150: Seal ring 151: First seal ring 152: Second seal ring D1: 1st area D2:Second area

Claims

1. a dielectric substrate having a mounting surface on which an object to be attracted is placed; a plurality of seal rings, which are annular protrusions formed on the dielectric substrate, the tip surfaces of which form part of the mounting surface; a plurality of dots, which are protrusions formed on the dielectric substrate and have tip surfaces that form part of the mounting surface; The plurality of seal rings include: a first seal ring disposed at a position on the mounting surface that is the outermost circumferential edge; a second seal ring disposed inside the first seal ring without any other seal ring sandwiched between the first seal ring and the second seal ring, When viewed from a direction perpendicular to the placement surface, a region between the first seal ring and the second seal ring including a first region on the first seal ring side and a second region on the second seal ring side; The ratio of the total area of all the dots arranged in the first region to the total area of the first region is a ratio of the total area of all the dots arranged in the second region to the total area of the dots arranged in the second region, the ratio being higher than the total area of the dots arranged in the second region.

2. When viewed from a direction perpendicular to the placement surface, the areas of all the dots are the same, The arrangement density of the dots in the first region is 2. The electrostatic chuck according to claim 1, wherein the dots are arranged at a higher density in the first region than in the second region.

3. 2. The electrostatic chuck of claim 1, wherein the surface roughness of the first seal ring is greater than the surface roughness of the second seal ring.

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