Semiconductor device and semiconductor package

Abstract

To provide a semiconductor device capable of alleviating stress generated during mounting using Cu pillars on a Cu conductive layer, and a semiconductor package including the same.SOLUTION: A recess is formed in one end face of a Cu columnar body 18, and the recess has a plurality of side faces spaced apart from one another, and in cross section, the side faces extend upward in a convex arc shape.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a semiconductor package including the same. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, Cu wiring formed on the semiconductor substrate, a plating layer covering the surface and side surfaces of the Cu wiring, and Cu wires wire-bonded onto the Cu wiring via the plating layer. The plating layer has a Ni / Pd / Au laminated structure.

[0003] The manufacturing process of this semiconductor device includes, for example, a step of forming Cu wiring via a barrier metal film on an insulating film covering a semiconductor substrate. The barrier metal film includes a Ti / Cu seed layer formed by sputtering. The Cu wiring is formed on the barrier metal film by electroplating using a resist film on the barrier metal film as a mask. After plating the Cu wiring, the resist film is removed, and the exposed Ti / Cu seed layer is then removed by wet etching. For example, the Cu seed layer is first removed with a mixture of hydrogen peroxide and nitric acid, and then the Ti film is removed with a mixture of hydrogen peroxide and ammonia. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-171386 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device that can alleviate stress that occurs when mounting using Cu pillars on a Cu conductive layer, and a semiconductor package including the same. [Means for solving the problem]

[0006] A semiconductor device according to one aspect of the present invention includes: a semiconductor layer having a first surface; an insulating layer formed on the first surface of the semiconductor layer; a Cu conductive layer formed on the insulating layer and made of a metal mainly composed of Cu; a second insulating layer formed on the insulating layer and covering the Cu conductive layer; Cu pillars extending in a thickness direction through the second insulating layer, made of a metal mainly composed of Cu, and electrically connected to the Cu conductive layer; and an intermediate layer formed between the Cu conductive layer and the Cu pillars, made of a material having a linear expansion coefficient smaller than that of the Cu conductive layer and the Cu pillars.

[0007] A semiconductor package according to one aspect of the present invention includes a conductive member having a first surface and a second surface opposite the first surface, a semiconductor device flip-chip bonded to the first surface of the conductive member, and a sealing resin covering a portion of the conductive member and the semiconductor device. [Effects of the Invention]

[0008] According to one aspect of the present invention, a semiconductor device and a semiconductor package include an intermediate layer formed between a Cu conductive layer and Cu columns, the intermediate layer being made of a material having a linear expansion coefficient smaller than that of the Cu conductive layer and the Cu columns. This allows for the relaxation of stress generated when packaging a semiconductor device using Cu columns. This is particularly effective for flip-chip mounting packages, since semiconductor devices are susceptible to stress when flip-chip mounting them on conductive members. This makes it possible to provide a highly reliable semiconductor package. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view of a semiconductor package according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a plan view (through the sealing resin) of the semiconductor package shown in FIG. [Figure 3]FIG. 3 is a plan view of the semiconductor package shown in FIG. 1 (with the semiconductor element and sealing resin transparent). [Figure 4] FIG. 4 is a bottom view of the semiconductor package shown in FIG. [Figure 5] FIG. 5 is a front view of the semiconductor package shown in FIG. [Figure 6] FIG. 6 is a rear view of the semiconductor package shown in FIG. [Figure 7] FIG. 7 is a right side view of the semiconductor package shown in FIG. [Figure 8] FIG. 8 is a left side view of the semiconductor package shown in FIG. [Figure 9] FIG. 9 is a partially enlarged view of FIG. [Figure 10] FIG. 10 is a partially enlarged view of FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a partially enlarged view (near the first electrode) of FIG. [Figure 16] FIG. 16 is a partially enlarged view of FIG. 11 (near the second electrode). [Figure 17] FIG. 17 is a diagram for explaining the wiring structure of the semiconductor device. [Figure 18A] FIG. 18A is a diagram for explaining a part of the manufacturing process of the semiconductor package. [Figure 18B] FIG. 18B is a diagram showing the next step of FIG. 18A. [Figure 18C] FIG. 18C shows the next step in FIG. 18B. [Figure 18D] FIG. 18D shows the next step in FIG. 18C. [Figure 18E]FIG. 18E shows the next step of FIG. 18D. [Figure 18F] FIG. 18F shows the next step of FIG. 18E. [Figure 18G] FIG. 18G shows the next step in FIG. 18F. [Figure 18H] FIG. 18H shows the next step of FIG. 18G. [Figure 18I] FIG. 18I shows the next step of FIG. 18H. [Figure 18J] FIG. 18J shows the next step of FIG. 18I. [Figure 18K] FIG. 18K shows the next step in FIG. 18J. [Figure 18L] FIG. 18L shows the next step in FIG. 18K. [Figure 18M] FIG. 18M shows the next step in FIG. 18L. [Figure 18N] FIG. 18N shows the next step of FIG. 18M. [Figure 18O] FIG. 18O shows the next step of FIG. 18N. [Figure 18P] FIG. 18P shows the next step in FIG. 18O. [Figure 19] FIG. 19 is a diagram for explaining the effect of stress relaxation by the semiconductor device. [Figure 20] FIG. 20 is a diagram for explaining the effect of stress relaxation by the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] <Embodiments of the present invention> First, embodiments of the present invention will be listed and described.

[0011] A semiconductor device according to one embodiment of the present invention includes: a semiconductor layer having a first surface; an insulating layer formed on the first surface of the semiconductor layer; a Cu conductive layer formed on the insulating layer and made of a metal mainly composed of Cu; a second insulating layer formed on the insulating layer and covering the Cu conductive layer; Cu pillars extending in a thickness direction of the second insulating layer, made of a metal mainly composed of Cu, and electrically connected to the Cu conductive layer; and an intermediate layer formed between the Cu conductive layer and the Cu pillars, made of a material having a linear expansion coefficient smaller than that of the Cu conductive layer and the Cu pillars.

[0012] According to this configuration, an intermediate layer made of a material having a linear expansion coefficient smaller than that of the Cu conductive layer and the Cu columnar body is formed between the Cu conductive layer and the Cu columnar body, thereby making it possible to alleviate stress that occurs when packaging a semiconductor device using the Cu columnar body.

[0013] In the semiconductor device according to one embodiment of the present invention, the linear expansion coefficient of the Cu conductive layer and the Cu columnar body is 16.0 to 18.0 (10 -6 / °C), and the linear expansion coefficient of the intermediate layer is 10.0 to 15.0 (10 -6 / °C).

[0014] In a semiconductor device according to one embodiment of the present invention, the intermediate layer may include a laminated structure of a first intermediate layer and a second intermediate layer stacked in this order from the Cu conductive layer, and the first intermediate layer may have a linear expansion coefficient greater than that of the second intermediate layer and a thickness greater than that of the second intermediate layer.

[0015] In the semiconductor device according to one embodiment of the present invention, the first intermediate layer may include a Ni layer, and the second intermediate layer may include a Pd layer.

[0016] In the semiconductor device according to one embodiment of the present invention, the Cu columnar body may have a thickness of 20 μm to 60 μm.

[0017] In the semiconductor device according to one embodiment of the present invention, the Cu conductive layer may have a thickness of 2 μm to 6 μm.

[0018] A semiconductor device according to one embodiment of the present invention may further include a bonding layer formed on the Cu columnar body and used for external connection, and the bonding layer may have, in a portion in contact with the Cu columnar body, a layer made of a material having a linear expansion coefficient smaller than that of the Cu columnar body.

[0019] In the semiconductor device according to one embodiment of the present invention, the bonding layer may be an external bonding layer used for flip-chip bonding.

[0020] In a semiconductor device according to one embodiment of the present invention, the bonding layer includes a first layer formed on the Cu columnar body and made of a metal primarily containing Ni, and a second layer formed on the first layer and made of a metal primarily containing solder, and the second layer may be used for external connection.

[0021] In the semiconductor device according to one embodiment of the present invention, the second layer may be formed in a substantially spherical shape.

[0022] A semiconductor device according to one embodiment of the present invention includes a barrier layer formed between the insulating layer and the Cu conductive layer, the Cu conductive layer having a first surface and a second surface located opposite the first surface and in contact with the barrier layer, and the periphery of the Cu conductive layer on the second surface side may be spaced inward from the periphery of the barrier layer.

[0023] A semiconductor package according to one embodiment of the present invention includes a conductive member having a first surface and a second surface opposite the first surface, a semiconductor device flip-chip bonded to the first surface of the conductive member, and a sealing resin covering a portion of the conductive member and the semiconductor device.

[0024] According to this configuration, an intermediate layer made of a material having a linear expansion coefficient smaller than that of the Cu conductive layer and the Cu columnar bodies is formed between the Cu conductive layer and the Cu columnar bodies. This makes it possible to alleviate stress generated when packaging a semiconductor device using the Cu columnar bodies. This is particularly effective for flip-chip mounting packages, since semiconductor devices are susceptible to stress when flip-chip mounting them on conductive members. Therefore, a highly reliable semiconductor package can be provided.

[0025] A semiconductor package according to another embodiment of the present invention includes a conductive member having a first surface and a second surface opposite the first surface, a semiconductor device mounted on the first surface of the conductive member and having the Cu pillar-shaped body connected to the first surface of the conductive member, and a sealing resin covering a portion of the conductive member and the semiconductor device.

[0026] A semiconductor package according to another embodiment of the present invention includes a conductive member having a first surface and a second surface opposite to the first surface; a semiconductor device mounted on the first surface of the conductive member and having the Cu pillars connected to the first surface of the conductive member; a bonding material formed between the conductive member and the Cu pillars and made of a metal primarily composed of solder; and a sealing resin covering a portion of the conductive member, the semiconductor device, and the bonding material.

[0027] In a semiconductor package according to another embodiment of the present invention, the Cu pillars may be partially embedded in the bonding material.

[0028] <Detailed Description of the Embodiments of the Present Invention> Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0029] A semiconductor package A10 according to a first embodiment of the present invention will be described with reference to FIGS.

[0030] The semiconductor package A10 includes a conductive member 10, a semiconductor device 20, a bonding layer 30, and a sealing resin 40. As shown in FIG. 1, the semiconductor package A10 is in the QFN (Quad For Non-Lead Package) format. The semiconductor device 20 is a flip-chip LSI. The semiconductor device 20 includes a switching circuit 212A and a control circuit 212B (each of which will be described in detail later).

[0031] In the semiconductor package A10, DC power (voltage) is converted into AC power (voltage) by the switching circuit 212A. The semiconductor package A10 is used, for example, as one element constituting a circuit of a DC / DC converter. Here, for ease of understanding, FIG. 2 shows a perspective view through the sealing resin 40. For ease of understanding, FIG. 3 shows a perspective view through the semiconductor device 20 and the sealing resin 40. In these figures, the transparent semiconductor device 20 and the sealing resin 40 are respectively indicated by imaginary lines (two-dot chain lines).

[0032] In the description of the semiconductor package A10, the thickness direction Z of the conductive member 10 is referred to as the "thickness direction Z." A direction perpendicular to the thickness direction Z is referred to as the "first direction x." A direction perpendicular to both the thickness direction Z and the first direction x is referred to as the "second direction y."

[0033] 1 and 2, the semiconductor package A10 has a square shape when viewed along the thickness direction Z. In addition, in the description of the semiconductor package A10, for convenience, the side on which the plurality of second leads 12 (described in detail later) are located in the second direction y will be referred to as "one side in the second direction y." The side on which the plurality of first leads 11 (described in detail later) are located in the second direction y will be referred to as "the other side in the second direction y."

[0034] 2, the conductive member 10 supports the semiconductor device 20 and also serves as a terminal for mounting the semiconductor package A10 on a wiring board. As shown in FIGS. 11 to 14, a portion of the conductive member 10 is covered with a sealing resin 40. The conductive member 10 has a main surface 101 (first surface) and a back surface 102 (second surface) that face opposite each other in the thickness direction Z. The main surface 101 faces one side in the thickness direction Z and faces the semiconductor device 20.

[0035] The semiconductor device 20 is supported on a main surface 101. The main surface 101 is covered with a sealing resin 40. The back surface 102 faces the other side in the thickness direction Z. The conductive member 10 is composed of a single lead frame. The lead frame is made of, for example, copper (Cu) or a copper alloy. The conductive member 10 includes a plurality of first leads 11, a plurality of second leads 12, and a pair of third leads 13.

[0036] 3 and 4, the multiple first leads 11 are strip-shaped and extend in the second direction y when viewed along the thickness direction Z. The multiple first leads 11 are arranged along the second direction y. In the example shown in semiconductor package A10, the multiple first leads 11 are configured with three terminals: a first input terminal 111A, a second input terminal 11B, and an output terminal 11C.

[0037] The multiple first leads 11 are arranged in the order of the first input terminal 11A, the output terminal 11C, and the second input terminal 11B from one side to the other side in the second direction y. The first input terminal 11A and the second input terminal 11B receive DC power (voltage) to be converted in the semiconductor package A10. The first input terminal 11A is a positive terminal (P terminal). The second input terminal 11B is a negative terminal (N terminal). The output terminal 11C outputs AC power (voltage) converted by the switching circuit 212A configured in the semiconductor device 20.

[0038] As shown in FIG. 3, the first input terminal 11A is located between the plurality of second leads 12 and the output terminal 11C in the second direction y. The output terminal 11C is located between the first input terminal 11A and the second input terminal 11B in the second direction y. Each of the first input terminal 11A and the output terminal 11C includes a main portion 111 and a pair of side portions 112. As shown in FIGS. 3 and 4, the main portion 111 extends in the first direction x. In the plurality of first leads 11, the semiconductor device 20 is supported by the main surface 101 of the main portion 111.

[0039] The pair of side portions 112 are connected to both ends of the main portion 111 in the first direction x. As shown in FIGS. 3, 4, 12, and 13, each of the pair of side portions 112 has a first end surface 112A. The first end surface 112A is connected to both the main surface 101 and the back surface 102 of the first lead 11, and faces the first direction x. The first end surface 112A is exposed from the sealing resin 40.

[0040] 9, a constricted portion 112B is formed on each of a pair of side portions 112 of the first input terminal 11A and the output terminal 11C. The constricted portion 112B extends from the main surface 101 to the back surface 102 of the first lead 11, and is recessed inward from both sides in the second direction y into the side portions 112. The constricted portion 112B is in contact with the sealing resin 40. Due to the constricted portion 112B, in the first input terminal 11A and the output terminal 11C, the dimension b in the second direction y of each of the pair of first end faces 112A is smaller than the dimension B in the second direction y of the back surface 102 of the main portion 111.

[0041] 3, the second input terminal 11B is located on the other side in the second direction y than the output terminal 11C. Therefore, the second input terminal 11B is located on the other side in the second direction y among the multiple first leads 11. The second input terminal 11B includes a main portion 111, a pair of side portions 112, and multiple protrusions 113.

[0042] The multiple protrusions 113 protrude from the other side of the main portion 111 in the second direction y. Sealing resin 40 is filled between two adjacent protrusions 113. As shown in FIG. 12, each of the multiple protrusions 113 has a minor end face 113A. The minor end face 113A is connected to both the main surface 101 and the back surface 102 of the second input terminal 11B and faces the other side in the second direction y. The minor end face 113A is exposed from the sealing resin 40. As shown in FIG. 7, the multiple minor end faces 113A are arranged at predetermined intervals along the first direction x.

[0043] As shown in FIG. 10, a notch 112C is formed in each of the pair of side portions 112 of the second input terminal 11B. The notch 112C extends from the main surface 101 to the back surface 102 of the second input terminal 11B and is recessed in the first direction x from the first end surface 112A. This divides the first end surface 112A into two regions spaced apart in the second direction y. Due to the notch 112C, in the second input terminal 11B, the dimension b in the second direction y of each of the pair of first end surfaces 112A is smaller than the dimension B in the second direction y of the back surface 102 of the main portion 111. Note that the dimension b here is the sum of the dimension b1 in the second direction y of one region of the first end surface 112A and the dimension b2 in the second direction y of the other region of the first end surface 112A (b=b1+b2). The notch 112C is filled with sealing resin 40.

[0044] 3 and 4, in each of the multiple first leads 11, the area of the main surface 101 is larger than the area of the back surface 102. In the example shown in semiconductor package A10, the areas of the back surfaces 102 of the first input terminal 11A and the output terminal 11C are equal. The area of the back surface 102 of the second input terminal 11B is larger than the areas of the back surfaces 102 of the first input terminal 11A and the output terminal 11C.

[0045] In each of the first input terminal 11A, the second input terminal 11B, and the output terminal 11C, the main surface 101 of the main portion 111 on which the semiconductor device 20 is supported may be plated with, for example, silver (Ag). Furthermore, in each of the first input terminal 11A, the second input terminal 11B, and the output terminal 11C, the back surface 102 exposed from the sealing resin 40, the pair of first end faces 112A, and the plurality of sub-end faces 113A may be plated with, for example, tin (Sn). Note that instead of tin plating, multiple metal platings may be employed, for example, in which nickel (Ni), palladium (Pd), and gold (Au) are layered in this order.

[0046] As shown in FIG. 3, the second leads 12 are located on one side of the first leads 11 in the second direction y. One of the second leads 12 is a ground terminal of a control circuit 212B configured in the semiconductor device 20. Each of the other second leads 12 receives power (voltage) for driving the control circuit 212B or an electrical signal for transmission to the control circuit 212B. As shown in FIGS. 3, 4, and 11, each of the second leads 12 has a second end surface 121. The second end surface 121 is connected to both the main surface 101 and the back surface 102 of the second lead 12 and faces one side in the second direction y. The second end surface 121 is exposed from the sealing resin 40. As shown in FIG. 8, the second end surfaces 121 are arranged at predetermined intervals along the first direction.

[0047] 3 and 4, the area of the main surface 101 of each of the multiple second leads 12 is larger than the area of the back surface 102. The areas of the back surfaces 102 of the multiple second leads 12 are all equal. The back surfaces 102 of the multiple second leads 12 on which the semiconductor device 20 is supported may be plated with silver, for example. Furthermore, the back surfaces 102 and second end surfaces 121 of the multiple second leads 12 exposed from the sealing resin 40 may be plated with tin, for example. Instead of tin plating, multiple metal platings may be used, for example, in which nickel, palladium, and gold are layered in this order.

[0048] 3, the pair of third leads 13 are located between the first lead 11 (first input terminal 11A) and the plurality of second leads 12 in the second direction y. The pair of third leads 13 are spaced apart from each other in the first direction x. An electrical signal or the like is input to each of the pair of third leads 13 to be transmitted to the control circuit 212B configured in the semiconductor device 20.

[0049] 3, 4, and 14, each of the pair of third leads 13 has a third end surface 131. The third end surface 131 is connected to both the main surface 101 and the back surface 102 and faces the first direction x. The third end surface 131 is exposed from the sealing resin 40. The third end surface 131, together with the first end surfaces 112A of the multiple first leads 11, is arranged along the second direction y.

[0050] 3 and 4, the area of the main surface 101 of each of the pair of third leads 13 is larger than the area of the back surface 102. The main surfaces 101 of the pair of third leads 13 on which the semiconductor device 20 is supported may be plated with, for example, silver. Furthermore, the back surfaces 102 and third end surfaces 131 of the pair of third leads 13 exposed from the sealing resin 40 may be plated with, for example, tin. Note that instead of tin plating, multiple metal platings may be employed, for example, in which nickel, palladium, and gold are layered in this order.

[0051] As shown in Figures 11 to 14, the semiconductor device 20 is electrically joined to and supported by a conductive member 10 (plurality of first leads 11, plural second leads 12, and a pair of third leads 13) by flip-chip bonding. The semiconductor device 20 is covered with a sealing resin 40. As shown in Figures 12 to 18, the semiconductor device 20 has an element body 21, plural electrodes 22, and a surface protection film 23 as an example of the second insulating layer of the present invention.

[0052] The element body 21 forms the main part of the semiconductor device 20. As shown in Figures 15 and 16, the element body 21 has a semiconductor substrate 211 and a semiconductor layer 212.

[0053] 15 and 16, the semiconductor substrate 211 supports therebelow a semiconductor layer 212, a plurality of electrodes 22, and a surface protection film 23. The constituent material of the semiconductor substrate 211 is, for example, Si (silicon) or silicon carbide (SiC).

[0054] 11 to 14, semiconductor layer 212 is laminated on the side of semiconductor substrate 211 facing main surface 101 of conductive member 10. Semiconductor layer 212 includes multiple types of p-type semiconductors and n-type semiconductors that are doped with different amounts of elements. Semiconductor layer 212 includes switching circuit 212A and control circuit 212B that is electrically connected to switching circuit 212A. Switching circuit 212A is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), or the like.

[0055] In the example shown in the semiconductor package A10, the switching circuit 212A is divided into two regions: a high-voltage region (upper arm circuit) and a low-voltage region (lower arm circuit). Each region is configured with one n-channel MOSFET. The control circuit 212B includes a gate driver for driving the switching circuit 212A, a bootstrap circuit corresponding to the high-voltage region of the switching circuit 212A, and the like, and performs control for normally driving the switching circuit 212A. A wiring layer (described later) is configured in the semiconductor layer 212. The switching circuit 212A and the control circuit 212B are mutually conductive via the wiring layer.

[0056] 11 to 14, the plurality of electrodes 22 protrude from the side of the element body 21 facing the main surface 101 of the conductive member 10 toward the main surface 101 of the conductive member 10. The plurality of electrodes 22 are electrically connected to the main surface 101 of the conductive member 10. The plurality of electrodes 22 include a plurality of first electrodes 22A and a plurality of second electrodes 22B. The plurality of first electrodes 22A are electrically connected to the switching circuit 212A of the semiconductor layer 212. In addition, the plurality of first electrodes 22A are electrically connected to the main surfaces 101 of the plurality of first leads 11. As a result, the plurality of first leads 11 are electrically connected to the switching circuit 212A. In addition, the plurality of second electrodes 22B are electrically connected to the control circuit 212B of the semiconductor layer 212. In addition, most of the plurality of second electrodes 22B are electrically connected to the main surfaces 101 of the plurality of second leads 12. The remaining second electrodes 22B are electrically joined to the main surfaces 101 of the pair of third leads 13. As a result, the plurality of second leads 12 and the pair of third leads 13 are electrically connected to the control circuit 212B.

[0057] As shown in FIGS. 15 and 16 , each of the multiple electrodes 22 has a base 221 and a columnar portion 222. The base 221 is electrically connected to either the switching circuit 212A or the control circuit 212B of the semiconductor layer 212. The columnar portion 222 protrudes from the base 221 toward the main surface 101 of the conductive member 10. The columnar portion 222 has a tip surface 222A and a side surface 222B. The tip surface 222A faces the main surface 101 of the conductive member 10. The side surface 222B is connected to the tip surface 222A and faces in a direction perpendicular to the thickness direction Z. In the semiconductor package A10, the columnar portion 222 has a recess 222C recessed from the tip surface 222A toward the element body 21.

[0058] 15 and 16 , the surface protective film 23 covers the side of the element body 21 facing the main surface 101 of the conductive member 10. In each of the multiple electrodes 22, the tip surface 222A of the columnar portion 222 is located between the main surface 101 of the conductive member 10 and the surface protective film 23 in the thickness direction Z. In the semiconductor package A10, the surface protective film 23 contacts both the base portions 221 and the columnar portions 222 of the multiple electrodes 22.

[0059] As shown in FIGS. 15 and 16 , the bonding layer 30 is in contact with both the main surface 101 of the conductive member 10 and the plurality of electrodes 22. The bonding layer 30 is conductive. As a result, the plurality of electrodes 22 are electrically bonded to the main surface 101 of the conductive member 10. In each of the plurality of electrodes 22, the bonding layer 30 is in contact with both the tip surface 222A and the side surface 222B of the columnar portion 222. In the semiconductor package A10, the bonding layer 30 is also in contact with the recess 222C of the columnar portion 222. Furthermore, the columnar portion 222 of the semiconductor device 20 is embedded in the bonding layer 30. As a result, not only the tip surface 222A and the recess 222C of the columnar portion 222 but also part of the side surface is covered with the bonding layer 30.

[0060] 5 to 8, the sealing resin 40 has a top surface 41, a bottom surface 42, a pair of first side surfaces 431, and a pair of second side surfaces 432. The sealing resin 40 is made of, for example, a black epoxy resin.

[0061] 11 to 14, the top surface 41 faces the same side as the main surface 101 of the conductive member 10 in the thickness direction Z. As shown in FIGS. 5 to 8, the bottom surface 42 faces the opposite side to the top surface 41. As shown in FIG. 4, the back surfaces 102 of the multiple first leads 11, the back surfaces 102 of the multiple second leads 12, and the back surfaces 102 of the pair of third leads 13 are exposed from the bottom surface 42.

[0062] 7 and 8, the pair of first side surfaces 431 are connected to both the top surface 41 and the bottom surface 42 and face in the first direction. The pair of first side surfaces 431 are spaced apart from each other in the second direction y. As shown in FIGS. 12 to 14, the first end surfaces 112A of the multiple first leads 11 and the third end surface 131 of the third lead 13 are exposed from each of the pair of first side surfaces 431 so as to be flush with the first side surfaces 431.

[0063] As shown in FIGS. 5 and 6, the pair of second side surfaces 432 are connected to all of the top surface 41, the bottom surface 42, and the pair of first side surfaces 431, and face the second direction y. The pair of second side surfaces 432 are spaced apart in the first direction x. As shown in FIG. 11, the second end surfaces 121 of the plurality of second leads 12 are exposed from the second side surface 432 located on one side in the second direction y so as to be flush with the second side surface 432. The plurality of minor end surfaces 113A of the second input terminal 11B (first lead 11) are exposed from the second side surface 432 located on the other side in the second direction y so as to be flush with the second side surface 432.

[0064] The semiconductor package A10 includes a conductive member 10 having a main surface 101, a semiconductor device 20 having an element body 21 and a plurality of electrodes 22 electrically joined to the main surface 101, and a bonding layer 30 in contact with both the main surface 101 and the plurality of electrodes 22. Each of the plurality of electrodes 22 has a base 221 in contact with the side of the element body 21 facing the main surface 101, and a columnar portion 222 that protrudes from the base 221 toward the main surface 101 and in contact with the bonding layer 30. As a result, the semiconductor device 20 is electrically joined to the conductive member 10 by flip-chip bonding.

[0065] Fig. 17 is a diagram for explaining the wiring structure of the semiconductor device 20. Fig. 17 shows the semiconductor device 20 before it is bonded to the conductive member 10 by flip-chip bonding. Fig. 17 also shows the semiconductor device 20 in a state where the columnar portions 222 protrude upward. Therefore, Fig. 17 is upside down compared to the above-mentioned Figs. 11 to 16.

[0066] The semiconductor device 20 includes a multilayer wiring structure 1, a passivation film 2 as an example of an insulating layer of the present invention, a base 221 of an electrode 22, a surface protective film 23, a columnar portion 222 of the electrode 22, and a bonding layer 30. Note that only one electrode 22 of the multiple electrodes 22 is shown in FIG.

[0067] The multilayer wiring structure 1 includes a plurality of interlayer insulating films 4 to 7 formed on an element forming surface 3 (first surface) of the semiconductor layer 212, and a plurality of electrode layers 14 to 16 formed in the plurality of interlayer insulating films 4 to 7. Since the electrode layers 14 to 16 form the multilayer wiring structure 1, they may also be referred to as wiring layers 14 to 16, respectively.

[0068] The multiple interlayer insulating films 4 to 7 include a first interlayer insulating film 4 formed on the element forming surface 3 of the semiconductor layer 212, a second interlayer insulating film 5 formed on the first interlayer insulating film 4, a third interlayer insulating film 6 formed on the second interlayer insulating film 5, and a fourth interlayer insulating film 7 formed on the third interlayer insulating film 6. The first interlayer insulating film 4, the second interlayer insulating film 5, the third interlayer insulating film 6, and the fourth interlayer insulating film 7 may each include an oxide film (SiO2 film) or a nitride film (SiN film).

[0069] The plurality of electrode layers 14 to 16 are electrically connected to a switching circuit 212A and a control circuit 212B formed on the semiconductor layer 212 (only the switching circuit 212A is shown in FIG. 17).

[0070] The multiple electrode layers 14 to 16 include a first electrode layer 14 formed on the first interlayer insulating film 4 and covered with a second interlayer insulating film 5, a second electrode layer 15 formed on the second interlayer insulating film 5 and covered with a third interlayer insulating film 6, and a third electrode layer 16 formed on the third interlayer insulating film 6 and covered with a fourth interlayer insulating film 7. The first electrode layer 14, the second electrode layer 15, and the third electrode layer 16 may each contain copper or aluminum.

[0071] A first barrier layer 31 is formed on the lower surface of the first electrode layer 14. The first barrier layer 31 prevents the electrode material constituting the first electrode layer 14 from diffusing into the first interlayer insulating film 4.

[0072] A first barrier layer 32 is formed on the upper surface of the first electrode layer 14. The first barrier layer 32 prevents the electrode material constituting the first electrode layer 14 from diffusing into the second interlayer insulating film 5.

[0073] A second barrier layer 33 is formed on the lower surface of the second electrode layer 15. The second barrier layer 33 prevents the electrode material constituting the second electrode layer 15 from diffusing into the second interlayer insulating film 5.

[0074] A second barrier layer 34 is formed on the upper surface of the second electrode layer 15. The second barrier layer 34 prevents the electrode material constituting the second electrode layer 15 from diffusing into the third interlayer insulating film 6.

[0075] A third barrier layer 35 is formed on the lower surface of the third electrode layer 16. The third barrier layer 35 prevents the electrode material constituting the third electrode layer 16 from diffusing into the third interlayer insulating film 6.

[0076] A third barrier layer 36 is formed on the upper surface of the third electrode layer 16. The third barrier layer 36 prevents the electrode material constituting the third electrode layer 16 from diffusing into the fourth interlayer insulating film 7.

[0077] Each of the barrier layers 31-36 may have a single layer structure made of a titanium nitride layer or a titanium layer, or may have a multilayer structure including a titanium nitride layer and a titanium layer formed on the titanium nitride layer. The barrier layers 31-36 may be made of the same material or different materials.

[0078] The passivation film 2 is formed on the multilayer wiring structure 1 so as to cover the multilayer wiring structure 1. More specifically, the passivation film 2 covers the fourth interlayer insulating film .

[0079] The passivation film 2 may include an oxide film (SiO2 film), a BPSG (Boron Phosphorus Silicon Glass) film, or a nitride film (SiN film). In this embodiment, the passivation film 2 is formed of a nitride film (SiN film).

[0080] A first via 39 penetrating the second interlayer insulating film 5 is formed in the second interlayer insulating film 5 between the upper surface of the first electrode layer 14 and the lower surface of the second electrode layer 15. The first electrode layer 14 is electrically connected to the second electrode layer 15 through the first via 39.

[0081] A first via barrier film 43 is formed between the first via 39 and the second interlayer insulating film 5. The first via 39 may contain tungsten. The first via barrier film 43 may contain titanium nitride.

[0082] A second via 44 penetrating the third interlayer insulating film 6 is formed in the third interlayer insulating film 6 between the upper surface of the second electrode layer 15 and the lower surface of the third electrode layer 16. The second electrode layer 15 is electrically connected to the third electrode layer 16 through the second via 44.

[0083] A second via barrier film 45 is formed between the second via 44 and the third interlayer insulating film 6. The second via 44 may contain tungsten. The second via barrier film 45 may contain titanium nitride.

[0084] A third via 46 is formed in the passivation film 2 and the fourth interlayer insulating film 7 on the third electrode layer 16, penetrating the passivation film 2 and the fourth interlayer insulating film 7. The third via 46 is exposed from the passivation film 2 and is electrically connected to the third electrode layer 16.

[0085] The exposed surface of the third via 46 is formed flush with the surface of the passivation film 2. A third via barrier film 47 is formed between the third via 46 and the fourth interlayer insulating film 7, and between the third via 46 and the passivation film 2. The third via 46 may contain tungsten. The third via barrier film 47 may contain titanium nitride.

[0086] The base 221 of the electrode 22 is formed on the passivation film 2 so as to cover the third via 46. The base 221 of the electrode 22 has a layered structure including a barrier electrode layer 48 formed on the passivation film 2 and a Cu electrode layer 49, which contains a metal mainly composed of copper and is an example of the Cu conductive layer of the present invention, formed on the main surface of the barrier electrode layer 48. The barrier electrode layer 48 prevents the electrode material constituting the Cu electrode layer 49 from diffusing into the passivation film 2.

[0087] Here, the term "metal containing copper as a main component" refers to a metal in which the mass ratio (mass %) of copper constituting the Cu electrode layer 49 is the highest relative to the other components constituting the Cu electrode layer 49 (the same applies hereinafter). When the Cu electrode layer 49 is made of an aluminum-copper alloy (Al-Cu alloy), the mass ratio R of copper is Cu is the mass ratio of aluminum R Al Higher than (R Cu >R Al ).

[0088] When the Cu electrode layer 49 is made of an aluminum-silicon-copper alloy (Al-Si-Cu alloy), the mass ratio R Cu is the mass ratio of aluminum R Al and the mass ratio of silicon, R Si Higher than (R Cu >R Al , and R Cu >R Si ).

[0089] "Metals primarily composed of copper" may contain trace amounts of impurities, but also include high-purity copper with a purity of 99.9999% (6N) or more, and high-purity copper with a purity of 99.99% (4N) or more.

[0090] The barrier electrode layer 48 is formed on the passivation film 2 so as to cover the third via 46. The barrier electrode layer 48 is electrically connected to the first electrode layer 14, the second electrode layer 15, and the third electrode layer 16 through the third via 46.

[0091] The barrier electrode layer 48 may have a thickness of 100 nm to 500 nm (approximately 100 nm in this embodiment). The barrier electrode layer 48 may have a single-layer structure made of a single metal layer. The barrier electrode layer 48 may have a laminated structure in which multiple metal layers are laminated.

[0092] The barrier electrode layer 48 preferably has a thermal expansion coefficient smaller than that of the Cu electrode layer 49. In addition, the barrier electrode layer 48 preferably has a rigidity coefficient larger than that of the Cu electrode layer 49.

[0093] The barrier electrode layer 48 may contain at least one of titanium, titanium nitride, tantalum, tungsten, molybdenum, chromium, and ruthenium. These metal materials can provide the barrier electrode layer 48 with a thermal expansion coefficient (4 μm / m·K to 9 μm / m·K) smaller than that of the Cu electrode layer 49. When the Cu electrode layer 49 is made of high-purity copper, the thermal expansion coefficient of the Cu electrode layer 49 is approximately 16.5 μm / m·K.

[0094] The barrier electrode layer 48 may contain at least one of tantalum, tungsten, molybdenum, chromium, and ruthenium. These metal materials allow the barrier electrode layer 48 to have a thermal expansion coefficient (4 μm / m·K to 7 μm / m·K) smaller than that of the Cu electrode layer 49.

[0095] Furthermore, these metal materials can provide a barrier electrode layer 48 having a modulus of rigidity (50 Gpa to 180 Gpa) greater than that of the Cu electrode layer 49. When the Cu electrode layer 49 is made of high-purity copper, the modulus of rigidity of the Cu electrode layer 49 is approximately 48 Gpa.

[0096] The Cu electrode layer 49 occupies most of the base portion 221 of the electrode 22. The Cu electrode layer 49 may have a thickness of 2 μm to 6 μm. The Cu electrode layer 49 has an upper surface 49a (first surface), a lower surface 49b (second surface) located opposite the upper surface 49a, and a side surface 49c connecting the upper surface 49a and the lower surface 49b. The lower surface 49b of the Cu electrode layer 49 is mechanically and electrically connected to the barrier electrode layer 48.

[0097] The periphery of the lower surface 49b of the Cu electrode layer 49 is spaced inward from the periphery of the barrier electrode layer 48. The lower surface 49b of the Cu electrode layer 49 is formed narrower than the upper surface 49a of the Cu electrode layer 49 in the direction along the surface of the passivation film 2.

[0098] More specifically, in the Cu electrode layer 49, a recess 50 is formed in the region of the lower surface 49b of the side surface 49c, which recesses inward of the Cu electrode layer 49 and exposes the upper surface of the edge of the barrier electrode layer 48.

[0099] The recess 50 is formed in a convex curved shape that bulges obliquely upward from the Cu electrode layer 49. This makes the inner surface of the recess 50 a convex curved surface. Due to this recess 50, the lower surface 49b of the Cu electrode layer 49 is formed to be narrower than the upper surface 49a of the Cu electrode layer 49.

[0100] In this embodiment, the side surface 49c of the Cu electrode layer 49 is located outside the periphery (side surface) of the barrier electrode layer 48. Therefore, in this embodiment, the periphery (side surface) of the barrier electrode layer 48 is located in the region between the periphery of the lower surface 49b of the Cu electrode layer 49 and the side surface 49c of the Cu electrode layer 49. The side surface 49c of the Cu electrode layer 49 may be located inside the periphery (side surface) of the barrier electrode layer 48.

[0101] The base 221 of the electrode 22 includes a pad electrode layer 51, which is an example of an intermediate layer of the present invention, formed on the upper surface 49a of the Cu electrode layer 49. The pad electrode layer 51 is formed on the upper surface 49a of the Cu electrode layer 49 so as to cover the upper surface 49a of the Cu electrode layer 49.

[0102] The pad electrode layer 51 includes a first portion 52 mechanically and electrically connected to the upper surface 49a of the Cu electrode layer 49, and a second portion 53 extending from the first portion 52 to the side of the Cu electrode layer 49.

[0103] In this embodiment, the pad electrode layer 51 has a laminated structure including a first layer 54 formed on the upper surface 49a of the Cu electrode layer 49 and a second layer 55 formed on the first layer 54.

[0104] The first layer 54 and the second layer 55 are made of a material having a linear expansion coefficient smaller than that of the Cu electrode layer 49 and the Cu columns 18 (described later). For example, the linear expansion coefficient of the Cu electrode layer 49 and the Cu columns 18 is 16.0 to 18.0 (10 -6 / °C), and the linear expansion coefficient of the first layer 54 and the second layer 55 is 10.0 to 15.0 (10 -6 / °C).

[0105] The material used for the first layer 54 and the second layer 55 is, for example, Ni=13.3(10 -6 / ℃), Pd=11.8(10 -6 / ℃), Au=14.2(10 -6 / ℃) degree, W=4.3(10 -6 / ℃), Pt=8.9(10 -6 / ° C.) etc. In this embodiment, the first layer 54 is formed of a nickel (Ni) layer, and the second layer 55 is formed of a palladium (Pd) layer.

[0106] The second layer 55 is formed to a thickness smaller than that of the first layer 54. The second layer 55 may be a metal in which the mass ratio (mass %) of palladium constituting the second layer 55 is the highest relative to the other components constituting the second layer 55. In other words, the second layer 55 may be a metal containing palladium as a main component. The first layer 54 may be a metal in which the mass ratio (mass %) of nickel constituting the first layer 54 is the highest relative to the other components constituting the first layer 54. In other words, the first layer 54 may be a metal in which nickel is the main component.

[0107] The thickness of the first layer 54 may be 0.5 μm to 5 μm, and the thickness of the second layer 55 may be 0.05 μm to 0.5 μm.

[0108] The surface protective film 23 is formed on the passivation film 2. The surface protective film 23 covers the base 221 of the electrode 22. The surface protective film 23 has an opening 8 that exposes a part of the base 221 of the electrode 22. The surface protective film 23 has electrical insulation properties and is made of, for example, polyimide.

[0109] The columnar portion 222 of the electrode 22 contacts the base portion 221 within the opening 8 of the surface protective film 23 and protrudes from the opening 8 to the opposite side of the base portion 221. The columnar portion 222 of the electrode 22 has a layered structure including a barrier layer 17 formed on the surface protective film 23 and Cu columns 18, which contain a metal primarily composed of copper and are formed on the main surface of the barrier layer 17. The barrier layer 17 prevents the material constituting the Cu columns 18 from diffusing into the surface protective film 23. Here, the "metal primarily composed of copper" constituting the Cu columns 18 is defined the same as the Cu electrode layer 49 described above.

[0110] The barrier layer 17 is formed on the surface protection film 23 so as to cover the base portion 221 in the opening 8 of the surface protection film 23 (so as to be in contact with the second layer 55). The barrier layer 17 is electrically connected to the base portion 221.

[0111] The barrier layer 17 may have a thickness of 100 nm to 500 nm (approximately 100 nm in this embodiment). The barrier layer 17 may have a single-layer structure made of a single metal layer. The barrier layer 17 may have a laminated structure in which multiple metal layers are laminated.

[0112] The Cu pillars 18 may have a thickness of 20 μm to 60 μm. In addition, in the pillar-shaped portion 222, instead of the Cu pillars 18, pillars made of a material other than Cu may be used.

[0113] The bonding layer 30 is formed on the tip surface 222A of the columnar portion 222 of the electrode 22. The bonding layer 30 has a protruding portion 19 that partially protrudes laterally beyond the side surface 222B of the columnar portion 222.

[0114] The bonding layer 30 may have, in a portion in contact with the Cu columnar body 18, a layer made of a material having a linear expansion coefficient smaller than that of the Cu columnar body 18. In this embodiment, the bonding layer 30 has a layered structure including a first layer 24 formed on the columnar section 222 (Cu columnar body 18) and a second layer 25 formed on the first layer 24. The first layer 24 is made of a material having a linear expansion coefficient smaller than that of the Cu columnar body 18. More specifically, the first layer 24 may include a nickel layer, and the second layer 25 may include a solder layer.

[0115] The nickel layer may be a metal having the highest mass ratio (mass %) of nickel relative to the other components constituting the nickel layer. In other words, the first layer 24 may be any metal containing nickel as its main component.

[0116] The solder layer is preferably a lead-free solder containing no or almost no lead. Examples of lead-free solder that can be used include SnAgCu, SnZnBi, SnCu, SnAgInBi, and SnZnAl. The second layer 25 may be formed in a substantially spherical shape before flip-chip bonding, as shown in FIG. 17 .

[0117] 18A to 18P are diagrams for explaining some of the manufacturing steps for the semiconductor package A10 in the order of steps. In the following, an example will be described in which the Cu electrode layer 49 is made of high-purity copper.

[0118] In manufacturing the semiconductor package A10, first, the semiconductor device 20 is manufactured. Referring to FIG. 18A, a semiconductor substrate 211 (semiconductor layer 212) having a passivation film 2 formed on a multilayer wiring structure 1 is prepared. A third via 46 is formed through the passivation film 2 and the fourth interlayer insulating film 7. Next, a barrier electrode layer 48 is formed on the passivation film 2. The barrier electrode layer 48 may be formed by, for example, a sputtering method.

[0119] 18B, a Cu seed layer 9 is formed on the barrier electrode layer 48. The Cu seed layer 9 may be formed by, for example, a sputtering method. Next, a mask 26 having a predetermined pattern is formed on the Cu seed layer 9. The mask 26 selectively has openings 26a that expose regions of the Cu seed layer 9 where the Cu electrode layer 49 (including the Cu layer 84 in the third example described above) is to be formed.

[0120] Next, referring to FIG. 18C , a Cu electrode layer 49 is formed. The Cu electrode layer 49 is formed on the surface of the Cu seed layer 9 exposed from the opening 26a of the mask 26. The Cu electrode layer 49 may be formed by electrolytic copper plating. The Cu electrode layer 49 is formed up to a depth partway through the opening 26a of the mask 26. The Cu electrode layer 49 is formed integrally with the Cu seed layer 9.

[0121] 18D , a first layer 54 and a second layer 55 are formed in this order on the upper surface 49a of the Cu electrode layer 49. The first layer 54 and the second layer 55 are each formed on the upper surface 49a of the Cu electrode layer 49 exposed through the opening 26a of the mask 26. The first layer 54 and the second layer 55 may each be formed by electroless plating.

[0122] Next, referring to Figure 18E, the mask 26 is removed.

[0123] 18F, unnecessary portions of the Cu seed layer 9 are removed. The Cu seed layer 9 may be removed by wet etching. In this step, part of the Cu electrode layer 49 is side-etched. Therefore, a side surface 49c of the Cu electrode layer 49 is formed so as to be located more inward than a side surface of the pad electrode layer 51.

[0124] This forms the pad electrode layer 51. The pad electrode layer 51 includes a first portion 52 mechanically and electrically connected to the upper surface 49a of the Cu electrode layer 49, and a second portion 53 extending from the first portion 52 to the side of the barrier electrode layer 48.

[0125] 18G, unnecessary portions of the barrier electrode layer 48 are removed. The barrier electrode layer 48 may be removed by wet etching. In this step, the portion of the barrier electrode layer 48 located directly below the Cu electrode layer 49 is removed by an amount corresponding to the thickness of the barrier electrode layer 48. Therefore, the side surface of the barrier electrode layer 48 is formed so as to be located inward from the side surface 49c of the Cu electrode layer 49.

[0126] 18H, the corners of the Cu electrode layer 49 connecting the lower surface 49b and the side surface 49c are removed. The corners of the Cu electrode layer 49 may be removed by wet etching. The wet etching process is performed until the main surface of the barrier electrode layer 48 is exposed. As a result, a recess 50 is formed in the region of the Cu electrode layer 49 on the lower surface 49b side of the side surface 49c, exposing the upper surface of the edge of the barrier electrode layer 48.

[0127] Next, referring to FIG. 18I, a surface protection film 23 is formed on the passivation film 2 so as to cover the base portion 221. Next, the surface protection film 23 is patterned to form an opening 8 in the surface protection film 23. Next, a barrier layer 17 is formed on the surface protection film 23. The barrier layer 17 may be formed by, for example, a sputtering method. Next, a Cu seed layer 27 is formed on the barrier layer 17. The Cu seed layer 27 may be formed by, for example, a sputtering method.

[0128] 18J, a mask 28 having a predetermined pattern is formed on the Cu seed layer 27. The mask 28 selectively has openings 28a that expose regions of the Cu seed layer 27 where the Cu columns 18 are to be formed.

[0129] Next, referring to FIG. 18K, Cu pillars 18 are formed. The Cu pillars 18 are formed on the surface of the Cu seed layer 27 exposed through the openings 28a in the mask 28. The Cu pillars 18 may be formed by electrolytic copper plating. The Cu pillars 18 are formed to the middle of the depth direction of the openings 28a in the mask 28. The Cu pillars 18 are formed integrally with the Cu seed layer 27. The recesses 222C of the Cu pillars 18 are formed by continuing the recesses of the openings 8 in the surface protective film 23.

[0130] 18L, a first layer 24 (nickel layer) is formed on the Cu columnar bodies 18. The first layer 24 is formed on the upper surfaces of the Cu columnar bodies 18 exposed from the openings 28a of the mask 28. The first layer 24 may be formed by electroless plating.

[0131] Next, referring to Figure 18M, the mask 28 is removed.

[0132] 18N, unnecessary portions of the Cu seed layer 27 are removed. The Cu seed layer 27 may be removed by wet etching. In this process, parts of the Cu columnar bodies 18 are side-etched. Therefore, the side surfaces 222B of the Cu columnar bodies 18 are formed so as to be located more inward than the side surfaces of the first layer 24.

[0133] 18O, unnecessary portions of the barrier layer 17 are removed. The barrier layer 17 may be removed by wet etching.

[0134] Next, referring to FIG. 18P, a spherical second layer 25 (solder layer) is formed on the first layer 24.

[0135] Thereafter, the semiconductor device 20 is flip-bonded to the conductive member 10. Next, the semiconductor device 20 is sealed together with the conductive member 10 by the sealing resin 40. Then, a dicing process is performed on the sealing resin 40, and the semiconductor package A10 is cut out. Through the above processes, the semiconductor package A10 is manufactured.

[0136] As described above, in this semiconductor device 20, the pad electrode layer 51 made of a material having a linear expansion coefficient smaller than that of the Cu electrode layer 49 and the Cu columns 18 is formed between the Cu electrode layer 49 and the Cu columns 18. More specifically, the pad electrode layer 51 has a laminated structure of a first layer 54 made of a nickel layer and a second layer 55 made of a palladium layer. This makes it possible to alleviate stress that occurs when the semiconductor device 20 is packaged using the Cu columns 18.

[0137] In this regard, the effect of stress relaxation was verified by simulation, and the results are shown in Figures 19 and 20. Simulation 1 differs from Simulation 2 in the structures of the Cu electrode layer 49 and the pad electrode layer 51.

[0138] More specifically, in Simulation 1, a Cu electrode layer 49 (7.25 μm thick) and a pad electrode layer 51 (0 μm thick, i.e., no pad electrode layer) were used, while in Simulation 2, a Cu electrode layer 49 (4 μm thick), a nickel layer 54 (3 μm thick), and a palladium layer 55 (0.25 μm thick) were used.

[0139] Then, the von Mises stress acting on the third electrode layer 16 (aluminum in the simulation), which is the top-layer wiring, and the von Mises stress acting on the passivation film 2 (SiN film in the simulation) were simulated and verified. As a result, with the structure of Simulation 2, the von Mises stress acting on the third electrode layer 16 (aluminum) was reduced by about 1% (FIG. 19), and the von Mises stress acting on the passivation film 2 (SiN) was reduced by about 6% (FIG. 20). From the above, it was found that with the structure of the semiconductor device 20 described above, the stress generated when packaging the semiconductor device 20 using the Cu pillars 18 can be alleviated.

[0140] In particular, when the semiconductor device 20 is flip-chip mounted on the conductive member 10, stress is applied from the Cu pillars 18 and the conductive member 10, so this is particularly effective for a package for flip-chip mounting. This makes it possible to provide a semiconductor package A10 with excellent reliability.

[0141] Although the embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0142] For example, in the above-described embodiment, only the form in which the semiconductor device 20 is flip-chip bonded is shown, but the semiconductor device 20 may also be bonded by bonding the back surface of the semiconductor substrate 211 to the conductive member 10, and bonding the pad electrode layer 51 and each lead of the conductive member 10 by wire bonding.

[0143] In addition, various design modifications can be made within the scope of the claims. [Explanation of symbols]

[0144] A10 Semiconductor Package 2 Passivation film 3. Element formation surface 10 Conductive material 18 Cu column 20 Semiconductor Devices 23 Surface protective film 24 1st layer 25 2nd layer 30 Bonding layer 40 Sealing resin 48 Barrier electrode layer 49 Cu electrode layer 49a Top side 49b Bottom side 49c side 51 Pad electrode layer 54 1st layer 55 2nd layer 101 Main surface 102 Back side 211 Semiconductor substrate 212 Semiconductor layer 221 Base 222 Columnar part

Claims

1. a semiconductor layer having a first surface; a first insulating layer formed on the first surface of the semiconductor layer; a conductive layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer and covering the conductive layer; Cu columnar bodies extending in a thickness direction, formed above the conductive layer and the second insulating layer, made of a material containing Cu as a main component, and electrically connected to the conductive layer; a recessed portion is formed in one end face of the Cu columnar body, the recessed portion having a plurality of side faces spaced apart from one another, the plurality of side faces extending upward in a convex arc shape in cross-sectional view.

2. The semiconductor device further includes a bonding layer formed on the Cu pillars and used for external connection; The semiconductor device according to claim 1 , wherein said bonding layer has a plurality of first portions facing each of said side surfaces of said recessed portion.

3. The semiconductor device according to claim 2 , wherein the plurality of first portions of the bonding layer extend upward in a convex arc shape in a cross-sectional view.

4. The semiconductor device according to claim 3 , wherein the bonding layer is located outside the Cu columnar bodies in the plurality of first portions.

5. the bonding layer includes a first layer formed on the Cu columnar bodies and made of a metal containing Ni as a main component, and a second layer formed on the first layer and made of a metal containing solder as a main component, The semiconductor device according to claim 2 , wherein said second layer is used for external connection.

6. 6. The semiconductor device according to claim 5, wherein said first layer has a plurality of second portions facing each of said plurality of side surfaces of said recessed portion.

7. 7. The semiconductor device according to claim 6, wherein said second portions of said first layer extend upward in a convex arc shape in cross section.

8. The semiconductor device according to claim 7 , wherein said bonding layer is located outside said Cu columnar bodies in said plurality of second portions.

9. 9. The semiconductor device according to claim 2, wherein the bonding layer is an external bonding layer used for flip-chip bonding.

10. the second insulating layer has an opening that exposes a portion of the conductive layer; the Cu pillars are electrically connected to the conductive layer through the openings; 10. The semiconductor device according to claim 1, wherein said opening includes an opening portion formed in the other end face of said Cu pillar-shaped body and extending upward in a convex arc shape.

11. 11. The semiconductor device according to claim 1, further comprising an intermediate layer formed between said conductive layer and said Cu columnar body, said intermediate layer being made of a material having a linear expansion coefficient smaller than that of said conductive layer and said Cu columnar body.

12. the Cu pillars have a height in a first direction, which is a thickness direction of the semiconductor layer, and a width in a second direction orthogonal to the first direction; 12. The semiconductor device according to claim 1, wherein the height is greater than the width.

13. 13. The semiconductor device according to claim 1, wherein said conductive layer has a width greater than that of said Cu columnar body in a cross-sectional view.

14. 14. The semiconductor device according to claim 1, wherein the thickness of said Cu columnar body is greater than the thickness of said conductive layer in a cross-sectional view.

15. 15. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the thickness of said second insulating layer is greater than the thickness of said conductive layer.

16. 16. The semiconductor device according to claim 1, wherein the conductive layer includes a Cu conductive layer.

17. 17. The semiconductor device according to claim 1, wherein, in a cross-sectional view, said recessed portion has a bottom surface formed integrally with a plurality of said side surfaces.

18. a conductive member having a first surface and a second surface opposite the first surface; The semiconductor device according to any one of claims 1 to 17, which is flip-chip bonded to the first surface of the conductive member; A semiconductor package including a sealing resin that covers a portion of the conductive member and the semiconductor device.

19. a conductive member having a first surface and a second surface opposite the first surface; a semiconductor device according to any one of claims 1 to 17, which is mounted on the first surface of the conductive member and in which the Cu pillar-shaped bodies are connected to the first surface of the conductive member; A semiconductor package including a sealing resin that covers a portion of the conductive member and the semiconductor device.

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