Memory circuit

Abstract

To provide a memory circuit to read data stored in a non-volatile memory accurately.SOLUTION: A memory circuit includes: first and second transistors (M1, M2), each of which is configured by a MOSFET and has different gate threshold voltage; first and second nodes (ND1, ND2) provided on drain current paths of the first and second transistors; a charge supply circuit (20) that supplies a common initial voltage to the first and second nodes by supplying a charging electrical charge to the first and second nodes; a voltage supply circuit (31) for read configured to supply a read voltage (VRD) that gradually rises from a voltage lower than each gate threshold voltage of the first and second transistors to each gate of the first and second transistors in a state where the charging electrical charge is stopped to supply after supplying the initial voltage; and a data output circuit (40) that outputs a data signal (Dout) according to the difference between the voltage fluctuations at each node during the supply period of the voltage for read.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to memory circuits. [Background technology]

[0002] BACKGROUND ART There is a memory circuit in which a memory cell is formed by two transistors, and data is stored in a nonvolatile manner by utilizing the difference in gate threshold voltage between the two transistors (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 74967

[0004] [overview] In this type of memory circuit, various error factors, including manufacturing variations, can sometimes prevent correct data reading.

[0005] a first node provided on a path of a drain current of the first transistor; a second node provided on a path of a drain current of the second transistor; a charge supply circuit configured to supply a common initial voltage to the first node and the second node by supplying a charge to the first node and the second node; a read voltage supply circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, the read voltage gradually increasing from a voltage lower than the gate threshold voltages of the first transistor and the second transistor after the initial voltage is supplied to the first node and the second node and the supply of the charge is cut off; and a data output circuit configured to output a data signal corresponding to a difference between a voltage fluctuation at the first node and a voltage fluctuation at the second node during a supply period of the read voltage. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of a memory circuit according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating the relationship of some voltages and signals associated with a memory circuit according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing the state of the memory circuit during a precharge period according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing the state of the memory circuit during a read period according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a waveform diagram of a read voltage according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a voltage waveform diagram during a precharge period and a read period in a first case according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a voltage waveform diagram during the precharge period and the read period in the second case according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing the relationship between the read voltage and two drain currents in the first case according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the relationship between the read voltage and two drain currents in the second case according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram showing the relationship between the read voltage and two drain currents according to the reference method. [Figure 11] FIG. 11 is a modified configuration diagram of a memory circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field-effect transistor), such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Additionally, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source.

[0010] The electrical characteristics of a MOSFET include the gate threshold voltage. For any transistor that is an N-channel and enhancement-mode MOSFET, when the gate potential of the transistor is higher than the source potential of the transistor and the magnitude of the gate-source voltage (gate potential as seen from the source potential) of the transistor is greater than or equal to the gate threshold voltage of the transistor, the transistor is in the on state; otherwise, the transistor is in the off state. For any FET, the gate threshold voltage is defined as the gate-source voltage required to pass a drain current of a predetermined magnitude when a predetermined voltage is applied between the drain and source of the FET under a predetermined ambient temperature environment.

[0011] Any switch can be composed of one or more FETs (field effect transistors). When a certain switch is in the on state, the two ends of the switch are conductive, while when a certain switch is in the off state, the two ends of the switch are non-conductive. Hereinafter, for any transistor or switch, the on state and the off state may sometimes be simply expressed as on and off.

[0012] Regarding the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., unless otherwise specified, it may be understood to refer to an electrical connection. When any two voltages to be compared are v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other equations including physical quantities other than voltage.

[0013] FIG. 1 shows the configuration of a memory circuit 1 according to an embodiment of the present disclosure. The memory circuit 1 is a non-volatile memory that stores 1-bit data, and includes a memory cell 10, a charge supply circuit 20, a drive circuit 30, a data output circuit 40, and a control circuit 50. The memory circuit 1 may be composed of a semiconductor integrated circuit.

[0014] One bit of data can be stored in the memory cell 10. Under the control of the control circuit 50, the memory circuit 1 can perform a program operation (write operation) for storing desired data (value) in the memory cell 10 and a read operation for reading the data stored in the memory cell 10.

[0015] The memory cell 10 includes memory elements M1 and M2, and stores data "0" or "1" in a nonvolatile manner in the memory cell 10. Each of the memory elements M1 and M2 is a transistor. Therefore, hereinafter, the memory element M1 will be referred to as the transistor M1, and the memory element M2 will be referred to as the transistor M2. Each of the transistors M1 and M2 is configured as an N-channel MOSFET.

[0016] The sources of the transistors M1 and M2 are commonly connected to a source wiring SL. A specific potential is applied to the source wiring SL. The potential of the source wiring SL may be fixed to the ground potential. The gates of the transistors M1 and M2 are commonly connected to a gate wiring GL. The drain of the transistor M1 is connected to a drain wiring DL1, and the drain of the transistor M2 is connected to a drain wiring DL2.

[0017] A node ND1 is provided on the drain wiring DL1, and a node ND2 is provided on the drain wiring DL2. That is, the drain of transistor M1 is connected to node ND1 via drain wiring DL1, and the drain of transistor M2 is connected to node ND2 via drain wiring DL2. In the memory circuit 1 of FIG. 1, no other element is provided between the drain of transistor M1 and node ND1 (i.e., the drain of transistor M1 is directly connected to node ND1), but other elements may be provided between the drain of transistor M1 and node ND1. Similarly, in the memory circuit 1 of FIG. 1, no other element is provided between the drain of transistor M2 and node ND2 (i.e., the drain of transistor M2 is directly connected to node ND2), but other elements may be provided between the drain of transistor M2 and node ND2.

[0018] In either case, when a drain current flows through transistor M1, node ND1 is located on the path of the drain current of transistor M1, and when a drain current flows through transistor M2, node ND2 is located on the path of the drain current of transistor M2. The voltage at node ND1 is referred to as voltage V1, and the voltage at node ND2 is referred to as voltage V2.

[0019] The charge supply circuit 20 includes switches SW1 and SW2. First terminals of the switches SW1 and SW2 are connected to a terminal to which a power supply voltage VDD is applied and are supplied with the power supply voltage VDD. The power supply voltage VDD is a positive DC voltage. A second terminal of the switch SW1 is connected to a node ND1, and a second terminal of the switch SW2 is connected to a node ND2. That is, the switch SW1 is inserted in series between the terminal to which the power supply voltage VDD is applied and the node ND1, and the switch SW2 is inserted in series between the terminal to which the power supply voltage VDD is applied and the node ND2.

[0020] The drive circuit 30 is connected to the gate line GL and supplies the necessary voltage to the gate line GL. The voltage on the gate line GL is supplied to the gates of the transistors M1 and M2 as the gate voltages of the transistors M1 and M2. Therefore, the drive circuit 30 supplies the gate voltages to the gates of the transistors M1 and M2. The drive circuit 30 is also connected to the source line SL. The drive circuit 30 may have a function to control the voltage of the source line SL. The drive circuit 30 includes a read voltage supply circuit 31 and a program circuit 32. As will be described in detail later, a read operation is realized using the read voltage supply circuit 31, and a program operation is realized using the program circuit 32.

[0021] The data output circuit 40 includes a sense amplifier 41 and a latch circuit 42. The data output circuit 40 operates significantly only during a read operation, and the operation of the data output circuit 40 may be stopped under the control of the control circuit 50 during a period when a read operation is not being performed.

[0022] The sense amplifier 41 includes a non-inverting input terminal connected to the node ND1, an inverting input terminal connected to the node ND2, and an output terminal. The sense amplifier 41 outputs, as a sense signal Sout, a signal obtained by amplifying the difference between the voltage V1 at the node ND1 and the voltage V2 at the node ND2 from its output terminal. The sense signal Sout has a potential corresponding to the high-low relationship between the voltages V1 and V2. The amplification factor in the sense amplifier 41 is sufficiently large, and when there is a significant difference between the voltages V1 and V2, the sense signal Sout has either a high-level or low-level signal level. Specifically, when "V1 > V2" (i.e., when the voltage V1 is higher than the voltage V2), the sense signal Sout has a high-level signal level, and when "V1 < V2" (i.e., when the voltage V2 is higher than the voltage V1), the sense signal Sout has a low-level signal level. The sense amplifier 41 may be a comparator.

[0023] The latch circuit 42 latches the sense signal Sout output from the sense amplifier 41 at the latch timing set by the control circuit 50 and outputs the latched signal as a data signal Dout. Figure 2 summarizes the relationships between several voltages and signals related to the memory circuit 1. The data signal Dout is a 1-bit digital signal having a value of "0" or "1." Here, a high-level sense signal Sout has a value of "1," and a low-level sense signal Sout has a value of "0." In the first case, the sense signal Sout has a high signal level at the latch timing, latching a value of "1" in the latch circuit 42 and outputting a data signal Dout of "1." Conversely, in the second case, the sense signal Sout has a low signal level at the latch timing, latching a value of "0" in the latch circuit 42 and outputting a data signal Dout of "0." The overall content shown in Figure 2 will become clear from the following explanation. The output of a data signal Dout of "1" from the latch circuit 42 corresponds to the reading of data "1" (data having a value of "1") from the memory cell 10. The output of a data signal Dout of "0" from the latch circuit 42 corresponds to the reading of data "0" (data having a value of "0") from the memory cell 10. Therefore, the latch timing can also be called the data read timing.

[0024] The control circuit 50 comprehensively controls the operation of each component within the memory circuit 1. Specifically, the control circuit 50 controls the on / off states of the switches SW1 and SW2. The control circuit 50 also controls the execution of read and program operations through control of the drive circuit 30. In addition, the control circuit 50 operates the sense amplifier 41 and latch circuit 42 during a read operation, and sets the latch timing described above.

[0025] 1, capacitance C1 is a parasitic capacitance formed between node ND1 and ground. Specifically, the parasitic capacitance formed between node ND1 and ground is a parasitic capacitance formed between the wiring connected to node ND1 and ground. A capacitor may be provided between node ND1 and ground in the memory circuit 1. In this case, capacitance C1 represents the combined capacitance of the parasitic capacitance formed between node ND1 and ground and the capacitor provided between node ND1 and ground.

[0026] 1, capacitance C2 is a parasitic capacitance formed between node ND2 and ground. Specifically, the parasitic capacitance formed between node ND2 and ground is a parasitic capacitance formed between the wiring connected to node ND2 and ground. A capacitor may be provided between node ND2 and ground in the memory circuit 1. In this case, capacitance C2 represents the combined capacitance of the parasitic capacitance formed between node ND2 and ground and the capacitor provided between node ND2 and ground.

[0027] In any case, the capacitances C1 and C2 have the same capacitance value. Here, "same" includes "substantially the same," and strictly speaking, the capacitance values of the capacitances C1 and C2 may be slightly different.

[0028] The transistors M1 and M2 have the same structure. Therefore, in the initial state immediately after the semiconductor integrated circuit including the memory circuit 1 is formed, the transistors M1 and M2 have the same electrical characteristics (and therefore the same gate threshold voltage). When a program operation is performed starting from the initial state, a difference occurs between the gate threshold voltage of the transistor M1 and the gate threshold voltage of the transistor M2. In the program operation, hot carriers are injected into either the transistor M1 or the transistor M2. The program operation is performed by the program circuit 32 under the control of the control circuit 50. The program operation performed by the program circuit 32 may be any one of the following first to fourth program operations. Hereinafter, the gate threshold voltage of the transistor M1 is represented by the symbol "Vth1," and the gate threshold voltage of the transistor M2 is represented by the symbol "Vth2." The gate threshold voltages Vth1 and Vth2 have positive voltage values.

[0029] In the first program operation, the program circuit 32 increases the gate threshold voltage Vth1 of the transistor M1 by injecting hot carriers only into the transistor M1 of the transistors M1 and M2. After the first program operation is performed, "Vth1>Vth2" holds. In the second program operation, the program circuit 32 injects hot carriers only into the transistor M1 of the transistors M1 and M2, thereby decreasing the gate threshold voltage Vth1 of the transistor M1. <Vth2”となる。 In the third program operation, the program circuit 32 increases the gate threshold voltage Vth2 of the transistor M2 by injecting hot carriers only into the transistor M2 out of the transistors M1 and M2. <Vth2”となる。 In the fourth program operation, the program circuit 32 injects hot carriers only into the transistor M2 out of the transistors M1 and M2, thereby decreasing the gate threshold voltage Vth2 of the transistor M2. After the fourth program operation is performed, "Vth1>Vth2" holds.

[0030] Hot carriers are electrons or holes. As a method of injecting hot carriers into the MOSFET, the program circuit 32 can utilize any hot carrier injection method including known methods. Since the method of injecting hot carriers into the MOSFET itself is known, a detailed description thereof will be omitted. The program circuit 32 can inject hot carriers into the transistor M1 by appropriately controlling the drain, source, and gate potentials of the transistor M1 in the first or second program operation. The program circuit 32 can inject hot carriers into the transistor M2 by appropriately controlling the drain, source, and gate potentials of the transistor M2 in the third or fourth program operation.

[0031] For example, when a data write command is input from an external device provided outside the semiconductor device including the memory circuit 1 to the semiconductor device including the memory circuit 1, the control circuit 50 causes the program circuit 32 to execute a program operation. The data write command specifies that either "1" or "0" should be written to the memory cell 10. When it is specified by the data write command that "1" should be written to the memory cell 10, the control circuit 50 causes the program circuit 32 to perform the first or fourth program operation so that "Vth1 > Vth2" after the program operation. Thereafter, if a read operation is performed, a data signal Dout of "1" is output from the latch circuit 42 (see FIG. 2). When it is specified by the data write command that "0" should be written to the memory cell 10, the control circuit 50 causes the program circuit 32 to perform the second or third program operation so that "Vth1 < Vth2" after the program operation. Thereafter, if a read operation is performed, a data signal Dout of "0" is output from the latch circuit 42 (see FIG. 2).

[0032] In this way, in the memory circuit 1, by using the program operations (selectively executing any one of the first to fourth program operations), either the state of "Vth1 > Vth2" or the state of "Vth1 < Vth2" is selectively realized. Hereinafter, in this embodiment, unless otherwise specified, the operation of the memory circuit 1 when either "Vth1 > Vth2" or "Vth1 < Vth2" is realized by executing any one of the first to fourth program operations will be described. The gate threshold voltages Vth1 and Vth2 in the following description are, unless otherwise specified, the gate threshold voltages Vth1 and Vth2 (the gate threshold voltages Vth1 and Vth2 in the read period described later) when the read operation is performed after any one of the first to fourth program operations is executed, and are understood to refer to these.

[0033] In the read operation, the control circuit 50 first sets a precharge period and then sets a read period after the precharge period. In the read operation, based on the magnitude relationship of the drain currents of the transistors M1 and M2 in the read period, the data stored in the memory cell 10 is read out.

[0034] FIG. 3 and FIG. 4 show the voltage or current states in the precharge period and the read period. The setting and application of the voltages of each part in the precharge period and the read period are executed under the control of the control circuit 50.

[0035] As shown in FIG. 3, during the precharge period, the drive circuit 30 sets the voltage of the source line SL to 0V and the voltage of each gate of transistors M1 and M2 to 0V. That is, during the precharge period, the drive circuit 30 sets the gate-source voltage of each of transistors M1 and M2 to 0V, thereby keeping transistors M1 and M2 in the off state. Meanwhile, during the precharge period, the control circuit 50 keeps switches SW1 and SW2 in the off state. Therefore, during the precharge period, charge is supplied to capacitor C1 from the application terminal of the power supply voltage VDD through switch SW1, thereby charging capacitor C1, and charge is supplied to capacitor C2 from the application terminal of the power supply voltage VDD through switch SW2, thereby charging capacitor C2. As a result, "V1 = V2 = VDD" holds true shortly after the start of the precharge period. The length of the precharge period is set so that "V1 = V2 = VDD" holds true at the end of the precharge period.

[0036] In this way, the charge supply circuit 20 applies a common initial voltage (here, the power supply voltage VDD) to the nodes ND1 and ND2 by supplying charge to the nodes ND1 and ND2 during the precharge period (in other words, by supplying charge to the capacitors C1 and C2). Note that, as long as "V1=V2=VDD" is not prevented from being satisfied during the precharge period, the gate-source voltages of the transistors M1 and M2 may deviate slightly from 0 V during the precharge period.

[0037] After the precharge period, as shown in FIG. 4, a read voltage V is applied to the gates of the transistors M1 and M2. RD The read period begins when the read voltage V RD is supplied to the gates of the transistors M1 and M2 from the read voltage supply circuit 31. During the read period, the voltage of the source line SL is set to 0V by the drive circuit 30 (for example, by the read voltage supply circuit 31). Therefore, during the read period, the read voltage V RDis the gate-source voltage of transistor M1 and the gate-source voltage of transistor M2. During the read period, under the control of the control circuit 50, the charge supply circuit 20 keeps the switches SW1 and SW2 in the off state. That is, during the read period, the supply of the charge to nodes ND1 and ND2 is cut off.

[0038] The drain currents of the transistors M1 and M2 during the read period are respectively represented by the symbol "I D1 ", "I D2 During the read period, the input impedances of the charge supply circuit 20 and the sense amplifier 41 seen from the node ND1 and the input impedances of the charge supply circuit 20 and the sense amplifier 41 seen from the node ND2 are sufficiently high. As a result, during the read period, the drain current I D1 The voltage V1 drops only when D2 The voltage V2 drops only when

[0039] Figure 5 shows the lead voltage V RD During the read period, the read voltage supply circuit 31 supplies the read voltage V RD The starting voltage V S to a given end voltage V E Therefore, "V S <V E " is established. The starting voltage V S It can be 0V or it can be slightly different from 0V. However, the start voltage V S is lower than both of the gate threshold voltages Vth1 and Vth2. The gate threshold voltages Vth1 and Vth2 here are the gate threshold voltages Vth1 and Vth2 at the time when the read operation is performed (i.e., the gate threshold voltages Vth1 and Vth2 during the read period). Therefore, when it is considered that a program operation is performed before the read operation is performed, the start voltage V is lower than the gate threshold voltages Vth1 and Vth2 after the program operation is performed. Sis low. Incidentally, as will be described in detail later, the timings Ta, Tb, and Tc shown in FIG. 5 represent candidates for latch timings.

[0040] End voltage V E shall be higher than both of the gate threshold voltages Vth1 and Vth2. That is, even when the gate threshold voltages Vth1 and Vth2 in the lead period satisfy either "Vth1 > Vth2" or "Vth1 < Vth2", "Vth1 < V E " and "Vth2 < V E ". However, as a variation, the end voltage V E may be higher than only one of the gate threshold voltages Vth1 and Vth2. That is, when the gate threshold voltages Vth1 and Vth2 in the lead period satisfy "Vth1 > Vth2", it may be "Vth1 > V E > Vth2", and when the gate threshold voltages Vth1 and Vth2 in the lead period satisfy "Vth1 < Vth2", it may be "Vth1 < V E < Vth2". As still another variation, the end voltage V E may be lower than both of the gate threshold voltages Vth1 and Vth2.

[0041] During the lead period, the drain current I D1 flows, causing the voltage V1 to gradually decrease from the initial voltage (VDD). Similarly, during the lead period, the drain current I D2 flows, causing the voltage V2 to gradually decrease from the initial voltage (VDD). When the lead voltage V RD is lower than the gate threshold voltage Vth1 of the transistor M1, the drain current I D1 does not completely become zero, and a certain amount of drain current I RD flows according to the lead voltage V D1 . That is, for example, even when the lead voltage V RD is lower than the gate threshold voltage Vth1 of the transistor M1, a drain current I D1 flows through the transistor M1 due to subthreshold conduction. The same applies to the transistor M2.

[0042] Fig. 6 schematically shows waveforms of voltages V1 and V2 during the pre-charge period and the lead period in the first case. The first case is a case where "Vth1 > Vth2" holds during the lead period (see Fig. 2). In the first case, since "Vth1 > Vth2", "I D1 <I D2 " holds at least in the latter half of the lead period. Immediately after the start of the lead period according to the first case, a period where "I D1 >I D2 " may occur for a temporary and short time, but the difference between the drain currents I D1 and I D2 is slight. Therefore, in the first case, when at least a certain time has elapsed from the start of the lead period, the voltage V2 becomes significantly lower than the voltage V1.

[0043] Fig. 7 schematically shows waveforms of voltages V1 and V2 during the pre-charge period and the lead period in the second case. The second case is a case where "Vth1 < Vth2" holds during the lead period (see Fig. 2). In the second case, since "Vth1 < Vth2", "I D1 >I D2 " holds at least in the latter half of the lead period. Immediately after the start of the lead period according to the second case, a period where "I D1 <I D2 " may occur for a temporary and short time, but the difference between the drain currents I D1 and I D2 is slight. Therefore, in the second case, when at least a certain time has elapsed from the start of the lead period, the voltage V1 becomes significantly lower than the voltage V2.

[0044] Fig. 8 shows the standard relationship between the lead voltage V RD and the drain currents I D1 and I D2 in the first case. Fig. 9 shows the standard relationship between the lead voltage V RD and the drain currents I D1 and I D2The reason why it is called "standard" here is that the read voltage V RD and the drain current I D1 and I D2 In a read operation, the sense amplifier 41 compares the voltages V1 and V2 to generate a data signal Dout, but the drain current I D1 and I D2 The drain current I D1 and I D2 When the drain current I D1 and I D2 This can be a factor in reducing the difference between the two (i.e., a factor in generating an erroneous data signal Dout).

[0045] A constant gate voltage V during the lead period CNST to the gates of the transistors M1 and M2. FIG. 10 shows the application of the reference method to the first case. However, in the reference method, even though a program operation is performed to store data "1" in the memory cell 10, the drain current I during the read period may be increased due to the influence of the various variations described above. D1 and I D2 The magnitude relationship between the two is reversed from what it should be, or even if it is not reversed, the drain current I D1 and I D2 If the difference between the gate voltages V and V becomes too small, data "0" may be read from the memory cell 10 (i.e., incorrect data may be read). CNST If the gate voltage V can be optimized, such erroneous data reading can be suppressed. CNST Since the gate voltage V CNST It is also not easy to optimize the system.

[0046] On the other hand, due to the characteristics of the MOSFETs used as transistors M1 and M2, the lead voltage V RD In the process of increasing the voltage from a sufficiently low level, the common lead voltage V RD For the drain current I D1 and I D2 There is a region 610 (see FIG. 10) where the difference between the read voltage V RD and the drain current I D1 and I D2 In the graph showing the relationship between the read voltage V RD If the voltage is increased from a sufficiently low voltage, the lead voltage V RD always crosses the region 610. During the read period, the read voltage V RD The lead voltage V RD By changing the voltage V1, it is possible to reliably set voltage V1 higher than voltage V2 at the latch timing in the first case, despite the above-mentioned variations, and correct data can be read out. The same is true for the second case.

[0047] In view of these, as described above, during the read period, the read voltage supply circuit 31 supplies the read voltage V RD The starting voltage V S to a given end voltage V E During the read period, the read voltage V RD is the end voltage V E , the read voltage supply circuit 31 then supplies the read voltage V RD The end voltage V E During the read period, the read voltage supply circuit 31 supplies the read voltage V RD may be increased linearly as time passes as shown in Figure 5. That is, when the elapsed time from the start time of the read period is represented by Δt, after the start of the read period, the read voltage V RD is the end voltage V E Until it reaches "V RD =V S+k·Δt” holds, where k represents a positive coefficient with voltage as the unit. During the read period, the read voltage supply circuit 31 supplies the read voltage V RD may be increased nonlinearly over time.

[0048] A start voltage V that is lower than both the gate threshold voltages Vth1 and Vth2 S to lead voltage V RD In the process of increasing the read voltage V RD will cross the voltage range corresponding to the region 610. As a result, in the first case, despite the above-mentioned variations, voltage V1 can be reliably and sufficiently higher than voltage V2 at the latch timing, and correct data can be read out. The same is true for the second case.

[0049] Lead voltage V RD During the supply period (i.e., during the lead period), the voltage V1 increases with the passage of time. D1 The voltage V2 decreases in accordance with the drain current I D2 The control circuit 50 sets the timing when a predetermined time has elapsed after the start of the read period as the latch timing, and the latch circuit 42 latches the sense signal Sout at the latch timing to generate and output the data signal Dout. For this reason, the data output circuit 40 generates and outputs the data signal Dout by using the read voltage V RD The voltage fluctuation of node ND1 during the supply period and the lead voltage V RD The control circuit 50 outputs a data signal Dout corresponding to the difference between the voltage fluctuation at node ND2 during the supply period of and the data signal Dout. The control circuit 50 ends the read period after the latch timing. When the read period ends, the drive circuit 30 may fix the voltages of the source line SL and the gate line GL to 0V.

[0050] The voltage V1 at the latch timing is symbolized as "V1 LATCH " and the voltage V2 at the latch timing is represented by the symbol "V2 LATCH Then, the lead voltage V RDThe voltage drop ΔV1 of the voltage V1 from the supply start time to the latch timing is "ΔV1 = VDD - V1 LATCH ", and the voltage drop ΔV2 of the voltage V2 from the supply start time to the latch timing of the lead voltage V RD is expressed as "ΔV2 = VDD - V2 LATCH ". In the first case corresponding to FIG. 6, since "ΔV1 < ΔV2", "V1 > V2" holds at the latch timing (that is, "V1 LATCH > V2 LATCH " holds), and as a result, the data signal Dout of "1" is generated and output (see also FIG. 2). In the second case corresponding to FIG. 7, since "ΔV1 > ΔV2", "V1 < V2" holds at the latch timing (that is, "V1 LATCH < V2 LATCH " holds), and as a result, the data signal Dout of "0" is generated and output (see also FIG. 2).

[0051] The control circuit 50 sets one of the timings Ta, Tb, and Tc shown in FIG. 5 as the latch timing. The timing Ta is the timing during the period when the lead voltage V RD rises from the start voltage V S to the end voltage V E . Therefore, "V S < V RD < V E " holds at the timing Ta. On the other hand, "V RD = V E " holds at the timings Tb and Tc. The timing Tb is the timing when the lead voltage V S ; rising from the start voltage V RD just reaches the end voltage V E . The timing Tc is the timing after the timing Tb by a predetermined time. That is, the timing Tc is the timing after the lead voltage V RD reaches the end voltage V E . Thus, the latch timing is during the rising period of the lead voltage V RD (Ta), at the end point of the rise of the lead voltage V RD (Tb), or after the lead voltage V RDIt may be set after the end of the rise (Tc).

[0052] Read voltage V at latch timing RD may be higher than both the gate threshold voltages Vth1 and Vth2. Alternatively, the read voltage V RD may be higher than only one of the gate threshold voltages Vth1 and Vth2. RD may be lower than both of the gate threshold voltages Vth1 and Vth2.

[0053] The memory circuit 1a of FIG. 11 may be formed by modifying the memory circuit 1 of FIG. 1. The memory circuit 1a of FIG. 11 is obtained by adding transistors M3 and M4 to the memory circuit 1 of FIG. 1. The transistors M3 and M4 are configured as N-channel MOSFETs. Except for the addition of the transistors M3 and M4, the configuration and operation of the memory circuits are the same between the memory circuits 1 and 1a. However, in the memory circuit 1a, with the addition of the transistors M3 and M4, the transistor M3 is cascode-connected to the transistor M1 between the node ND1 and the transistor M1 (in other words, the transistor M3 is inserted in series between the node ND1 and the transistor M1), and the transistor M4 is cascode-connected to the transistor M2 between the node ND2 and the transistor M2 (in other words, the transistor M4 is inserted in series between the node ND2 and the transistor M2). More specifically, in the memory circuit 1a, the drain of the transistor M1 is connected to the source of the transistor M3, the drain of the transistor M3 is connected to a node ND1, the drain of the transistor M2 is connected to the source of the transistor M4, and the drain of the transistor M4 is connected to a node ND2.

[0054] A constant positive DC voltage Vc (VDD > Vc) is applied to the gates of transistors M3 and M4 during at least the read period. In memory circuit 1a, during the read period, the drain current of transistor M1 flows through the channel (drain-source) of transistor M3, and the drain current of transistor M2 flows through the channel (drain-source) of transistor M4. In memory circuit 1a, as in memory circuit 1, node ND1 is located on the path of the drain current of transistor M1, and node ND2 is located on the path of the drain current of transistor M2. In memory circuit 1 of FIG. 1, a difference occurs between the drain-source voltage of transistor M1 and the drain-source voltage of transistor M2 during the read period. This difference may hinder correct data reading due to the difference in gate threshold voltages Vth1 and Vth2. Configuring memory circuit 1a as shown in FIG. 11 can eliminate the difference between the drain-source voltage of transistor M1 and the drain-source voltage of transistor M2 during the read period.

[0055] FIG. 12 shows a schematic configuration of a semiconductor device 100 incorporating the above-described memory circuit 1 or 1a. The semiconductor device 100 has a memory circuit 110 and a functional circuit 120. The semiconductor device 100 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing to the outside of the semiconductor device 100. The semiconductor chip is encapsulated in a housing (package) made of resin to form the semiconductor device 100. The memory circuit 110 and the functional circuit 120 are included in the semiconductor integrated circuit.

[0056] A memory circuit 1 or 1a is provided in the memory circuit 110. In this case, n memory cells 10 are provided for the memory circuit 110. The memory circuit 110 is a nonvolatile memory that stores n bits of data in a nonvolatile manner using the n memory cells 10. Although n may be 1, hereinafter, n will represent an integer of 2 or more. Although n memory circuits 1 or 1a may be provided for the memory circuit 110, some of the components of the memory circuit 1 or 1a shown in FIG. 1 or FIG. 11 may be shared by multiple memory cells 10. That is, for example, a block consisting of the charge supply circuit 20, the drive circuit 30, the data output circuit 40, and the control circuit 50 may be shared by multiple memory cells 10.

[0057] The functional circuit 120 performs a predetermined functional operation to be realized by the semiconductor device 100. For example, if the semiconductor device 100 is a power supply control device for controlling a DC / DC converter that generates an output voltage from an input voltage, the functional circuit 120 stabilizes the output voltage at a desired voltage by controlling the switching of the input voltage based on a feedback voltage corresponding to the output voltage. Alternatively, if the semiconductor device 100 is a motor driver, the functional circuit 120 supplies a three-phase drive voltage to a three-phase motor connected to the semiconductor device 100 so that the motor rotates at a desired rotational speed. Any other functional operation may be performed.

[0058] The memory circuit 110 can store data for adjusting the characteristics of the functional circuit 120. For example, consider a case where an amplifier circuit is provided in the functional circuit 120. Assume that the gain of the amplifier circuit can be adjusted by using a ladder resistor or the like. In this case, data for adjusting the gain (trimming data) is written to the memory circuit 110 using a program operation during the manufacturing process of the semiconductor device 100. After the semiconductor device 100 is shipped, the functional circuit 120 reads the data for adjusting the gain stored in the memory circuit 110 each time the semiconductor device 100 is started up, and determines the gain of the amplifier circuit based on the read data. The memory circuit 110 can also be used in any other way.

[0059] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0060] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0061] A memory circuit (1, 1a) according to one aspect of the present disclosure includes a first transistor (M1) and a second transistor (M2), each configured as a MOSFET and having a different gate threshold voltage from each other; a first node (ND1) provided on a path of a drain current of the first transistor; a second node (ND2) provided on a path of a drain current of the second transistor; a charge supply circuit (20) configured to supply a common initial voltage (VDD) to the first node and the second node by supplying a charge to the first node and the second node; and a read voltage (V) that gradually rises from a voltage lower than the gate threshold voltages of the first transistor and the second transistor when the supply of the charge is cut off after the initial voltage is supplied to the first node and the second node. RD a read voltage supply circuit (31) configured to supply a read voltage to the gates of the first transistor and the second transistor; and a data output circuit (40) configured to output a data signal (Dout) corresponding to the difference between the voltage fluctuation at the first node and the voltage fluctuation at the second node during a supply period of the read voltage (first configuration).

[0062] This facilitates accurate reading of the data stored in the first and second transistors.

[0063] In the memory circuit (1) according to the first configuration, the drain of the first transistor may be connected to the first node, and the drain of the second transistor may be connected to the second node (second configuration).

[0064] The memory circuit (1a) according to the second configuration may further include a third transistor (M3) cascode-connected to the first transistor between the first node and the first transistor, and a fourth transistor (M4) cascode-connected to the second transistor between the second node and the second transistor (third configuration).

[0065] In the memory circuit according to any one of the first to third configurations, the data output circuit may be configured (fourth configuration) to latch a signal according to the high / low relationship between the voltage of the first node and the voltage of the second node during the rising period of the read voltage, at a latch timing (Ta, Tb or Tc) set at the end of the rise of the read voltage or after the rising period of the read voltage, and output the latched signal as the data signal.

[0066] The memory circuit according to any one of the first to fourth configurations may be configured (fifth configuration) to include a program circuit (32) configured to perform a program operation of injecting hot carriers into either the first transistor or the second transistor, and to selectively realize, using the program operation, either a first state in which the gate threshold voltage of the first transistor is higher than the gate threshold voltage of the second transistor, or a second state in which the gate threshold voltage of the second transistor is higher than the gate threshold voltage of the first transistor. [Explanation of symbols]

[0067] 1, 1a Memory circuit 10 memory cells 20 Charge supply circuit 30 Drive circuit 31 Lead voltage supply circuit 32 Program Circuit 40 Data output circuit 41 Sense amplifier 42 Latch circuit 50 Control circuit M1, M2, M3, M4 transistors SL Source wiring GL gate wiring DL1, DL2 drain wiring SW1 and SW2 switches ND1, ND2 nodes V1, V2 voltage VDD power supply voltage V RD Lead Voltage V S Starting Voltage V E End Voltage C1, C2 capacity Sout Sense signal Dout Data signal I D1 , I D2 Drain Current 100 Semiconductor device 110 Memory circuit 120 Functional Circuits

Claims

1. a first transistor and a second transistor, each of which is configured by a MOSFET and has a gate threshold voltage different from each other; a first node provided on a path of a drain current of the first transistor; a second node provided on a path of a drain current of the second transistor; a charge supply circuit configured to supply a common initial voltage to the first node and the second node by supplying charging charges to the first node and the second node; a read voltage supply circuit configured to supply a read voltage, which gradually increases from a voltage lower than a gate threshold voltage of each of the first transistor and the second transistor, to each gate of the first transistor and the second transistor in a state in which the supply of the charged charges is cut off after the initial voltage is applied to the first node and the second node; a data output circuit configured to output a data signal corresponding to a difference between a voltage fluctuation at the first node and a voltage fluctuation at the second node during a supply period of the read voltage. , memory circuits.

2. The drain of the first transistor is connected to the first node, and the drain of the second transistor is connected to the second node.

10. The memory circuit of claim 1.

3. a third transistor cascode-connected to the first transistor between the first node and the first transistor, and a fourth transistor cascode-connected to the second transistor between the second node and the second transistor.

10. The memory circuit of claim 1.

4. The data output circuit latches a signal according to the level relationship between the voltage of the first node and the voltage of the second node at a latch timing set during the rising period of the read voltage, at the end of the rise of the read voltage, or after the rising period of the read voltage, and outputs the latched signal as the data signal.

4. The memory circuit according to claim 1.

5. a program circuit configured to perform a program operation of injecting hot carriers into either the first transistor or the second transistor; Using the program operation, selectively realize either a first state in which the gate threshold voltage of the first transistor is higher than the gate threshold voltage of the second transistor, or a second state in which the gate threshold voltage of the second transistor is higher than the gate threshold voltage of the first transistor.

4. The memory circuit according to claim 1.

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