Semiconductor device and method for manufacturing semiconductor device

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device includes; a field plate electrode FP formed via a first insulating film IF1 in a trench TR formed in a semiconductor substrate SUB; and a gate electrode GE formed over the field plate electrode FP via a second insulating film IF2. The first insulating film IF1 includes a stacked film including a first oxide film IF1a in contact with the semiconductor substrate SUB and a second oxide film IF1b in contact with the field plate electrode FP. The inclination of an upper surface of the first insulating film IF1 changes at a boundary between the first oxide film IF1a and the second oxide film IF1b.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a gate electrode and a field plate electrode inside a trench, and a method for manufacturing the same. [Background technology]

[0002] Semiconductor devices equipped with semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) employ a trench gate structure in which a gate electrode is embedded inside a trench. One type of trench gate structure known as a split gate structure is one in which a field plate electrode is formed at the bottom of the trench and a gate electrode is formed at the top of the trench. A source potential is supplied to the field plate electrode from a source electrode. By expanding the depletion layer in the drift region using this field plate electrode, the drift region can be highly concentrated, thereby enabling the drift region to have a low resistance.

[0003] For example, Patent Document 1 discloses a MOSFET with a split-gate structure. The field plate electrode and gate electrode in Patent Document 1 are formed as follows: First, a field plate electrode is formed inside a trench, and then the upper surface of the field plate electrode is recessed. Next, a gate insulating film is formed inside the trench by thermal oxidation, and an insulating film is formed on the upper surface of the field plate electrode. Next, a gate electrode is formed on the field plate electrode so as to fill the inside of the trench. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-199109 Summary of the Invention [Problem to be solved by the invention]

[0005] In a MOSFET with a split gate structure, as the potential of the field plate electrode (FP potential) increases, the BV DSS (MOSFET breakdown voltage) rises once, and when the FP potential exceeds a certain level, BV DSS There is a problem that BV decreases rapidly as the FP potential increases. DSS In other words, the decline in BV DSS A structure with high robustness is required. DSS In processes that increase BV, the BV is often affected by process variations. DSS Deterioration becomes more likely.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] A semiconductor device according to one embodiment includes a semiconductor substrate having an upper surface and a lower surface, a trench formed in the semiconductor substrate so as to extend from the upper surface toward the lower surface of the semiconductor substrate to a predetermined depth, a first insulating film formed from the bottom surface of the trench to a portion of the side surface, a gate insulating film connected to the first insulating film and formed on the side surface of the trench, a field plate electrode formed in the trench via the first insulating film, a gate electrode formed in the trench via the gate insulating film, and a second insulating film separating the field plate electrode and the gate electrode. The first insulating film includes a stacked film made of a first oxide film in contact with the side surface of the trench and a second oxide film in contact with the field plate electrode, and the slope of the upper surface of the first insulating film connected to the gate insulating film changes at the boundary between the first oxide film and the second oxide film.

[0009] A method for manufacturing a semiconductor device according to one embodiment includes: (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface toward the lower surface of the semiconductor substrate; (c) after the step (b), forming a first insulating film in the trench and on the upper surface of the semiconductor substrate; (d) after the step (c), forming a field plate electrode on the first insulating film so as to fill the trench; and (e) after the step (d), etching the field plate electrode toward the bottom of the trench. (f) after step (e), removing the first insulating film located on the upper surface of the semiconductor substrate by etching and recessing the first insulating film located in the trench toward the bottom of the trench; (g) after step (f), forming a gate insulating film on the upper surface of the semiconductor substrate and in the trench, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film; and (h) after step (g), forming a gate electrode on the gate insulating film, the first insulating film, and the second insulating film so as to fill the trench. Step (c) includes a step of forming a first oxide film in contact with the semiconductor substrate and a step of forming a second oxide film, and in step (d), the field plate electrode is formed so as to be in contact with the second oxide film, and in step (f), the first insulating film located in the trench is recessed toward the bottom of the trench so that the slope of the upper surface of the first insulating film changes at the boundary between the first oxide film and the second oxide film. [Effects of the Invention]

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. [Figure 3]FIG. 3 is a plan view of a main part of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a plan view of a main part of the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing the configuration of the first insulating film of the semiconductor device in the first embodiment. [Figure 7] 7A to 7C are schematic cross-sectional views showing the configurations of the semiconductor device in the first embodiment before and after etching of the first insulating film. [Figure 8] FIG. 8 is a diagram showing the condition settings for simulating how the BVDSS characteristics change depending on the cross-sectional shape of the first oxide film included in the first insulating film. [Figure 9] FIG. 9 is a diagram showing the results of a simulation of how the BVDSS characteristics change depending on the cross-sectional shape of the first oxide film included in the first insulating film. [Figure 10] FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 16] FIG. 16 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 18] FIG. 18 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 21] FIG. 21 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 23] FIG. 23 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing step subsequent to FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Structure of semiconductor device> 1 to 5, a semiconductor device 100 according to a first embodiment will be described below. The semiconductor device 100 includes a MOSFET with a trench gate structure as a semiconductor element. The MOSFET according to the first embodiment has a split gate structure including a gate electrode GE and a field plate electrode FP.

[0015] 1 and 2 are plan views of a semiconductor chip that is a semiconductor device 100. FIGS. 3 and 4 are enlarged plan views of a main portion of region 1A shown in FIGS. 1 and 2. FIGS. 2 and 4 show the structure below FIGS. 1 and 3, and mainly show a trench gate structure formed in a semiconductor substrate SUB. The positions of contact holes CH1, CH2, and CH3 indicated by dashed lines in FIG. 3 coincide with the positions of contact holes CH1, CH2, and CH3 shown in FIG. 4. FIG. 5 is a cross-sectional view taken along lines AA and BB shown in FIGS. 3 and 4.

[0016] 1 shows a wiring pattern formed mainly above a semiconductor substrate SUB. The semiconductor device 100 has a cell region CR and an outer periphery region OR that surrounds the cell region CR in a plan view. Major semiconductor elements such as multiple MOSFETs are formed in the cell region CR. The outer periphery region OR is used to connect gate wiring GW to a gate electrode GE and to function as a termination region.

[0017] As shown in FIGS. 1 and 2, most of the cell region CR is covered with the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE. Although not shown here, the source electrode SE and the gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a portion of the protective film, and the source electrode SE and the gate wiring GW exposed in the opening become the source pad SP and the gate pad GP. By connecting external connection members to the source pad SP and the gate pad GP, the semiconductor device 100 is electrically connected to another semiconductor chip, a lead frame, a wiring board, or the like. The external connection members are, for example, wires made of aluminum, gold, or copper, or clips made of copper plate.

[0018] 4, a plurality of trenches TR are formed in the semiconductor substrate SUB in the cell region CR. The plurality of trenches TR are formed in stripes, each extending in the Y direction, and adjacent to each other in the X direction.

[0019] 5, inside the trench TR, a field plate electrode FP is formed in the lower part of the trench TR, and a gate electrode GE is formed in the upper part of the trench TR. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0020] 5, a part of the field plate electrode FP in the cell region CR forms an extension portion FPa. The field plate electrode FP constituting the extension portion FPa is formed inside the trench TR not only in the lower part of the trench TR but also in the upper part of the trench TR.

[0021] 2, the trenches TR formed in the peripheral region OR extend in the Y and X directions so as to surround the cell region CR in a plan view. A field plate electrode FP constituting an extraction portion FPa is formed inside the trenches TR in the peripheral region OR.

[0022] In the cell region CR, a contact hole CH3 is formed on the lead-out portion FPa. The lead-out portion FPa is electrically connected to the source electrode SE via the contact hole CH3. Furthermore, in the cell region CR, a contact hole CH1 is formed on the body region PB and the source region NS, which will be described later. The body region PB and the source region NS are electrically connected to the source electrode SE via the contact hole CH1. In the outer periphery region OR, a contact hole CH2 is formed on the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW via the contact hole CH2.

[0023] The cross-sectional structure of the semiconductor device 100 will be described below with reference to FIG.

[0024] As shown in FIG. 5, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the semiconductor substrate SUB may be a stacked body of an n-type silicon substrate and an n-type semiconductor layer grown on the n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In this case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0025] An n-type drain region ND is formed in the semiconductor substrate SUB so as to extend from the lower surface BS of the semiconductor substrate SUB to a predetermined depth toward the upper surface TS of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film in which these metal films are appropriately laminated. The drain region ND and the drain electrode DE are formed across the cell region CR and the peripheral region OR. A drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0026] In the semiconductor substrate SUB, a plurality of trenches TR are formed, each extending from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB to a predetermined depth.

[0027] 5, inside the trench TR, a field plate electrode FP is formed via a first insulating film IF1 at the bottom of the trench TR. The position of the upper surface of the first insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

[0028] The first insulating film IF1 includes a first oxide film IF1a in contact with the semiconductor substrate SUB and a second oxide film IF1b in contact with the field plate electrode FP. The slope of the top surface of the first insulating film IF1 in a cross-sectional view changes at the boundary between the first oxide film IF1a and the second oxide film IF1b. In one example, the top surfaces of the first oxide film IF1a and the second oxide film IF1b each have a shape that rises from the field plate electrode FP toward the semiconductor substrate SUB in a cross-sectional view, as shown in FIG. 5 , and the rate of rise of the top surface of the first oxide film IF1a in a cross-sectional view is greater than the rate of rise of the top surface of the second oxide film IF1b in a cross-sectional view. The top surface of the second oxide film IF1b does not necessarily have a shape that rises from the field plate electrode FP toward the semiconductor substrate SUB; for example, it may be flat. The change in slope here may also refer to a change in curvature.

[0029] The gate insulating film GI is formed inside the trench TR on the first insulating film IF1. The second insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the first insulating film IF1. A gate electrode GE is formed on the field plate electrode FP via the second insulating film IF2. The field plate electrode FP and the gate electrode GE are each made of, for example, a polycrystalline silicon film doped with n-type impurities. The impurity concentration of this polycrystalline silicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0030] A part of the gate electrode GE is also formed in a space between the field plate electrode FP and the semiconductor substrate SUB and surrounded by the first insulating film IF1, the second insulating film IF2, and the gate insulating film GI.

[0031] The first insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. The second insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. These films electrically insulate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from one another.

[0032] For example, the etching rate of the second oxide film IF1b in the first insulating film IF1 is higher than that of the first oxide film IF1a with respect to a predetermined etching solution such as BHF (Buffered Hydrofluoric Acid), DHF (Dilute Hydrofluoric Acid), or vapor-phase hydrofluoric acid. In one example, the first oxide film IF1a is made of a dry oxide film (silicon oxide film) formed by thermal oxidation treatment of a silicon substrate, and the second oxide film IF1b is made of an LPCVD-TEOS film formed by depositing a silicon oxide film on the first oxide film IF1a using TEOS (Tetra Ethoxy Silane) as a raw material in an LPCVD (Low-Pressure Chemical Vapor Deposition) apparatus. The second insulating film IF2 and the gate insulating film GI are made of, for example, silicon oxide films.

[0033] A p-type body region PB is formed in the semiconductor substrate SUB, extending from an upper surface TS of the semiconductor substrate SUB to a predetermined depth toward a lower surface BS of the semiconductor substrate SUB. The depth of the body region PB from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR from the upper surface TS of the semiconductor substrate SUB. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0034] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0035] A contact hole CH1 is formed in the interlayer insulating film IL, penetrating the interlayer insulating film IL and the source region NS and reaching the body region PB. A high-concentration diffusion region PR is formed in the body region PB at the bottom of the contact hole CH1. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. The high-concentration diffusion region PR is provided mainly to reduce contact resistance with the plug PG and to prevent latch-up.

[0036] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the heavily doped diffusion region PR via a contact hole CH1, and supplies a source potential to these impurity regions.

[0037] 5, a part of the field plate electrode FP forms an extension portion FPa of the field plate electrode FP. The position of the upper surface of the first insulating film IF1 in contact with the extension portion FPa is higher than the position of the upper surface of the first insulating film IF1 in contact with the field plate electrode FP other than the extension portion FPa.

[0038] The second insulating film IF2 is formed so as to cover the drawn portion FPa exposed from the first insulating film IF1. Further, the body region PB is formed in the semiconductor substrate SUB adjacent to the drawn portion FPa, but the source region NS is not formed in this body region PB.

[0039] A contact hole CH3 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and reaches the lead portion FPa. The source electrode SE is electrically connected to the lead portion FPa through the contact hole CH3, and supplies a source potential to the field plate electrode FP.

[0040] Although not shown here, a contact hole CH2 is formed in the interlayer insulating film IL, which penetrates the interlayer insulating film IL and reaches the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE through the contact hole CH2 and supplies a gate potential to the gate electrode GE.

[0041] A plug PG is buried inside each of the contact holes CH1, CH2, and CH3. The plug PG is made of, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film is made of, for example, a stacked film of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film.

[0042] The source electrode SE and the gate wiring GW are made of, for example, a second barrier metal film and a second conductive film formed on the second barrier metal film. The second barrier metal film is, for example, a titanium tungsten film. The second conductive film is, for example, an aluminum alloy film doped with copper or silicon.

[0043] <Features of the First Embodiment> 6 is a schematic cross-sectional view showing the configuration of the first insulating film IF1 of the semiconductor device 100 according to the first embodiment. Since the upper surface of the first oxide film IF1a included in the first insulating film IF1 is inclined, the electric field near point A at the end of the upper surface of the first oxide film IF1a on the semiconductor substrate SUB side is relaxed, and the BV DSS It is believed that this will improve the robustness of the system.

[0044] FIG. 7 is a schematic cross-sectional view showing the structure of the semiconductor device 100 according to the first embodiment before and after etching of the first insulating film IF1. If the etching rate of the first oxide film IF1a is ER1=V1 (micrometers / second) and the etching rate of the second oxide film IF1b is ER2=V2 (micrometers / second), then after t seconds of etching, when V2>V1, φ<θ. This configuration reduces the electric field near point A in FIG. 6, as described above. Examples of combinations of an etchant, first oxide film IF1a, and second oxide film IF1b that satisfy V2>V1 include a combination of BHF, DHF, or vapor-phase hydrofluoric acid as the etchant, the first oxide film IF1a being the aforementioned dry oxide film, and the second oxide film IF1b being an LPCVD-TEOS film. However, the combinations are not limited to these, and the first oxide film IF1a may alternatively be a wet oxide film.

[0045] FIG. 8 shows the relationship between the BV and the cross-sectional shape of the first oxide film IF1a included in the first insulating film IF1. DSS 8 is a diagram showing the condition settings for simulating how the characteristics change (the X direction in FIG. 8 corresponds to the Z direction in FIG. 5, and the Y direction in FIG. 8 corresponds to the X direction in FIG. 5). The angle a (degrees) and height h (arbitrary unit) of the top surface of the first oxide film IF1a are changed, and the BV with respect to the change in the field plate potential Vfp (V) is calculated. DSS By calculating the change in BV DSS A simulation was performed to evaluate the robustness of the first insulating film IF1. DSS 9 is a graph showing the results of a simulation of how the characteristics change. In the graph of FIG. 9, the horizontal axis represents the field plate potential Vfp (V), and the vertical axis represents BV DSS(V). From the simulation results, it can be seen that the angle a is preferably 40 degrees or more and 60 degrees or less. Although the upper surface of the first oxide film IF1a actually formed does not necessarily have a linear shape in cross section as shown in FIG. 8, including the case where the upper surface of the first oxide film IF1a has a curved shape in cross section, it is considered that the average rising angle of the upper surface of the first oxide film IF1a in cross section (which can be expressed as arctan(h / w) in FIG. 8 using the width w of the first oxide film and the height h of the first oxide film) is preferably 40 degrees or more and 60 degrees or less.

[0046] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device 100 will be described below with reference to FIGS.

[0047] 10, first, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by epitaxial growth.

[0048] Next, for example, a silicon oxide film is formed on the semiconductor substrate SUB by a film formation process using, for example, a CVD (Chemical Vapor Deposition) method. Next, the silicon oxide film is patterned by photolithography and anisotropic etching to form a hard mask HM. Next, an anisotropic etching process is performed using the hard mask HM as a mask to form a trench TR in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by isotropic etching using, for example, a solution containing hydrofluoric acid.

[0049] 11, first, a first insulating film IF1 including a first oxide film IF1a and a second oxide film IF1b is formed inside the trench TR and on the upper surface TS of the semiconductor substrate SUB. The first oxide film IF1a is a dry oxide film (silicon oxide film) formed by, for example, thermal oxidation. The second oxide film IF1b is an LPCVD-TEOS film formed by depositing a silicon oxide film on the first oxide film IF1a using, for example, TEOS (Tetra Ethoxy Silane) as a raw material in an LPCVD (Low-Pressure Chemical Vapor Deposition) apparatus.

[0050] Next, a conductive film CF1 is formed on the first insulating film IF1 by a film formation process using, for example, a CVD method. The conductive film CF1 is, for example, an n-type polycrystalline silicon film.

[0051] As shown in FIG. 12, the thickness of the conductive film CF1 located inside the trench TR is reduced and the conductive film CF1 located outside the trench TR is removed by etching.

[0052] As shown in FIG. 13, a conductive film CF2 is formed on the first insulating film IF1 and the conductive film CF1 by a film formation process using, for example, a CVD method so as to fill the inside of the trench TR. The conductive film CF2 is also formed on the first insulating film IF1 outside the trench TR. The conductive film CF2 is, for example, an n-type polycrystalline silicon film. In the manufacturing process of FIG. 12, the thickness of the conductive film CF1 decreases toward the top of the trench TR. Therefore, the conductive film CF2 can be formed with a lower aspect ratio than when the conductive film CF1 is not formed. This makes it easier to fill the inside of the trench TR with the conductive film CF2.

[0053] 14, the conductive film CF2 located outside the trench TR is removed by polishing using, for example, CMP (Chemical Mechanical Polishing) so that the conductive films CF1 and CF2 remain inside the trench TR. The conductive films CF1 and CF2 left inside the trench TR constitute a field plate electrode FP. In this way, the field plate electrode FP is formed on the first insulating film IF1 so as to fill the inside of the trench TR.

[0054] The field plate electrode FP can also be formed using only the conductive film CF2. In this case, the conductive film CF1 is not formed, and the conductive film CF2 is formed on the first insulating film IF1 so as to fill the inside of the trench TR. The conductive film CF2 located outside the trench TR is removed so that the conductive film CF2 remains inside the trench TR. The conductive film CF2 left inside the trench TR constitutes the field plate electrode FP. In this case, the manufacturing process can be simplified compared to when the field plate electrode FP is formed using the conductive films CF1 and CF2.

[0055] However, from the viewpoint of properly embedding the conductive film CF2 inside the trench TR, it is preferable to form a conductive film CF1 processed into a sidewall shape in advance inside the trench TR, as described in Figures 12 to 14.

[0056] As shown in FIG. 15, a portion of the field plate electrode FP is selectively recessed so that the other portion of the field plate electrode FP remains as an extraction portion FPa.

[0057] Specifically, first, as shown in the BB cross section of Figure 15, a resist pattern RP1 is formed to selectively cover a portion of the field plate electrode FP that will become the lead portion FPa. Next, using the resist pattern RP1 as a mask, an etching process (etch-back process) such as dry etching or plasma etching using SF6 gas is performed on the other portion of the field plate electrode FP that will not become the lead portion FPa. That is, as shown in the AA cross section of Figure 15, the other portion of the field plate electrode FP that is exposed from the resist pattern RP1 is selectively set back toward the bottom of the trench TR. The portion of the field plate electrode FP that is not set back becomes the lead portion FPa.

[0058] Although not shown here, the upper surface of the field plate electrode FP is subjected to an etching process (smoothing process) and a thermal oxidation process, thereby rounding the upper portion of the field plate electrode FP.

[0059] As shown in FIG. 16, in one example, the first insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB is removed by an isotropic etching process using a solution containing hydrofluoric acid. At the same time, the first insulating film IF1 located inside the trench TR is recessed toward the bottom of the trench TR so that the position of the upper surface of the first insulating film IF1 located inside the trench TR is lower than the position of the upper surface of the field plate electrode FP in a cross-sectional view. By selecting a combination of the etching solution, first oxide film IF1a, and second oxide film IF1b that satisfies the conditions described with reference to FIG. 7, a structure in which the upper surface of the first oxide film IF1a is inclined can be obtained, as shown in FIG. 16. At the end of the isotropic etching process, the upper surface of the first oxide film IF1a rises as it approaches the semiconductor substrate SUB.

[0060] As shown in FIG. 17, a gate insulating film GI is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR located on the first insulating film IF1 by thermal oxidation treatment, and a second insulating film IF2 is formed so as to cover the field plate electrode FP exposed from the first insulating film IF1.

[0061] 18, a conductive film CF3 is formed on the gate insulating film GI, the second insulating film IF2, and the first insulating film IF1 by a film formation process using, for example, a CVD method so as to fill the inside of the trench TR. The conductive film CF3 is, for example, an n-type polycrystalline silicon film.

[0062] As shown in FIG. 19, first, the conductive film CF3 is polished using the CMP method. This reduces the thickness of the conductive film CF3 and flattens the upper surface of the conductive film CF3. Next, the conductive film CF3 is anisotropically etched to remove the conductive film CF3 located outside the trench TR. As a result, as shown in the AA cross section of FIG. 19, the conductive film CF3 remaining inside the trench TR on the field plate electrode FP is formed as the gate electrode GE.

[0063] In order to completely remove the conductive film CF3 located outside the trench TR, the anisotropic etching process is performed by over-etching. Therefore, as shown in the AA cross section of Fig. 19, the position of the upper surface of the gate electrode GE is lower than the position of the upper surface TS of the semiconductor substrate SUB. Furthermore, as shown in the BB cross section of Fig. 19, the anisotropic etching process removes the conductive film CF3 formed on the first insulating film IF1 and the second insulating film IF2 that are in contact with the drawn-out portion FPa.

[0064] As shown in FIG. 20, a third insulating film IF3 is formed on the gate insulating film GI, the gate electrode GE, the second insulating film IF2, and the first insulating film IF1 by a film formation process using, for example, a CVD method so as to cover the trench TR.

[0065] 21, an anisotropic etching process is performed on the third insulating film IF3. As a result, the third insulating film IF3 and the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB, and the second insulating film IF2 on the field plate electrode FP are removed. Also, as shown in FIG. 21, the third insulating film IF3 is left on a part of the gate electrode GE and on the first insulating film IF1 in contact with the drawn-out portion FPa.

[0066] 22, first, a p-type body region PB is selectively formed in the semiconductor substrate SUB by introducing an impurity such as boron (B) using photolithography and ion implantation techniques. The body region PB is formed so that its depth from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR.

[0067] Next, by introducing an impurity such as arsenic (As) using photolithography and ion implantation, an n-type source region NS is selectively formed in the body region PB of the cell region CR, as shown in the AA cross section of Fig. 22. Note that, as shown in the BB cross section of Fig. 22, the source region NS is not formed in the body region PB adjacent to the leader portion FPa. Thereafter, the semiconductor substrate SUB is subjected to a heat treatment to activate the impurities contained in the source region NS and the body region PB.

[0068] As shown in FIG. 23, first, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR.

[0069] Next, contact holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. Specifically, first, a resist pattern having a pattern that opens above the source region NS is formed on the interlayer insulating film IL. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a contact hole CH1 that penetrates the interlayer insulating film IL and the source region NS and reaches the inside of the body region PB. Next, an impurity such as boron (B) is introduced by ion implantation into the body region PB at the bottom of the contact hole CH1 to form a p-type high-concentration diffusion region PR. After that, the resist pattern is removed by ashing.

[0070] Next, a resist pattern having a pattern that opens above the lead-out portion FPa and above the gate electrode GE is formed on the interlayer insulating film IL. Next, an anisotropic etching process is performed using the resist pattern as a mask to form a contact hole CH3 that penetrates the interlayer insulating film IL and reaches the lead-out portion FPa. Although not shown here, a contact hole CH2 is also formed in the manufacturing process that forms the contact hole CH3. The contact hole CH2 penetrates the interlayer insulating film IL and reaches the gate electrode GE. The resist pattern is then removed by ashing.

[0071] As shown in FIG. 24, plugs PG are formed inside each of the contact holes CH1, CH2, and CH3, and a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL.

[0072] First, a first barrier metal film is formed inside the contact holes CH1, CH2, and CH3 and on the interlayer insulating film IL by a film formation process using a sputtering method or a CVD method. The first barrier metal film is made of, for example, a stacked film of a titanium nitride film and a titanium film. Next, a first conductive film is formed on the first barrier metal film by a film formation process using a CVD method. The first conductive film is made of, for example, a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the contact holes CH1, CH2, and CH3 are removed by a polishing process using a CMP method or an anisotropic etching process. This forms plugs PG made of the first barrier metal film and the first conductive film so as to fill the insides of the contact holes CH1, CH2, and CH3.

[0073] Next, a second barrier metal film is formed on the interlayer insulating film IL by a film formation process using a sputtering method. The second barrier metal film is made of, for example, a titanium tungsten film. Next, a second conductive film is formed on the second barrier metal film by a film formation process using a sputtering method. The second conductive film is, for example, an aluminum alloy film with copper or silicon added. Next, the second barrier metal film and the second conductive film are patterned to form a source electrode SE and a gate wiring GW.

[0074] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. Openings are formed in parts of the protective film to expose the regions of the source electrode SE and the gate wiring GW that will become the source pad SP and the gate pad GP.

[0075] Thereafter, the structure shown in FIG. 5 is obtained through the following manufacturing steps. First, the lower surface BS of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface BS of the semiconductor substrate SUB by ion implantation. Note that if the semiconductor substrate SUB is configured as a stack of an n-type silicon substrate and an n-type semiconductor layer, the highly doped n-type silicon substrate forms the drain region ND, and therefore the formation of the drain region ND by the above-mentioned ion implantation can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by a film formation process using a sputtering method.

[0076] Although the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. (Addendum) (Appendix 1) a semiconductor substrate having an upper surface and a lower surface; a trench formed in the semiconductor substrate so as to extend from the upper surface toward the lower surface of the semiconductor substrate to a predetermined depth; a first insulating film formed on the bottom surface of the trench and on a part of the side surface; a gate insulating film connected to the first insulating film and formed on a side surface of the trench; a field plate electrode formed in the trench via the first insulating film; a gate electrode formed in the trench via the gate insulating film; a second insulating film separating the field plate electrode from the gate electrode; Equipped with the first insulating film comprises a stacked film made of a first oxide film in contact with a side surface of the trench and a second oxide film in contact with the field plate electrode; a slope of an upper surface of the first insulating film connected to the gate insulating film changes at a boundary between the first oxide film and the second oxide film; Semiconductor device. (Appendix 2) In the semiconductor device according to Supplementary Note 1, an upper surface of the first oxide film and an upper surface of the second oxide film each have a shape that rises from the field plate electrode toward the semiconductor substrate in a cross-sectional view; a rate of increase of the rise of the upper surface of the first oxide film in a cross-sectional view is greater than a rate of increase of the rise of the upper surface of the second oxide film in a cross-sectional view; Semiconductor device. (Appendix 3) In the semiconductor device according to Supplementary Note 2, the etching rate of the second oxide film is greater than the etching rate of the first oxide film with respect to a predetermined etching solution; Semiconductor device. (Appendix 4) In the semiconductor device according to Supplementary Note 3, The predetermined etching solution includes any one of BHF (Buffered Hydrofluoric Acid), DHF (Dilute Hydrofluoric Acid), and vapor-phase hydrofluoric acid. Semiconductor device. (Appendix 5) In the semiconductor device according to Supplementary Note 4, The first oxide film is a dry oxide film, and the second oxide film is a LPCVD (Low-Pressure Chemical Vapor Deposition)-TEOS (Tetra Ethoxy Silane) film. Semiconductor device. (Appendix 6) In the semiconductor device according to Supplementary Note 2, an average rising angle of the upper surface of the first oxide film in a cross-sectional view is 40 degrees or more and 60 degrees or less; Semiconductor device. (Appendix 7) (a) providing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate from the upper surface toward the lower surface of the semiconductor substrate to a predetermined depth; (c) after the step (b), forming a first insulating film in the trench and on the top surface of the semiconductor substrate; (d) after the step (c), forming a field plate electrode on the first insulating film so as to fill the trench; (e) after step (d), etching the field plate electrode to recess it toward the bottom of the trench; (f) after the step (e), removing the first insulating film located on the upper surface of the semiconductor substrate by etching, and recessing the first insulating film located in the trench toward the bottom of the trench; (g) after the step (f), forming a gate insulating film on the upper surface of the semiconductor substrate and in the trench, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film; (h) after the step (g), forming a gate electrode on the gate insulating film, the first insulating film, and the second insulating film so as to fill the trench; Equipped with The step (c) includes a step of forming a first oxide film in contact with the semiconductor substrate and a step of forming a second oxide film; In the step (d), the field plate electrode is formed so as to be in contact with the second oxide film; In the step (f), the first insulating film located in the trench is recessed toward the bottom of the trench so that the slope of the top surface of the first insulating film changes at the boundary between the first oxide film and the second oxide film. A method for manufacturing a semiconductor device. (Appendix 8) 8. The method for manufacturing a semiconductor device according to claim 7, In the step (f), the first insulating film located in the trench recedes toward the bottom of the trench so that an upper surface of the first oxide film and an upper surface of the second oxide film each have a shape that rises from the field plate electrode toward the semiconductor substrate in a cross-sectional view, and so that a rate of rise of the upper surface of the first oxide film in a cross-sectional view is greater than a rate of rise of the upper surface of the second oxide film in a cross-sectional view. A method for manufacturing a semiconductor device. (Appendix 9) 9. The method for manufacturing a semiconductor device according to claim 8, The etching treatment in the step (f) is a wet etching treatment using a predetermined etching solution, the etching rate of the second oxide film is higher than the etching rate of the first oxide film with respect to the predetermined etching solution; A method for manufacturing a semiconductor device. (Appendix 10) 10. The method for manufacturing a semiconductor device according to claim 9, The predetermined etching solution includes any one of BHF (Buffered Hydrofluoric Acid), DHF (Dilute Hydrofluoric Acid), and vapor-phase hydrofluoric acid. A method for manufacturing a semiconductor device. (Appendix 11) 11. The method for manufacturing a semiconductor device according to claim 10, the step of forming the first oxide film in the step (c) includes the step of forming a dry oxide film; The step of forming the second oxide film in the step (c) includes a step of forming an LPCVD (Low-Pressure Chemical Vapor Deposition)-TEOS (Tetra Ethoxy Silane) film. A method for manufacturing a semiconductor device. (Appendix 12) 9. The method for manufacturing a semiconductor device according to claim 8, The step (f) is performed so that the average angle of the rise of the upper surface of the first oxide film in a cross-sectional view is 40 degrees or more and 60 degrees or less. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0077] 100 Semiconductor device 1A area BS Bottom surface of semiconductor substrate CF1, CF2, CF3 conductive film CH1, CH2, CH3 contact holes CR Cell Area DE drain electrode FP field plate electrode FPa drawer section GE gate electrode GI gate insulating film GP Gate Pad GW Gate wiring HM Hard Mask IF1, IF2, IF3 insulating films IF1a, IF1b oxide film IL Interlayer insulating film ND drain region NS Source Region NV drift region OR outer area OX1 Silicon oxide film PB body region PG plug PR high concentration diffusion region RP1 resist pattern SE source electrode SP sauce pad SUB Semiconductor substrate TR Trench TS Top surface of semiconductor substrate

Claims

1. a semiconductor substrate having an upper surface and a lower surface; a trench formed in the semiconductor substrate so as to reach a predetermined depth from the upper surface toward the lower surface of the semiconductor substrate; a first insulating film formed on a bottom surface of the trench and a portion of a side surface of the trench; a gate insulating film connected to the first insulating film and formed on a side surface of the trench; a field plate electrode formed in the trench via the first insulating film; a gate electrode formed in the trench via the gate insulating film; a second insulating film separating the field plate electrode from the gate electrode; Equipped with the first insulating film comprises a stacked film made of a first oxide film in contact with a side surface of the trench and a second oxide film in contact with the field plate electrode; a slope of an upper surface of the first insulating film connected to the gate insulating film changes at a boundary between the first oxide film and the second oxide film; Semiconductor device.

2. 2. The semiconductor device according to claim 1, an upper surface of the first oxide film and an upper surface of the second oxide film each have a shape that rises from the field plate electrode toward the semiconductor substrate in a cross-sectional view; a rate of increase of the rise of the upper surface of the first oxide film in a cross-sectional view is greater than a rate of increase of the rise of the upper surface of the second oxide film in a cross-sectional view; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the etching rate of the second oxide film is greater than the etching rate of the first oxide film with respect to a predetermined etching solution; Semiconductor device.

4. 4. The semiconductor device according to claim 3, The predetermined etching solution contains any one of BHF (Buffered Hydrofluoric Acid), DHF (Dilute Hydrofluoric Acid), and vapor-phase hydrofluoric acid; Semiconductor device.

5. 5. The semiconductor device according to claim 4, The first oxide film is a dry oxide film, and the second oxide film is a LPCVD (Low-Pressure Chemical Vapor Deposition)-TEOS (Tetra Ethoxy Silane) film. Semiconductor device.

6. 3. The semiconductor device according to claim 2, an average rising angle of the upper surface of the first oxide film in a cross-sectional view is equal to or greater than 40 degrees and equal to or less than 60 degrees; Semiconductor device.

7. (a) providing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate from the upper surface toward the lower surface of the semiconductor substrate to a predetermined depth; (c) after the step (b), forming a first insulating film in the trench and on the upper surface of the semiconductor substrate; (d) after the step (c), forming a field plate electrode on the first insulating film so as to fill the trench; (e) after the step (d), a step of recessing the field plate electrode toward the bottom of the trench by an etching process; (f) after the step (e), removing the first insulating film located on the upper surface of the semiconductor substrate by an etching process, and recessing the first insulating film located in the trench toward the bottom of the trench; (g) after the step (f), forming a gate insulating film on the upper surface of the semiconductor substrate and in the trench, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film; (h) after the step (g), forming a gate electrode on the gate insulating film, the first insulating film, and the second insulating film so as to fill the trench; Equipped with the step (c) includes a step of forming a first oxide film in contact with the semiconductor substrate and a step of forming a second oxide film; In the step (d), the field plate electrode is formed so as to be in contact with the second oxide film; In the step (f), the first insulating film located in the trench is recessed toward the bottom of the trench so that a slope of an upper surface of the first insulating film changes at a boundary between the first oxide film and the second oxide film. A method for manufacturing a semiconductor device.

8. 8. The method for manufacturing a semiconductor device according to claim 7, In the step (f), the first insulating film located in the trench recedes toward the bottom of the trench so that an upper surface of the first oxide film and an upper surface of the second oxide film each have a shape that rises from the field plate electrode toward the semiconductor substrate in a cross-sectional view, and so that a rate of rise of the upper surface of the first oxide film in a cross-sectional view is larger than a rate of rise of the upper surface of the second oxide film in a cross-sectional view. A method for manufacturing a semiconductor device.

9. 9. The method for manufacturing a semiconductor device according to claim 8, the etching treatment in the step (f) is a wet etching treatment using a predetermined etching solution; an etching rate of the second oxide film is higher than an etching rate of the first oxide film with respect to the predetermined etching solution; A method for manufacturing a semiconductor device.

10. 10. The method for manufacturing a semiconductor device according to claim 9, The predetermined etching solution contains any one of BHF (Buffered Hydrofluoric Acid), DHF (Dilute Hydrofluoric Acid), and vapor-phase hydrofluoric acid; A method for manufacturing a semiconductor device.

11. 11. The method for manufacturing a semiconductor device according to claim 10, the step of forming the first oxide film in the step (c) includes the step of forming a dry oxide film; The step of forming the second oxide film in the step (c) includes a step of forming an LPCVD (Low-Pressure Chemical Vapor Deposition)-TEOS (Tetra Ethoxy Silane) film. A method for manufacturing a semiconductor device.

12. 9. The method for manufacturing a semiconductor device according to claim 8, The step (f) is performed so that the average angle of the rise of the upper surface of the first oxide film in a cross-sectional view is 40 degrees or more and 60 degrees or less. A method for manufacturing a semiconductor device.

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