Operational amplifier circuit

Abstract

To provide an operational amplifier in which overshoot and undershoot are suppressed while an increase in circuit current is suppressed.SOLUTION: Reference current sources 142 and 144 generate respective reference currents Iref P_and Iref_N which define idle currents Iidle_P and Iidle_N of a P-type output transistor MP1 and an N-type output transistor MN1 of a source-grounded class AB output stage 130, respectively. The reference current sources 142 and 144 are capable of switching an amount of current of the respective reference currents Iref_P and Iref_N according to a control signal BOOST. A boost circuit 150 generates the control signal BOOST such that the reference currents Iref_P and Iref N_increase when a potential difference ΔV of respective differential input signals +IN and -IN becomes larger than a predetermined threshold voltage ΔVth, and, after a certain time has passed since the potential difference ΔV of each different input signal becomes smaller than the threshold voltage ΔVth, the amounts of the reference currents Iref_P and Iref_N return to their original amounts.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to operational amplifier circuits. [Background technology]

[0002] In electronic circuits, operational amplifiers are important circuit elements. When a transient fluctuation occurs in an operational amplifier with a slow response speed, the output voltage overshoots or undershoots, and it takes a long time for the overshoot or undershoot to settle down.

[0003] There is a trade-off between the response speed of a class AB op-amp and its operating current; increasing the response speed increases the operating current, while designing it to have a small operating current decreases the response speed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2023-178679

[0005] [overview] The present disclosure has been made in light of such a situation, and an exemplary purpose of an embodiment thereof is to provide an operational amplifier that suppresses overshoot and undershoot while suppressing an increase in circuit current.

[0006] An operational amplifier circuit according to one embodiment of the present disclosure includes a common-source class AB output stage including a P-type output transistor and an N-type output transistor; a reference current source that generates a reference current that defines the idle current of the P-type output transistor and the N-type output transistor, the amount of which is switchable in response to a control signal; and a boost circuit that generates a control signal such that the reference current increases when the potential difference between differential input signals exceeds a predetermined threshold voltage, and returns to its original amount after a predetermined time has elapsed since the potential difference between the differential input signals becomes smaller than the threshold voltage.

[0007] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram of an operational amplifier circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of a voltage follower circuit including an operational amplifier circuit. [Figure 3] FIG. 3 is a diagram illustrating the operation of the operational amplifier circuit in the voltage follower circuit of FIG. [Figure 4] FIG. 4 is a circuit diagram of the operational amplifier circuit according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram of an operational amplifier circuit according to a second embodiment. [Figure 6] FIG. 6 is a circuit diagram of an operational amplifier circuit according to a third embodiment. [Figure 7] FIG. 7 is a circuit diagram of an operational amplifier circuit according to a fourth embodiment. [Figure 8] FIG. 8 is a circuit diagram of a boost circuit according to one embodiment. [Figure 9] FIG. 9 is a circuit diagram of a boost circuit according to one embodiment.

[0009] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] An operational amplifier circuit according to one embodiment includes a source-grounded class AB output stage including a P-type output transistor and an N-type output transistor; a reference current source that generates a reference current that defines the idle current of the P-type output transistor and the N-type output transistor, the amount of which is switchable in response to a control signal; and a boost circuit that generates a control signal such that, when the potential difference of the differential input signals becomes larger than a predetermined threshold voltage, the reference current increases, and the reference current returns to its original amount after a predetermined time has elapsed since the potential difference of the differential input signals became smaller than the threshold voltage.

[0011] In this configuration, in the steady state, an imaginary short exists in the op-amp circuit, so the difference between the differential input signals is essentially zero. At this time, the idle current of the class AB output stage is small, so the operating current of the op-amp circuit can be reduced.

[0012] When a transient fluctuation occurs, the difference between the differential input signals of the operational amplifier circuit increases. The boost circuit detects this difference and temporarily increases the idle current (also called idling current) of the class AB output stage compared to the steady state, thereby improving response speed. Feedback maintains the boosted state for the period during which overshoot, undershoot, or ringing may occur after the difference between the differential input signals becomes small, suppressing overshoot and undershoot and shortening the time it takes for the output to stabilize.

[0013] In one embodiment, the reference current source may include a first transistor having a bias voltage applied to its gate, a second transistor having its gate and source connected to those of the first transistor, and a third transistor connected between the drain of the first transistor and the drain of the second transistor and controlled to be turned on and off in response to a control signal. The third transistor may function as a switch that can be digitally switched on and off, or may function as an impedance element that can be continuously controlled between an on state and an off state in an analog manner.

[0014] In one embodiment, the class AB output stage may be a cross-coupled feed-forward class AB output stage.

[0015] In one embodiment, the boost circuit may include a first comparator that outputs a first boost signal indicating a comparison result between one of the differential input signals and a voltage that is higher by a threshold voltage than the other of the differential input signals, a second comparator that generates a second boost signal that indicates a comparison result between the other of the differential input signals and a voltage that is higher by a threshold voltage than the one of the differential input signals, a first logic gate that performs a logical operation on the first boost signal and the second boost signal, and an edge delay circuit that delays one edge of the first logic gate.

[0016] In one embodiment, the boost circuit includes a first comparator that asserts a first boost signal when one of the differential input signals exceeds a voltage that is higher by a threshold voltage than the other of the differential input signals; a second comparator that asserts a second boost signal when the other of the differential input signals exceeds a voltage that is higher by a threshold voltage than the one of the differential input signals; an inverting driver that generates a control signal of an inverted logic of an analog voltage based on the first boost signal and the second boost signal; and a non-inverting driver that generates a control signal of a true logic of an analog voltage based on the first boost signal and the second boost signal.

[0017] (Embodiment) The present disclosure will be described below with reference to the drawings based on preferred embodiments. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples rather than limitations on the invention or disclosure, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention or disclosure.

[0018] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or impair the functions or effects achieved by their combination.

[0019] Similarly, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0020] 1 is a circuit diagram of an operational amplifier circuit 100 according to an embodiment. The operational amplifier circuit 100 includes a differential input stage 110, a gain stage 120, a class AB output stage 130, an idle current control circuit 140, and a boost circuit 150.

[0021] The class AB output stage 130 is a common-source output stage including a P-type output transistor (P-channel MOSFET: Metal Oxide Semiconductor Field Effect Transistor) MP1 and an N-type output transistor (N-channel MOSFET) MN1.

[0022] The differential input stage 110 outputs a signal corresponding to the error between the differential input signals +IN and −IN. The gain stage 120 amplifies the output of the differential input stage 110 and supplies it to the class AB output stage 130. Note that the gain stage 120 may be omitted, in which case the output signal of the differential input stage 110 is supplied directly to the class AB output stage 130.

[0023] The idle current control circuit 140 controls and adjusts the idle currents Iidle_P and Iidle_N flowing through the P-type output transistor MP1 and the N-type output transistor MN1 of the class AB output stage 130. The idle current control circuit 140 includes reference current sources 142 and 144 that generate reference currents Iref_P and Iref_N that define the idle currents Iidle1 and Idle2 of the P-type output transistor MP1 and the N-type output transistor MN1.

[0024] The reference current sources 142 and 144 are variable current sources, and the current amounts of the reference currents Iref_P and Iref_N can be switched in response to the control signal BOOST. Note that the reference current sources 142 and 144 may be a single reference current source.

[0025] The boost circuit 150 generates the control signal BOOST so that the reference currents Iref_P and Iref_N increase when the potential difference ΔV between the differential input signals +IN and −IN becomes larger than a predetermined threshold voltage ΔVth. The boost circuit 150 also generates the control signal BOOST so that the reference currents Iref_P and Iref_N return to their original amounts after a predetermined time τ has elapsed since the potential difference ΔV between the differential input signals +IN and −IN became smaller than the threshold voltage ΔVth.

[0026] The above is the configuration of the operational amplifier circuit 100. Next, its operation will be described. Next, the operation of the operational amplifier circuit 100 will be described. Since the operational amplifier circuit 100 is usually used by being incorporated into a feedback loop, the following explanation will be given of a voltage follower circuit including the operational amplifier circuit 100.

[0027] 2 is a circuit diagram of a voltage follower circuit 200 including an operational amplifier circuit 100. The output OUT of the operational amplifier circuit 100 is connected to an inverting input terminal (-). A smoothing capacitor Cout is connected to the output OUT of the operational amplifier circuit 100. A voltage signal +IN that defines a target voltage for the output voltage Vout is supplied to the non-inverting input terminal of the operational amplifier circuit 100. In order to evaluate the transient response of the operational amplifier circuit 100, the voltage signal +IN is changed in a stepwise manner.

[0028] 3 is a diagram illustrating the operation of the operational amplifier circuit 100 in the voltage follower circuit 200 of FIG. 2. Before time t0, the input voltage +IN of the voltage follower circuit 200 is at a constant first level V1, and the voltage follower circuit 200 is in a steady state. The operational amplifier circuit 100 is in an imaginary short state, i.e., feedback is applied so that +IN and -IN are equal, and the gate voltage PGATE of the P-type output transistor MP1 and the gate voltage NGATE of the N-type output transistor MN1 are stabilized at appropriate voltage levels Vp1 and Vn1, respectively, depending on the load state.

[0029] At time t1, the input voltage +IN transitions to the second level V2. Immediately after time t1, the output voltage OUT (i.e., -IN) becomes larger as the error ΔV of the input voltage +IN increases. At this time, the gate voltage PGATE of the P-type output transistor MP1 becomes 0V (V SS ) side, and the N-type output transistor MN1 is fully on. The gate voltage NGATE of the N-type output transistor MN1 is also 0V (V SS ) side and turns off. This causes the output voltage OUT to rise towards the input voltage +IN (second level V2).

[0030] At time t1, when the error ΔV between the output voltage OUT (i.e., -IN) and the input voltage +IN exceeds the threshold value ΔVth, the reference currents Iref_P and Iref_N generated by the reference current sources 142 and 144 increase, and the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 increase (boost).

[0031] At time t2, the error ΔV between the output voltage OUT (i.e., -IN) and the input voltage +IN becomes smaller than the threshold value ΔVth. When the error ΔV between the output voltage OUT (i.e., -IN) and the input voltage +IN becomes small to a certain extent, the gate voltage PGATE and the gate voltage NGATE of the N-type output transistor MN1 approach the appropriate voltage levels Vp2 and Vn2 according to the load state.

[0032] At time t3, a predetermined time τ after time t2, the reference currents Iref_P and Iref_N generated by the reference current sources 142 and 144 return to their original current amounts, and the boosting of the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 ends. As the idle currents Iidle_P and Iidle_N decrease, the operating points of the P-type output transistor MP1 and the N-type output transistor MN1 change, and the gate voltages PGATE and NGATE approach the appropriate voltage levels Vp3 and Vn3 in the steady state.

[0033] At time t4, the input voltage +IN transitions to the first level V1. Immediately after time t4, the output voltage OUT (i.e., -IN) becomes larger as the error ΔV of the input voltage +IN increases. At this time, the gate voltage PGATE of the P-type output transistor MP1 becomes larger than the power supply voltage V DD The gate voltage NGATE of the N-type output transistor MN1 is also tied to the power supply voltage V DD This causes the output voltage OUT to decrease toward the input voltage +IN (first level V1).

[0034] At time t5, when the error ΔV between the output voltage OUT (i.e., -IN) and the input voltage +IN exceeds the threshold value ΔVth, the reference currents Iref_P and Iref_N generated by the reference current sources 142 and 144 increase, and the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 increase (boost).

[0035] At time t6, the error ΔV between the output voltage OUT (i.e., -IN) and the input voltage +IN becomes smaller than the threshold value ΔVth. When the error ΔV between the output voltage OUT (i.e., -IN) and the input voltage +IN becomes small to a certain extent, the gate voltage PGATE and the gate voltage NGATE of the N-type output transistor MN1 approach the appropriate voltage levels Vp4 and Vn4 according to the load state.

[0036] At time t7, a predetermined time τ after time t6, the reference currents Iref_P and Iref_N generated by the reference current sources 142 and 144 return to their original current amounts, and the boosting of the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 ends. As the idle currents Iidle_P and Iidle_N decrease, the operating points of the P-type output transistor MP1 and the N-type output transistor MN1 change, and the gate voltages PGATE and NGATE approach the appropriate voltage levels Vp4 and Vn4 in the steady state.

[0037] The operation of the operational amplifier circuit 100 in the voltage follower circuit 200 has been described above.

[0038] The period from time t2 to t3 is a period during which overshoot and subsequent ringing are likely to occur. In the embodiment, the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 are boosted during this period, thereby increasing the response speed of the operational amplifier circuit 100. This makes it possible to suppress overshoot and speed up the convergence of the subsequent ringing.

[0039] Furthermore, the period from time t6 to t7 is a period during which undershoot and subsequent ringing are likely to occur. In this embodiment, the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 are boosted during this period, thereby increasing the response speed of the operational amplifier circuit 100. This makes it possible to suppress undershoot and speed up the convergence of subsequent ringing.

[0040] The present disclosure covers various devices and methods that can be understood as the block diagram or circuit diagram of Figure 1 or derived from the above description, and is not limited to a specific configuration. Below, more specific configuration examples and examples will be described not to narrow the scope of the present disclosure, but to aid in understanding and clarify the essence and operation of the present disclosure and the present invention.

[0041] Example 1 4 is a circuit diagram of an operational amplifier circuit 100A in accordance with Example 1. The idle current control circuit 140A includes an N-type bias transistor MN3 and a P-type bias transistor MP3 that are cross-coupled between the gate of the P-type output transistor MP1 and the gate of the N-type output transistor MN1, and the class AB output stage 130A is referred to as a cross-coupled feed-forward class AB output stage.

[0042] The idle current control circuit 140A includes reference current sources 142 and 144, transistors MP2 to MP4, MN2 to MN4 to M16, and current sources CS1 and CS2.

[0043] When the gate-source voltages of transistors MP3 and MP4 are equal, the gate-source voltages of the P-type output transistor MP1 and the P-type replica transistor MP2 are equal, and the transistor pair MP1 and MP2 form a current mirror circuit (called a floating current mirror circuit). Therefore, an idle current Iidle_P proportional to the reference current Iref_P flows through the P-type output transistor MP1.

[0044] Similarly, when the gate-source voltages of transistors MN3 and MN4 are equal, the gate-source voltages of N-type output transistor MN1 and N-type replica transistor MN2 are also equal, and the transistor pair MN1 and MN2 form a floating current mirror circuit. As a result, an idle current Iidle_N proportional to the reference current Iref_N flows through N-type output transistor MN1.

[0045] The reference current sources 142 and 144 are variable current sources, and the reference currents Iref_P and Iref_N can be switched in response to a control signal BOOST generated by the boost circuit 150. Therefore, by boosting the reference currents Iref_P and Iref_N, the idle currents Iidle_P and Iidle_N of the P-type output transistor MP1 and the N-type output transistor MN1 can be boosted.

[0046] Example 2 5 is a circuit diagram of an operational amplifier circuit 100B according to Example 2. In Example 2, the gain stage 120 is omitted.

[0047] The differential input stage 110B includes a differential pair 112, a tail current source 114, and a current mirror load 116. The output signal of the differential input stage 110B is supplied to the gate of an N-type output transistor MN1.

[0048] The configuration and operation of the idle current control circuit 140B are as described in Fig. 4. The gate voltage of the P-type output transistor MP1 is controlled by the idle current control circuit 140B in accordance with the output signal of the differential input stage 110B.

[0049] Example 3 6 is a circuit diagram of an operational amplifier circuit 100C according to a third embodiment. The operational amplifier circuit 100C is a rail-to-rail amplifier. A differential input stage 110C includes a differential pair 112P, 112N and tail current sources 114P, 114N.

[0050] The idle current control circuit 140C is configured integrally with the gain stage 120C. The gain stage 120C is a folded cascode circuit and includes transistors MN5 to MN8 and MP5 to MP8. The cross-coupled transistor pairs MP3_1, MN3_1 and MP3_2, MN3_2, which are part of the idle current control circuit 140C, are incorporated into the gain stage 120C. In the figure, P_bias_R, N_bias_R, P_bias_ref, and N_bias_ref indicate bias voltages.

[0051] The reference current source 142C includes a first transistor MN11, a second transistor MN12, a third transistor MN13, and a driver DRV1. The gates and sources of the first transistor MN11 and the second transistor MN12 are connected in common, and a common bias voltage N_bias_ref is supplied to these gates. The third transistor MN13 is connected in series with the second transistor MN12. The driver DRV1 is a buffer that switches the third transistor MN13 on and off in response to a control signal BOOST.

[0052] When the control signal BOOST is negated (e.g., low), the third transistor MN13 is off, and the current flowing through transistor MN11 becomes the reference current Iref_P. When the control signal BOOST is asserted (e.g., high), the third transistor MN13 is on, and the sum of the current flowing through transistor MN11 and the current flowing through transistor MN12 becomes the reference current Iref_P, which is boosted. In other words, the third transistor MN13 is a switch that can be digitally switched on and off. As will be described later, the third transistor MN13 may function as an impedance element that can be continuously controlled between an on state and an off state in an analog manner.

[0053] The reference current source 144C includes a first transistor MP11, a second transistor MP12, a third transistor MP13, and a driver DRV2. The gates and sources of the first transistor MP11 and the second transistor MP12 are commonly connected, and a common bias voltage P_bias_ref is supplied to their gates. The third transistor MP13 is connected in series with the second transistor MP12. The driver DRV2 is an inverter that switches the third transistor MP13 on and off in response to a control signal BOOST.

[0054] When the control signal BOOST is negated (e.g., low), the third transistor MP13 is off, and the current flowing through the transistor MP11 becomes the reference current Iref_N. When the control signal BOOST is asserted (e.g., high), the third transistor MP13 is on, and the sum of the current flowing through the transistor MP11 and the current flowing through the transistor MP12 becomes the reference current Iref_N, which is boosted.

[0055] Example 4 7 is a circuit diagram of an operational amplifier circuit 100D according to Example 4. The operational amplifier circuit 100D is a rail-to-rail amplifier, similar to the operational amplifier circuit 100C in FIG.

[0056] The idle current control circuit 140D in Fig. 7 is provided with an operational amplifier OA1 instead of the transistor MP14 in the idle current control circuit 140C in Fig. 6, and an operational amplifier OA2 instead of the transistor MN14. The operational amplifier OA1 generates a bias voltage P_bias_C so that the gate voltage of the P-type output transistor MP1 is equal to the gate voltage of the P-type replica transistor MP2. As a result, the P-type output transistor MP1 and the P-type replica transistor MP2 operate as a current mirror circuit, and an idle current Iidle_P proportional to the reference current Iref_P flows through the P-type output transistor MP1.

[0057] The operational amplifier OA2 generates a bias voltage N_bias_C so that the gate voltage of the N-type output transistor MN1 is equal to the gate voltage of the N-type replica transistor MN2. As a result, the N-type output transistor MN1 and the N-type replica transistor MN2 operate as a current mirror circuit, and an idle current Iidle_N proportional to the reference current Iref_N flows through the N-type output transistor MN1.

[0058] Next, an example of the configuration of the boost circuit 150 will be described.

[0059] 8 is a circuit diagram of a boost circuit 150E according to one embodiment. A first comparator COMP1 compares one of the differential input signals, +IN, with a voltage that is higher by a threshold voltage ΔVth than the other, -IN, and generates a first boost signal S1 indicative of the comparison result. A second comparator COMP2 compares the other, -IN, with a voltage that is higher by a threshold voltage ΔVth than the other, +IN, and generates a second boost signal S2 indicative of the comparison result.

[0060] The first logic gate 152 performs a logical operation on the first boost signal S1 and the second boost signal S2. In this example, the first logic gate 152 is an OR gate.

[0061] The edge delay circuit 154 delays one edge (in this example, the negative edge) of the first logic gate 152. The edge delay circuit 154 includes a delay circuit 156 and an OR gate 158. The delay circuit 156 delays the output of the first logic gate 152 by a predetermined time τ. The OR gate 158 generates the logical sum of the signal before and after the delay, and generates the control signal BOOST.

[0062] 9 is a circuit diagram of a boost circuit 150F according to one embodiment. While the boost circuit 150E of FIG. 8 generates a binary control signal BOOST (high / low), the boost circuit 150F of FIG. 9 generates an analog voltage control signal BOOST and an inverted control signal / BOOST. The analog control signal BOOST is directly supplied to the gate of the third transistor MN13 of the reference current source 142, and the inverted analog control signal / BOOST is directly supplied to the gate of the third transistor MP13 of the reference current source 144.

[0063] The first comparator COMP1 compares one of the differential input signals, +IN, with a voltage that is higher by a threshold voltage ΔVth than the other, -IN, and generates a first boost signal S1 indicative of the comparison result. The second comparator COMP2 compares the other of the differential input signals, -IN, with a voltage that is higher by a threshold voltage ΔVth than the other, +IN, and generates a second boost signal S2 indicative of the comparison result.

[0064] The inverting driver 160 includes switches SW21 and SW22, current sources CS21 and CS22, a resistor R21, and a capacitor C21. The current sources CS21 and CS22, the third transistor MN13, SW22, and the resistor R21 function as a NOR gate. The capacitor C21 is connected in parallel with the resistor R21 and dulls the waveform of the inverted control signal / BOOST, which is an analog voltage, and delays its edge.

[0065] The non-inverting driver 162 includes switches SW31 and SW32, current sources CS31 and CS32, current mirror circuits CM31 and CM32, a resistor R31, and a capacitor C31. This non-inverting driver 162 behaves like an OR gate. The capacitor C31 is connected in parallel with the resistor R31 and dulls the waveform of the control signal BOOST, which is an analog voltage, and delays its edge.

[0066] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also included in the present disclosure and can constitute the scope of the present invention.

[0067] (Addendum) The present specification discloses the following techniques.

[0068] (Item 1) a source-grounded class AB output stage including a P-type output transistor and an N-type output transistor; a reference current source that generates a reference current that defines an idle current of the P-type output transistor and the N-type output transistor, the amount of the reference current being switchable in response to a control signal; a boost circuit that generates the control signal such that when a potential difference between the differential input signals becomes larger than a predetermined threshold voltage, the reference current increases, and the reference current returns to its original amount after a predetermined time has elapsed since the potential difference between the differential input signals becomes smaller than the threshold voltage; An operational amplifier circuit comprising:

[0069] (Item 2) The reference current source is a first transistor having a bias voltage applied to its gate; a second transistor whose gates and sources are commonly connected to those of the first transistor; a third transistor connected between the drain of the first transistor and the drain of the second transistor, and controlled to be turned on and off in response to the control signal; Item 2. The operational amplifier circuit of item 1, comprising:

[0070] (Item 3) 3. The operational amplifier circuit according to item 1 or 2, wherein the class AB output stage is a cross-coupled feed-forward class AB output stage.

[0071] (Item 4) The boost circuit comprises: a first comparator that asserts a first boost signal when one of the differential input signals exceeds a voltage that is the threshold voltage higher than the other of the differential input signals; a second comparator that asserts a second boost signal when the other of the differential input signals exceeds a voltage that is higher than the one of the differential input signals by the threshold voltage; a first logic gate that performs a logical operation on the first boost signal and the second boost signal; an edge delay circuit that delays one edge of the first logic gate; 4. The operational amplifier circuit of any one of items 1 to 3, comprising:

[0072] (Item 5) The boost circuit comprises: a first comparator that asserts a first boost signal when one of the differential input signals exceeds a voltage that is the threshold voltage higher than the other of the differential input signals; a second comparator that asserts a second boost signal when the other of the differential input signals exceeds a voltage that is higher than the one of the differential input signals by the threshold voltage; an inverting driver that generates a control signal of an inverted logic of an analog voltage based on the first boost signal and the second boost signal; a non-inverting driver that generates a true logic control signal of an analog voltage based on the first boost signal and the second boost signal; 4. The operational amplifier circuit of any one of items 1 to 3, comprising: [Explanation of symbols]

[0073] 100 Op-amp Circuits 110 Differential Input Stage 112 Tail Current Source 114 Differential Pair 120 gain stage 130 AB class output stage MP1 P-type output transistor MN1 N-type output transistor 140 Idle current control circuit 142,144 Reference current source 150 Boost Circuit 200 Voltage follower circuit

Claims

1. a source-grounded class AB output stage including a P-type output transistor and an N-type output transistor; a reference current source that generates a reference current that defines an idle current of the P-type output transistor and the N-type output transistor, the amount of the reference current being switchable in response to a control signal; a boost circuit that generates the control signal such that when a potential difference between the differential input signals becomes larger than a predetermined threshold voltage, the reference current increases, and when a predetermined time has elapsed since the potential difference between the differential input signals becomes smaller than the threshold voltage, the reference current returns to its original amount; An operational amplifier circuit comprising:

2. The reference current source is a first transistor having a bias voltage applied to its gate; a second transistor whose gates and sources are commonly connected to those of the first transistor; a third transistor connected between the drain of the first transistor and the drain of the second transistor, and controlled to be turned on and off in response to the control signal; 2. The operational amplifier circuit of claim 1, comprising:

3. 3. The operational amplifier circuit according to claim 1, wherein the class AB output stage is a cross-coupled feed-forward class AB output stage.

4. The boost circuit comprises: a first comparator that asserts a first boost signal when one of the differential input signals exceeds a voltage that is the threshold voltage higher than the other of the differential input signals; a second comparator that asserts a second boost signal when the other of the differential input signals exceeds a voltage that is higher than the one of the differential input signals by the threshold voltage; a first logic gate that performs a logical operation on the first boost signal and the second boost signal; an edge delay circuit that delays one edge of the first logic gate; 3. The operational amplifier circuit of claim 1, comprising:

5. The boost circuit comprises: a first comparator that asserts a first boost signal when one of the differential input signals exceeds a voltage that is the threshold voltage higher than the other of the differential input signals; a second comparator that asserts a second boost signal when the other of the differential input signals exceeds a voltage that is higher than the one of the differential input signals by the threshold voltage; an inverting driver that generates a control signal of an inverted logic of an analog voltage based on the first boost signal and the second boost signal; a non-inverting driver that generates a true logic control signal of an analog voltage based on the first boost signal and the second boost signal; 3. The operational amplifier circuit of claim 1, comprising:

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