Power supply device and memory system

Abstract

To provide a power supply device or the like capable of suppressing power consumption.SOLUTION: A power supply device according to one embodiment of the present invention includes: a power supply terminal to which an input voltage is supplied from an external device; a first step-down circuit that generates a first output voltage supplied to a memory device; a second step-down circuit that generates a second output voltage supplied to the memory device; a first connection line that connects between the power supply terminal and the first step-down circuit; a second connection line that connects between the power supply terminal and the second step-down circuit; a booster circuit that is arranged between the power supply terminal and the first step-down circuit on the first connection line, and boosts the input voltage supplied from the power supply terminal; a switch element arranged between the booster circuit and the first step-down circuit on the first connection line; a capacitive element arranged between the switch element and the first step-down circuit on the first connection line; and a first back-flow prevention diode arranged between the power supply terminal and the second step-down circuit on the second connection line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power supply unit that generates a voltage to be supplied to a memory device, and to a memory system that includes such a power supply unit and a memory device. [Background technology]

[0002] BACKGROUND ART Various memory systems have been proposed that include a memory device such as a flash memory and a power supply unit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6384306 Summary of the Invention [Problem to be solved by the invention]

[0004] In such memory systems, etc., there is a demand for reducing power consumption, and it is desirable to provide a power supply device and a memory system that can reduce power consumption. [Means for solving the problem]

[0005] A power supply apparatus according to one embodiment of the present invention is an apparatus for generating a voltage to be supplied to a memory device, and includes: a power supply terminal to which an input voltage is supplied from an external source; a first step-down circuit that generates a first output voltage to be supplied to the memory device; a second step-down circuit that generates a second output voltage to be supplied to the memory device; a first connection line connecting the power supply terminal and the first step-down circuit; a second connection line connecting the power supply terminal and the second step-down circuit; a step-up circuit arranged on the first connection line between the power supply terminal and the first step-down circuit and that steps up the input voltage supplied from the power supply terminal; a switch element arranged on the first connection line between the step-up circuit and the first step-down circuit; a capacitance element arranged on the first connection line between the switch element and the first step-down circuit; and a first backflow prevention diode arranged on the second connection line between the power supply terminal and the second step-down circuit.

[0006] A memory system according to one embodiment of the present invention includes the power supply apparatus according to the embodiment of the present invention and the memory device. [Effects of the Invention]

[0007] According to the power supply device and memory system according to an embodiment of the present invention, it is possible to reduce power consumption. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing an example of a schematic configuration of a memory system according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing a schematic configuration of a memory system according to a comparative example. [Figure 3] FIG. 3 is a timing diagram illustrating an example of the operation of the memory system shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing an example of an operating state during normal operation in FIG. [Figure 5] FIG. 5 is a circuit diagram showing an example of an operating state when the power supply in FIG. 3 is shut off. [Figure 6] FIG. 6 is a circuit diagram showing a schematic configuration example of a memory system according to the first modification of the present invention. [Figure 7] FIG. 7 is a timing diagram illustrating an example of the operation of the memory system shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing an example of an operating state during normal operation in FIG. [Figure 9] FIG. 9 is a circuit diagram showing an example of an operating state when the power supply in FIG. 7 is cut off. [Figure 10] FIG. 10 is a circuit diagram showing a schematic configuration example of a memory system according to the second modification of the present invention. [Figure 11] FIG. 11 is a circuit diagram showing an example of an operating state during normal operation in FIG. [Figure 12] FIG. 12 is a circuit diagram showing an example of an operating state when the power supply in FIG. 10 is cut off. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The description will be made in the following order: 1. Embodiment (Application to a memory system including a flash memory and a power supply unit) 2. Variations Modification 1 (Example of a case where the timings at which the output voltages are supplied are synchronized) Modification 2 (Example of a case where a part of the circuit configuration in the power supply device is changed) 3. Other Modifications

[0010] <1. Embodiment> [composition] 1 is a circuit diagram showing an example of the schematic configuration of a memory system (memory system 4) according to an embodiment of the present invention. This memory system 4 is a system (flash memory system) that is applied to a memory device (flash memory device) such as a flash memory 21 described below. As shown in FIG. 1, the memory system 4 includes a power supply device 1, a flash memory 21, a memory controller 22, and a host I / F (interface) 3.

[0011] (Flash Memory 21, etc.) The flash memory 21 is a nonvolatile memory that stores (memorizes) data supplied from the outside (host) via a host I / F 3 (described later), as indicated by the arrow in Fig. 1. The memory controller 22 is a controller that writes data supplied from the host via the host I / F 3 to the flash memory 21 (write operation) and reads data stored in the flash memory 21 (read operation), as indicated by the arrow in Fig. 1.

[0012] The signal FBSY transmitted from the flash memory 21 to the memory controller 22 indicates whether the flash memory 21 is capable of accepting commands from the memory controller 22. Specifically, when FBSY="H (High)", the flash memory 21 is capable of accepting commands from the memory controller 22 (the flash memory 21 is accessible from the memory controller 22). On the other hand, when FBSY="L (Low)", the flash memory 21 is not capable of accepting commands from the memory controller 22 (the flash memory 21 is not accessible from the memory controller 22: Busy state). In such a Busy state, data received from the memory controller 22 is being written to cells in the flash memory 21 (write period). If the power is interrupted at this time (when the externally supplied voltage V1, described below, drops below a predetermined threshold), the data in the flash memory 21 is likely to be destroyed.

[0013] Here, the above-mentioned flash memory 21 and memory controller 22 each correspond to a specific example of a "memory device" in the present invention.

[0014] The host I / F 3 is an interface for data transfer between the memory system 4 (flash memory 21 and memory controller 22) and the host. In the case of an SSD (Solid State Drive) standard, examples of such a host I / F 3 include SATA (Serial Advanced Technology Attachment), PATA (Parallel Advanced Technology Attachment), and PCIe (Peripheral Component Interconnect-Express).

[0015] (Power supply 1) The power supply device 1 is a device that generates voltages (voltages V2a to V2c, which will be described later) to be supplied to the above-mentioned memory devices (flash memory 21 and memory controller 22). As shown in Fig. 1, the power supply device 1 includes a power supply terminal Tin, connection lines L1 to L3, a voltage boost circuit 11, multiple (three) voltage drop circuits 12a to 12c, an AND (logical product) circuit 132, voltage detection circuits 14a and 14b, a switch element SW, a capacitor C, diodes D1 and D2, and dummy resistors Ra to Re.

[0016] Here, connection line L1 corresponds to a specific example of a "first connection line" in the present invention, connection line L2 corresponds to a specific example of a "second connection line" in the present invention, and connection line L3 corresponds to a specific example of a "third connection line" in the present invention. Furthermore, step-down circuit 12a corresponds to a specific example of a "first step-down circuit" in the present invention, and step-down circuits 12b and 12c each correspond to a specific example of a "second step-down circuit" in the present invention. Furthermore, voltage detection circuit 14a corresponds to a specific example of a "voltage detection circuit" in the present invention, and capacitor C corresponds to a specific example of a "capacitor" in the present invention. Furthermore, diode D1 corresponds to a specific example of a "first backflow prevention diode" in the present invention, and diode D2 corresponds to a specific example of a "second backflow prevention diode" in the present invention.

[0017] 1, the power supply terminal Tin is a terminal to which a voltage V1 (host supply voltage) is supplied from the outside (host) of the memory system 4. Note that this voltage V1 is, for example, 3.3V.

[0018] The connection line L1 connects the power supply terminal Tin to the step-down circuit 12a (described later), and the connection line L2 connects the power supply terminal Tin to the step-down circuits 12b and 12c (described later). The connection line L3 connects the output side of the step-down circuit 12a (connection point P3 in FIG. 1) to the input side of the step-down circuits 12b and 12c (connection point P4 in FIG. 1). Specifically, as shown in FIG. 1, the connection line L1 is connected from the power supply terminal Tin to the step-down circuit 12a via the connection point P1, the boost circuit 11, the switch element SW, and the connection point P2, in that order. The connection line L2 is connected from the power supply terminal Tin to the step-down circuits 12b and 12c via the diode D1 and the connection point P4, in that order. The connection line L3 is connected from the connection point P3 to the connection point P4 via the diode D2.

[0019] As described above, the boost circuit 11 is disposed on the connection line L1 (between the power supply terminal Tin and the step-down circuit 12a), and is a circuit that boosts the voltage V1 (e.g., 3.3 V) supplied from the power supply terminal Tin and outputs the boosted voltage V2 (boosted voltage: e.g., 5 V). This voltage V2 is a voltage for power supply backup when the power supply is shut off (when the voltage V1 drops below a predetermined threshold), which will be described later, and is stored as an electric charge in a capacitor C, which will be described later.

[0020] 1, the step-down circuits 12a to 12c are circuits that step down the voltage supplied via any of the above-mentioned connection lines L1 to L3 to generate voltages V2a to V2c (step-down voltages) to be supplied to the flash memory 21 and the memory controller 22. Specifically, the step-down circuit 12a steps down the voltage V2 (the step-up voltage output from the step-up circuit 11) supplied via the connection line L1 to generate voltage V2a, and supplies this voltage to the flash memory 21 and the memory controller 22, respectively. The step-down circuit 12b steps down the voltage supplied via the connection line L2 or the connection line L3 to generate voltage V2b, and supplies this voltage to the memory controller 22. The step-down circuit 12c steps down the voltage supplied via the connection line L2 or the connection line L3 to generate voltage V2c, and supplies this voltage to the flash memory 21 and the memory controller 22, respectively.

[0021] In this manner, in this embodiment, the voltages V2a to V2c output from the plurality of step-down circuits 12a to 12c have different voltage values that are suited to the memory devices (flash memory 21 and memory controller 22). Specifically, in the example of FIG. 1, the voltages V2a to V2c satisfy the magnitude relationship V2a ≥ V2b ≥ V2c. In addition, in the example of FIG. 3, which will be described later, the voltages V2b and V2c output from the step-down circuits 12b and 12c are lower than the voltage V2a output from the step-down circuit 12a (V2b, V2c <V2a)。

[0022] Here, the voltage V1 corresponds to a specific example of the "input voltage" in the present invention. The voltage V2a corresponds to a specific example of the "first output voltage" in the present invention, and the voltages V2b and V2c each correspond to a specific example of the "second output voltage" in the present invention.

[0023] As shown in FIG. 1, the voltage detection circuit 14a detects the voltage V1 supplied from the power supply terminal Tin via the connection point P1. Furthermore, as will be described in detail later, the voltage detection circuit 14a outputs a signal V1_EN (="L" or "H") depending on the magnitude of the detected voltage V1 (depending on the magnitude relationship between the voltage V1 and a predetermined threshold voltage Vth). When the signal V1_EN is "L", a switch element SW (described later) is set to the OFF state (shutdown state), and the boost circuit 11 is set to the stopped state. On the other hand, when the signal V1_EN is "H", the switch element SW is set to the ON state, and the boost circuit 11 is set to the operative state. By setting the ON / OFF state of the switch element SW in this manner, the power supply path (power supply routes Rp1 to Rp3 (described later)) within the power supply device 1 is controlled.

[0024] 1, the voltage detection circuit 14b is a circuit that detects the voltage V2a output from the step-down circuit 12a. Furthermore, this voltage detection circuit 14b outputs a signal FWP (="L" or "H") depending on the magnitude of the detected voltage V2a. When this signal FWP="L", a data write operation to the flash memory 21 is prohibited, and when the signal FWP="H", a data write operation to the flash memory 21 is permitted (write prohibition is lifted).

[0025] 1, the AND circuit 132 is a circuit that outputs a signal POR, which is a logical product (AND) signal of the signal V1_EN output from the voltage detection circuit 14a and the signal FWP output from the voltage detection circuit 14b, to the memory controller 22. When this signal POR="L", the operation of the memory controller 22 is stopped, and when the signal POR="H", the operation of the memory controller 22 is permitted (the operation stop is released).

[0026] 1, the switch element SW is disposed on the connection line L1 between the boost circuit 11 and the step-down circuit 12a (between the boost circuit 11 and the connection point P2). The switch element SW is set to an ON state or an OFF state by a signal V1_EN output from the voltage detection circuit 14a.

[0027] Such a switch element SW is configured using a switch element having a backflow prevention function.

[0028] 1, capacitor C is a capacitive element (large-capacity capacitor) arranged on connection line L1 between switch element SW and step-down circuit 12a. Specifically, one end of capacitor C is connected to connection point P2, and the other end of capacitor C is connected to ground. This capacitor C is a backup capacitor for supplying charge to flash memory 21 and memory controller 22 when power is interrupted (when voltage V1 drops below a predetermined threshold), as will be described in detail later. When such a power interruption occurs, charge is supplied from capacitor C to step-down circuits 12a to 12c, thereby ensuring power supply when flash memory 21 is in a busy state and preventing data corruption in flash memory 21.

[0029] The diodes D1 and D2 are each a diode (backflow prevention diode) for preventing the reverse flow of charge, and are configured, for example, by a Schottky diode or an ideal diode. As shown in FIG. 1, the diode D1 is disposed on the connection line L2 between the power supply terminal Tin and the step-down circuits 12b and 12c (between the connection points P1 and P4). Specifically, on the connection line L2, the anode of the diode D1 is disposed on the connection point P1 side, and the cathode of the diode D1 is disposed on the connection point P4 side. On the other hand, the diode D2 is disposed on the connection line L3 (between the connection points P3 and P4). Specifically, on the connection line L3, the anode of the diode D2 is disposed on the connection point P3 side, and the cathode of the diode D2 is disposed on the connection point P4 side.

[0030] Each of the dummy resistors Ra to Re is a resistive element for discharging excess charge. As shown in FIG. 1, the dummy resistor Ra is arranged between the output line of the voltage V2a from the step-down circuit 12a and ground. Similarly, the dummy resistor Rb is arranged between the output line of the voltage V2b from the step-down circuit 12b and ground, and the dummy resistor Rc is arranged between the output line of the voltage V2c from the step-down circuit 12c and ground. Furthermore, the dummy resistor Rd is arranged between the input line (connection point P4) of each of the step-down circuits 12b and 12c and ground, and the dummy resistor Re is arranged in parallel with the capacitor C between the connection point P2 and ground.

[0031] [Operation, Actions and Effects] Next, with reference to FIGS. 2 to 5 in addition to FIG. 1, an example of operation of the present embodiment (an example of operation of the memory system 4 and the power supply device 1) will be described in detail in comparison with a comparative example.

[0032] (A. Comparative example) Fig. 2 is a circuit diagram showing the schematic configuration of a memory system (memory system 104) according to a comparative example. Memory system 104 of this comparative example corresponds to memory system 4 of the present embodiment shown in Fig. 1, except that power supply device 101 is provided instead of power supply device 1. As shown in Fig. 2, power supply device 101 of this comparative example includes a power supply terminal Tin, four step-down circuits 91a to 91d, a voltage detection circuit 92, a discharge circuit 93, a step-up circuit 94, voltage detection circuits 95 to 97, a switch element SW, a capacitor C, diodes D1 and D2, and dummy resistors Ra to Rd.

[0033] In this power supply device 101, a voltage V1 supplied to a power supply terminal Tin is detected by voltage detection circuits 95 and 96, and a signal POR is supplied from the voltage detection circuit 95 to the memory controller 22. Meanwhile, a signal VA_EN is supplied from the voltage detection circuit 96 to each of the switch element SW and the boost circuit 94, thereby controlling the on / off state of the switch SW and setting the boost circuit 94 to an active or inactive state. The voltage obtained from the power supply terminal Tin via a diode D1 is boosted by the boost circuit 94. The boosted voltage (voltage V2) output from the boost circuit 94 via the switch element SW is supplied to a capacitor C and also to each of the discharge circuit 93 and the step-down circuits 91a-91d via a diode D2. The voltages supplied to the step-down circuits 91a-91d are detected by a voltage detection circuit 92, and a signal VB_EN output from the voltage detection circuit 92 is supplied to the discharge circuit 93 and the step-down circuits 91a-91d. The step-down circuits 91a to 91d step down the supply voltages described above, and output the voltages as voltages V3a, V3b, V3c, and V3d to the flash memory 21 and memory controller 22. The voltage detection circuit 97 detects the voltage V3a, and supplies a signal FWP to the flash memory 21. Dummy resistors Ra to Rd are disposed between the output lines of the step-down circuits 91a to 91d and ground, respectively.

[0034] In the power supply device 101 configured as described above, the step-down circuits 91a to 91d generate voltages required for the flash memory 21 and the memory controller 22 based on the voltage V1 supplied from the outside (host) to the power supply terminal Tin. At this time, as described above, the capacitor C is charged using the voltage V2 boosted by the boost circuit 94.

[0035] In this power supply device 101, when a drop in voltage V1 (a power cutoff) is detected by the voltage detection circuits 95 and 96, the operation of the memory controller 22 is stopped by a signal POR output from the voltage detection circuit 95. Furthermore, when such a drop in voltage V1 is detected, a signal VA_EN output from the voltage detection circuit 96 switches the switch element SW from the ON state to the OFF state. Then, the charge stored in the capacitor C (large-capacity capacitor) is supplied to each of the step-down circuits 91a-91d via the diode D2, thereby ensuring the power supply voltage. In this way, the power supply voltage of each of the step-down circuits 91a-91d is ensured during the busy state of the flash memory 21 (the period during which data is written to the cells), and thus the data written during the busy state is guaranteed even during the power cutoff described above.

[0036] However, in the power supply device 101 (memory system 104) of this comparative example, as shown in FIG. 2, the boosted voltage from the boost circuit 94 is set to be supplied to all (four) of the step-down circuits 91a to 91d, which increases the operating load on the boost circuit 94 and may result in increased power consumption.

[0037] (B. Operation Example of This Embodiment) In contrast to this, in the memory system 4 of this embodiment, the circuit configuration shown in FIG. 1 is configured to perform, for example, the following operations.

[0038] FIG. 3 is a timing diagram illustrating an example of operation of the memory system 4 shown in FIG. 1 (operation examples during normal operation, "Power_Down," and "Power_UP," which will be described later). Specifically, FIG. 3(A) collectively illustrates the voltages V1, V2, V2a-V2c, and VL, which will be described later. FIG. 3(B) illustrates the signal V1_EN, and FIG. 3(C) illustrates the on / off state of the switch element SW. FIGS. 3(D), 3(E), and 3(G) illustrate the signals FWP, POR, and FBSY, respectively, and FIG. 3(F) illustrates data (DATA) supplied to the flash memory 21. The horizontal axis in FIG. 3 represents time t, and timings t1 to t7 along this time t are shown in FIG. 3.

[0039] 4 is a circuit diagram showing an example of the operating state during normal operation in FIG. 3 (when voltage V1≧threshold voltage Vth (the period from timing t2 to t6 in FIG. 3)). Meanwhile, FIG. 5 is a circuit diagram showing an example of the operating state during power-off in FIG. 3 (when voltage V1<threshold voltage Vth (the period after timing t6 in FIG. 3)). The period up to timing t2 shown in FIG. 3 corresponds to the above-mentioned "Power_UP" state (voltage V1<threshold voltage Vth). In addition, in FIGS. 4 and 5, the power supply routes Rp1 to Rp3 described below are indicated by arrows.

[0040] (B-1. During normal operation) First, during the normal operation shown in FIG. 3, the memory system 4 of this embodiment operates as shown in FIG. 4, for example.

[0041] That is, during this normal operation, the voltage V1 supplied to the power supply terminal Tin is equal to or higher than a predetermined threshold voltage Vth (e.g., 2.7 V) (V1≧Vth: see FIGS. 3A and 3B), and therefore the signal V1_EN is set to “H.” Therefore, the voltage detection circuit 14a sets the switch element SW to the on state (see FIG. 3C), and sets the boost circuit 11 to the operating state. Then, as shown in FIG. 4, the power supply device 1 is provided with the following two power supply routes Rp1 and Rp2.

[0042] In the power supply route Rp1, based on the supply voltage (boosted voltage V2 output from the boost circuit 11) to the step-down circuit 12a from the power supply terminal Tin via the connection line L1, a voltage V2a is supplied from this step-down circuit 12a to the flash memory 21 and the memory controller 22 (see FIG. 4). That is, during normal operation, the power supply route Rp1 is used to supply the voltage V2a to the flash memory 21 and the memory controller 22. Also during normal operation, the power supply route Rp1 is used to supply the boosted voltage V2 output from the boost circuit 11 to the step-down circuit 12a and also to the capacitor C, thereby charging the capacitor C (see FIG. 4).

[0043] On the other hand, in the power supply route Rp2, based on the supply voltage (voltage VL after passing through diode D1) to the step-down circuits 12b and 12c from the power supply terminal Tin via connection line L2, voltages V2b and V2c are supplied from the step-down circuits 12b and 12c to the flash memory 21 and memory controller 22, respectively (see FIG. 4). That is, during normal operation, voltages V2b and V2c are supplied to the flash memory 21 and memory controller 22, respectively, using this power supply route Rp2.

[0044] Furthermore, during this normal operation, the voltage V2a is monitored by the voltage detection circuit 14b, and when it is confirmed that the voltage V2a is sufficient to power the flash memory 21, the signal FWP becomes "H" (see FIG. 3(D)). Then, since the signal V1_EN is "H" as described above, the signal POR output from the AND circuit 132 becomes "H" (see FIG. 3(E)), and the memory controller 22 is set to an operating state. Therefore, for example, as shown in FIGS. 3(F) and 3(G), data is written to cells in the flash memory 21 based on the data (DATA: Write Data_A, Write Data_B) supplied to the flash memory 21 during the period when the signal FBSY is "L".

[0045] During this normal operation, the following magnitude relationship is set to be satisfied so that voltage V2a output from step-down circuit 12a is not supplied to step-down circuits 12b and 12c via diode D2 (see the dashed arrow near diode D2 in FIG. 4): In other words, during this normal operation, unlike when the power is shut off as described below, power is not supplied from step-down circuit 12a to step-down circuits 12b and 12c using power supply route Rp3 (see FIG. 4). (V2a-D2_Vf) <VL(=V1-D1_Vf) (D1_Vf, D2_Vf: forward voltage of diodes D1 and D2)

[0046] (B-2. When power is cut off) Furthermore, when the power supply is shut off as shown in FIG. 3, the memory system 4 of this embodiment operates as shown in FIG. 5, for example.

[0047] That is, when the power supply is cut off, the voltage V1 supplied to the power supply terminal Tin is less than the above-described threshold voltage Vth (V1 < Vth: refer to FIGS. 3(A) and 3(B)), so the signal V1_EN = "L". Therefore, the voltage detection circuit 14a sets the switch element SW to the off state (refer to FIG. 3(C)), and at the same time, sets the operation of the boost circuit 11 to the stop state. Further, since the above-described signal V1_EN = "L", the signal POR output from the AND circuit 132 becomes "L" (refer to FIG. 3(E)), and the operation of the memory controller 22 is also set to the stop state.

[0048] Then, as shown in FIG. 5 when the power supply is cut off, the following operations are performed using the above-described power supply route Rp1 and the following power supply route Rp3. That is, the power stored in the capacitor C is supplied to the step-down circuit 12a, and the voltage V2a is supplied from this step-down circuit 12a to the flash memory 21 and the memory controller 22 (refer to FIG. 5). Further, the power stored in the capacitor C is supplied to the step-down circuits 12b and 12c via the connection line L3 (diode D2). Based on the power (supply voltage) supplied to these step-down circuits 12b and 12c, the voltages V2b and V2c are respectively supplied from these step-down circuits 12b and 12c to the flash memory 21 and the memory controller 22 (refer to FIG. 5). That is, when the power supply is cut off, the voltage V2a is supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp1, and the voltages V2b and V2c are respectively supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp3.

[0049] Note that when the power supply is cut off, as described above, since the switch element SW is set to the off state, the power stored in the capacitor C does not escape to the host side via the power supply terminal Tin. Further, when the power supply is cut off, since the voltage V2a output from the step-down circuit 12a is supplied to the step-down circuits 12b and 12c via the power supply route Rp3 (diode D2), it is set to satisfy the following magnitude relationship, which is opposite to the above-described normal operation. (V2a-D2_Vf)>VL(=V1-D1_Vf)

[0050] Thus, in this embodiment, even when the power is cut off ("Power_Down"), the following occurs during the busy period of the flash memory 21 (the period during which data is written to the cells). That is, each power supply voltage (the voltages V2a to V2c described above) is maintained for a certain period (see timings t6 to t7 in FIG. 3A). Note that the capacitor C (large-capacity capacitor) has a capacity that can maintain a voltage for a period longer than the busy period of the flash memory 21 (the period during which data is written to the cells). Therefore, even if the power is cut off as described above during the period during which data is written to the cells in the flash memory 21, the data is guaranteed.

[0051] In the comparative example described above, the switch element SW is switched from the on state to the off state, and then the charge stored in the capacitor C (large-capacity capacitor) is supplied to the step-down circuits 91a to 91d via the diode D2. Also in this embodiment, when a power interruption occurs, the switch element SW only serves to separate the step-up circuit 11 side from the capacitor C and step-down circuit 12a side, and the charge stored in the capacitor C is not supplied via this switch element SW. In other words, because charge is continuously supplied from the capacitor C, no delay due to switching of the switch element SW occurs in this embodiment as in the comparative example.

[0052] As described above, when the power supply is shut down, the operation of the memory controller 22 (such as internal operations and communication with the flash memory 21) is stopped. At this time, the load on the voltage V1 is suddenly reduced, which may cause the voltage V1 to momentarily rise. In this case, the voltage detection circuit 14a may react to the instantaneous rise in the voltage V1 and switch the signal POR from "L" to "H," which may cause the switch element SW to malfunction. Therefore, when the voltage detection circuit 14a detects the voltage V1, for example, hysteresis may be applied to the threshold voltage Vth. Specifically, when the voltage V1 rises, the voltage detection circuit 14a switches the signal V1_EN from "L" to "H" if the voltage V1 exceeds the threshold voltage Vth1 (=2.75 V). On the other hand, when the voltage V1 drops, the voltage detection circuit 14a switches the signal V1_EN from "H" to "L" when the voltage V1 falls below the threshold voltage Vth2 of 2.65 V. In this way, when hysteresis is provided for the threshold voltage Vth, it is possible to prevent the above-mentioned malfunction.

[0053] The power supply route Rp1 corresponds to a specific example of a "first power supply route" in the present invention, the power supply route Rp2 corresponds to a specific example of a "second power supply route" in the present invention, and the power supply route Rp3 corresponds to a specific example of a "third power supply route" in the present invention.

[0054] (C. Actions and Effects) In this embodiment, the step-down circuits 12a to 12c, the step-up circuit 11, the switch element SW, the capacitor C, and the diode D1 are arranged on the connection lines L1 and L2 in the above-described configuration. As a result, when the step-down circuits 12a to 12c supply the voltages V2a to V2c to the flash memory 21 and the memory controller 22 (power supply) based on the voltage V1 supplied from the power supply terminal Tin, the following occurs. That is, the boosted voltage V2 output from the step-up circuit 11 is supplied to the step-down circuit 12a and the capacitor C via the connection line L1, while the voltage is supplied to the step-down circuits 12b and 12c via the connection line L2 (diode D1). That is, the voltage V2 (boosted voltage) output from the step-up circuit 11 is supplied only to the step-down circuit 12a out of the step-down circuits 12a, 12b, and 12c. As a result, in this embodiment, the operational load on the boost circuit 11 is reduced compared to the case where the boost voltage is supplied to all of the multiple step-down circuits, as in the comparative example described above, etc. As a result, in this embodiment, it is possible to reduce the power consumption in the power supply device 1 and the memory system 4 compared to the comparative example.

[0055] In addition, in the present embodiment, the above three power supply routes Rp1 to Rp3 are provided respectively. During normal operation (when V1 ≥ Vth), based on the voltage V1, the voltage V2a is supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp1, and based on the same voltage V1, the voltages V2b and V2c are respectively supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp2. On the other hand, during power-off (when V1 < Vth), since power supply based on the voltage V1 cannot be expected, the voltage V2a is supplied to the flash memory 21 and the memory controller 22 from the capacitor C using the power supply route Rp1. Also, the voltage V2a is supplied to the step-down circuits 12b and 12c using the power supply route Rp3 from the step-down circuit 12a via the diode D2, so that the voltages V2b and V2c are respectively supplied to the flash memory 21 and the memory controller 22. In this way, according to the magnitude relationship between the voltage V1 and the threshold voltage Vth, the power supply routes Rp1 to Rp3 to be used are switched, so that the power consumption in the power supply device 1 and the memory system 4 can be effectively suppressed.

[0056] <2. Modified Example> Subsequently, modified examples (modified examples 1 and 2) of the above embodiment will be described. In the following, the same components as those in the embodiment are denoted by the same reference numerals, and the description will be omitted as appropriate.

[0057] [Modified Example 1] (Configuration) FIG. 6 shows a schematic configuration example of a memory system (memory system 4A) according to Modified Example 1 of the present invention, represented by a circuit diagram. The memory system 4A of this Modified Example 1 corresponds to the memory system 4 of the embodiment in which a power supply device 1A is provided instead of the power supply device 1. Also, this power supply device 1A corresponds to the power supply device 1 (see FIG. 1) of the embodiment in which a voltage detection circuit 14c described below is further provided, and the other configurations are basically the same.

[0058] As shown in FIG. 6, the voltage detection circuit 14c detects the voltage at a point (connection point P2) on the connection line L1 between the switch element SW and the step-down circuit 12a. The voltage detection circuit 14c outputs a signal P_EN (="L" or "H") depending on the magnitude of the detected voltage. When the signal P_EN="L", the step-down circuits 12a to 12c are set to a stopped state, and the voltages V2a to V2c are not output. On the other hand, when the signal P_EN="H", the step-down circuits 12a to 12c are set to an operating state, and the voltages V2a to V2c are output. In this way, the operating state and the stopped state of the step-down circuits 12a to 12c are set together, and the supply timings (and stop timings) of the voltages V2a to V2c from the step-down circuits 12a to 12c are controlled to be synchronized, as will be described in detail later.

[0059] (operation) Next, an example of operation of this modified example (an example of operation of the memory system 4A and the power supply device 1A) will be described in detail with reference to FIGS. 7 to 9 in addition to FIG.

[0060] FIG. 7 is a timing diagram illustrating an example of operation of the memory system 4A shown in FIG. 6 (operational examples during the normal operation, "Power_Down," and "Power_UP" states described above). Specifically, FIG. 7(A) collectively illustrates the voltages V1, V2, V2a-V2c, and VL described above. FIG. 7(B) illustrates the signal V1_EN described above, FIG. 7(C) illustrates the on / off state of the switch element SW, and FIG. 7(D) illustrates the signal P_EN described above. FIGS. 7(E), 7(F), and 7(H) respectively illustrate the signals FWP, POR, and FBSY described above, and FIG. 7(G) illustrates the data (DATA) supplied to the flash memory 21. The horizontal axis in FIG. 7 represents time t, and timings t1 to t7 along this time t are shown in FIG. 7.

[0061] 8 is a circuit diagram showing an example of the operating state during normal operation in FIG. 7 (when voltage V1≧threshold voltage Vth (the period from timing t2 to t6 in FIG. 7)). Meanwhile, FIG. 9 is a circuit diagram showing an example of the operating state during power-off in FIG. 7 (when voltage V1<threshold voltage Vth (the period from timing t6 onward in FIG. 7)). The period up to timing t2 shown in FIG. 7 corresponds to the above-mentioned "Power_UP" state (voltage V1<threshold voltage Vth). In addition, in FIGS. 8 and 9, the above-mentioned power supply routes Rp1 to Rp3 are respectively indicated by arrows.

[0062] The memory system 4A of this modified example also operates basically in the same manner as the memory system of the above-described embodiment.

[0063] First, during normal operation (when V1≧Vth) shown in Fig. 7, the memory system 4A operates in the same manner as in the embodiment (Fig. 4), for example, as shown in Fig. 8. That is, during this normal operation, a voltage V2a is supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp1, and the capacitor C is charged based on the voltage V2 output from the boost circuit 11. Also during this normal operation, voltages V2b and V2c are supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp2.

[0064] In this modification, as described above, the signal P_EN output from the voltage detection circuit 14c is used to control the timing at which the voltages V2a to V2c are supplied (and stopped) to the flash memory 21 and the memory controller 22. That is, the timing at which the voltage V2a is supplied from the step-down circuit 12a and the timing at which the voltages V2b and V2c are supplied from the step-down circuits 12b and 12c are respectively controlled to be synchronized (for example, see the timing within symbol P11 shown in FIG. 7).

[0065] On the other hand, when the power supply is cut off as shown in FIG. 7 (when V1 < Vth), in the memory system 4A, as in the case of the embodiment (FIG. 5), for example, as shown in FIG. 9, the operation is performed. That is, when the power supply is cut off, the voltage V2a is supplied to the flash memory 21 and the memory controller 22 based on the stored charge in the capacitor C using the power supply route Rp1. Also, the voltages V2b and V2c are supplied to the flash memory 21 and the memory controller 22 respectively using the power supply route Rp3.

[0066] (Operation and Effect) Even in such a modified example, basically, the same operation as in the embodiment is performed, and the same effects can be obtained. That is, even in this modified example, compared with the above-described comparative example, it is possible to suppress the power consumption in the power supply device 1A and the memory system 4A.

[0067] Also, particularly in this modified example, as described above, since the timing at which the voltage V2a is supplied from the step-down circuit 12a and the timings at which the voltages V2b and V2c are supplied from the step-down circuits 12b and 12c respectively are controlled to be aligned with each other, the following occurs. That is, without waiting for the rising time of each voltage (voltages V2a to V2c) used inside the flash memory 21 and the memory controller 22, it is possible to prepare for the host system as a storage device in a minimum amount of time.

[0068] [Modified Example 2] (Configuration) FIG. 10 is a schematic configuration example of a memory system (memory system 4B) according to a modified example 2 of the present invention, represented by a circuit diagram. The memory system 4B of this modified example 2 corresponds to the memory system 4 of the embodiment in which a power supply device 1B is provided instead of the power supply device 1, and the other configurations are the same.

[0069] The power supply device 1B corresponds to the power supply device 1 with a partial change in the circuit configuration (wiring connection configuration) on the output side of the step-down circuit 12a, but the other configurations are the same. Specifically, in the power supply device 1 (see FIG. 1), the anode side (connection point P3) of the diode D2 on the output side of the step-down circuit 12a is connected to one end of the dummy resistor Ra. In contrast, in the power supply device 1B (see FIG. 10), the cathode side (connection point P4) of the diode D2 on the output side of the step-down circuit 12a is connected to one end of the dummy resistor Ra.

[0070] (operation) With this configuration, memory system 4B (power supply unit 1B) operates as follows, unlike memory system 4 (power supply unit 1). Note that the following mainly describes the differences between the operation example of memory system 4B (power supply unit 1B) and the operation example of memory system 4 (power supply unit 1) (see FIGS. 4 and 5).

[0071] Fig. 11 is a circuit diagram showing an example of the operating state during normal operation (when voltage V1≧threshold voltage Vth) described above in Fig. 10. On the other hand, Fig. 12 is a circuit diagram showing an example of the operating state during power-off (when voltage V1<threshold voltage Vth) described above in Fig. 10.

[0072] First, during normal operation shown in FIG. 11, unlike power supply device 1, power supply device 1B is in a state where (the voltage on the cathode side of diode D1 is greater than the voltage on the cathode side of diode D2), and therefore voltage V2a is not supplied from step-down circuit 12a to flash memory 21 or memory controller 22. That is, during normal operation in power supply device 1B, voltage VL after passing through diode D1 is supplied to flash memory 21 and memory controller 22 via the connection line of dummy resistor Ra using power supply route Rp2 (see FIG. 11). Also during normal operation in power supply device 1B, voltages V2b and V2c are supplied from step-down circuits 12b and 12c to flash memory 21 and memory controller 22, respectively, using power supply route Rp2, just as during normal operation in power supply device 1 (see FIG. 4).

[0073] On the other hand, during the power-off state shown in FIG. 12, unlike the power supply device 1, the power supply device 1B is in a state where (the voltage at the cathode side of diode D1 is less than the voltage at the cathode side of diode D2), and therefore voltages V2a, V2b, and V2c are supplied to the flash memory 21 and memory controller 22 via the power supply route Rp3. Specifically, during the power-off state in the power supply device 1B, unlike the power-off state in the power supply device 1 (see FIG. 5), the voltage output from the step-down circuit 12a and passing through the connection line L3 (diode D2) is supplied as voltage V2a to the flash memory 21 and memory controller 22 (see FIG. 12). Note that voltages V2b and V2c output from the step-down circuits 12b and 12c based on the voltage from the step-down circuit 12a passing through the connection line L3 are supplied to the flash memory 21 and memory controller 22, respectively, in the same manner as during the power-off state in the power supply device 1.

[0074] (Actions and Effects) In this modified example, the same effects as those of the embodiment can be obtained by basically operating in the same manner. That is, in this modified example, it is possible to reduce the power consumption of the power supply device 1B and the memory system 4B compared to the comparative example described above.

[0075] Furthermore, particularly in this modification, as described above, during normal operation, the voltage VL and the voltages V2b and V2c after passing through the diode D1 are supplied to the flash memory 21 and the memory controller 22 using the power supply route Rp2 instead of the power supply route Rp1 as in the embodiment. As a result, in this modification, the load on the boost circuit 11 is reduced compared to the embodiment, and the specifications (current capacity) of the boost circuit 11 can be reduced.

[0076] <3. Other Modifications> Although the present invention has been described above by way of embodiments and modifications, the present invention is not limited to the above-described embodiments, and various modifications are possible.

[0077] For example, in the above embodiments, specific circuit configurations of the memory system and power supply device have been given and explained, but the present invention is not limited to the examples of the above embodiments, and other circuit configurations may be used, for example.

[0078] Specifically, in the above-described embodiment, an example has been described in which a plurality (two) of the "second step-down circuits" of the present invention are provided in the power supply device (step-down circuits 12b, 12c), but the present invention is not limited to this example. For example, the power supply device may be provided with only one "second step-down circuit" of the present invention, or may be provided with three or more "second step-down circuits."

[0079] Furthermore, in the above-described embodiment, an example has been described in which the "second reverse current prevention diode" (diode D2) and the "third power supply route" (power supply route Rp3) of the present invention are provided in the power supply device, but the present invention is not limited to this example. That is, for example, the "second reverse current prevention diode" and the "third power supply route" may not be provided in the power supply device.

[0080] Furthermore, in the above embodiments, as a specific example of a "memory device" in the present invention, an example in which a flash memory and a memory controller are each provided in a memory system has been described, but the present invention is not limited to this example. For example, the memory system may be provided with only one of the flash memory and the memory controller.

[0081] In addition, in the above embodiments, specific examples of operation of the memory system and power supply device are given and explained, but the operation examples are not limited to those explained in the above embodiments, and other operation examples may be used.

[0082] Furthermore, in the above embodiments, an example of a memory system (flash memory system) applied to a memory device (flash memory device) such as a flash memory has been described, but the present invention is not limited to this example. That is, for example, the memory system of the present invention may be applied to memory devices other than such flash memory devices.

[0083] Furthermore, the configuration examples described so far may be applied in any combination.

[0084] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0085] The present invention can also be configured as follows. (1) 1. An apparatus for generating a voltage to supply to a memory device, comprising: a power supply terminal to which an input voltage is supplied from an external source; a first step-down circuit that generates a first output voltage that is supplied to the memory device; a second step-down circuit that generates a second output voltage that is supplied to the memory device; a first connection line connecting the power supply terminal and the first step-down circuit; a second connection line connecting the power supply terminal and the second step-down circuit; a boost circuit that is arranged on the first connection line between the power supply terminal and the first step-down circuit and that boosts the input voltage supplied from the power supply terminal; a switch element disposed on the first connection line between the voltage step-up circuit and the first voltage step-down circuit; a capacitance element disposed on the first connection line between the switch element and the first step-down circuit; a first reverse current prevention diode disposed on the second connection line between the power supply terminal and the second step-down circuit; A power supply unit comprising: (2) a first power supply route, in which the first output voltage is supplied from the first step-down circuit to the memory device based on a supply voltage to the first step-down circuit via the first connection line; a second power supply route through which the second output voltage is supplied from the second step-down circuit to the memory device based on a supply voltage to the second step-down circuit via the second connection line; Each is provided The power supply device according to (1) above. (3) a third connection line connecting the output side of the first step-down circuit and the input side of the second step-down circuit; a second reverse current prevention diode disposed on the third connection line; Further provided with A third power supply route is further provided, through which the second output voltage is supplied from the second step-down circuit to the memory device based on a supply voltage to the second step-down circuit via the third connection line. The power supply device according to (2) above. (4) when the input voltage is equal to or greater than a threshold voltage, the first output voltage is supplied to the memory device using the first power supply route, and the second output voltage is supplied to the memory device using the second power supply route; When the input voltage is less than the threshold voltage, the first output voltage is supplied to the memory device using the first power supply route, and the second output voltage is supplied to the memory device using the third power supply route. The power supply device according to (3) above. (5) when the input voltage is equal to or higher than a threshold voltage, the voltage that has passed through the first backflow prevention diode and the second output voltage are each supplied to the memory device using the second power supply route; When the input voltage is less than the threshold voltage, the first and second output voltages are respectively supplied to the memory device using the third power supply route. The power supply device according to (3) above. (6) further comprising a voltage detection circuit for detecting the input voltage; The voltage detection circuit when the input voltage is equal to or higher than a threshold voltage, turning on the switch element so that the boosted voltage output from the boost circuit is supplied to each of the first step-down circuit and the capacitive element; When the input voltage is less than the threshold voltage, the switch element is set to an off state, thereby controlling so that the power stored in the capacitive element is supplied to the first step-down voltage circuit. The power supply device according to any one of (1) to (5) above. (7) The second output voltage output from the second step-down circuit is lower than the first output voltage output from the first step-down circuit. The power supply device according to any one of (1) to (6) above. (8) The timing at which the first output voltage is supplied from the first step-down circuit to the memory device and the timing at which the second output voltage is supplied from the second step-down circuit to the memory device are configured to be synchronized with each other. The power supply device according to any one of (1) to (7) above. (9) The memory device is at least one of a flash memory and a memory controller. The power supply device according to any one of (1) to (8) above. (10) The power supply device according to any one of (1) to (9) above; the memory device; A memory system comprising: [Explanation of symbols]

[0086] 1, 1A, 1B... power supply device, 11... step-up circuit, 12a to 12c... step-down circuit, 132... AND circuit, 14a to 14c... voltage detection circuit, 21... flash memory, 22... memory controller, 3... host I / F, 4, 4A, 4B... memory system, Tin... power supply terminal, SW... switch element, C... capacitor, D1, D2... diode, Ra to Re... dummy resistor, P1 to P4... connection point, L1 to L3... connection line, Rp1 to Rp3... power supply route, V1, V2, V2a to V2c, VL... voltage, Vth... threshold voltage, V1_EN, P_EL, FWP, POR, FBSY... signal, t... time, t1 to t7... timing.

Claims

1. 1. An apparatus for generating a voltage to supply to a memory device, comprising: a power supply terminal to which an input voltage is supplied from an external source; a first step-down circuit that generates a first output voltage that is supplied to the memory device; a second step-down circuit that generates a second output voltage that is supplied to the memory device; a first connection line connecting the power supply terminal and the first step-down circuit; a second connection line connecting the power supply terminal and the second step-down circuit; a boost circuit disposed on the first connection line between the power supply terminal and the first step-down circuit, and configured to boost the input voltage supplied from the power supply terminal; a switch element disposed on the first connection line between the voltage step-up circuit and the first voltage step-down circuit; a capacitance element disposed on the first connection line between the switch element and the first step-down circuit; a first backflow prevention diode disposed on the second connection line between the power supply terminal and the second step-down circuit; A power supply unit comprising:

2. a first power supply route, in which the first output voltage is supplied from the first step-down circuit to the memory device based on a supply voltage to the first step-down circuit via the first connection line; a second power supply route through which the second output voltage is supplied from the second step-down circuit to the memory device based on a supply voltage to the second step-down circuit via the second connection line; Each is provided The power supply device of claim 1 .

3. a third connection line connecting the output side of the first step-down circuit and the input side of the second step-down circuit; a second backflow prevention diode disposed on the third connection line; Further provided with A third power supply route is further provided, through which the second output voltage is supplied from the second step-down circuit to the memory device based on a supply voltage to the second step-down circuit via the third connection line. The power supply device according to claim 2 .

4. when the input voltage is equal to or greater than a threshold voltage, the first output voltage is supplied to the memory device using the first power supply route, and the second output voltage is supplied to the memory device using the second power supply route; When the input voltage is less than the threshold voltage, the first output voltage is supplied to the memory device using the first power supply route, and the second output voltage is supplied to the memory device using the third power supply route. The power supply device according to claim 3.

5. when the input voltage is equal to or higher than a threshold voltage, the voltage that has passed through the first backflow prevention diode and the second output voltage are each supplied to the memory device using the second power supply route; When the input voltage is less than the threshold voltage, the first and second output voltages are respectively supplied to the memory device using the third power supply route. The power supply device according to claim 3.

6. further comprising a voltage detection circuit for detecting the input voltage; The voltage detection circuit when the input voltage is equal to or higher than a threshold voltage, the switch element is set to an on state, thereby controlling so that the boosted voltage output from the boost circuit is supplied to each of the first step-down circuit and the capacitive element; When the input voltage is less than the threshold voltage, the switch element is set to an off state, thereby controlling so that the power stored in the capacitive element is supplied to the first step-down voltage circuit. The power supply device according to any one of claims 1 to 5.

7. The second output voltage output from the second step-down circuit is lower than the first output voltage output from the first step-down circuit. The power supply device according to any one of claims 1 to 5.

8. The timing at which the first output voltage is supplied from the first step-down circuit to the memory device and the timing at which the second output voltage is supplied from the second step-down circuit to the memory device are configured to be synchronized with each other. The power supply device according to any one of claims 1 to 5.

9. The memory device is at least one of a flash memory and a memory controller. The power supply device according to any one of claims 1 to 5.

10. The power supply device according to any one of claims 1 to 5; the memory device; A memory system comprising:

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