Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing a reduction in on-breakdown voltage.SOLUTION: A semiconductor device comprises: a source region and a drain region provided on a main surface of a semiconductor substrate; a gate insulating film provided on the main surface between the source region and the drain region; a gate electrode provided on the gate insulating film; first wiring electrically connected to the drain region; second wiring electrically connected to the gate electrode; and a first conductive film disposed between the first wiring and the second wiring in a plan view perpendicular to the main surface, and having a fixed potential.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A field effect transistor may be used as a high voltage element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-124206 [Patent Document 2] Japanese Patent Application Publication No. 60-260150 [Patent Document 3] Japanese Patent Application Publication No. 62-009645 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device including a conventional field effect transistor, the on-state breakdown voltage may decrease.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing a decrease in on-breakdown voltage. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a source region and a drain region provided on a main surface of a semiconductor substrate, a gate insulating film provided on the main surface between the source region and the drain region, a gate electrode provided on the gate insulating film, a first wiring electrically connected to the drain region, a second wiring electrically connected to the gate electrode, and a first conductive film provided between the first wiring and the second wiring in a plan view perpendicular to the main surface and having a fixed potential. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to suppress a decrease in on-breakdown voltage. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing the layout of wiring layers and conductive films in the semiconductor device according to the first embodiment. [Figure 3] FIG. 2 is an exploded view showing the layout of wiring layers and conductive films in the semiconductor device according to the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment. [Figure 6] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 10 is a diagram showing the results of a simulation. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present inventors have investigated the cause of the decrease in on-state breakdown voltage in conventional semiconductor devices assembled in a package. They have concluded that when a high voltage is applied to the drain of a semiconductor device assembled in a package, mobile charges in the package move onto a protective film near the drain, causing an electric field to spread from the mobile charges to the semiconductor substrate. Therefore, the present inventors have conducted further intensive research to suppress the spread of the electric field from the mobile charges, and have come up with the following embodiment.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0011] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor device. FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the layout of wiring layers and conductive films in the semiconductor device according to the first embodiment. FIG. 3 is an exploded view showing the layout of wiring layers and conductive films in the semiconductor device according to the first embodiment. FIG. 1 corresponds to a cross-sectional view taken along line II in FIG. 2.

[0012] The semiconductor device 100 according to the first embodiment has a p-type semiconductor substrate 10. The semiconductor substrate 10 has a main surface 10A. An n-type well 11 is provided in the main surface 10A, and a p-type well 12 is provided within the well 11 in the main surface 10A. An n-type source region 13 is provided within the well 12 in the main surface 10A. Furthermore, an n-type high-concentration well 14 having a high impurity concentration is provided within the well 11 at a distance from the well 12 in the main surface 10A. The well 11 and the high-concentration well 14 function as a drain region.

[0013] An insulating film 20 is provided on the main surface 10A, and openings 21 and 22 are formed in the insulating film 20. The source region 13, the well 12, and a portion of the well 11 are connected to each other and exposed through the opening 21, and the high-concentration well 14 is exposed through the opening 22. Inside the opening 21, a gate insulating film 31 is provided on the main surface 10A in contact with the wells 11 and 12. A gate electrode 32 is provided on the gate insulating film 31. A portion of the gate electrode 32 is on the insulating film 20. The gate electrode 32 is made of, for example, polycrystalline silicon.

[0014] An insulating film 91 is provided on the insulating film 20, the source region 13, the heavily doped well 14, and the gate electrode 32. The insulating film 91 is composed of a plurality of interlayer insulating films. The semiconductor device 100 has, in the insulating film 91, conductive vias 71, 72, and 73, a wiring layer 40, conductive vias 81, 82, and 83, a wiring layer 50, and a conductive film 61.

[0015] The wiring layer 40 is composed of a conductive film such as an aluminum (Al)-silicon (Si) alloy film. The wiring layer 40 includes regions 41, 42, 43, and 44. The region 41 is provided above the source region 13 and is electrically connected to the source region 13 by a conductive via 71. The region 42 is provided above the gate electrode 32 and is electrically connected to the gate electrode 32 by a conductive via 72. The region 43 is provided above the high-concentration well 14 and is electrically connected to the high-concentration well 14 by a conductive via 73. The region 44 is provided between the regions 42 and 43 in a plan view and is electrically floating. The wiring layer 40 is an example of a first wiring layer. The region 43 is an example of a first region, the region 42 is an example of a third region, and the region 44 is an example of a second conductive film.

[0016] The wiring layer 50 is composed of a conductive film such as an aluminum (Al)-silicon (Si) alloy film. The wiring layer 50 includes regions 51, 52, 53, and 54. Region 51 is provided above region 41 and is electrically connected to region 41 by a conductive via 81. Region 52 is provided above region 42 and is electrically connected to region 42 by a conductive via 82. Region 53 is provided above region 43 and is electrically connected to region 43 by a conductive via 83. Region 54 is provided between regions 52 and 53 in a plan view, and the potential of region 54 is fixed to a constant potential such as ground potential. The wiring layer 50 is an example of a second wiring layer. Region 53 is an example of a second region, region 52 is an example of a fourth region, and region 54 is an example of a first conductive film.

[0017] The conductive via 71, region 41, conductive via 81, and region 51 are electrically connected to the source region 13 and are included in the source wiring 101. The conductive via 72, region 42, conductive via 82, and region 52 are electrically connected to the gate electrode 32 and are included in the gate wiring 102. The conductive via 73, region 43, conductive via 83, and region 53 are electrically connected to the heavily doped well 14 and are included in the drain wiring 103. The drain wiring 103 is an example of a first wiring, and the gate wiring 102 is an example of a second wiring.

[0018] As shown in Figures 2 and 3, region 53 is provided in a disk shape, region 54 is provided annularly around region 53, region 52 is provided annularly around region 54, and region 51 is provided annularly around region 52. Region 43 is provided annularly. In plan view, the inner edge and outer edge of region 43 are inside the outer edge of region 53. Region 44 is provided annularly around region 43. In plan view, the inner edge of region 44 is inside the outer edge of region 53, and the outer edge is between the inner edge and outer edge of region 54. That is, in plan view, a portion of region 53 overlaps a portion of region 44, and a portion of region 54 overlaps a portion of region 44. Region 42 is provided annularly around region 44. In plan view, the inner edge of region 42 overlaps the inner edge of region 52, and the outer edge overlaps the outer edge of region 52. In plan view, the inner edge of region 42 does not have to overlap with the inner edge of region 52, and the outer edge does not have to overlap with the outer edge of region 52. Region 41 is provided in a ring shape around region 42. In plan view, the inner edge of region 41 overlaps with the inner edge of region 51, and the outer edge overlaps with the outer edge of region 51. In plan view, the inner edge of region 41 does not have to overlap with the inner edge of region 51, and the outer edge does not have to overlap with the outer edge of region 51.

[0019] In plan view, the conductive film 61 is provided between the drain wiring 103 and the gate wiring 102, and closer to the main surface 10A than the region 44. The conductive film 61 is electrically floating. The conductive film 61 is formed of, for example, polycrystalline silicon. The conductive film 61 is provided in a ring shape. In plan view, the inner edge of the conductive film 61 is between the inner edge and outer edge of the region 54 and between the inner edge and outer edge of the region 44, and the outer edge is between the inner edge and outer edge of the region 54. That is, in plan view, a part of the region 44 and a part of the conductive film 61 overlap each other, and the entire conductive film 61 is covered by the region 54. The conductive film 61 is an example of a third conductive film.

[0020] A protective film 92 is provided on the insulating film 91. The protective film 92 is, for example, a polyimide film.

[0021] As described above, in the semiconductor device 100, the region 54, whose potential is fixed to the ground potential or the like, is provided between the drain wiring 103 and the gate wiring 102 in a plan view. That is, a part of the area between the region 52 and the region 53 is shielded by the region 54. Therefore, even if mobile charges are generated on the surface of the protective film 92, the influence of the mobile charges on the part between the high-concentration well 14 of the well 11 and the well 12 can be suppressed, and a decrease in the on-breakdown voltage can be suppressed.

[0022] Furthermore, region 44 is provided between region 42 and region 43, and region 44 also serves to suppress the influence of mobile charges. If the distance between region 53 and region 54 is too small, dielectric breakdown may occur in insulating film 91 between region 53 and region 54. For this reason, regions 53 and 54 are preferably spaced apart enough to prevent dielectric breakdown. Region 44 is provided so as to overlap the gap between region 53 and region 54 in plan view, thereby suppressing the influence of mobile charges, particularly through the gap between region 53 and region 54. Furthermore, because region 44 is electrically floating, its potential fluctuates arbitrarily depending on the potentials of regions 43, 53, and 54, affecting the electric field of well 11 and suppressing a decrease in on-breakdown voltage.

[0023] In addition, the conductive film 61 is provided between the gate wiring 102 and the drain wiring 103, and the influence of the mobile charges can also be suppressed by the conductive film 61. Furthermore, since the conductive film 61 is electrically floating, its potential fluctuates arbitrarily depending on the potentials of the regions 42, 44, and 54, and affects the electric field of the well 11, thereby suppressing a decrease in the on-breakdown voltage.

[0024] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configurations of the wiring layer 40 and the conductive film 61. Fig. 4 is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment.

[0025] In the semiconductor device 200 according to the second embodiment, the outer edge of region 44 of the wiring layer 40 is closer to the outer edge of region 54 in plan view than in the first embodiment. Also, in plan view, the inner edge of conductive film 61 is between the outer edge of region 53 and the inner edge of region 54, and between the inner edge and outer edge of region 44, and the outer edge is between the inner edge and outer edge of region 54, and between the inner edge and outer edge of region 44. That is, in plan view, part of region 54 and part of conductive film 61 overlap, and the entire conductive film 61 is covered by region 44.

[0026] Other configurations of the second embodiment are similar to those of the first embodiment.

[0027] According to the second embodiment, it is also possible to suppress the influence of mobile charges, to influence the electric field of the well 11, and to suppress a decrease in the on-breakdown voltage.

[0028] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the wiring layer 40. Fig. 5 is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment.

[0029] In the semiconductor device 300 according to the third embodiment, the wiring layer 40 includes a region 45. The region 45 is provided in a ring shape between the region 42 and the region 44. In a plan view, the inner edge of the region 45 is between the inner edge and the outer edge of the region 54 and between the inner edge and the outer edge of the conductive film 61, and the outer edge is between the outer edge of the region 54 and the inner edge of the region 52 and outside the outer edge of the conductive film 61. The semiconductor device 300 also has a conductive via 74 and a conductive via 84 in the insulating film 91. The conductive via 74 electrically connects the conductive film 61 and the region 45, and the conductive via 84 electrically connects the region 45 and the region 54.

[0030] Other configurations of the third embodiment are similar to those of the first embodiment.

[0031] According to the third embodiment, it is also possible to suppress the influence of mobile charges, to influence the electric field of the well 11, and to suppress a decrease in the on-breakdown voltage.

[0032] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in that a conductive film is further included. Fig. 6 is a cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment.

[0033] The semiconductor device 400 according to the fourth embodiment has a conductive film 62 within an insulating film 91. The conductive film 62 is provided on the insulating film 20, between the drain wiring 103 and the gate wiring 102 in a plan view. The conductive film 62 is electrically floating. The conductive film 62 is formed of, for example, polycrystalline silicon. The conductive film 62 is provided in a ring shape. In a plan view, the inner edge of the conductive film 62 is between the inner edge and outer edge of the region 54 and outside the outer edge of the conductive film 61, and the outer edge is between the outer edge of the region 54 and the inner edge of the region 52. The inner edge of the conductive film 62 may be between the inner edge and outer edge of the region 54 and inside the outer edge of the conductive film 61. Alternatively, the outer edge of the conductive film 62 may be between the inner edge and outer edge of the region 54.

[0034] Other configurations of the fourth embodiment are similar to those of the first embodiment.

[0035] The fourth embodiment can also achieve the same effects as the first embodiment. Furthermore, since the conductive film 62 is included, it is easier to suppress a decrease in the on-breakdown voltage.

[0036] Here, a simulation performed by the inventors of the present application will be described. In this simulation, the relationship between the drain voltage Vd and the drain current Id when the semiconductor device was operated was calculated for each of the first, second, and third embodiments. The results are shown in FIG.

[0037] 7, in all of the first, second and third embodiments, the drain current Id is 10 mA or less when a drain voltage Vd of 600 V is applied. In particular, the second embodiment can achieve a higher on-breakdown voltage than the third embodiment, and the first embodiment can achieve a higher on-breakdown voltage than the second embodiment.

[0038] Although the preferred embodiments have been described above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0039] 10: Semiconductor substrate 10A: Main surface 13: Source area 14: High concentration well 31: Gate insulating film 32: Gate electrode 40, 50: Wiring layer 41, 42, 43, 44, 45, 51, 52, 53, 54: Area 61, 62: Conductive film 100, 200, 300, 400: Semiconductor device 101: Source wiring 102: Gate wiring 103: Drain wiring

Claims

1. a source region and a drain region provided on a main surface of a semiconductor substrate; a gate insulating film provided on the main surface between the source region and the drain region; a gate electrode provided on the gate insulating film; a first wiring electrically connected to the drain region; a second wiring electrically connected to the gate electrode; a first conductive film provided between the first wiring and the second wiring in a plan view perpendicular to the main surface, the first conductive film having a fixed potential; A semiconductor device having:

2. a first wiring layer provided above the main surface; a second wiring layer provided above the first wiring layer; and The first wiring is a first region included in the first wiring layer; a second region included in the second wiring layer; and The second wiring is a third region included in the first wiring layer; a fourth region included in the second wiring layer; and The semiconductor device according to claim 1 , wherein the first conductive film is included in the second wiring layer and is provided between the second region and the fourth region in the plan view.

3. 3. The semiconductor device according to claim 2, further comprising a second conductive film that is included in the first wiring layer, that is provided between the first region and the third region in the plan view, and that is electrically floating.

4. The semiconductor device according to claim 3 , wherein a portion of the second region and a portion of the second conductive film overlap each other in the plan view.

5. The semiconductor device according to claim 3 , wherein a portion of the first conductive film and a portion of the second conductive film overlap each other in the plan view.

6. 5. The semiconductor device according to claim 3, further comprising a third conductive film that is electrically floating and is provided between the first wiring and the second wiring in the plan view, closer to the main surface than the second conductive film.

7. The semiconductor device according to claim 6 , wherein a portion of the third conductive film and a portion of the second conductive film overlap each other in the plan view.

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