Semiconductor optical element and method for manufacturing the same

Abstract

To provide a semiconductor optical element capable of suppressing generation of voids due to out-gas, and a method for manufacturing the semiconductor optical element.SOLUTION: A semiconductor optical element has a substrate with a silicon layer, and a semiconductor element including a III-V compound semiconductor layer, where a waveguide, a terrace, and an out-gas countermeasure structure are provided in the silicon layer, and the out-gas countermeasure structure is a portion recessed with respect to an upper surface of the silicon layer. A method for manufacturing the semiconductor optical element has the steps of: arranging the semiconductor element on the waveguide and the out-gas countermeasure structure and bringing it into contact with the upper surface of the silicon layer; and bonding the semiconductor element to the substrate by performing heat treatment after the contacting step.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor optical device and a method for manufacturing the same. [Background technology]

[0002] There is a known technology for bonding a semiconductor element formed of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) on which a waveguide is formed. After the semiconductor element is brought into contact with the substrate, heat treatment is performed to bond the semiconductor element. The heat treatment reaches temperatures of several hundred degrees. The heat treatment evaporates moisture and generates outgassing. The outgas expands at the bonding interface, creating voids that reduce the bonding strength. The outgas in the voids may expand and cause the semiconductor element to explode. Technology has been developed to provide an SOI substrate with a structure that allows outgassing to escape from the interface (for example, Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] D. Liang, JEBowers “Highly efficient vertical outgassing channels for low-temperature InP-to-silicon direct wafer bonding on the silicon-on-insulator substrate”, Journal of Vaccum Science & Technology B:Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 26,1560(2008) Summary of the Invention [Problem to be solved by the invention]

[0004] However, outgassing may occur in processes after bonding, which may result in the formation of voids. Therefore, an object of the present invention is to provide a semiconductor optical element that can suppress the generation of voids due to outgassing, and a method for manufacturing the same. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor optical device according to the present disclosure is a method for manufacturing a semiconductor optical device having a substrate having a silicon layer and a semiconductor device including a III-V compound semiconductor layer, wherein the silicon layer is provided with a waveguide, a terrace, and an outgassing prevention structure, and the outgassing prevention structure is a portion recessed below an upper surface of the silicon layer, and the manufacturing method includes the steps of: placing the semiconductor device on the waveguide and the outgassing prevention structure and bringing it into contact with the upper surface of the silicon layer; and bonding the semiconductor device to the substrate by performing a heat treatment after the contacting step. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a semiconductor optical element capable of suppressing the generation of voids due to outgassing, and a method for manufacturing the same. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating an example of a silicon wafer. [Figure 2A] FIG. 2A is a plan view illustrating the semiconductor optical device according to the first embodiment. [Figure 2B] FIG. 2B is a plan view illustrating the substrate. [Figure 3] FIG. 3 is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 4A] FIG. 4A is an enlarged view of the recess. [Figure 4B] FIG. 4B is a cross-sectional view illustrating an example of a recess. [Figure 4C] FIG. 4C is an enlarged view of the recess. [Figure 5A]FIG. 5A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 5B] FIG. 5B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 5C] FIG. 5C is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 5D] FIG. 5D is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 6A] FIG. 6A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 6B] FIG. 6B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 7A] FIG. 7A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 7B] FIG. 7B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 8A] FIG. 8A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 8B] FIG. 8B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 9A] FIG. 9A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 9B] FIG. 9B is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device. [Figure 10] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor optical device according to the first modification. [Figure 11A] FIG. 11A is a plan view illustrating a recess according to a second modification. [Figure 11B] FIG. 11B is a plan view illustrating a recess according to the second modification. [Figure 11C] FIG. 11C is a plan view illustrating a recess according to a second modification. [Figure 12] FIG. 12 is a plan view illustrating the substrate according to the second embodiment. [Figure 13A] FIG. 13A is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 13B] FIG. 13B is a plan view illustrating a method for manufacturing a semiconductor optical device. [Figure 14A] FIG. 14A is a plan view illustrating a substrate according to the third embodiment. [Figure 14B] FIG. 14B is a plan view illustrating a method for manufacturing a semiconductor optical device. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure is (1) a method for manufacturing a semiconductor optical device having a substrate with a silicon layer and a semiconductor element including a III-V compound semiconductor layer, wherein the silicon layer is provided with a waveguide, a terrace, and an outgassing countermeasure structure, and the outgassing countermeasure structure is a portion recessed below an upper surface of the silicon layer, the method comprising the steps of: placing the semiconductor element on the waveguide and the outgassing countermeasure structure and bringing them into contact with the upper surface of the silicon layer; and bonding the semiconductor element to the substrate by performing heat treatment after the contacting step. Outgassing occurs during the bonding step. The outgassing enters the outgassing countermeasure structure. The generation of voids due to outgassing can be suppressed. (2) In the above (1), the outgassing countermeasure structure may include a first recess, and in the contacting step, the first recess may be located below the semiconductor element. Since the outgassing is trapped in the first recess, it is possible to suppress the generation of voids. (3) In the above (2), the first recess may have a ring-shaped planar shape. Outgassing is less likely to concentrate in one place inside the first recess. The internal pressure of the first recess is less likely to increase, so the generation of voids can be suppressed. (4) In the above (2) or (3), the planar shape of the first recess may include a curve. Outgassing is less likely to concentrate in one place inside the first recess. Since the internal pressure of the first recess is less likely to increase, the generation of voids can be suppressed. (5) In any one of (2) to (4) above, the substrate may have the silicon layer and a box layer, the box layer being provided on the surface of the silicon layer opposite to the top surface, and the bottom surface of the first recess may be the silicon layer or the box layer. Since outgassing is trapped in the first recess, the generation of voids can be suppressed. (6) In any of (1) to (5) above, the outgassing countermeasure structure may include a second recess, and in the contacting step, a first end of the second recess may extend from below the semiconductor element to outside the semiconductor element. Outgassing passes through the second recess and is released to the outside. This can suppress the generation of voids. (7) In the above (6), at least one end of the second recess may be located below the semiconductor element and have a curved shape. This prevents outgassing from concentrating in one location in the second recess, making it difficult for the internal pressure to increase. This can suppress the occurrence of voids. (8) In the above (6) or (7), the substrate may have the silicon layer and a box layer, the box layer may be provided on a surface of the silicon layer opposite to the upper surface, and the bottom surface of the second recess may be the silicon layer. The box layer may be protected by the silicon layer. (9) A semiconductor device includes a substrate having a silicon layer and a semiconductor element including a III-V compound semiconductor layer, the silicon layer being provided with a waveguide, a terrace, and an outgassing countermeasure structure, the outgassing countermeasure structure being a portion recessed from the upper surface of the silicon layer, and the semiconductor element being a semiconductor optical element bonded to the upper surface of the silicon layer on the waveguide and the outgassing countermeasure structure. Outgassing occurs during the bonding process. The outgassing enters the outgassing countermeasure structure. The generation of voids due to outgassing can be suppressed.

[0010] [Details of the embodiments of the present disclosure] Specific examples of semiconductor optical devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] First Embodiment (semiconductor optical element) 1 is a plan view illustrating a silicon wafer. A plurality of semiconductor optical devices 100 are formed on the silicon wafer 1. The silicon wafer 1 is diced to separate the plurality of semiconductor optical devices 100 from one another.

[0012] FIG. 2A is a plan view illustrating a semiconductor optical device 100 according to the first embodiment, with one semiconductor optical device 100 enlarged. The insulating film covering the substrate and the like is shown in a see-through view. As shown in FIG. 2A, the semiconductor optical device 100 is a Mach-Zehnder modulator and includes a substrate 10 and two semiconductor devices 11. The semiconductor devices 11 are bonded to one surface of the substrate 10. The Z-axis direction is the normal direction to the top surface of the substrate 10. Two sides of the substrate 10 are parallel to the X-axis. The other two sides are parallel to the Y-axis. The X-axis, Y-axis, and Z-axis directions are perpendicular to each other. The length L1 of the substrate 10 in the X-axis direction is, for example, 2 mm. The length L2 of the substrate 10 in the Y-axis direction is, for example, 1 mm.

[0013] 2B is a plan view illustrating the substrate 10. The substrate 10 has two waveguides 20, two waveguides 22, two multiplexers / demultiplexers 24, a terrace 26, a terrace 28, and an outgassing prevention structure 30. The waveguide 20, the multiplexer / demultiplexer 24, the two waveguides 22, the multiplexer / demultiplexer 24, and the waveguide 20 are arranged in this order in the X-axis direction. The multiplexer / demultiplexer 24 is a 1×2 MMI (Multi-Mode Interference).

[0014] One end of one waveguide 20 is optically coupled to one multiplexer / demultiplexer 24. One end of each of two waveguides 20 is optically coupled to one multiplexer / demultiplexer 24, and the other end is coupled to the other multiplexer / demultiplexer 24. The other waveguide 20 is coupled to the other multiplexer / demultiplexer 24.

[0015] Terraces 26 are located on both sides of the waveguide in the Y-axis direction and are spaced apart from the waveguide. Terrace 28 is located between two waveguides 22. Terraces 26 and 28 are flat portions of substrate 10. Recesses 21 are provided between the waveguide and terrace 26, and between the waveguide and terrace 28. The width of the waveguide in the Y-axis direction is, for example, 1 μm. The width of recess 21 is, for example, 1 μm.

[0016] 2A, two semiconductor elements 11 are located on the waveguide 22, the terrace 26, and the terrace 28. The semiconductor elements 11 have electrodes 50 and 52. The portion of the semiconductor elements 11 above the waveguide 22 may have a tapered shape. The tapered portion narrows along the waveguide 22, thereby increasing the coupling efficiency.

[0017] The outgassing countermeasure structure 30 includes a plurality of recesses 32 (first recesses) and a plurality of recesses 34 (second recesses). The recesses 32 are provided in the terrace 28. The recesses 34 are provided in the terrace 26. The outgassing countermeasure structure 30 will be described later.

[0018] FIG. 3 is a cross-sectional view illustrating the semiconductor optical device 100, taken along line CC in FIG. 2A. This cross-section includes the semiconductor device 11. As shown in FIG. 3, the substrate 10 is an SOI (Silicon on Insulator) substrate and includes a substrate 12, a box layer 14, and a silicon (Si) layer 16, which are stacked in this order in the Z-axis direction. The substrate 12 is made of, for example, Si. The box layer 14 is made of, for example, silicon oxide (SiO2). The thickness of the substrate 12 is, for example, 100 μm. The thickness of the box layer 14 is, for example, 3 μm. The thickness of the silicon layer 16 is, for example, 400 nm. The silicon layer 16 has a surface 61 (upper surface) and a surface 62 (lower surface). The semiconductor device 11 is bonded to the surface 61. The surface 62 is the surface opposite to the surface 61, and the box layer 14 is provided on the surface 62. The upper surface of the substrate 10 is covered with an insulating film 18. The insulating film 18 is, for example, made of SiO2 with a thickness of 1 μm. The refractive index of the silicon layer 16 is 3.45. The refractive index of the box layer 14 and the insulating film 18 is lower than that of the silicon layer 16, being 1.45.

[0019] 3, the terrace 26, the waveguide 22, and the terrace 28 of the silicon layer 16 are arranged from left to right. The upper surface of the waveguide 22 is located at the same height as the upper surfaces of the terraces 26 and 28. The upper surfaces of the waveguide 22, the terrace 26, and the terrace 28 are located at the same height in the Z-axis direction as the surface 61 of the silicon layer 16. The recess 21 is recessed in the Z-axis direction from the waveguide 22, the terrace 26, and the terrace 28. The depth of the recess 21 is, for example, 300 nm. The recess 21 may extend partway through the silicon layer 16, or may extend through the silicon layer 16 to the box layer 14.

[0020] The semiconductor device 11 has a damage mitigation layer 40, a cladding layer 42, a core layer 44, a cladding layer 46, and a contact layer 48. The damage mitigation layer 40 is bonded to the upper surface of the silicon layer 16 of the substrate 10. The cladding layer 42, the core layer 44, the cladding layer 46, and the contact layer 48 are stacked in this order on the damage mitigation layer 40. Optical confinement layers (not shown) may be provided between the core layer 44 and the cladding layer 42, and between the core layer 44 and the cladding layer 46.

[0021] The semiconductor element 11 has a mesa 54, a protrusion 55, and a protrusion 56. The protrusion 55, mesa 54, and protrusion 56 are arranged in this order from left to right in FIG. 3 . The protrusion 55 is located on the terrace 26. The protrusion 56 is located on the terrace 28. The mesa 54 is located on the waveguide 22. The mesa 54 and the protrusion include a core layer 44, a cladding layer 46, and a contact layer 48, and protrude in the Z-axis direction from the upper surface of the cladding layer 42. The mesa 54, the protrusion 55, and the protrusion 56 are spaced apart from one another.

[0022] The semiconductor element 11 is covered with an insulating film 18. The insulating film 18 has openings on the mesa 54 and between the mesa 54 and the protrusion 56. The electrode 50 is provided between the mesa 54 and the protrusion 56, and is in contact with the cladding layer 42 exposed from the opening of the insulating film 18, and is electrically connected to the cladding layer 42. The electrode 52 extends from the mesa 54 onto the protrusion 55, and is in contact with the contact layer 48 of the mesa 54, and is electrically connected to the contact layer 48.

[0023] The damage mitigation layer 40 is made of, for example, 200 nm thick non-doped gallium indium arsenide phosphide (i-GaInAsP). The bandgap wavelength of the damage mitigation layer 40 is 1.2 μm. The cladding layer 42 is made of, for example, 200 nm thick n-type indium phosphide (n-InP). The n-type semiconductor layer is doped with, for example, Si. The doping concentration in the cladding layer 42 is, for example, 1×10 19 cm -3The cladding layer 46 is made of, for example, p-type InP with a thickness of 1500 nm. The contact layer 48 is made of, for example, (p+)-gallium indium arsenide (GaInAs) with a thickness of 200 nm. The p-type semiconductor layer is doped with, for example, zinc (Zn) or carbon (C). The doping concentration in the cladding layer 46 is, for example, 1×10 18 cm -3 The doping concentration in the contact layer 48 is, for example, 1×10 19 cm -3 is.

[0024] The core layer 44 includes multiple well layers and barrier layers alternately stacked to form a multi-quantum well (MQW) structure. The well layers and barrier layers are formed of, for example, undoped gallium indium arsenide phosphide (i-GaInAsP). The core layer 44 has a thickness of, for example, 300 nm. The well layers are formed of, for example, 6 nm. The barrier layers are formed of, for example, 10 nm. The core layer 44 has optical gain and emits light with a wavelength of, for example, 1.55 μm. The optical confinement layer (not shown) is formed of, for example, i-GaInAsP with a thickness of 100 nm. The bandgap wavelength is, for example, 1.2 μm. Each layer of the semiconductor device 11 may be a III-V compound semiconductor layer other than those described above.

[0025] The electrode 50 is made of a metal such as an alloy of gold, germanium, and nickel (AuGeNi). The electrode 52 is a laminated body in which, for example, a titanium (Ti) layer, a platinum (Pt) layer, and an Au layer are laminated in this order from the side closest to the substrate 10. The electrodes 50 and 52 may be provided with an Au plating layer or the like.

[0026] (Outgassing prevention structure) 4A is an enlarged view of the recess 32. The planar shape of the recess 32 is, for example, a ring. The width W1 of the recess 32 is, for example, 1 μm or more and 10 μm or less, and may be 5 μm. The outer diameter D1 of the recess 32 is, for example, 10 μm or more and 100 μm or less, and may be 50 μm. The multiple recesses 32 are aligned in the X-axis direction. The center-to-center distance (pitch) D2 between two adjacent recesses 32 is, for example, 100 μm or more and 200 μm or less.

[0027] 4B is a cross-sectional view illustrating recess 32, showing box layer 14 and silicon layer 16 of substrate 10. Recess 32 is recessed from surface 61 of silicon layer 16 and extends halfway through silicon layer 16. Depth D3 of recess 32 is, for example, 190 nm. The interior of recess 32 is hollow.

[0028] FIG. 4C is an enlarged view of recess 34. Recess 34 is, for example, a groove parallel to the Y axis. The width W2 of recess 34 is, for example, 1 μm or more and 5 μm or less. Multiple recesses 34 are aligned in the X axis direction. The pitch P between recesses 34 is, for example, 100 μm or more and 200 μm or less. The depth of recess 34 is, for example, 190 nm, the same as recess 32. The interior of recess 34 is hollow. One end 35 of recess 34 in the Y axis direction includes a curve, for example, an arc shape. The other end 36 has a vertex.

[0029] The semiconductor element 11 and the substrate 10 are evanescently optically coupled. Light is incident on one waveguide 20. The light is split into two waveguides 22 by the multiplexer / demultiplexer 24. The light is transferred to the semiconductor element 11. The light is modulated by applying a voltage to the electrodes 50 and 52. The modulated light is transferred to the waveguide 22 and emitted from the other waveguide 20.

[0030] (Manufacturing method) 5A, 6A, 7A, 8A, and 9A are plan views illustrating a method for manufacturing the semiconductor optical device 100. Figures 5B to 5D, 6B, 7B, 8B, and 9B are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100. Figures 5B, 6B, 7B, 8B, and 9B are cross-sectional views at positions corresponding to Figure 3.

[0031] Before bonding the semiconductor element 11, the silicon wafer 1 is dry-etched to form the recess 21, the outgassing prevention structure 30, and the like. A contact layer 48, a cladding layer 46, a core layer 44, a cladding layer 42, and a damage mitigation layer 40 are epitaxially grown in this order on a p-type indium phosphide (p-InP) wafer by organometallic vapor-phase epitaxy (OMVPE). The damage mitigation layer 40 is located on the surface of the wafer. The wafer is cut to produce multiple semiconductor elements 11.

[0032] As shown in Figures 5A to 5D, the semiconductor element 11 is bonded to the substrate 10. The length of the semiconductor element 11 in the X-axis direction is, for example, 1 mm or more and 2 mm or less. The length of the semiconductor element 11 in the Y-axis direction is, for example, 0.5 mm. As shown in Figure 5B, the damage mitigation layer 40 contacts the silicon layer 16. The semiconductor element 11 has an InP substrate 49 on a contact layer 48.

[0033] In the bonding process, activation and cleaning are performed on the surface 61 of the silicon layer 16 and the surface of the damage mitigation layer 40. Activation is performed, for example, by ultraviolet (UV) ozone treatment. Cleaning is performed using ultrasonic cleaning water. At room temperature in the air, the damage mitigation layer 40 is brought into contact with the surface 61 of the silicon layer 16 to perform temporary bonding. After temporary bonding, heat treatment is performed, for example, at 150°C for about two hours. The heat treatment removes moisture and strengthens the bond strength.

[0034] Heat treatment can vaporize water molecules and carbon-based impurities, generating outgassing. The outgassing can get into the bonding interface, potentially forming voids. These voids can cause the semiconductor element 11 to lift off the substrate 10, reducing bonding strength. In the first embodiment, the substrate 10 is provided with an outgassing prevention structure 30.

[0035] FIG. 5C is a cross-sectional view taken along line AA in FIG. 5A, illustrating a cross section including recesses 32. As shown in FIGS. 5A and 5C, multiple recesses 32 are located below semiconductor element 11 and are sealed. Outgassing enters and is trapped within recesses 32. This suppresses the generation of voids. The planar shape of recesses 32 is annular and does not have a vertex. Because outgassing is unlikely to concentrate at one location within recesses 32, pressure is unlikely to be applied to semiconductor element 11 above recesses 32.

[0036] FIG. 5D is a cross-sectional view taken along line BB in FIG. 5A, illustrating a cross section including the recess 34. As shown in FIGS. 5A and 5D, the recess 34 extends from below the semiconductor element 11 to outside the semiconductor element 11. That is, a portion of the recess 34 is located below the semiconductor element 11, and another portion is exposed to the space outside the semiconductor element 11. Outgassing enters the recess 34 and is released from the recess 34 to the outside air. As shown in FIG. 5A, the end 36 is located outside the semiconductor element 11. The end 35 of the recess 34 is located below the semiconductor element 11. Because the end 35 has an arc shape, outgassing is less likely to concentrate. As described above, the outgassing countermeasure structure 30 can suppress the occurrence of voids.

[0037] 6A and 6B, the substrate 49 is removed by wet etching using, for example, a hydrochloric acid-based etchant. The contact layer 48 serves as an etching stop layer, and the damage mitigating layer 40 is not etched from the contact layer 48.

[0038] As shown in FIGS. 7A and 7B, the semiconductor element 11 is etched to remove portions thereof above the recesses 32 and 34. Specifically, a 300-nm-thick insulating film such as SiN is formed on the contact layer 48, and a resist is applied. A resist pattern is formed by photolithography. The pattern is transferred to the insulating film by etching using BHF (buffered hydrofluoric acid) or CF4 (carbon tetrafluoride) and oxygen (O2). Using the insulating film as a mask, reactive ion etching (CH4 / H2-RIE) is performed using, for example, a mixed gas of methane and hydrogen. The mask is then removed with BHF. Two semiconductor elements 11 remain on the waveguide 22.

[0039] As shown in Figures 8A and 8B, a mesa 54, protrusions 55, and protrusions 56 are formed in the semiconductor element 11. An insulating film and resist are formed. A resist pattern is formed by photolithography. A pattern is transferred to the insulating film, and CH4 / H2-RIE is performed using the insulating film as a mask. In the areas not protected by the mask, the contact layer 48 to the core layer 44 are removed. In the areas where the core layer 44, cladding layer 46, and contact layer 48 remain, the mesa 54, protrusions 55, and protrusions 56 are formed.

[0040] As shown in Figures 9A and 9B, an insulating film 18 is formed to cover the semiconductor element 11. The recesses 32 and 34 are also covered with the insulating film 18. A resist pattern is formed by photolithography. The pattern is transferred to the insulating film 18. The insulating film 18 is removed from above the mesa 54. The insulating film 18 is removed from the portion of the insulating film 18 between the mesa 54 and the protrusion 56. The electrodes 50 and 52 are formed by vapor deposition and lift-off. The substrate 12 is polished to a total thickness of the substrate 10 of, for example, 350 μm to 150 μm. The silicon wafer 1 is diced to form a plurality of semiconductor optical elements 100.

[0041] According to the first embodiment, the substrate 10 has an outgassing countermeasure structure 30. The outgassing countermeasure structure 30 is a recess that is recessed below the surface 61 of the silicon layer 16. More specifically, the outgassing countermeasure structure 30 includes a recess 32 and a recess 34. The semiconductor element 11 is placed on the recess 32 and the recess 34 and is bonded to the silicon layer 16 by heat treatment. The heat treatment raises the temperature to, for example, several hundred degrees. Because outgassing penetrates the outgassing countermeasure structure 30, it is less likely to accumulate at the bonding interface. The generation of voids at the bonding interface can be suppressed. The bonding strength of the semiconductor element 11 is increased, the rupture of the semiconductor element 11 is suppressed, and the yield is improved.

[0042] 4B, recess 32 is located below semiconductor element 11 and is closed by semiconductor element 11. Outgassing is trapped inside recess 32, making it possible to suppress the occurrence of voids.

[0043] As shown in FIG. 2B, the planar shape of the recess 32 is ring-shaped, for example, an annular shape. The recess 32 includes curves and has no vertices. Outgassing is less likely to concentrate in one place inside the recess 32. The internal pressure of the recess 32 is less likely to increase, so the generation of voids can be suppressed. The planar shape of the recess 32 may be a closed ring, or may be a partially open shape as described below. The planar shape of the recess 32 may be other than an annular shape.

[0044] 5D, the recess 34 extends from below the semiconductor element 11 to the outside of the semiconductor element 11. The outgas passes through the recess 34 and is released from below the semiconductor element 11 to the outside. This makes it possible to suppress the generation of voids.

[0045] As shown in Fig. 5A, the end 35 of the recess 34 is located below the semiconductor element 11. As shown in Fig. 4C, the end 35 has a curved shape, such as an arc shape, and does not have a vertex. Outgassing is less likely to concentrate in one place in the recess 34, and the internal pressure is less likely to increase. This makes it possible to suppress the occurrence of voids.

[0046] The number and size of the recesses 32 and recesses 34 may be changed. If the area occupied by the recesses on the surface of the substrate 10 increases, the contact area between the semiconductor element 11 and the substrate 10 decreases, which may result in a decrease in bonding strength. By arranging many and large recesses 32 and recesses 34, a large amount of outgas can be taken into the recesses. However, there is a risk that the outgas will leak from the recesses, causing voids.

[0047] According to the first embodiment, outgassing is trapped in the recesses 32 and re-emission is suppressed. The width W1 of the recesses 32 is, for example, 1 μm or more and 10 μm or less, and is approximately 5 μm. The diameter D1 of the recesses 32 is, for example, 10 μm or more and 100 μm or less, and is, for example, 50 μm. The pitch D2 is, for example, 100 μm or more and 200 μm.

[0048] According to the first embodiment, outgassing is released from the recesses 34 to the outside air, suppressing the generation of voids due to outgassing within the recesses 34. The width W2 of the recesses 34 is, for example, 1 μm or more and 10 μm or less, and is approximately 5 μm. The pitch P is, for example, 100 μm or more and 200 μm. The recesses 34 may be parallel to the Y axis or may be inclined with respect to the Y axis direction. The recesses 34 may be linear or may include a curve.

[0049] 5C and 5D, the recesses 32 and 34 extend partway through the silicon layer 16 of the substrate 10. The bottom surfaces of the recesses 32 and 34 are the silicon layer 16. Outgassing is trapped in the recesses 32 and is released to the outside air through the recesses 34. This makes it possible to suppress the generation of voids.

[0050] (First Modification) In the first modified example, the depth of the recess 32 is changed. FIG. 10 is a cross-sectional view illustrating a method for manufacturing a semiconductor optical device according to the first modified example, illustrating a step corresponding to FIG. 5C. The recess 32 penetrates the silicon layer 16 and extends partway through the box layer 14. The depth D4 from the top surface of the box layer 14 to the bottom surface of the recess 32 is, for example, 100 nm. According to the modified example, outgas is trapped in the recess 32 and absorbed by the box layer 14. The generation of voids can be suppressed.

[0051] The recess 34 may extend up to the box layer 14. However, a part of the box layer 14 will be exposed from the silicon layer 16 and will not be protected by the silicon layer 16. The recess 34 is a structure for allowing outgassing to escape, and it is important that a part of the recess 34 is exposed to the outside of the semiconductor element 11. The effect of releasing outgassing can be obtained whether the recess 34 extends up to the box layer 14 or not. By having the recess 34 extend partway through the silicon layer 16 without penetrating it, the box layer 14 will be covered by and protected by the silicon layer 16.

[0052] (Second Modification) In the second modified example, the planar shape of the recess 32 is changed. Figures 11A to 11C are plan views illustrating recesses according to the second modified example. The recess 32a in Figure 11A has a partially open annular shape. The angle θ of the missing portion is greater than 0° and less than 360°.

[0053] 11B shows two recesses 32b. The recesses 32b are formed by dividing the annular recess 32 into two. The two recesses 32b are spaced apart from each other and separated by the silicon layer 16. The planar shape of the recesses 32b is, for example, an arc shape.

[0054] 11C, the planar shape of the recess 32c is elliptical.

[0055] Any of the recesses 32, 32a, 32b, and 32c may be provided in the substrate 10 and positioned below the semiconductor element 11. The outgassing is trapped in these recesses, thereby suppressing the generation of voids. The edges of the recesses 32a and 32b may be curved.

[0056] Second Embodiment 12 is a plan view illustrating the substrate 10 according to the second embodiment. Description of the same configuration as in the first embodiment will be omitted.

[0057] As shown in Figure 12, the substrate 10 does not have a recess 34, but has multiple recesses 32 as an outgassing countermeasure structure. A plurality of waveguides 20 are provided on the substrate 10. A recess 21 and a terrace 26 are arranged in this order on both sides of each waveguide 20. The multiple recesses 32 are provided on the terrace 26 and are aligned in the X-axis direction. One or two rows of recesses 32 are arranged on the terrace 26.

[0058] 13A and 13B are plan views illustrating a method for manufacturing a semiconductor optical device. FIG. 13A illustrates a step corresponding to FIG. 5A. As shown in FIG. 13A, a semiconductor device 11 is bonded to a substrate 10. The planar shape of the semiconductor device 11 is rectangular. The lengths L3 and L4 of the semiconductor device 11 are, for example, 2 mm each. The semiconductor device 11 is located on three waveguides 20 and is bonded to four terraces 26. The semiconductor device 11 covers a plurality of recesses 32. Outgassing generated during the bonding process is trapped in the recesses 32.

[0059] 13B, the semiconductor element 11 is etched. The semiconductor element 11 remains on the three waveguides 20. The recessed portion 32 is exposed, and the outgas is released to the outside air. Mesas, electrodes, etc. are formed on the three semiconductor elements 11.

[0060] According to the second embodiment, the substrate 10 has a recess 32. The semiconductor element 11 is placed on the recess 32 and bonded to the silicon layer 16 by heat treatment. Outgassing is trapped in the recess 32. This can suppress the generation of voids, and the bonding strength of the semiconductor element 11 is increased.

[0061] At the time of bonding, all of the recesses 32 are located under the semiconductor element 11 and are sealed by the semiconductor element 11. Outgassing can be trapped in the recesses 32. The number and positions of the recesses 32 may be changed depending on the sizes of the substrate 10 and the semiconductor element 11, etc.

[0062] Third Embodiment 14A is a plan view illustrating the substrate 10 according to the third embodiment. Description of the same configuration as in the first or second embodiment will be omitted.

[0063] 14A, the substrate 10 does not have a recess 32, but has a plurality of recesses 34 as an outgassing countermeasure structure. The plurality of recesses 34 are provided on the terrace 26 and are aligned in the X-axis direction. One or two rows of recesses 32 are arranged on the terrace 26. The recesses 34 extend in the Y-axis direction.

[0064] The multiple recesses 34 include recesses 34a and recesses 34b. Recess 34a has ends 35 and 36. End 35 faces the waveguide 20 and has, for example, an arc shape. End 36 is located opposite end 35 and has an apex. Recess 34b has two ends 37. End 37 faces the waveguide 20 and has an arc shape.

[0065] FIG. 14B is a plan view illustrating a method for manufacturing a semiconductor optical device, illustrating steps corresponding to those in FIG. 5A. A plurality of semiconductor devices 11 are manufactured from a wafer of III-V compound semiconductor. For example, three semiconductor devices 11 are bonded to a substrate 10. One semiconductor device 11 is provided on one waveguide 20. The planar shape of the semiconductor device 11 is rectangular. The length L5 of the semiconductor device 11 in the X-axis direction is, for example, 2 mm. The length L6 of the semiconductor device 11 in the Y-axis direction is, for example, 1 mm.

[0066] A part of the recess 34 is located below the semiconductor element 11, and another part is exposed to the outside of the semiconductor element 11. An end 35 of the recess 34a is located below the semiconductor element 11, and an end 36 is located outside the semiconductor element 11. Two ends 37 of the recess 34b are located below the semiconductor element 11. The part of the recess 34b between the two ends 37 is located outside the semiconductor element 11. Outgassing generated during the bonding process is released from the recess 34 into the outside air.

[0067] According to the third embodiment, when the semiconductor element 11 is bonded to the substrate 10, the recess 34 extends from below the semiconductor element 11 to the outside of the semiconductor element 11. Outgassing passes through the recess 34 and is released from below the semiconductor element 11 to the outside. This makes it possible to suppress the generation of voids.

[0068] The number and positions of the recesses 34 may be changed depending on the sizes of the substrate 10 and the semiconductor element 11. As shown in Fig. 14B, it is sufficient that at least a portion of the recesses 34 is exposed from the semiconductor element 11 at the time of bonding.

[0069] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0070] 1 silicon wafer 10, 12, 49 board 11 Semiconductor elements 14 Box Layer 16 Silicon Layer 18 insulating film 20, 22 Waveguide 21, 32, 32a, 32b, 32c, 34, 34a, 34b recesses 24 Multiplexer / demultiplexer 26, 28 Terrace 30 Outgassing prevention structure 35, 36, 37 Ends 40 Damage Mitigation Layer 42, 46 Cladding layer 44 Core Layer 48 Contact layer 50, 52 electrodes 54 Mesa 55, 56 protrusion 61, 62 sides 100 Semiconductor optical element

Claims

1. A method for manufacturing a semiconductor optical device having a substrate with a silicon layer and a semiconductor device including a III-V compound semiconductor layer, comprising: the silicon layer is provided with a waveguide, a terrace, and an outgassing prevention structure; the outgassing prevention structure is a portion recessed from an upper surface of the silicon layer, The manufacturing method includes: placing the semiconductor device over the waveguide and the outgassing structure and in contact with the top surface of the silicon layer; and performing a heat treatment after the contacting step to bond the semiconductor element to the substrate.

2. the outgassing countermeasure structure includes a first recess, 2. The method for manufacturing a semiconductor optical device according to claim 1, wherein in the contacting step, the first recess is located below the semiconductor device.

3. 3. The method for manufacturing a semiconductor optical device according to claim 2, wherein the first recess has a ring-like planar shape.

4. 4. The method for manufacturing a semiconductor optical device according to claim 2, wherein the planar shape of the first recess includes a curve.

5. the substrate has the silicon layer and a box layer; the box layer is provided on a surface of the silicon layer opposite to the upper surface, 4. The method for manufacturing a semiconductor optical device according to claim 2, wherein the bottom surface of the first recess is the silicon layer or the box layer.

6. the outgassing countermeasure structure includes a second recess, 3. The method for manufacturing a semiconductor optical device according to claim 1, wherein in the contacting step, the first end of the second recess extends from below the semiconductor device to outside the semiconductor device.

7. 7. The method for manufacturing a semiconductor optical device according to claim 6, wherein at least one end of the second recess is located below the semiconductor device and has a curved shape.

8. the substrate has the silicon layer and a box layer; the box layer is provided on a surface of the silicon layer opposite to the upper surface, 7. The method for manufacturing a semiconductor optical device according to claim 6, wherein the bottom surface of the second recess is the silicon layer.

9. a substrate having a silicon layer; a semiconductor element including a III-V compound semiconductor layer, the silicon layer is provided with a waveguide, a terrace, and an outgassing prevention structure; the outgassing prevention structure is a portion recessed from an upper surface of the silicon layer, The semiconductor element is a semiconductor optical element bonded to the upper surface of the silicon layer, on top of the waveguide and the outgassing prevention structure.

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