Wiring board

Abstract

To provide a technique capable of manufacturing a semiconductor module which is improved in a heat dissipation property and reduces variations of heat dissipation properties between the modules.SOLUTION: A wiring board 10 comprises: two or more organic insulation layers 101 and 104 which are mutually laminated; one or more wiring layers 105A each of which is interposed between adjacent two of the organic insulation layers 101 and 104 and includes a main conductor layer consisting of a first metal material; and one or more heat conduction layers 106 each of which is interposed between the organic insulation layers 101 and 104 and consists of a heat conduction material of which the heat conductivity is higher in relative to the organic insulation layers 101 and 104. Each of the heat conduction layers 106 includes an end face which is exposed at positions of end faces of the organic insulation layers 101 and 104 and is adjacent with one of the wiring layers 105 in an in-plane direction. The heat conduction material contains a non-metal material or consists of a second metal material of which malleability is lower in relative to the first metal material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Semiconductor integrated circuits are prone to malfunction when exposed to high temperatures. Therefore, in order to cool a semiconductor chip containing a semiconductor integrated circuit, for example, a heat sink may be placed in contact with the top surface of the semiconductor chip mounted on a wiring substrate. With this cooling method, heat generated in the semiconductor chip is transferred from the semiconductor chip to the heat sink, and then dissipated from the heat sink into the atmosphere.

[0003] In addition, a heat sink having a recess on one main surface of a wiring board on which a semiconductor chip is mounted may be joined to the wiring board at the peripheral edge of the main surface so that the semiconductor chip is positioned within the recess (Patent Document 1). With this cooling method, heat generated in the semiconductor chip is transferred from the semiconductor chip to the heat sink via the wiring board, and then dissipated from the heat sink to the atmosphere.

[0004] As the speed of semiconductor integrated circuits increases, their power consumption also increases. As a result, the amount of heat generated by semiconductor chips containing semiconductor integrated circuits increases significantly. Therefore, it is becoming difficult to achieve sufficient cooling using the cooling methods described above.

[0005] Another cooling method is to immerse the wiring board on which the semiconductor chip is mounted in an insulating liquid. However, this cooling method has the problem of requiring a large-scale device configuration, since it is necessary to seal the entire wiring board on which the semiconductor chip is mounted to prevent the liquid from leaking out. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-101243 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a technique that makes it possible to manufacture semiconductor modules that have excellent heat dissipation properties and little variation in heat dissipation properties between modules. [Means for solving the problem]

[0008] According to one aspect of the present invention, there is provided a wiring substrate comprising: two or more organic insulating layers stacked on top of each other; one or more wiring layers interposed between adjacent ones of the two or more organic insulating layers, each including a main conductor layer made of a first metal material; and one or more heat transfer layers interposed between the two or more organic insulating layers, each made of a heat transfer material having a higher thermal conductivity than the two or more organic insulating layers, wherein each of the one or more heat transfer layers has an end face exposed at the position of an end face of the two or more organic insulating layers and is adjacent to one of the one or more wiring layers in the in-plane direction, and the heat transfer material includes a non-metallic material or is made of a second metal material having lower malleability than the first metal material.

[0009] According to another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein the heat conductive material includes an insulating resin and an inorganic material.

[0010] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the heat transfer material has a Young's modulus of 3 GPa or less.

[0011] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the heat transfer material has a breaking elongation of 15% or less.

[0012] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the heat conductive material has a thermal conductivity within a range of 2 to 100 W / m·K.

[0013] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the one or more heat transfer layers have a higher electrical resistivity than the one or more wiring layers.

[0014] According to yet another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the first metal material includes copper.

[0015] According to yet another aspect of the present invention, there is provided a semiconductor module comprising a wiring board according to any of the above aspects, a semiconductor chip mounted on the wiring board, and a heat sink joined to the one or more heat transfer layers.

[0016] According to yet another aspect of the present invention, there is provided the semiconductor module according to the above aspect, wherein the heat sink is joined to the one or more heat transfer layers via solder or a conductive paste.

[0017] Alternatively, according to yet another aspect of the present invention, there is provided a semiconductor module according to the above aspect, wherein the heat sink is joined to the one or more heat transfer layers via an insulating material containing grease.

[0018] According to yet another aspect of the present invention, there is provided the semiconductor module according to the above aspect, wherein the insulating material further includes inorganic particles dispersed in the grease.

[0019] According to yet another aspect of the present invention, there is provided an aggregate substrate that is divided into a plurality of wiring substrates, each of which is a wiring substrate according to any of the above aspects.

[0020] According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate, the method including dividing the aggregate substrate according to the above aspect into the plurality of wiring substrates. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a wiring board according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view schematically showing one step in the manufacture of the wiring board shown in FIG. [Figure 3] 3A to 3C are cross-sectional views schematically showing other steps in the manufacture of the wiring board shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 5] FIG. 5 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 8] FIG. 8 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 10] FIG. 10 is a top view of the structure shown in FIG. [Figure 11] FIG. 11 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 17]FIG. 17 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 19] FIG. 19 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 20] FIG. 20 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 21] FIG. 21 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 22] FIG. 22 is a cross-sectional view schematically showing still another step in the manufacture of the wiring board shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view schematically showing an example of a semiconductor package including the wiring board shown in FIG. [Figure 24] FIG. 24 is a cross-sectional view schematically showing an example of a semiconductor module including the semiconductor package shown in FIG. [Figure 25] FIG. 25 is a cross-sectional view schematically showing a semiconductor module according to a first comparative example. [Figure 26] FIG. 26 is a heat dissipation equivalent circuit diagram of the semiconductor module shown in FIG. [Figure 27] FIG. 27 is a heat radiation equivalent circuit diagram of the semiconductor module shown in FIG. [Figure 28] FIG. 28 is a graph showing the heat dissipation performance of the semiconductor modules according to the example and the comparative example. [Figure 29] FIG. 29 is a cross-sectional view schematically showing a semiconductor module according to a second comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are more specific embodiments of any of the above aspects. The following items can be incorporated into each of the above aspects, either singly or in combination.

[0023] The following embodiments are examples that embody the technical idea of the present invention, and the technical idea of the present invention is not limited to the materials, shapes, structures, and arrangements of the components described below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

[0024] In the drawings referred to in the following description, components having the same or similar functions are denoted by the same reference numerals. It should be noted that the drawings are schematic, and the relationship between the dimension in the thickness direction and the dimension in the direction perpendicular to the thickness direction, i.e., the in-plane direction, and the relationship between the dimensions of multiple layers in the thickness direction may differ from the actual dimensions. Therefore, specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationship between two or more components may differ between multiple drawings.

[0025] In this disclosure, the terms "top surface" and "bottom surface" refer to the two main surfaces of a plate-like member or a layer contained therein, i.e., the surface perpendicular to the thickness direction and having the largest area, and the back surface thereof, respectively, the surface shown at the top and the surface shown at the bottom in the drawings. Furthermore, the term "end surface" refers to the surface of a plate-like member or a layer contained therein that is located on the periphery when viewed from a direction parallel to the thickness direction. Furthermore, the term "side surface" refers to a surface that is perpendicular or inclined to an in-plane direction.

[0026] Furthermore, in this disclosure, the expression "AA on BB" is used regardless of the direction of gravity. The state specified by the expression "AA on BB" includes a state in which AA is in contact with BB. The expression "AA on BB" does not exclude the presence of one or more other components between AA and BB.

[0027] <Wiring board> Fig. 1 is a cross-sectional view that schematically shows a wiring board according to one embodiment of the present invention. The vertical direction in Fig. 1 is the thickness direction of wiring board 10. Fig. 1 depicts a portion of wiring board 10 near one end face thereof.

[0028] 1 is a multilayer wiring board. Here, as an example, it is assumed that wiring board 10 has a square shape when viewed in the thickness direction.

[0029] The wiring board 10 includes a core insulating layer 101, a conductor layer 102, a hole filling resin 103, an insulating layer 104, a conductor layer 105A, a conductor layer 105B, a heat transfer layer 106, an insulating layer 107, and a joining conductor 108.

[0030] Here, the core insulating layer 101 is an organic insulating layer. According to one example, the core insulating layer 101 is a composite material containing glass fiber and a cured resin. The core insulating layer 101 has a plurality of through holes each extending in the thickness direction thereof.

[0031] The conductor layer 102 is a layer made of a metal material. The conductor layer 102 may have a single-layer structure or a multi-layer structure. Here, the conductor layer 102 constitutes a through electrode that covers the side wall of a through hole provided in the core insulating layer 101. The conductor layer 102 may fill the through hole provided in the core insulating layer 101.

[0032] The filling resin 103 is an insulator made of a cured resin. The filling resin 103 fills the through holes of the core insulating layer 101 whose side walls are covered with the conductor layer 102. When the conductor layer 102 fills the through holes provided in the core insulating layer 101, the filling resin 103 can be omitted.

[0033] The insulating layer 104 is an organic insulating layer. The insulating layer 104 is made of, for example, a cured resin. Each insulating layer 104 may have a single-layer structure or a multi-layer structure. Each insulating layer 104 has a plurality of through holes extending in its thickness direction. Here, two insulating layers 104 are stacked on each main surface of the core insulating layer 101. The number of insulating layers 104 provided on each main surface of the core insulating layer 101 may be one, or may be three or more. Furthermore, as long as one or more insulating layers 104 are provided on one main surface, it is not necessary that an insulating layer 104 is provided on the other main surface.

[0034] Each of the conductor layers 105A and 105B is a wiring layer including a main conductor layer. Here, the "main conductor layer" is the thickest conductive layer included in the wiring layer. The main conductor layer is made of a first metal material such as copper. As described below, each of the conductor layers 105A and 105B may further include one or more other layers, such as an adhesion layer and a seed layer.

[0035] Each of the conductor layers 105A is provided between the core insulating layer 101 and the insulating layer 104. Each of the conductor layers 105A is a conductor pattern including a pad portion and a wiring portion. The pad portions include those arranged at the positions of the through holes provided in the core insulating layer 101 and those arranged at positions away from the through holes provided in the core insulating layer 101. The wiring portion connects the former pad portion to the latter pad portion.

[0036] The conductor layer 105B includes one provided between two stacked insulating layers 104. Each of these conductor layers 105B includes a pad portion, a wiring portion, and a via portion. In each of these conductor layers 105B, the pad portions include one located at the position of a through hole provided in the insulating layer 104 interposed between the conductor layer 105B and the core insulating layer 101, and one located at a position away from the through hole. The wiring portion connects the former pad portion to the latter pad portion. The via portion fills the through hole provided in the insulating layer 104 interposed between the above conductor layer 105B and the core insulating layer 101, and electrically connects the former pad portion to the pad portion included in the conductor layer 105A.

[0037] The conductor layers 105B further include one provided between the insulating layer 104 and the insulating layer 107. Each of these conductor layers 105B includes a pad portion and a via portion. In each of these conductor layers 105B, the pad portion is located at the position of a through hole provided in the insulating layer 104 that is in contact with the insulating layer 107. The via portion fills the through hole provided in the insulating layer 104 that is in contact with the insulating layer 107, and electrically connects the pad portion included in this conductor layer 105B to the pad portion included in the conductor layer 105B that is provided between the two stacked insulating layers 107. In addition to the pad portion and via portion described above, this conductor layer 105B may further include a pad portion located away from the through hole provided in the insulating layer 104 that is in contact with the insulating layer 107, and a wiring portion that connects the former pad portion to the latter pad portion.

[0038] Each heat transfer layer 106 is interposed between two adjacent organic insulating layers. Here, each heat transfer layer 106 is interposed between the core insulating layer 101 and the insulating layer 104. Each heat transfer layer 106 may be provided between two stacked insulating layers 104, or may be provided between the insulating layer 104 and the insulating layer 107. Also, here, the number of heat transfer layers 106 is two, but the number of heat transfer layers 106 may be one, or three or more.

[0039] Each of the heat transfer layers 106 has an end face exposed at the end faces of the organic insulating layers sandwiching it, in this case, the core insulating layer 101 and the insulating layer 104. Here, each of the heat transfer layers 106 has a frame shape when viewed from the thickness direction of the wiring substrate 10, and the entire outer peripheral end face is exposed at the end faces of the core insulating layer 101 and the insulating layer 104. Each of the heat transfer layers 106 may have only a portion of its outer peripheral end face exposed at the end faces of the core insulating layer 101 and the insulating layer 104. Furthermore, each of the heat transfer layers 106 may have a shape other than a frame shape when viewed from the thickness direction of the wiring substrate 10.

[0040] Each of the heat transfer layers 106 is adjacent to one of the wiring layers, in this case, the conductor layer 105A, in the in-plane direction. Each of the heat transfer layers 106 may be spaced apart from the wiring layer adjacent to it in the in-plane direction. However, it is preferable that each of the heat transfer layers 106 be in contact with the wiring layer adjacent to it in the in-plane direction, as shown in FIG.

[0041] Each of the heat transfer layers 106 is made of a heat transfer material that has a higher thermal conductivity than the organic insulating layers that sandwich it, here core insulating layer 101 and insulating layer 104 .

[0042] The thermal conductivity of the heat transfer material is preferably in the range of 2 to 100 W / m·K, more preferably in the range of 4.5 to 100 W / m·K. The materials constituting the core insulating layer 101 and the insulating layers 104 and 107 have a thermal conductivity in the range of, for example, 0.58 to 0.65 W / m·K. On the other hand, the thermal conductivity of copper is approximately 400 W / m·K.

[0043] The Young's modulus of the heat transfer material is preferably 3 GPa or less, and more preferably 2.5 GPa or less. For example, the Young's modulus of the heat transfer material is 1.0 GPa or more. The materials constituting the core insulating layer 101 and the insulating layers 104 and 107 have a Young's modulus in the range of, for example, 8 to 15 GPa. On the other hand, the Young's modulus of copper is, for example, 129 GPa.

[0044] The thermal conductive material preferably has a breaking elongation of 15% or less, more preferably 30% or less. For example, this breaking elongation is 3% or more. The materials constituting the core insulating layer 101 and the insulating layers 104 and 107 have a breaking elongation of, for example, about 2.5%. On the other hand, the breaking elongation of copper is, for example, 50%.

[0045] According to one example, the heat transfer material includes a non-metallic material, such as a composite material including an insulating resin and an inorganic material.

[0046] The insulating resin is a binder resin that binds inorganic materials together, and is, for example, a cured thermosetting resin.

[0047] According to one example, the inorganic material is dispersed in the insulating resin. The inorganic material has a higher thermal conductivity than the insulating resin and the organic insulating layer sandwiching the heat transfer layer 106. The inorganic material is, for example, a metallic material, an inorganic non-metallic material, or a combination thereof. The metallic material is, for example, one or more of silver, nickel, gold, and copper. The inorganic non-metallic material is, for example, one or more of carbon, silica, boron nitride, and aluminum nitride. The inorganic material may be in a particulate or fibrous form.

[0048] In another example, the heat transfer material is made of a second metal material that is less malleable than the first metal material. The second metal material is, for example, iron, aluminum, or an alloy containing at least one of them. When the heat transfer material is the second metal material, higher heat dissipation performance can be achieved compared to when the heat transfer material contains a non-metallic material. However, in general, heat transfer materials made of the second metal material are more malleable than heat transfer materials containing a non-metallic material. Therefore, when the heat transfer material is made of the second metal material, heat dissipation performance is more likely to vary between modules compared to when the heat transfer material contains a non-metallic material.

[0049] According to an example, each of the heat transfer layers 106 has a higher electrical resistivity than the wiring layers, i.e., the conductor layers 105A and 105B. For example, each of the heat transfer layers 106 is electrically insulating. The electrically insulating heat transfer layer 106 preferably has an electrical resistivity of 10×10 12 Ω·m or more, and more preferably 10×10 2 The electrically insulating heat transfer layer 106 has an electrical resistivity of, for example, 10×10 12 Ω·m or less.

[0050] Each of the heat-conducting layers 106 may be electrically conductive. When the wiring substrate 10 and the semiconductor chip mounted thereon each include dummy wiring that is unrelated to the operation of the integrated circuit, the dummy wiring of the semiconductor chip is connected to the dummy wiring of the wiring substrate, and the heat-conducting layer 106 is brought into contact with the dummy wiring of the wiring substrate 10, the heat-conducting layer 106 does not adversely affect the operation of the integrated circuit even if the heat-conducting layer 106 is electrically conductive.

[0051] Each of the heat-transfer layers 106 is preferably thicker than the wiring and pad portions interposed between the organic insulating layers sandwiching the heat-transfer layer 106, i.e., the wiring and pad portions of the conductor layer 105A in this case. Increasing the thickness of the heat-transfer layer 106 improves its thermal conductivity. Furthermore, when the heat-transfer layer 106 is formed so that its end faces contact the conductor layer 105A using, for example, a paste containing a heat-transfer material or a precursor thereof, the thickening of the heat-transfer layer 106 allows the paste to flow toward the peripheral portion of the main surface of the conductor layer 105A, ensuring more reliable contact between the heat-transfer layer 106 and the conductor layer 105A.

[0052] Each of the heat transfer layers 106 is preferably thinner than the organic insulating layer that covers it, in this case, the insulating layer 104 that is in contact with the core insulating layer 101. If the heat transfer layers 106 are made excessively thick, the portion of the wiring board 10 that corresponds to the heat transfer layer 106 may become thicker than other portions of the wiring board 10.

[0053] Each of the heat transfer layers 106 preferably has a thickness in the range of 2 to 40 μm, more preferably in the range of 10 to 20 μm.

[0054] The insulating layers 107 are organic insulating layers. The insulating layers 107 are made of, for example, solder resist. Each insulating layer 107 covers the uppermost insulating layer 104 and the uppermost conductor layer 105B. Each insulating layer 107 has a through hole at the position of the pad portion of the conductor layer 105B that it covers.

[0055] The bonding conductors 108 cover the pad portions of the conductor layer 105B covered by the insulating layer 107 at the positions of the through holes formed in the insulating layer 107. Each of the bonding conductors 108 includes a portion located within the through hole formed in the insulating layer 107 and a portion protruding from the insulating layer 107. The bonding conductors 108 are, for example, solder bumps. The arrangement pitch of the bonding conductors 108 on the lower surface of the wiring board 10 is larger than the arrangement pitch of the bonding conductors 108 on the upper surface of the wiring board 10.

[0056] <Method of manufacturing wiring board> The above wiring board 10 can be manufactured, for example, by the following method.

[0057] 2 to 9 and 11 to 22 are cross-sectional views that schematically show the manufacturing process of the wiring substrate shown in Fig. 1. Fig. 10 is a top view of the structure shown in Fig. 9.

[0058] First, as shown in FIG. 2, a composite material including a core insulating layer 101 and conductor layers 105A1 provided on both sides thereof is prepared, and through holes TH1 are formed in this composite material to electrically connect the front and back surfaces of the composite material. Here, as will be described later, an aggregate substrate is first manufactured, and this aggregate substrate is then singulated into multiple wiring substrates 10. Therefore, the dimensions of the composite material prepared here are larger than the dimensions of an assembly formed by arranging multiple wiring substrates 10. The conductor layers 105A1 are, for example, copper foil attached to the core insulating layer 101. The through holes TH1 are formed, for example, using a drill.

[0059] Next, as shown in Fig. 3, a conductor layer 105A2 is formed on the sidewall of the through hole TH1 and on the surface of the conductor layer 105A1. Here, the conductor layer 105A2 is formed so as not to completely fill the through hole TH1. The conductor layer 105A2 may be formed so as to completely fill the through hole TH1. Note that the portion of the conductor layer 105A2 that covers the sidewall of the through hole TH1 is the above-mentioned conductor layer 102.

[0060] The conductor layer 105A2 is, for example, a laminate of a seed layer and a plating layer provided thereon.

[0061] The seed layer can be formed by, for example, electroless plating. When the seed layer is formed by electroless plating, the material can be, for example, a metal material such as Cu, Pd, Al, Sn, Ni, or Cr.

[0062] The plating layer can be formed, for example, by electroplating using the seed layer as a power supply layer. Materials for the plating layer include, for example, metal materials such as Cu, Cu alloys, Ag, Ag alloys, Sn, Pd, Au, Ni, Cr, Pt, Fe, and combinations of two or more of these.

[0063] Next, as shown in Fig. 4, the through hole TH1 is filled with a filling resin 103. For example, the through hole TH1 is filled with resin, the resin is cured, and then any unnecessary resin spilling out of the through hole TH1 is removed by buffing or the like. Note that if the through hole TH1 is completely filled with the conductor layer 105A2 in the process described with reference to Fig. 3, the process described with reference to Fig. 4 is omitted.

[0064] Next, conductor layers 105A3 are formed on both sides of the composite material obtained as described above, as shown in Fig. 5. The conductor layer 105A3 is, for example, a laminate of a seed layer and a plating layer provided thereon. The seed layer and plating layer of the conductor layer 105A3 can be formed using, for example, the methods and materials described above for the seed layer and plating layer of the conductor layer 105A2.

[0065] The seed layer of the conductor layer 105A3 can also be formed by sputtering. When forming the seed layer by sputtering, the material can be, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu3N4, a Cu alloy, or a combination of two or more of these.

[0066] 3, if the through hole TH1 is completely filled with the conductor layer 105A2, the process described with reference to Fig. 5 may be omitted. Also, if there is no need to cover the filling resin 103 with a conductor layer, the process described with reference to Fig. 5 may be omitted.

[0067] Next, a resist resin is applied to both sides of the composite material obtained as described above, or a dry film resist is laminated thereon, and then these resist layers are subjected to pattern exposure and development in sequence to obtain a resist pattern 121 shown in FIG.

[0068] Next, etching is performed using the resist pattern 121 as an etching mask to remove the portions of the conductor layers 105A1, 105A2, and 105A3 that correspond to the openings of the resist pattern 121, as shown in Fig. 7. In this way, the portions of the laminate consisting of the conductor layers 105A1, 105A2, and 105A3 that are located on the main surface of the core insulating layer 101 are obtained as the above-mentioned conductor layer 105A.

[0069] Next, resist pattern 121 is removed from conductor layer 105A, thereby obtaining the core substrate shown in Fig. 8. Note that the core substrate may also be manufactured by other methods.

[0070] Next, as shown in Figures 9 and 10, a heat transfer layer 106 is provided on the core substrate. The cross section shown in Figure 9 is taken along line IX-IX of the structure shown in Figure 10. Also, in Figure 10, the conductor layer 105A is omitted.

[0071] Each of the heat transfer layers 106 has one or more openings at the respective positions of the portions of the core substrate corresponding to the wiring board 10 (hereinafter referred to as wiring board portions), and is provided so as to have at least one of a first portion spanning a first boundary region between adjacent wiring board portions in a first direction and a second portion spanning a second boundary region between adjacent wiring board portions in a second direction intersecting the first direction. For example, the heat transfer layers 106 are provided in a substantially lattice pattern corresponding to the dicing lines.

[0072] Here, as described above, the wiring substrate 10 has a square shape when viewed in its thickness direction, and the heat-transfer layer 106 is provided in a substantially square lattice pattern as shown in Fig. 10. If the wiring substrate 10 has a rectangular shape when viewed in its thickness direction, the heat-transfer layer 106 can be provided in a substantially rectangular lattice pattern.

[0073] The first portions may each have a shape extending in the second direction and extending along first dicing lines aligned in the first direction, or the first portions may be aligned along the first dicing lines and spaced apart from one another.

[0074] The second portions may each have a shape extending in the first direction and extending along second dicing lines aligned in the second direction, or the second portions may be aligned along the second dicing lines and spaced apart from one another.

[0075] The heat transfer layer 106 may include only one of the first portion and the second portion. For example, the heat transfer layer 106 may be provided in a substantially striped pattern.

[0076] Each of the heat transfer layers 106 is preferably provided so as to be in contact with the conductor layer 105A in each wiring substrate portion, as shown in Fig. 9. In this case, each of the heat transfer layers 106 may be provided so as to be in contact with only the end face of the conductor layer 105A in each wiring substrate portion, or may be provided so as to partially cover the main surface of the conductor layer 105A.

[0077] The heat-conductive layer 106 can be formed, for example, by printing a paste containing a heat-conductive material or a precursor thereof onto the core substrate and then curing the printed layer. For this printing, for example, a screen printing method or an inkjet printing method can be used.

[0078] The heat-conductive layer 106 may be provided on the core substrate by a transfer method. That is, a transfer material including the heat-conductive layer 106 and a support supporting the heat-conductive layer 106 in a peelable manner may be prepared, and the heat-conductive layer 106 may be transferred from the support to the core substrate, thereby providing the heat-conductive layer 106 on the core substrate. In this case, the transfer material may further include an adhesive layer covering the heat-conductive layer 106.

[0079] The heat transfer layer 106 may be a layer that can be handled independently. In this case, the heat transfer layer 106 can be provided on the core substrate by, for example, attaching it to the core substrate via an adhesive.

[0080] Next, as shown in FIG. 11, insulating layers 104 having through holes TH2 are formed on both sides of the core substrate provided with the heat transfer layer 106 at the positions of the pad portions of the conductor layer 105A. The insulating layers 104 are formed using, for example, a thermosetting resin or a photosensitive resin. When using a thermosetting resin, a coating film made of the thermosetting resin is cured, and the cured film is subjected to laser processing such as CO2 laser processing and UV laser processing to obtain the insulating layer 104 having through holes TH2. When using a photosensitive resin, the coating film made of the photosensitive resin is subjected to pattern exposure and development to obtain the insulating layer 104 having through holes TH2.

[0081] 12, a seed layer 105B1 is formed to cover the main surface of the insulating layer 104, the sidewalls of the through-holes TH2, and the areas of the surface of the pad portions of the conductor layer 105A that are adjacent to the internal spaces of the through-holes TH2. The seed layer 105B1 can be formed using the methods and materials described above for the seed layers of the conductor layers 105A2 and 105A3.

[0082] Next, a resist resin is applied to both sides of the composite material obtained as described above, or a dry film resist is laminated thereon, and then these resist layers are subjected to pattern exposure and development in sequence to obtain a resist pattern 122 shown in FIG.

[0083] Next, the plating layer 105B2 shown in Fig. 14 is formed by electrolytic plating using the seed layer 105B1 as a power supply layer. The plating layer 105B2 can be made of the metal materials described above for the plating layer of the conductor layer 105A2.

[0084] Next, as shown in FIG. 15, the resist pattern 122 is removed. Next, as shown in Fig. 16, the portion of the seed layer 105B1 that is not covered with the plating layer 105B2 is removed by etching. This results in the conductor layer 105B, which is composed of the seed layer 105B1 and the plating layer 105B2. Note that the portion of the conductor layer 105B that fills the through hole TH2 is a via portion, and the other portions are a pad portion and a wiring portion.

[0085] Next, the cycle including the steps described with reference to Figures 11 to 16 is repeated, thereby obtaining the structure shown in Figure 17.

[0086] Next, as shown in FIG. 18, insulating layers 107 are formed as continuous films on both sides of the composite material obtained as described above. The insulating layers 107 as continuous films are solder resist layers. The solder resist layer can be formed on the composite material by applying a liquid solder resist or laminating a dry film solder resist. The solder resist is, for example, a photosensitive epoxy resin or a non-photosensitive thermosetting resin. The solder resist may further contain an inorganic filler.

[0087] Next, as shown in Fig. 19, through holes TH3 are formed in the insulating layer 107. The through holes TH3 are formed at the positions of the pad portions of the conductor layer 105B covered by the insulating layer 107. When a solder resist containing a photosensitive resin is used, the through holes TH3 can be formed by subjecting the insulating layer 107 in the form of a continuous film to pattern exposure and development. When a solder resist containing a thermosetting resin is used, the through holes TH3 can be formed by subjecting the insulating layer 107 in the form of a continuous film to laser processing such as CO2 laser processing and UV laser processing.

[0088] 20, a surface treatment layer 109 is formed to cover the area of the surface of the pad portion of the conductor layer 105B adjacent to the internal space of the through hole TH3. The surface treatment layer 109 is provided for the purposes of preventing oxidation of the surface of the conductor layer 105B and improving wettability to solder.

[0089] The surface treatment layer 109 is, for example, an electroless Ni / Pd / Au plating layer. The surface treatment layer 109 may be an OSP (Organic Solderability Preservative) film, i.e., a surface treatment layer made of a water-soluble preflux. Alternatively, the surface treatment layer 109 may be an electroless tin plating or an electroless Ni / Au plating layer.

[0090] Next, as shown in FIG. 21, bonding conductors 108 are formed on the surface treatment layer 109. The bonding conductors 108 are, for example, metal bumps such as solder bumps. The bonding conductors 108 can be formed, for example, by printing a metal paste such as solder paste onto the surface treatment layer 109 using a screen printing method. Alternatively, the bonding conductors 108 can be formed by printing flux onto the surface treatment layer 109 using a screen printing method, placing metal balls such as solder balls in the through holes TH3 using a ball transfer method or the like, melting them, and then cooling them. In this manner, the aggregate substrate 10C shown in FIG. 22 is obtained.

[0091] Next, the aggregate substrate 10C is divided into a plurality of wiring substrates 10. Specifically, dicing is performed along dicing lines indicated by dashed lines BL in Fig. 22. In this manner, the wiring substrate 10 shown in Fig. 1 is obtained.

[0092] As described above, in the aggregate substrate 10C, the heat-transfer layer 106 is provided so as to straddle the boundary regions between adjacent wiring substrate portions. Because these boundary regions correspond to dicing lines, the heat-transfer layer 106 is cut when the aggregate substrate 10C is diced. Therefore, in the wiring substrate 10 obtained in this manner, the cut surfaces of the heat-transfer layer 106 are exposed at the end faces thereof.

[0093] <Semiconductor package> FIG. 23 is a cross-sectional view schematically showing an example of a semiconductor package including the wiring board shown in FIG.

[0094] The semiconductor package shown in FIG. 23 includes the above-described wiring substrate 10, a semiconductor chip 20, and a sealing resin layer 30.

[0095] The semiconductor chip 20 is, for example, a silicon chip. The semiconductor chip 20 is provided with an integrated circuit. The semiconductor chip 20 is mounted on the wiring substrate 10. Here, the semiconductor chip 20 is flip-chip mounted on the wiring substrate 10. The semiconductor chip 20 is electrically and thermally connected to the conductor layer 105B of the wiring substrate, etc., via a bonding conductor 108 located on the upper surface of the wiring substrate 10.

[0096] The encapsulating resin layer 30 includes a portion interposed between the wiring substrate 10 and the semiconductor chip 20. The encapsulating resin layer 30 is also called an underfill layer. The encapsulating resin layer 30 fixes the semiconductor chip 20 to the wiring substrate 10. The encapsulating resin layer 30 is made of, for example, a thermosetting epoxy resin. The encapsulating resin layer 30 can be formed, for example, by injecting a thermosetting resin between the semiconductor chip 20 and the wiring substrate 10 and heating it.

[0097] This semiconductor package is mounted on a motherboard or the like via a joining conductor 108 located on the underside of the wiring board 10.

[0098] <Semiconductor module> FIG. 24 is a cross-sectional view schematically showing an example of a semiconductor module including the semiconductor package shown in FIG.

[0099] The semiconductor module 1 shown in FIG. 24 includes the above-described semiconductor package and heat sinks 40A and 40B.

[0100] The heat sinks 40A and 40B are, for example, metal parts with an increased surface area provided with a number of fins or pins.

[0101] The heat sink 40A is placed on the semiconductor chip 20. The semiconductor module 1 may include the above-mentioned heat dissipation plate instead of the heat sink 40A.

[0102] Heat sink 40B is disposed adjacent to wiring board 10 in the in-plane direction. Heat sink 40B is joined to heat-transfer layer 106 of wiring board 10. In the example shown in FIG. 24 , heat sink 40B is in contact with the cut surface of heat-transfer layer 106 exposed at the end face of wiring board 10.

[0103] The heat sink 40B may be bonded to the heat-conductive layer 106 via solder or conductive paste. Alternatively, the heat sink 40B may be bonded to the heat-conductive layer 106 via an insulating material containing grease. The insulating material containing grease may further contain inorganic particles dispersed in the grease. Such an insulating material has a higher thermal conductivity than an insulating material consisting only of grease.

[0104] The semiconductor module 1 may include only one heat sink 40B. The semiconductor module 1 may include multiple heat sinks 40B. For example, if the semiconductor module 1 includes four heat sinks 40B, the heat sinks 40B may be installed adjacent to the four end faces of the wiring substrate 10, respectively.

[0105] <Effects> By employing the above-described configuration for wiring board 10, it becomes possible to manufacture a semiconductor module with excellent heat dissipation properties, as will be described below.

[0106] FIG. 25 is a cross-sectional view schematically showing a semiconductor module according to a first comparative example. 25 is similar to the semiconductor module 1 except for the following points: The semiconductor module 1X includes, instead of the wiring board 10, a wiring board 10X that is similar to the wiring board 10 except that it does not include the heat-transfer layer 106. The semiconductor module 1X does not include a heat sink 40B.

[0107] Fig. 26 is a heat dissipation equivalent circuit diagram of the semiconductor module shown in Fig. 25. Fig. 27 is a heat dissipation equivalent circuit diagram of the semiconductor module shown in Fig. 24.

[0108] 25, the main heat dissipation paths through which heat generated in the semiconductor chip 20 is dissipated to the atmosphere are a first heat dissipation path through which the heat of the semiconductor chip 20 is dissipated to the atmosphere via a heat sink 40A, and a second heat dissipation path through which the heat of the semiconductor chip 20 is dissipated to the atmosphere via the wiring substrate 10X and a motherboard (not shown). The power consumption P of the semiconductor chip 20, the thermal resistance R1 of the first heat dissipation path, the thermal resistance R2 of the second heat dissipation path, the temperature T1 of the semiconductor chip 20, and the temperature T2 of the atmosphere have the relationship shown in the following equation (1), which can be expressed by the heat dissipation equivalent circuit shown in FIG.

[0109]

number

[0110] 24, the main heat dissipation paths through which heat generated in the semiconductor chip 20 is dissipated to the atmosphere are the first and second heat dissipation paths described above, and a third heat dissipation path through which heat from the semiconductor chip 20 is dissipated to the atmosphere via the wiring substrate 10X and the heat sink 40B. The power consumption P of the semiconductor chip 20, the thermal resistance R1 of the first heat dissipation path, the thermal resistance R2 of the second heat dissipation path, the thermal resistance R3 of the third heat dissipation path, the temperature T1 of the semiconductor chip 20, and the temperature T2 of the atmosphere have the relationship shown in the following equation (2), which can be expressed by the heat dissipation equivalent circuit shown in FIG.

[0111]

number

[0112] As is clear from a comparison of equations (1) and (2) and a comparison of Figures 26 and 27, the semiconductor module 1 shown in Figure 24 further includes a third heat dissipation path, and therefore can lower the temperature T1 of the semiconductor chip 20 compared to the semiconductor module 1X shown in Figure 25.

[0113] 28 is a graph showing the heat dissipation performance of semiconductor modules according to an example and a comparative example. In FIG. 28, the horizontal axis represents the power consumption P of the semiconductor chip 20, and the vertical axis represents the temperature T1 of the semiconductor chip 20. Curve L1 represents data obtained by performing a thermal simulation on the semiconductor module 1. Curve L2 represents data obtained by performing a thermal simulation under the same conditions as those for curve L1, except that the thermal conductivity of the heat transfer material constituting the heat transfer layer 106 was lowered. Curve L3 represents data obtained by performing a thermal simulation under the same conditions as those for curve L1, except that the third heat dissipation path was omitted.

[0114] As is clear from FIG. 28, the semiconductor module 1 shown in FIG. 24 further includes a third heat dissipation path, and therefore the temperature T1 of the semiconductor chip 20 can be lowered compared to the semiconductor module 1X shown in FIG.

[0115] Furthermore, by adopting the above-described configurations for the aggregate substrate 10C and the wiring substrate 10, it becomes possible to manufacture semiconductor modules with small variations in heat dissipation between modules, as will be described below.

[0116] FIG. 29 is a cross-sectional view schematically showing a semiconductor module according to a second comparative example.

[0117] 29 is similar to the semiconductor module 1 except for the following points: The semiconductor module 1Y does not include the heat-transfer layer 106, and instead of the wiring board 10, includes a wiring board 10Y that is similar to the wiring board 10 except that the conductor layer 105A has a cut surface created by dicing the aggregate substrate. The heat sink 40B is joined to the conductor layer 105A of the wiring board 10Y.

[0118] As shown in FIG. 29 , if the conductor layer 105A is extended to the edge of the organic insulating layer instead of providing the heat-transfer layer 106 and a heat sink 40B is bonded to the conductor layer 105A at this edge, a portion of the heat generated in the semiconductor chip 20 can be efficiently dissipated to the atmosphere via the bonding conductor 108, the conductor layers 105A and 105B, and the heat sink 40B. However, in manufacturing a wiring board 10Y employing such a structure, when dividing the aggregate board into individual wiring boards 10Y, the aggregate board must be cut at the conductor layer 105A. Copper is generally used for the main conductor layer of the conductor layer 105A. The present inventors have found that cutting an aggregate board whose main conductor layer is made of copper at the conductor layer 105A can result in the following problem. Specifically, when dividing the aggregate board into individual wiring boards 10Y, friction occurs between the dicing blade and the main conductor layer of the conductor layer 105A at the edge created by cutting the aggregate board. Because copper is highly malleable, the friction causes the exposed portion of the main conductor layer at the end face to expand along the direction of blade rotation. This expansion does not occur uniformly. This variation in expansion can cause variations in heat conduction from the conductor layer 105A to the heat sink 40B, i.e., variations in heat dissipation, between modules.

[0119] In contrast, in the aggregate substrate 10C shown in FIG. 22, no conductor layer with a copper main conductor layer is present at the dicing line indicated by the dashed line BL. Instead, a heat-transfer layer 106 is located. When this aggregate substrate 10C is diced into individual wiring substrates 10, friction between the dicing blade and the main conductor layer of the conductor layer 105A is unlikely to occur. Furthermore, as described above, the heat-transfer material constituting the heat-transfer layer 106 contains a non-metallic material or is made of a second metal material that is less malleable than the first metal material constituting the main conductor layer. Such a heat-transfer material is less likely to spread at the end surface due to friction with the dicing blade. Therefore, adopting the above-described configurations for the aggregate substrate 10C and the wiring substrate 10 can reduce the variation in the heat transfer from the wiring substrate 10 to the heat sink 40B, i.e., the variation in heat dissipation, between the semiconductor modules 1 can be reduced.

[0120] Table 1 below shows an example of the relationship between the material of heat-transfer layer 106 and the state of the cut surface of heat-transfer layer 106 that occurs when aggregate substrate 10C is diced.

[0121] [Table 1]

[0122] In Table 1, "composite material" refers to a composite material made of insulating resin and inorganic material dispersed therein. Table 1 shows the physical properties of the heat transfer material, and also shows the state of the cut surface of heat transfer layer 106 resulting from dicing of aggregate substrate 10C as "processability." Here, heat transfer materials marked with "A" in the "processability" column do not spread at the edge due to friction with the dicing blade. Heat transfer materials marked with "B" in the "processability" column slightly spread at the edge due to friction with the dicing blade. Heat transfer materials marked with "C" in the "processability" column significantly spread at the edge due to friction with the dicing blade.

[0123] Fe and Al have lower malleability than Cu. Therefore, when Fe or Al is used as the heat transfer material, spreading at the end surface due to friction with the dicing blade can be suppressed compared to when Cu is used as the heat transfer material, thereby reducing the variation in heat dissipation between semiconductor modules 1. Furthermore, when a composite material containing a non-metallic material is used as the heat transfer material, spreading at the end surface due to friction with the dicing blade can be further suppressed compared to when Fe or Al is used as the heat transfer material, thereby further reducing the variation in heat dissipation between semiconductor modules 1. [Explanation of symbols]

[0124] 1...semiconductor module, 1X...semiconductor module, 1Y...semiconductor module, 10...wiring board, 10C...assembly board, 10X...wiring board, 10Y...wiring board, 20...semiconductor chip, 30...sealing resin layer, 40A...heat sink, 40B...heat sink, 101...core insulating layer, 102...conductor layer, 103...filling resin, 104...insulating layer, 105A...conductor layer, 105A1...conductor layer, 105A2...conductor layer, 105A3...conductor layer, 105B...conductor layer, 105B1...seed layer, 105B2...plating layer, 106...heat transfer layer, 107...insulating layer, 108...bonding conductor, 109...surface treatment layer, 121...resist pattern, 122...resist pattern, BL...dashed line, TH1...through hole, TH2...through hole, TH3...through hole.

Claims

1. two or more organic insulating layers stacked on top of each other; one or more wiring layers each interposed between two adjacent ones of the two or more organic insulating layers, each including a main conductor layer made of a first metal material; one or more heat transfer layers interposed between the two or more organic insulating layers, each made of a heat transfer material having a higher thermal conductivity than the two or more organic insulating layers; Equipped with each of the one or more heat transfer layers has an end surface exposed at the position of an end surface of the two or more organic insulating layers, and is adjacent to one of the one or more wiring layers in an in-plane direction; The heat conductive material includes a non-metallic material or is made of a second metallic material having lower malleability than the first metallic material.

2. The wiring board according to claim 1 , wherein the heat conductive material contains an insulating resin and an inorganic material.

3. The wiring board according to claim 1 , wherein the heat transfer material has a Young's modulus of 3 GPa or less.

4. The wiring board according to claim 1 , wherein the heat transfer material has a breaking elongation of 15% or less.

5. 2. The wiring board according to claim 1, wherein the heat conductive material has a thermal conductivity in the range of 2 to 100 W / m·K.

6. The wiring board according to claim 1 , wherein the at least one heat transfer layer has a higher electrical resistivity than the at least one wiring layer.

7. The wiring board according to claim 1 , wherein the first metal material includes copper.

8. A wiring board according to any one of claims 1 to 7; a semiconductor chip mounted on the wiring substrate; a heat sink bonded to the one or more heat transfer layers; A semiconductor module comprising:

9. The semiconductor module according to claim 8 , wherein the heat sink is bonded to the at least one heat transfer layer via solder or conductive paste.

10. The semiconductor module according to claim 8 , wherein the heat sink is bonded to the at least one heat transfer layer via an insulating material containing grease.

11. The semiconductor module according to claim 10 , wherein the insulating material further includes inorganic particles dispersed in the grease.

12. 8. An aggregate substrate that is divided into a plurality of wiring substrates, each of the plurality of wiring substrates being the wiring substrate according to claim 1.

13. A method for manufacturing a wiring substrate, comprising: dividing the aggregate substrate according to claim 12 into the plurality of wiring substrates.

Images