Crystal oscillator and package for crystal oscillator

Abstract

To provide a crystal oscillator of which the package is made common for a plurality of kinds of IC chips with different electrode terminal configurations, and a package.SOLUTION: A crystal oscillator comprises: a package 2 including a first IC chip mounting pattern 22a corresponding to an array of terminals of a first IC chip 4a, a second IC chip mounting pattern corresponding to an array of terminals of a second IC chip and crystal vibration piece mounting terminals 16 and 17 for mounting a crystal vibration piece 3; any one of the first IC chip 4a mounted in the first IC chip mounting pattern 22a and the second IC chip mounted in the second IC chip mounting pattern; the crystal vibration piece 3 mounted in the crystal vibration piece mounting terminals 16 and 17; and a compatibility structure unit 80 for mutually connecting portions in the first IC chip mounting pattern and the second IC chip mounting pattern corresponding to terminals of the same function in the terminals of the first IC chip and the terminals of the second IC chip.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a crystal oscillator in which a crystal resonator and an integrated circuit chip are mounted, and a crystal oscillator package used therefor. [Background technology]

[0002] In various electronic devices such as mobile phones and personal computers, crystal oscillators are mounted in which a crystal unit and an integrated circuit (IC) chip are mounted in a single package to easily obtain the stable frequencies required for information processing, communication processing, etc. The IC chips mounted in such crystal oscillators include those for wire bonding (W / B), in which the electrode terminals of the IC chip are connected to the electrode terminals of the package via wires, and those for flip chip bonding (FCB), in which the IC chip is mounted on the electrode terminals of the package via bumps.

[0003] For example, Patent Document 1 discloses a crystal oscillator in which an IC chip is mounted by W / B. In the crystal oscillator disclosed in Patent Document 1, a crystal vibrating piece and an IC chip are mounted in a single mounting chamber having a step. In particular, the IC chip is mounted on the bottom surface of the opening of the package (i.e., the bottom surface of the mounting chamber), and electrode terminals of the IC chip are electrically connected to electrode terminals formed on the bottom surface of the package by wires.

[0004] Meanwhile, Patent Document 2 discloses a crystal oscillator in which an IC chip is mounted by FCB. In the crystal oscillator disclosed in Patent Document 2, a crystal chamber and an IC chamber are stacked, and a crystal vibrating element and an IC chip are mounted in a ceramic package with a so-called H-shaped cross section. In particular, the IC chip is mounted on electrode terminals formed in the IC chamber via conductive bonding members such as solder bumps. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2017-220906 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-91103 Summary of the Invention [Problem to be solved by the invention]

[0006] Even if the IC chips used as components for crystal oscillators have the same characteristics, the electrode terminal configurations may differ. For example, the electrode terminal arrangement may differ between an IC chip for W / B and an IC chip for FCB.

[0007] However, in a package in which an IC chip is mounted using an FCB, the electrode terminal pattern for the IC chip formed on the package is designed to correspond to the electrode terminals of the IC chip to be mounted. Therefore, IC chips for W / Bs and other IC chips that are not intended for mounting cannot be mounted because they do not match the electrode terminal pattern.

[0008] The present disclosure has been made in consideration of these problems, and its purpose is to provide a crystal oscillator in which a package is standardized for multiple types of IC chips with different electrode terminal configurations, and a crystal oscillator package used therefor. [Means for solving the problem]

[0009] According to one aspect of the present disclosure, there is provided a crystal oscillator comprising: a package having a first IC chip mounting pattern corresponding to the arrangement of the terminals of a first IC chip, a second IC chip mounting pattern corresponding to the arrangement of the terminals of a second IC chip, and crystal resonator blank mounting terminals for mounting a crystal resonator blank; one of the first IC chip mounted on the first IC chip mounting pattern and the second IC chip mounted on the second IC chip mounting pattern; a crystal resonator blank mounted on the crystal resonator blank mounting terminals; and a compatibility structure connecting portions of the first IC chip mounting pattern and the second IC chip mounting pattern that correspond to terminals with the same functions of the terminals of the first IC chip and the terminals of the second IC chip.

[0010] According to one aspect of the present disclosure, there is provided a package for a crystal oscillator, comprising: a first IC chip mounting pattern corresponding to the arrangement of the terminals of a first IC chip, a second IC chip mounting pattern corresponding to the arrangement of the terminals of a second IC chip, and a crystal vibrating piece mounting terminal for mounting a crystal vibrating piece; and a compatibility structure that connects portions of the first IC chip mounting pattern and the second IC chip mounting pattern that correspond to terminals of the same function of the terminals of the first IC chip and the terminals of the second IC chip. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to provide a crystal oscillator in which a package is standardized for a plurality of types of IC chips with different electrode terminal configurations, and a crystal oscillator package used therefor.

[0012] It should be noted that the above effects are merely examples for the sake of convenience of explanation, and the effects of the present disclosure are not limited to these. In addition to the above effects, the present disclosure can achieve any of the effects described herein. [Brief explanation of the drawings]

[0013] [Figure 1]FIG. 1 is a perspective view of a crystal oscillator according to a first embodiment. [Figure 2] 2(a) is an end view taken along dashed line AA in FIG. 1, FIG. 2(b) is a top view of a package constituting the crystal oscillator according to the first embodiment, and FIG. 2(c) is a top view of an IC chip constituting the crystal oscillator according to the first embodiment. [Figure 3] 3(a) is an end view of the package taken along the dashed line BB in FIG. 2(b), and FIG. 3(b) is an end view of another package taken along the dashed line BB in FIG. 2(b). [Figure 4] 4(a) is an end view taken along dashed line AA in FIG. 1, FIG. 4(b) is a top view of a package constituting the crystal oscillator according to the first embodiment, and FIG. 4(c) is a top view of an IC chip constituting the crystal oscillator according to the first embodiment. [Figure 5] FIG. 5(a) is a top view of a package constituting a crystal oscillator according to a modified example of the first embodiment, FIG. 5(b) is a top view of a package constituting a crystal oscillator according to a modified example of the first embodiment, and FIG. 5(c) is a top view of an IC chip constituting a crystal oscillator according to a modified example of the first embodiment. [Figure 6] FIG. 6(a) is a top view of a package constituting a crystal oscillator according to a modified example of the first embodiment, FIG. 6(b) is a top view of a package constituting a crystal oscillator according to a modified example of the first embodiment, and FIG. 6(c) is a top view of an IC chip constituting a crystal oscillator according to a modified example of the first embodiment. [Figure 7] FIG. 10 is a perspective view of a crystal oscillator according to a second embodiment. [Figure 8] FIG. 8(a) is an end view taken along the dashed dotted line CC in FIG. 7, and FIG. 8(b) is a top view of a package constituting the crystal oscillator according to the second embodiment. [Figure 9] 9(a) is an end view taken along the dashed-dotted line CC in FIG. 7, and FIG. 9(b) is a bottom view of the package that constitutes the crystal oscillator according to the second embodiment. [Figure 10]FIG. 10(a) is an end view of a crystal oscillator according to a modified example of the second embodiment, FIG. 10(b) is a bottom view of a package that constitutes the crystal oscillator according to the modified example of the second embodiment, and FIG. 10(c) is a top view of an IC chip that constitutes the crystal oscillator according to the modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] The crystal oscillator and crystal oscillator package used therein according to the present disclosure will be described in detail below with reference to the drawings. The present disclosure is not limited to the content described below and may be modified as desired without departing from the spirit and scope of the present disclosure. The drawings used in each embodiment are schematic illustrations of the crystal oscillator and crystal oscillator package according to the present disclosure. To facilitate understanding, some parts may be emphasized, enlarged, reduced, or omitted, and the scale and shape of each component may not be accurately represented. Furthermore, some numerical values used in each embodiment and its modified examples are merely examples and may be subject to various modifications as necessary. The same reference symbols are used to designate common components in the drawings.

[0015] (First embodiment) The basic structure of a crystal oscillator and its package according to the present disclosure will be described with reference to FIGS. 1 to 4. FIG. 1 is a perspective view of a crystal oscillator according to this embodiment. FIG. 2(a) is an end view taken along dashed line AA in FIG. 1. FIG. 2(b) is a top view of a package constituting the crystal oscillator according to this embodiment, particularly showing an example of the mounting position of an IC chip. FIG. 2(c) is a top view of an IC chip constituting the crystal oscillator according to this embodiment, particularly showing the configuration of the electrode terminals of the IC chip mounted in FIG. 2(b). FIG. 3(a) is an end view of the package taken along dashed line BB in FIG. 2(b), and FIG. 3(b) is an end view of another package taken along dashed line BB in FIG. 2(b). Like FIG. 2, FIG. 4(a) is an end view taken along dashed line AA in FIG. 1, showing the case where another IC chip is mounted. FIG. 4(b) is a top view of a package constituting the crystal oscillator according to this embodiment, particularly showing the mounting position of another IC chip. FIG. 4(c) is a top view of another IC chip that constitutes the crystal oscillator according to this embodiment, and particularly shows the configuration of the electrode terminals of the other IC chip mounted in FIG. 4(b).

[0016] 1 and 2(a) to 2(c), the crystal oscillator 1 comprises a crystal oscillator package 2 (hereinafter simply referred to as package 2), a crystal vibrating piece 3 and a first IC chip 4a mounted in a recessed mounting space 2a of the package 2, and a metal cover (lid) 5 for sealing the mounting space 2a. The crystal oscillator 1 is an electronic component in which the crystal vibrating piece 3 and the IC chip 4a are packaged together, and is capable of generating a stable frequency and a regular reference signal.

[0017] The package 2 is a ceramic package formed by stacking multiple ceramics on the surface of which a desired metal pattern is formed. Specifically, the package 2 has a laminated structure in which a first frame wall 11 with an opening of a predetermined size, a second frame wall 12 with an opening smaller than that of the first frame wall 11 and a greater thickness, and a rectangular bottom plate 13 are stacked. This laminated structure provides the package 2 with a recessed, stepped mounting space 2a for mounting the crystal vibrating piece 3 and IC chip 4a. The package 2 has a rectangular parallelepiped shape and is rectangular in top view ( FIG. 2(b) ). Hereinafter, the thickness direction of the crystal oscillator 1 and the package 2 is referred to as the vertical direction, and the direction perpendicular to the vertical direction is referred to as the horizontal direction. The horizontal direction may also be distinguished as the longitudinal direction (direction of the long sides) and the lateral direction (direction of the short sides) of the crystal oscillator 1 and the package 2.

[0018] A sealing conductor pattern 15 is formed on the upper surface 11a, which is the exposed surface of the first frame wall 11 of the package 2. The planar shape of the conductor pattern 15 is frame-like, just like the first frame wall 11. A cover 5 is bonded onto the conductor pattern 15 by known metal bonding. This seals the mounting space 2a of the package, and the mounting space 2a is sealed using a vacuum or a gas such as nitrogen.

[0019] Two rectangular crystal vibrating piece mounting terminals 16 and 17 are formed on the surface 12a of the second frame wall 12 of the package 2, which is the surface on which the first frame wall 11 is laminated. The crystal vibrating piece 3 is mounted on the crystal vibrating piece mounting terminals 16 and 17 via a conductive adhesive 18.

[0020] Four external connection terminals 20a, 20b, 20c, and 20d are formed on a first surface 13a of a bottom plate 13 of the package 2. Eight IC chip electrode terminals are formed on a second surface 13b of the bottom plate 13. Specifically, as shown in Fig. 2(b), a first terminal 21a (XTN) connected to one terminal of the crystal resonator, a second terminal 21b and a third terminal 21c for ground potential (GND), a fourth terminal 21d and a fifth terminal 21e for IC operating voltage (VDD), a sixth terminal 21f (Q) for IC output, a seventh terminal 21g (INHN) for IC control, and an eighth terminal 21h (XT) connected to the other terminal of the crystal resonator are formed on the same plane. In particular, the first terminal 21a, the second terminal 21b, the fourth terminal 21d, and the sixth terminal 21f are arranged side by side and spaced apart from each other in the longitudinal direction of the package 2 when viewed from above, and similarly, the third terminal 21c, the fifth terminal 21e, the seventh terminal 21g, and the eighth terminal 21h are also arranged side by side and spaced apart from each other in the longitudinal direction of the package 2 when viewed from above.

[0021] The first terminal 21a and the eighth terminal 21h are formed in rectangular shapes of approximately the same dimensions and are opposed to each other in the short-side direction of the package 2 in a top view. The second terminal 21b, the third terminal 21c, the fourth terminal 21d, and the fifth terminal 21e are formed in rectangular shapes of approximately the same dimensions. The sixth terminal 21f and the seventh terminal 21g are formed in square shapes of approximately the same dimensions. The second terminal 21b and the fourth terminal 21d are arranged side by side with a gap between them and are opposed to the seventh terminal 21g in the short-side direction of the package 2 in a top view. Similarly, the third terminal 21c and the fifth terminal 21e are arranged side by side with a gap between them and are opposed to the sixth terminal 21f in the short-side direction of the package 2 in a top view. Therefore, the areas of the second terminal 21b, the third terminal 21c, the fourth terminal 21d, and the fifth terminal 21e are approximately half those of the sixth terminal 21f and the seventh terminal 21g.

[0022] As shown in FIG. 3(a), the second terminal 21b and the third terminal 21c are electrically connected by an internal wiring 50 formed inside the bottom plate 13 of the package 2. Similarly, the fourth terminal 21d and the fifth terminal 21e are electrically connected by an internal wiring 51 formed inside the package 2. Here, in FIG. 3(a), the internal wiring 50 and the internal wiring 51 are preferably formed on the same level in the bottom plate 13. However, as shown in FIG. 3(b), the internal wiring 50 and the internal wiring 51 may be formed on the same level in the bottom plate 13. That is, in the case shown in FIG. 3(b), the internal wiring 51 is formed at a position closer to the second surface 13b of the bottom plate 13 (a shallower position), while the internal wiring 50 is formed at a position farther from the second surface 13b of the bottom plate 13 (a deeper position). These internal wirings 50 and 51 constitute an interchangeable structure, which will be described later.

[0023] In this embodiment, two types of IC chip mounting patterns are configured from the eight IC chip electrode terminals. Specifically, as shown in Fig. 2(b), a first IC chip mounting pattern 22a is configured from six terminals: the first terminal 21a, the third terminal 21c, the fourth terminal 21d, the sixth terminal 21f, the seventh terminal 21g, and the eighth terminal 21h. Also, as shown in Fig. 4(b), a second IC chip mounting pattern 22b is configured from six terminals: the first terminal 21a, the second terminal 21b, the fifth terminal 21e, the sixth terminal 21f, the seventh terminal 21g, and the eighth terminal 21h.

[0024] As can be seen from FIGS. 2(a) and 2(b), an IC chip 4a is mounted on the first IC chip mounting pattern 22a via six bumps 31a-31f. The IC chip 4a is a flip-chip bonding type IC. As can be seen from FIGS. 2(b) and 2(c), the IC chip 4a has a rectangular shape in a plan view and six IC terminals. Specifically, the IC chip 4a has a first terminal 41a (XTN) connected to one terminal of the crystal unit, a second terminal 41b (VDD) for IC operating voltage, a third terminal 41c (Q) for IC output, a fourth terminal 41d (GND) for ground potential, a fifth terminal 41e (INHN) for IC control, and a sixth terminal 41f (XT) connected to the other terminal of the crystal unit.

[0025] The IC chip 4a is mounted so as to be displaced in the longitudinal direction away from the crystal vibrating piece mounting terminals 16, 17. Specifically, the first terminal 41a of the IC chip 4a is electrically connected to the first terminal 21a of the package 2 via the bump 31a, the second terminal 41b of the IC chip 4a is electrically connected to the fourth terminal 21d of the package 2 via the bump 31b, the third terminal 41c of the IC chip 4a is electrically connected to the sixth terminal 21f of the package 2 via the bump 31c, the fourth terminal 41d of the IC chip 4a is electrically connected to the third terminal 21c of the package 2 via the bump 31d, the fifth terminal 41e of the IC chip 4a is electrically connected to the seventh terminal 21g of the package 2 via the bump 31e, and the sixth terminal 41f of the IC chip 4a is electrically connected to the eighth terminal 21h of the package 2 via the bump 31f. That is, the IC terminals of the IC chip 4a and the IC electrode terminals of the package are electrically connected such that the XTN terminals, GND terminals, VDD terminals, Q terminals, INHN terminals, and XT terminals correspond to each other.

[0026] Next, as can be seen from FIGS. 4(a) and 4(b), a second IC chip, IC chip 4b, is mounted on second IC chip mounting pattern 22b via six bumps 32a-32f. Here, IC chip 4b is a wire-bonded IC, but is flip-chip bonded using bumps rather than the usual wire connection. Also, as can be seen from FIGS. 4(b) and 4(c), IC chip 4b has a rectangular shape in a plan view and six IC terminals. Specifically, IC chip 4b has a first terminal 42a (XTN) connected to one terminal of the crystal unit, a second terminal 42b for ground potential (GND), a third terminal 42c for IC output (Q), a fourth terminal 42d for IC operating voltage (VDD), a fifth terminal 42e for IC control (INHN), and a sixth terminal 42f (XT) connected to the other terminal of the crystal unit. In particular, in the IC chip 4b, the positions of the electrode terminals for the ground potential and the electrode terminals for the IC operating voltage are interchanged compared to the IC chip 4a.

[0027] The IC chip 4b is mounted at a longitudinal position displaced closer to the crystal vibrating piece mounting terminals 16, 17 than the IC chip 4a. Specifically, the first terminal 42a of the IC chip 4b is electrically connected to the first terminal 21a of the package 2 via the bump 32a, the second terminal 42b of the IC chip 4b is electrically connected to the second terminal 21b of the package 2 via the bump 32b, the third terminal 42c of the IC chip 4b is electrically connected to the sixth terminal 21f of the package 2 via the bump 32c, the fourth terminal 42d of the IC chip 4b is electrically connected to the fifth terminal 21e of the package 2 via the bump 32d, the fifth terminal 42e of the IC chip 4b is electrically connected to the seventh terminal 21g of the package 2 via the bump 32e, and the sixth terminal 42f of the IC chip 4b is electrically connected to the eighth terminal 21h of the package 2 via the bump 32f. That is, with regard to the IC terminals of the IC chip 4b and the IC electrode terminals of the package, the XTN terminals, the GND terminals, the VDD terminals, the Q terminals, the INHN terminals, and the XT terminals are electrically connected to each other.

[0028] As can be seen from Figures 2(b) and 4(b), in the mounting positional relationship between the IC chip 4a and the IC chip 4b, the first terminals 41a and 42a, which are XTN terminals, the third terminals 41c and 42c, which are Q terminals, the fifth terminals 41e and 42e, which are INHN terminals, and the sixth terminals 41f and 42f, which are XT terminals, are adjacent to each other in a direction parallel to one side of the rectangular planar shape of the IC chip. That is, among the terminals of the IC chip 4a and the IC chip 4b, multiple pairs of terminals having the same function (first terminal group) are adjacent to each other in a direction parallel to one side of the rectangular shape. In contrast, in the mounting positional relationship between the IC chip 4a and the IC chip 4b, the second terminal 41b and the fourth terminal 42d, which are VDD terminals, and the fourth terminal 41d and the second terminal 42b, which are GND terminals, are arranged diagonally with respect to one side of the rectangular planar shape of the IC chip. That is, among the terminals of IC chip 4a and IC chip 4b, the terminals of a set other than the first terminal group (second terminal group) are positioned diagonally relative to one side of the quadrangle.

[0029] As can be seen from FIGS. 2(b) and 4(b), the second terminal 41b and the fourth terminal 42d, which are VDD terminals, and the fourth terminal 41d and the second terminal 42b, which are GND terminals, each have a dedicated terminal (the second terminal 21b, the third terminal 21c, the fourth terminal 21d, and the fifth terminal 21e) connected via a bump. That is, two terminals are formed for each of the VDD terminal and the GND terminal. More specifically, the second terminal 21b for GND is individually formed as an additional pattern in a diagonal direction relative to the third terminal 21c for GND. Similarly, the fifth terminal 21e for VDD is individually formed as an additional pattern in a diagonal direction relative to the fourth terminal 21d for VDD. That is, in the package 2, the additional patterns 21b and 21e (the second terminal 21b and the fifth terminal 21e) are individually formed in a diagonal direction in accordance with the positional relationship of the second terminal group described above.

[0030] 2(b) and 4(b), the first terminals 41a and 42a, which are XTN terminals, the third terminals 41c and 42c, which are Q terminals, the fifth terminals 41e and 42e, which are INHN terminals, and the sixth terminals 41f and 42f, which are XT terminals, are formed as common terminals (the first terminal 21a, the sixth terminal 21f, the seventh terminal 21g, and the eighth terminal 21h) for the same functions. That is, only one terminal is formed for the XTN terminal, the Q terminal, the INHN terminal, and the XT terminal, but these terminals are formed to be expanded compared to the terminals for the VDD terminal and the GND terminal. In other words, the areas of the terminals for the XTN terminal, the Q terminal, the INHN terminal, and the XT terminal are expanded compared to when they are not shared terminals of the terminals of the two types of IC chips, and an expanded pattern is formed. 4(b), the portions of the first terminal 21a, the sixth terminal 21f, the seventh terminal 21g, and the eighth terminal 21h to which the first terminal 42a, the third terminal 42c which is a Q terminal, the fifth terminal 42e which is an INHN terminal, and the sixth terminal 42f which is an XT terminal of the IC chip 4b are connected correspond to the extension pattern 71. That is, in the package 2, in accordance with the positional relationship of the first terminal group described above, the extension pattern 71 is formed by extending the area of the portion corresponding to the first terminal group to an area including adjacent positions.

[0031] 2(b) and 4(b), the package 2 includes a compatibility structure 80 for connecting the first IC chip mounting pattern 22a and the second IC chip mounting pattern 22b, which correspond to terminals of the IC chip 4a and the IC chip 4b, respectively, that have the same functions. In particular, in this embodiment, the compatibility structure 80 includes the additional patterns, the third terminal 21c for GND and the fifth terminal 21e for VDD, the extension pattern 71, and the internal wiring 50, 51. The provision of this compatibility structure 80 allows the terminals on the package to be positioned corresponding to the terminals of each IC chip, enabling proper mounting of either of two types of IC chips with different terminal configurations without impairing the IC chip's functionality.

[0032] Furthermore, in the package 2 of this embodiment, the short side dimensions of the electrode terminal for the ground potential and the electrode terminal for the IC operating voltage are approximately half those of the other electrode terminals. Furthermore, two electrode terminals of each type are provided. Therefore, a first IC chip mounting pattern 22a for mounting an IC chip 4a, which is a flip-chip bonding type IC, and a second IC chip mounting pattern 22b for mounting an IC chip 4b, which is a wire-bonding type IC, are formed on the same plane (second surface 13b) of the bottom plate 13. Therefore, depending on the IC chip to be mounted, it is possible to mount only one of the two types of IC chips simply by shifting the mounting position in the longitudinal direction of the package 2. In other words, even if two types of IC chips have different electrode patterns, they can be mounted using the same package 2, thereby achieving package standardization. In particular, in this embodiment, since flip-chip bonding type ICs and wire-bonding type ICs can be selectively mounted, it is possible to continuously manufacture crystal oscillators 1 using available IC chips, even if the IC chip supply situation in the market changes.

[0033] The different types of IC chips are not limited to flip-chip bonding type ICs and wire-bonding type ICs. For example, flip-chip bonding type ICs with different electrode terminal arrangements may be selected and mounted in package 2.

[0034] (Modification of the first embodiment) In the above embodiment, two electrode terminals for the ground potential and two electrode terminals for the IC operating voltage are provided, but two other electrode terminals may also be provided. For example, two XT terminals and two XTN terminals electrically connected to the crystal resonator blank mounting terminals may be provided. Such a modification will be described with reference to FIGS. 5(a) to 5(c). Here, FIG. 5(a) is a top view of a package 2' constituting a crystal oscillator according to a modification of the first embodiment, FIG. 5(b) is a top view of a package 2' constituting a crystal oscillator 1 according to a modification of the first embodiment, and FIG. 5(c) is a top view of an IC chip 4c constituting a crystal oscillator according to a modification of the first embodiment. Note that the same components as those in the above embodiment are designated by the same reference numerals, and their description will be omitted.

[0035] 5(a), the package 2' has eight IC chip electrode terminals formed on the same plane: a first terminal 23a and a second terminal 23b (XT) connected to one terminal of the crystal unit, a third terminal 23c and a fourth terminal 23d (XTN) connected to the other terminal of the crystal unit, a fifth terminal 23e (VDD) for IC operating voltage, a sixth terminal 23f (Q) for IC output, a seventh terminal 23g (GND) for ground potential, and an eighth terminal 23h (INHN) for IC control. The areas of the first terminal 23a, the second terminal 23b, the third terminal 23c, and the fourth terminal 23d are approximately half the areas of the other terminals. In this modified example, as shown in Figure 5(a), the first IC chip mounting pattern 24a is composed of six second terminals 23b, third terminal 23c, fifth terminal 23e, sixth terminal 23f, seventh terminal 23g and eighth terminal 23h.

[0036] 5(a), the IC chip 4a is mounted on the first IC chip mounting pattern 24a via six bumps 31a to 31f. The IC chip 4a is mounted while being displaced in the longitudinal direction away from the crystal vibrating piece mounting terminals 16 and 17. Specifically, the first terminal 41a of the IC chip 4a is electrically connected to the third terminal 23c of the package 2' via the bump 31a, the second terminal 41b of the IC chip 4a is electrically connected to the fifth terminal 23e of the package 2' via the bump 31b, the third terminal 41c of the IC chip 4a is electrically connected to the sixth terminal 23f of the package 2' via the bump 31c, the fourth terminal 41d of the IC chip 4a is electrically connected to the seventh terminal 23g of the package 2' via the bump 31d, the fifth terminal 41e of the IC chip 4a is electrically connected to the eighth terminal 23h of the package 2' via the bump 31e, and the sixth terminal 41f of the IC chip 4a is electrically connected to the second terminal 23b of the package 2' via the bump 31f.

[0037] Furthermore, in this modification, as shown in FIG. 5(b), a second IC chip mounting pattern 24b is formed by six terminals: a first terminal 23a, a fourth terminal 23d, a fifth terminal 23e, a sixth terminal 23f, a seventh terminal 23g, and an eighth terminal 23h. As can be seen from FIG. 5(b), an IC chip 4c, which corresponds to the second IC chip, is mounted on the second IC chip mounting pattern 24b via six bumps 33a-33f. Although the IC chip 4c is a wire-bonded IC, flip-chip bonding using bumps is performed instead of the usual connection using wires. As can be seen from FIGS. 5(b) and 5(c), the IC chip 4c has a rectangular shape in a plan view and six IC terminals. Specifically, the IC chip 4c has a first terminal 43a (XT) connected to one terminal of the crystal unit, a second terminal 43b (VDD) for IC operating voltage, a third terminal 43c (Q) for IC output, a fourth terminal 43d (GND) for ground potential, a fifth terminal 43e (INHN) for IC control, and a sixth terminal 43f (XTN) connected to the other terminal of the crystal unit. In particular, the positions of the XT terminal and the XTN terminal are swapped in the IC chip 4c compared to the IC chip 4a.

[0038] 5(a) and 5(b), the IC chip 4c is mounted so as to be displaced in the longitudinal direction relative to the IC chip 4a in a direction closer to the crystal vibrating piece mounting terminals 16, 17. Specifically, the first terminal 43a of the IC chip 4c is electrically connected to the first terminal 23a of the package 2′ via the bump 33a, the second terminal 43b of the IC chip 4c is electrically connected to the fifth terminal 23e of the package 2′ via the bump 33b, the third terminal 43c of the IC chip 4c is electrically connected to the sixth terminal 23f of the package 2′ via the bump 33c, the fourth terminal 43d of the IC chip 4c is electrically connected to the seventh terminal 23g of the package 2′ via the bump 33d, the fifth terminal 43e of the IC chip 4c is electrically connected to the eighth terminal 23h of the package 2′ via the bump 33e, and the sixth terminal 43f of the IC chip 4c is electrically connected to the fourth terminal 23d of the package 2′ via the bump 33f.

[0039] The first terminal 23a and the second terminal 23b are electrically connected by internal wiring (not shown) formed inside the package 2'. Similarly, the third terminal 23c and the fourth terminal 23d are electrically connected by internal wiring (not shown) formed inside the package 2'. For example, they may be connected by internal wiring on the same layer or internal wiring on different layers, as shown in FIG. 3(a) or 3(b).

[0040] 5(a) and 5(b), the first terminal 23a, which is an XT terminal, and the fourth terminal 23d, which is an XTN terminal, correspond to additional patterns, and the fifth terminal 23e, which is a VDD terminal, the sixth terminal 23f, which is a Q terminal, the seventh terminal 23g, which is a GND terminal, and the eighth terminal 23h, which is an INHN terminal, are provided with an extension pattern 71. The additional patterns 23a and 23d, the extension pattern 71, and the internal wiring constitute a compatibility structure 80.

[0041] As described above, in the package 2' of the above modification, the short side dimensions of the XT terminals and the XTN terminals are about half those of the other electrode terminals, and two of each type of electrode terminal are arranged, so that a first IC chip mounting pattern 24a for mounting an IC chip 4a, which is a flip-chip bonding type IC, and a second IC chip mounting pattern 24b for mounting an IC chip 4c, which is a wire-bonding type IC, are formed on the same plane (second surface 13b) of the bottom plate 13. Therefore, two types of IC chips can be mounted simply by displacing the mounting position in the longitudinal direction of the package 2' depending on the IC chip to be mounted.

[0042] Naturally, the two electrode terminals arranged in each package are not limited to the above-mentioned electrode terminals, and can be selected appropriately depending on the configuration of the IC chip. Furthermore, the arrangement of the electrode terminals in the package is not limited to the above-mentioned contents, and the position of each electrode terminal can be changed appropriately depending on the IC chip to be mounted.

[0043] Next, in the above embodiment, two types of electrodes are arranged in pairs, but two of each of all electrode terminals may be arranged. Such a modification will be described with reference to FIGS. 6(a) to 6(c). Here, FIG. 6(a) is a top view of a package 2" that constitutes a crystal oscillator according to a modification of the first embodiment, FIG. 6(b) is a top view of a package 2" that constitutes a crystal oscillator 1 according to a modification of the first embodiment, and FIG. 6(c) is a top view of an IC chip 4d that constitutes a crystal oscillator according to a modification of the first embodiment. Note that the same components as those in the above embodiment are given the same reference numerals, and their description will be omitted.

[0044] First, as shown in FIG. 6(a), in the package 2″, twelve IC chip electrode terminals are formed on the same plane: a first terminal 25a and a second terminal 25b (XT) connected to one terminal of the crystal resonator; a third terminal 25c and a fourth terminal 25d (XTN) connected to the other terminal of the crystal resonator; a fifth terminal 25e and a sixth terminal 25f (INHN) for IC control; a seventh terminal 25g and an eighth terminal 25h (VDD) for IC operating voltage; a ninth terminal 25i and a tenth terminal 25j (GND) for ground potential; and an eleventh terminal 25k and a twelfth terminal 25m (Q) for IC output. In this modified example, as shown in FIG. 6(a), a first IC chip mounting pattern 26a is formed by the six terminals: the second terminal 25b, the third terminal 25c, the sixth terminal 25f, the seventh terminal 25g, the tenth terminal 25j, and the eleventh terminal 25k.

[0045] 6(a), the IC chip 4a is mounted on the first IC chip mounting pattern 26a via six bumps 31a to 31f. The IC chip 4a is mounted so as to be displaced away from the crystal vibrating piece mounting terminals 16 and 17. Specifically, the first terminal 41a of the IC chip 4a is electrically connected to the third terminal 25c of the package 2" via the bump 31a, the second terminal 41b of the IC chip 4a is electrically connected to the seventh terminal 25g of the package 2" via the bump 31b, the third terminal 41c of the IC chip 4a is electrically connected to the eleventh terminal 25k of the package 2" via the bump 31c, the fourth terminal 41d of the IC chip 4a is electrically connected to the tenth terminal 25j of the package 2" via the bump 31d, the fifth terminal 41e of the IC chip 4a is electrically connected to the sixth terminal 25f of the package 2" via the bump 31e, and the sixth terminal 41f of the IC chip 4a is electrically connected to the second terminal 25b of the package 2" via the bump 31f.

[0046] Furthermore, in this modification, as shown in FIG. 6(b), a second IC chip mounting pattern 26b is configured by six terminals: a first terminal 25a, a fourth terminal 25d, a fifth terminal 25e, an eighth terminal 25h, a ninth terminal 25i, and a twelfth terminal 23m. As can be seen from FIG. 6(b), an IC chip 4d, which corresponds to the second IC chip, is mounted on the second IC chip mounting pattern 26b via six bumps 34a-34f. Although the IC chip 4d is a wire-bonded IC, it is flip-chip bonded using bumps rather than the usual connection using wires. Each terminal constituting the second IC chip mounting pattern 26b corresponds to an additional pattern.

[0047] 6(b) and 6(c), the IC chip 4d has a rectangular shape in a plan view and six IC terminals. Specifically, the IC chip 4d has a first terminal 44a (XT) connected to one terminal of the crystal unit, a second terminal 44b (INHN) for IC control, a third terminal 44c (GND) for ground potential, a fourth terminal 44d (Q) for IC output, a fifth terminal 44e (VDD) for IC operating voltage, and a sixth terminal 44f (XTN) connected to the other terminal of the crystal unit. Compared to the IC chip 4a, the electrode terminals of the IC chip 4c are symmetrically swapped with respect to the longitudinal direction of the IC chip. That is, the XT terminal and the XTN terminal, the INHN terminal and the VDD terminal, and the GND terminal and the Q terminal are swapped.

[0048] 6(a) and 6(b), the IC chip 4d is mounted so as to be displaced in the longitudinal direction relative to the IC chip 4a in a direction closer to the crystal vibrating piece mounting terminals 16 and 17. Specifically, the first terminal 44a of the IC chip 4d is electrically connected to the first terminal 25a of the package 2″ via the bump 34a, the second terminal 44b of the IC chip 4c is electrically connected to the fifth terminal 25e of the package 2″ via the bump 34b, the third terminal 44c of the IC chip 4c is electrically connected to the ninth terminal 25i of the package 2″ via the bump 34c, the fourth terminal 44d of the IC chip 4c is electrically connected to the twelfth terminal 25m of the package 2″ via the bump 34d, the fifth terminal 44e of the IC chip 4c is electrically connected to the eighth terminal 25h of the package 2″ via the bump 34e, and the sixth terminal 44f of the IC chip 4c is electrically connected to the fourth terminal 25d of the package 2″ via the bump 34f.

[0049] The first terminal 25a and the second terminal 25b are electrically connected by internal wiring (not shown) formed inside the package 2". Similarly, the third terminal 25c and the fourth terminal 25d, the fifth terminal 25e and the sixth terminal 25f, the seventh terminal 25g and the eighth terminal 25h, the ninth terminal 25i and the tenth terminal 25j, and the eleventh terminal 25k and the twelfth terminal 25m are electrically connected by internal wiring (not shown) formed inside the package 2". For example, as shown in FIG. 3(a) or 3(b), they may be connected by internal wiring in the same layer or internal wiring in different layers.

[0050] As described above, the terminals constituting the second IC chip mounting pattern 26b correspond to additional patterns, and are not formed as extended patterns. Therefore, in this modification, the terminals constituting the second IC chip mounting pattern 26b and the above-mentioned internal wiring form the compatibility structure 80.

[0051] As described above, in the package 2" of the above modified example, all of the electrode terminals are arranged in pairs, so that the first IC chip mounting pattern 26a for mounting the IC chip 4a, which is a flip-chip bonding type IC, and the second IC chip mounting pattern 26b for mounting the IC chip 4d, which is a wire-bonding type IC, are formed on the same plane (second surface 13b) of the bottom plate 13. Therefore, two types of IC chips can be mounted simply by displacing the mounting position in the longitudinal direction of the package 2" depending on the IC chip to be mounted.

[0052] Naturally, the two electrode terminals do not have to be all types, and three or more electrode terminals may be selected as appropriate. That is, electrode terminals for oscillation input, IC control, ground potential, IC output, IC operating voltage, and oscillation output may be selected as appropriate depending on the configuration of the IC chip. Furthermore, the arrangement of the electrode terminals in the package is not limited to the above, and the position of each electrode terminal may be changed as appropriate depending on the IC chip to be mounted.

[0053] (Second embodiment) In the first embodiment, the first IC chip mounting pattern 22a and the second IC chip mounting pattern 22b were formed on the same plane of the bottom plate 13 of the package 2, and the IC chips 4a and 4b could be mounted by shifting them horizontally, but the mounting patterns corresponding to the IC chips may be formed on different planes. Such a case will be described as the second embodiment with reference to Figures 7, 8(a)-(b), and 9(a)-(b).

[0054] Here, FIG. 7 is a perspective view of the crystal oscillator according to this embodiment. Also, FIG. 8(a) is an end view taken along dashed line CC in FIG. 7. Furthermore, FIG. 8(b) is a top view of the package constituting the crystal oscillator according to this embodiment, particularly showing an example of the mounting position of the IC chip. FIG. 9(a) is an end view taken along dashed line CC in FIG. 7, showing the case where another IC chip is mounted. Furthermore, FIG. 9(b) is a bottom view of the package constituting the crystal oscillator according to this embodiment, particularly showing the mounting position of another IC chip. Note that only the parts that differ from the first embodiment and its modifications will be described, and descriptions of the same parts will be omitted, and the same reference numerals will be used in the drawings.

[0055] 7, 8(a), and 8(b), the crystal oscillator 101 includes a package 102, a crystal vibrating piece 3 and an IC chip 4a mounted in a recessed first mounting space 102a of the package 102, and a metal cover (lid) 5 for sealing the first mounting space 102a. The package 102 also includes a second mounting space (second room) 102b formed on the opposite side of the first mounting space (first room) 102a.

[0056] The package 102 is a ceramic package formed by laminating multiple ceramics on the surface of which a desired metal pattern is formed. Specifically, the package 102 has a laminated structure in which a first frame wall 11, a second frame wall 12, a rectangular bottom plate 113, and a third frame wall 114, each having an opening of a predetermined size, are laminated. Due to this laminated structure, the package 102 has a first mounting space 102a with a recessed and stepped shape for mounting the crystal vibrating piece 3 and the IC chip 4a, and a second mounting space 102b with a recessed shape for mounting the IC chip 4d. That is, the first mounting space 102a and the second mounting space 102b have a structure in which the bottom plate 113 is commonly laminated. Due to this laminated structure, the package 102 has a so-called H-shaped structure. Furthermore, the package 102 has a rectangular parallelepiped shape and is rectangular when viewed from above ( FIG. 8( b) ). The vertical direction, horizontal direction, longitudinal direction, and lateral direction are the same as those in the first embodiment.

[0057] Four external connection terminals 20a, 20b, 20c, and 20d are formed on a third frame wall 114 laminated on a first surface 113a of a bottom plate 113 of the package 102. Six IC chip electrode terminals are formed on a second surface 113b of the bottom plate 113. Specifically, as can be seen from Figures 8(a) and 8(b), a first terminal 121a (XTN) connected to one terminal of the crystal resonator, a second terminal 121b (VDD) for IC operating voltage, a third terminal 121c (Q) for IC output, a fourth terminal 121d (GND) for ground potential, a fifth terminal 121e (INHN) for IC control, and a sixth terminal 121f (XT) connected to the other terminal of the crystal resonator are formed on the same plane. In particular, the first terminal 121a, the second terminal 121b, and the third terminal 121c are arranged side by side and spaced apart from each other in the longitudinal direction of the package 102 when viewed from above, and similarly, the fourth terminal 121d, the fifth terminal 121e, and the sixth terminal 121f are also arranged side by side and spaced apart from each other in the longitudinal direction of the package 102 when viewed from above. Each terminal is formed in a rectangular shape of approximately the same dimensions, and the first terminal 121a and the sixth terminal 121f, the second terminal 121b and the fifth terminal 121e, and the third terminal 121c and the fourth terminal 121d are formed to face each other in the short direction of the package 102 when viewed from above.

[0058] Furthermore, six electrode terminals for the IC chip are also formed on the first surface 113a of the bottom plate 113. Specifically, as can be seen from Figures 9(a) and 9(b), a seventh terminal 151a (XTN) connected to one terminal of the crystal resonator, an eighth terminal 151b for IC operating voltage (VDD), a ninth terminal 151c for IC output (Q), a tenth terminal 151d for ground potential (GND), an eleventh terminal 151e for IC control (INHN), and a twelfth terminal 151f (XT) connected to the other terminal of the crystal resonator are formed on the same plane. In particular, the seventh terminal 151a, the eighth terminal 151b, and the ninth terminal 151c are arranged side by side and spaced apart from each other in the longitudinal direction of the package 102 when viewed from above, and similarly, the tenth terminal 151d, the eleventh terminal 151e, and the twelfth terminal 151f are also arranged side by side and spaced apart from each other in the longitudinal direction of the package 102 when viewed from above. Each terminal is formed in a rectangular shape of approximately the same dimensions, and the seventh terminal 151a and the twelfth terminal 151f, the eighth terminal 151b and the eleventh terminal 151e, and the ninth terminal 151c and the tenth terminal 151d are formed to face each other in the short direction of the package 102 when viewed from above.

[0059] The electrode terminals for the IC chip formed on the first surface 113a of the bottom plate 113 and the electrode terminals for the IC chip formed on the second surface 113b are electrically connected via via wiring that penetrates the bottom plate 113. 8(a), 8(b), 9(a), and 9(b), the first terminal 121a and the seventh terminal 151a are electrically connected via the via wiring 161a, the second terminal 121b and the eighth terminal 151b are electrically connected via the via wiring 161b, the third terminal 121c and the ninth terminal 151c are electrically connected via the via wiring 161c, the fourth terminal 121d and the tenth terminal 151d are electrically connected via the via wiring 161d, the fifth terminal 121e and the eleventh terminal 151e are electrically connected via the via wiring 161e, and the sixth terminal 121f and the twelfth terminal 151f are electrically connected via the via wiring 161f. That is, the XTN terminals face each other, the GND terminals face each other, the VDD terminals face each other, the Q terminals face each other, the INHN terminals face each other, and the XT terminals face each other through the bottom plate 113 and are electrically connected through the respective via wirings.

[0060] In this embodiment, one mounting pattern is formed from the IC chip electrode terminals on the second surface 113b, and another mounting pattern is formed from the IC chip electrode terminals on the first surface 113a. Specifically, as shown in Fig. 8(b), a first IC chip mounting pattern 122a is formed by six terminals: a first terminal 121a, a second terminal 121b, a third terminal 121c, a fourth terminal 121d, a fifth terminal 121e, and a sixth terminal 121f. Also, as shown in Fig. 9(b), a second IC chip mounting pattern 122b is formed by six terminals: a seventh terminal 151a, an eighth terminal 151b, a ninth terminal 151c, a tenth terminal 151d, an eleventh terminal 151e, and a twelfth terminal 151f. Therefore, as shown in Figures 8(a) and 9(a), each via wiring connects the same functional terminals of the first IC chip mounting pattern 122a and the second IC chip mounting pattern 122b, thereby forming a compatibility structure 180 that connects the parts of the terminals of the two types of IC chips that correspond to terminals with the same function.

[0061] As can be seen from FIGS. 8(a) and 8(b), an IC chip 4a is mounted on the first IC chip mounting pattern 122a via six bumps 31a to 31f. Specifically, the first terminal 41a of the IC chip 4a is electrically connected to the first terminal 121a of the package 102 via the bump 31a, the second terminal 41b of the IC chip 4a is electrically connected to the second terminal 121b of the package 102 via the bump 31b, the third terminal 41c of the IC chip 4a is electrically connected to the third terminal 121c of the package 102 via the bump 31c, the fourth terminal 41d of the IC chip 4a is electrically connected to the fourth terminal 121d of the package 102 via the bump 31d, the fifth terminal 41e of the IC chip 4a is electrically connected to the fifth terminal 121e of the package 102 via the bump 31e, and the sixth terminal 41f of the IC chip 4a is electrically connected to the sixth terminal 121f of the package 102 via the bump 31f.

[0062] On the other hand, as can be seen from FIGS. 9(a) and 9(b), an IC chip 4d is mounted on the second IC chip mounting pattern 122b via six bumps 34a-34f. Here, the IC chip 4d is a wire-bonded IC, but flip-chip bonding is performed using the bumps. Also, as can be seen from FIGS. 9(b) and 6(c), the IC chip 4d has a rectangular shape in a plan view and six IC terminals. Specifically, the IC chip 4d has a first terminal 44a (XT) connected to one terminal of the crystal unit, a second terminal 44b (INHN) for IC control, a third terminal 44c (GND) for ground potential, a fourth terminal 44d (Q) for IC output, a fifth terminal 44e (VDD) for IC operating voltage, and a sixth terminal 44f (XTN) connected to the other terminal of the crystal unit.

[0063] The first terminal 44a of the IC chip 4d is electrically connected to the twelfth terminal 151f of the package 102 via the bump 34a, the second terminal 44b of the IC chip 4d is electrically connected to the eleventh terminal 151e of the package 102 via the bump 34b, the third terminal 44c of the IC chip 4d is electrically connected to the tenth terminal 151d of the package 102 via the bump 34c, the fourth terminal 44d of the IC chip 4d is electrically connected to the ninth terminal 151c of the package 102 via the bump 34d, the fifth terminal 44e of the IC chip 4d is electrically connected to the eighth terminal 151b of the package 102 via the bump 34e, and the sixth terminal 44f of the IC chip 4d is electrically connected to the seventh terminal 151a of the package 102 via the bump 34f. That is, with regard to the IC terminals of the IC chip 4d and the IC electrode terminals of the package, the XTN terminals, the GND terminals, the VDD terminals, the Q terminals, the INHN terminals, and the XT terminals are electrically connected to each other.

[0064] As described above, in package 102 of this embodiment, the XTN terminals, GND terminals, VDD terminals, Q terminals, INHN terminals, and XT terminals formed on the surface of bottom plate 113 face each other across bottom plate 113 and are electrically connected through via wirings extending in the vertical direction. As a result, first IC chip mounting pattern 122a for mounting IC chip 4a, which is a flip-chip bonding type IC, and second IC chip mounting pattern 122b for mounting IC chip 4d, which is a wire-bonding type IC, are formed on mutually opposing flat surfaces of bottom plate 113.

[0065] Therefore, depending on the IC chip to be mounted, its mounting position can be selected from the first surface 113a or the second surface 113b of the package 102, making it possible to mount two types of IC chips. In other words, even two types of IC chips with different electrode patterns can be mounted using the same package 102, thereby achieving package standardization. The two types of IC chips have terminals that are identically arranged when viewed through the thickness of the IC chip. In particular, since this embodiment also allows for selective mounting of flip-chip bonding type ICs and wire bonding type ICs, it is possible to continue manufacturing crystal oscillators 101 using available IC chips, even if the IC chip supply situation in the market changes.

[0066] (Modification of the second embodiment) In the second embodiment, the XTN terminals, the GND terminals, the VDD terminals, the Q terminals, the INHN terminals, and the XT terminals are arranged so as to face each other across the bottom plate 113, and the via wirings extend in straight lines in the vertical direction, but this structure is not limited to this. For example, all or any of the XTN terminals, the GND terminals, the VDD terminals, the Q terminals, the INHN terminals, and the XT terminals may be arranged so as not to face each other across the bottom plate 113, and terminals with the same function may be connected to each other through via wirings. An example of such a case will be described as a modified example of the second embodiment with reference to FIGS. 10(a) to 10(c).

[0067] Here, FIG. 10(a) is an end view of a crystal oscillator according to a modification of the second embodiment, showing the case where another IC chip is mounted. FIG. 10(b) is a bottom view of the package constituting the crystal oscillator according to the modification of the second embodiment, showing the case where another IC chip is mounted on the bottom side. FIG. 10(c) is a top view of the other IC chip constituting the crystal oscillator according to the modification of the second embodiment. Note that the same components as those in the above embodiment and its modifications are designated by the same reference numerals, and their description will be omitted.

[0068] First, in the package 102′ according to this modification, the bottom plate 113′ has a laminated structure in which a first bottom plate 213 and a second bottom plate 214 are laminated. Also, on the second surface 113b of the bottom plate 113′, similar to the package 102, a first terminal 121a (XTN) connected to one terminal of the crystal unit, a second terminal 121b for IC operating voltage (VDD), a third terminal 121c for IC output (Q), a fourth terminal 121d for ground potential (GND), a fifth terminal 121e for IC control (INHN), and a sixth terminal 121f (XT) connected to the other terminal of the crystal unit are formed on the same plane. Therefore, the package 102′ has a first IC chip mounting pattern 122a. 10(a) and 10(b), the seventh terminal 152a for IC output (Q), the eighth terminal 152b for IC operating voltage (VDD), the ninth terminal 152c for connection to one terminal of the crystal resonator (XTN), the tenth terminal 152d for connection to the other terminal of the crystal resonator (XT), the eleventh terminal 152e for IC control (INHN), and the twelfth terminal 152f for ground potential (GND) are formed on the same plane on the first surface 113a of the bottom plate 113'. As a result, the package 102' has a second IC chip mounting pattern 122c.

[0069] The first terminal 121a and the ninth terminal 152c for (XTN) connected to one terminal of the crystal oscillator are electrically connected via via wiring 162a, the second terminal 121b and the eighth terminal 152b for the IC operating voltage (VDD) are electrically connected via via wiring 162b, the third terminal 121c and the seventh terminal 152a for the IC output (Q) are electrically connected via via wiring 162c, the sixth terminal 121f and the tenth terminal 152d for (XT) connected to the other terminal of the crystal oscillator are electrically connected via via wiring 162d, the fifth terminal 121e and the eleventh terminal 152e for IC control (INHN) are electrically connected via via wiring 162e, and the fourth terminal 121d and the twelfth terminal 152f for the ground potential (GND) are electrically connected via via wiring 162f.

[0070] Here, the XTN terminals, the Q terminals, the XT terminals, and the GND terminals are not arranged opposite each other across the bottom plate 113', so the via wirings 162a, 162c, 162d, and 162f have a bent shape. More specifically, each of these via wirings is composed of a portion extending in the vertical direction and a portion extending in the horizontal direction. In particular, as shown in FIG. 10(a), the portion extending in the horizontal direction is formed at the interface between the first bottom plate 213 and the second bottom plate 214. On the other hand, the VDD terminals and the INHN terminals are arranged opposite each other across the bottom plate 113', so the via wirings 162b and 162e extend linearly in the vertical direction.

[0071] In this modification, as can be seen from FIG. 10(b), an IC chip 4e corresponding to the second IC chip is mounted on the second IC chip mounting pattern 122c via six bumps 35a-35f. Here, although the IC chip 4e is a wire-bonded IC, it is connected by flip-chip bonding using bumps rather than the usual wire connection. Also, as can be seen from FIGS. 10(b) and 10(c), the IC chip 4e has a rectangular shape in a plan view and six IC terminals. Specifically, the IC chip 4e has a first terminal 45a for IC output (Q), a second terminal 45b for IC operating voltage (VDD), a third terminal 45c for (XTN) connected to one terminal of the crystal resonator, a fourth terminal 45d for (XT) connected to the other terminal of the crystal resonator, a fifth terminal 45e for IC control (INHN), and a sixth terminal 45f for ground potential (GND). In particular, in the IC chip 4e, compared to the IC chip 4a, the GND terminal and the XTN terminal are swapped, the Q terminal and the XT terminal are swapped, and the INHN terminal and the VDD terminal are swapped.

[0072] As can be seen from Figures 10(a) and 10(b), the first terminal 45a of the IC chip 4e is electrically connected to the seventh terminal 152a of the package 102' via the bump 35a, the second terminal 45b of the IC chip 4e is electrically connected to the eighth terminal 152b of the package 102' via the bump 35b, the third terminal 45c of the IC chip 4e is electrically connected to the ninth terminal 152c of the package 102' via the bump 35c, the fourth terminal 45d of the IC chip 4e is electrically connected to the tenth terminal 152d of the package 102' via the bump 35d, the fifth terminal 45e of the IC chip 4e is electrically connected to the eleventh terminal 152e of the package 102' via the bump 35e, and the sixth terminal 45f of the IC chip 4e is electrically connected to the twelfth terminal 152f of the package 102' via the bump 35f.

[0073] As described above, in the package 102' of the above-described modified example, the XTN terminals, GND terminals, VDD terminals, Q terminals, INHN terminals, and XT terminals formed on the surface of the bottom plate 113' are electrically connected to each other through the via wirings. As a result, a first IC chip mounting pattern 122a for mounting the IC chip 4a, which is a flip-chip bonding type IC, and a second IC chip mounting pattern 122c for mounting the IC chip 4e, which is a wire-bonding type IC, are formed on opposing flat surfaces of the bottom plate 113'. Therefore, depending on the IC chip to be mounted, the mounting position can be selected from the first surface 113a or the second surface 113b of the package 102', making it possible to mount two types of IC chips.

[0074] Naturally, the arrangement of the electrode terminals on the first surface 113a and the second surface 113b of the bottom plate 113' can be changed as appropriate to correspond to the IC chip to be mounted, and the shape of the via wiring can also be changed as appropriate to correspond to the arrangement.

[0075] (Embodiments of the present disclosure) A first embodiment of the present disclosure is a crystal oscillator including: a package having a first IC chip mounting pattern corresponding to the arrangement of the terminals of a first IC chip, a second IC chip mounting pattern corresponding to the arrangement of the terminals of a second IC chip, and crystal resonator blank mounting terminals for mounting a crystal resonator blank; one of the first IC chip mounted on the first IC chip mounting pattern and the second IC chip mounted on the second IC chip mounting pattern; a crystal resonator blank mounted on the crystal resonator blank mounting terminals; and an interchangeable structure connecting portions of the first IC chip mounting pattern and the second IC chip mounting pattern that correspond to terminals with the same function on the terminals of the first IC chip and the terminals of the second IC chip. The inclusion of such an interchangeable structure allows two types of IC chips with different terminal arrangements to be mounted on either the first IC chip mounting pattern or the second IC chip mounting pattern, thereby enabling a common package.

[0076] A second embodiment of the present disclosure is the first embodiment, in which the first IC chip mounting pattern includes mounting terminals arranged differently from those of the second IC chip mounting pattern, thereby resulting in the two IC chip mounting patterns having mutually different arrangements, making it possible to accurately mount IC chips suited to each of them.

[0077] A third embodiment of the present disclosure is that, in the first or second embodiment, the first IC chip mounting pattern and the second IC chip mounting pattern are provided on the same plane of the package, the first IC chip or the second IC chip to be mounted has a rectangular shape in a planar view, one or more first terminal groups having the same function among the terminals of the first IC chip and the second IC chip are terminals positioned adjacent to each other in a direction parallel to one side of the rectangular shape, one or more second terminal groups other than the first terminal group and having the same function among the terminals of the first IC chip and the second IC chip are terminals positioned diagonally to one side of the rectangular shape, and the compatibility structure includes additional patterns individually provided in the diagonal direction corresponding to the second terminal groups of the first IC chip mounting pattern and the second IC chip mounting pattern. This makes it possible to mount two types of IC chips with different terminal arrangements simply by moving the IC chip on a horizontal plane.

[0078] A fourth embodiment of the present disclosure is the third embodiment, in which the compatibility structure further includes an extension pattern that extends the areas of the portions of the first and second IC chip mounting patterns corresponding to the first terminal groups to an area that includes the adjacent positions, thereby making it possible to mount two types of IC chips with different terminal arrangements simply by moving the IC chips on a horizontal plane.

[0079] A fifth embodiment of the present disclosure is the first or second embodiment, wherein the package has a first chamber and a second chamber stacked on a bottom plate common to the first chamber, the first IC chip mounting pattern is provided on the bottom plate of the first chamber, the second IC chip mounting pattern is provided on the bottom plate of the second chamber, and the compatibility structure includes via wiring provided on the bottom plate and connecting identical functional terminals of the first IC chip mounting pattern and the second IC chip mounting pattern. This makes it possible to mount two types of IC chips with different terminal arrangements simply by changing the mounting positions of the IC chips in the vertical direction.

[0080] A sixth embodiment of the present disclosure is the fifth embodiment, in which the first IC chip or the second IC chip to be mounted has terminals that are arranged in the same manner when viewed through the thickness of the IC chip, thereby making it possible to mount two types of IC chips with different electrode arrangements with a line passing through the center of the IC chip as the axis of symmetry simply by changing the mounting position in the vertical direction.

[0081] A seventh embodiment of the present disclosure is any of the first to sixth embodiments, in which the first IC chip is a flip-chip bonding type IC mounted on the first IC chip mounting pattern, and the second IC chip is a wire-bonding type IC mounted on the second IC chip mounting pattern, thereby enabling a common package to be used for flip-chip type ICs and wire-bonding type ICs, which are mounted using different methods.

[0082] An eighth embodiment of the present disclosure is any of the first to seventh embodiments in which the mounted IC chip is mounted via bumps, thereby enabling the IC chip to be reliably mounted to the terminals.

[0083] A ninth embodiment of the present disclosure provides a package for a crystal oscillator, the package including a first IC chip mounting pattern corresponding to the arrangement of the terminals of a first IC chip, a second IC chip mounting pattern corresponding to the arrangement of the terminals of a second IC chip, and crystal resonator blank mounting terminals for mounting a crystal resonator blank, and an interchangeable structure connecting portions of the first IC chip mounting pattern and the second IC chip mounting pattern that correspond to terminals with the same function on the first IC chip terminals and the second IC chip terminals. The inclusion of such an interchangeable structure allows two types of IC chips with different terminal arrangements to be mounted on either the first IC chip mounting pattern or the second IC chip mounting pattern, thereby enabling a common package. [Explanation of symbols]

[0084] 1. Crystal oscillator 2 Crystal oscillator package (package) 3 Crystal vibrating piece 4a First IC chip 4b, 4c, 4d, 4e Second IC chip 5 Cover (lid) 16,17 Crystal unit mounting terminals 18 Conductive adhesive 21b Additional pattern (second terminal) 21e Additional pattern (5th terminal) 22a First IC chip mounting pattern 22b Second IC chip mounting pattern 71 Extended Pattern

Claims

1. a package having a first IC chip mounting pattern corresponding to the arrangement of the terminals of the first IC chip, a second IC chip mounting pattern corresponding to the arrangement of the terminals of the second IC chip, and crystal resonator blank mounting terminals for mounting the crystal resonator blank; one of a first IC chip mounted on the first IC chip mounting pattern and a second IC chip mounted on the second IC chip mounting pattern; a quartz crystal vibrating piece mounted on the quartz crystal vibrating piece mounting terminal; and a compatibility structure portion that connects portions of the first IC chip mounting pattern and the second IC chip mounting pattern that correspond to terminals of the first IC chip and the second IC chip, respectively, that have the same functions.

2. 2. The crystal oscillator according to claim 1, wherein the first IC chip mounting pattern includes mounting terminals arranged differently from those of the second IC chip mounting pattern.

3. the first IC chip mounting pattern and the second IC chip mounting pattern are provided on the same plane of the package; The first IC chip or the second IC chip to be mounted has a rectangular shape in a plan view, and one or more sets of first terminal groups having the same function among the terminals of the first IC chip and the second IC chip are terminals positioned adjacent to each other in a direction parallel to one side of the quadrangular shape, one or more sets of second terminal groups, which are different from the first terminal group and have the same function as the first IC chip and the second IC chip, are terminals positioned in a diagonal direction with respect to one side of the quadrangular shape, The compatibility structure includes:

3. The crystal oscillator according to claim 2, further comprising additional patterns individually provided in the diagonal direction corresponding to the second terminal groups of the first IC chip mounting pattern and the second IC chip mounting pattern.

4. 4. The crystal oscillator according to claim 3, wherein the compatibility structure further includes an extension pattern in which the area of the portion of the first IC chip mounting pattern and the second IC chip mounting pattern corresponding to the first terminal group is extended to an area including the adjacent positions.

5. The package has a first chamber and a second chamber stacked on the first chamber with a common bottom plate, the first IC chip mounting pattern is provided on the bottom plate of the first chamber; the second IC chip mounting pattern is provided on the bottom plate of the second chamber; 3. The crystal oscillator according to claim 2, wherein the compatibility structure includes via wiring provided on the bottom plate and connecting identical functional terminals of the first IC chip mounting pattern and the second IC chip mounting pattern.

6. 6. The crystal oscillator according to claim 5, wherein the first IC chip or the second IC chip to be mounted has terminals that are arranged in the same manner when viewed through the thickness direction of the IC chip.

7. the first IC chip is a flip-chip bonding type IC mounted on the first IC chip mounting pattern, 3. The crystal oscillator according to claim 2, wherein the second IC chip is a wire-bonding type IC mounted on the second IC chip mounting pattern.

8. 8. The crystal oscillator according to claim 7, wherein the mounted IC chip is mounted via bumps.

9. a package having a first IC chip mounting pattern corresponding to the arrangement of the terminals of the first IC chip, a second IC chip mounting pattern corresponding to the arrangement of the terminals of the second IC chip, and crystal resonator blank mounting terminals for mounting the crystal resonator blank; and a compatibility structure portion that connects portions of the first IC chip mounting pattern and the second IC chip mounting pattern that correspond to terminals of the first IC chip and the second IC chip, respectively, that have the same functions.

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