Method of manufacturing semiconductor device

Abstract

To increase the reliability of a semiconductor device.SOLUTION: A resist pattern RP1 having an opening portion that exposes a part of a conductive film (CF1) located on a gate insulating film GI is formed on the conductive film (CF1). Next, an anisotropic etching treatment is performed using the resist pattern RP1 as a mask to selectively remove the conductive film (CF1) exposed from the resist pattern RP1 and to form a gate pattern GP and a dummy gate pattern DGP from the remaining conductive film (CF1). Next, an oblique ion implantation is performed using the resist pattern RP1 as a mask to form a p-type body region PB in a semiconductor substrate SUB.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] As disclosed in Patent Document 1, a laterally diffused metal oxide semiconductor (LDMOS) having a low concentration drift region disposed between a high concentration drain region and a gate electrode is known as a type of metal insulator semiconductor field effect transistor (MISFET).

[0003] In a semiconductor device having a plurality of LDMOSs, the LDMOSs are arranged symmetrically with respect to the drain and source regions, and adjacent LDMOSs share the drain or source region.

[0004] Another method is to pattern the conductive film for the gate electrode as a gate pattern, and then use the resist pattern used for that patterning as a mask to perform angled ion implantation. This forms a body region that constitutes the channel region of the LDMOS between adjacent gate patterns. Then, a source region is formed in the body region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-192741 Summary of the Invention [Problem to be solved by the invention]

[0006] In the LDMOS arranged at the outermost position among multiple LDMOSs (outermost LDMOS), the drain region is shared with the LDMOS adjacent to the outermost LDMOS, but the body region and source region are not shared with other LDMOSs. Therefore, in the outermost LDMOS, the body region is formed using only one gate pattern as a mask. Therefore, the impurity profile of the body region of the outermost LDMOS may differ from the impurity profile of the body regions of the other LDMOSs.

[0007] As a result, for example, the threshold voltage of the outermost LDMOS becomes lower than that of the other LDMOS, and leakage current flows more easily in the outermost LDMOS than in the other LDMOS, which may result in a decrease in the reliability of the semiconductor device.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] In one embodiment, a method for manufacturing a semiconductor device includes the steps of forming an element isolation portion in a semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a first conductive film on the gate insulating film and on the element isolation portion, forming a first resist pattern on the first conductive film, performing an anisotropic etching process using the first resist pattern as a mask to selectively remove the first conductive film exposed from the first resist pattern, and forming a first gate pattern and a dummy gate pattern from the first conductive film, and forming a first body region of a first conductivity type in the semiconductor substrate by performing oblique ion implantation using the first resist pattern as a mask. [Effects of the Invention]

[0010] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged plan view of a main part of FIG. [Figure 3] FIG. 3 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a main part of FIG. [Figure 5] FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 8] 8A to 8C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 11] FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 12] 12A to 12C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to that shown in FIG. [Figure 13] 13A to 13C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 14] 14A to 14C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 16] 16 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view for explaining the oblique ion implantation of FIG. [Figure 18] FIG. 18 is a graph showing experimental data obtained by the inventors of the present invention. [Figure 19] 19A to 19C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first modification. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor device according to the second modification. [Figure 21] FIG. 21 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device according to the second modification. [Figure 22] FIG. 22 is a cross-sectional view of a main part showing a manufacturing process of a semiconductor device according to the second modification. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, depth, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that a surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) <Structure of semiconductor device>

[0015] 1, the semiconductor device includes a plurality of n-type MISFETs 1Q each having a gate electrode GE, two dummy gate electrodes DGE, a p-type well region (impurity region) HPW1, an n-type well region (impurity region) HNW, and a p-type well region (impurity region) HPW2. The well region HPW1, the well region HNW, and the well region HPW2 extend in the X and Y directions so as to surround the plurality of MISFETs 1Q and the two dummy gate electrodes DGE in a planar view. The well region HNW surrounds the well region HPW1 in a planar view. The well region HPW2 surrounds the well region HNW in a planar view.

[0016] Although not shown here, the element isolation parts STI also extend in the X and Y directions so as to surround the multiple MISFETs 1Q in plan view. The two dummy gate electrodes DGE are each formed on the element isolation parts STI extending in the Y direction.

[0017] As shown in FIG. 2, each of the multiple MISFETs 1Q has a gate electrode GE, a p-type body region (impurity region) PB, an n-type source region (impurity region) NS, a p-type heavily doped diffusion region (impurity region) PR, an n-type drift region (impurity region) NLD, and an n-type drain region (impurity region) ND. The gate electrode GE is made of, for example, an n-type polycrystalline silicon film. The heavily doped diffusion region PR has a higher impurity concentration than the body region PB. The drift region NLD has a lower impurity concentration than the drain region ND and the source region NS.

[0018] The gate electrode GE, body region PB, drain region ND, and dummy gate electrode DGE extend in the Y direction. A plurality of source regions NS are formed in the body region PB so as to be spaced apart from each other in the Y direction. A high-concentration diffusion region PR is formed between each of the adjacent source regions NS in the Y direction. A portion of the body region PB that is located between the drain region ND and the source region NS and overlaps with the gate electrode GE in a plan view functions as a channel region of the MISFET1Q.

[0019] The multiple MISFETs 1Q are arranged symmetrically with respect to the drain region ND and source region NS. The drain region ND or the source region NS is shared between the MISFETs 1Q adjacent to each other in the X direction. The drain region ND of the MISFET 1Q arranged on the outermost side (the outermost MISFET 1Q) among the multiple MISFETs 1Q is shared with the MISFET 1Q adjacent to the outermost MISFET 1Q, but the body region PB and the source region NS are not shared with the other MISFETs 1Q.

[0020] Fig. 3 is a cross-sectional view taken along line A1-A3 shown in Fig. 1 and Fig. 2. Fig. 4 is a cross-sectional view taken along line A1-A2 shown in Fig. 1 and Fig. 2, and shows an enlarged view of a portion of Fig. 3.

[0021] The semiconductor substrate SUB is made of p-type silicon. In the first embodiment, the semiconductor substrate SUB includes, for example, a support substrate SS made of a p-type silicon substrate, and a p-type semiconductor layer (silicon layer) EP formed on the support substrate SS by epitaxial growth. In the following description, various impurity regions formed in the semiconductor substrate SUB may specifically be formed in the semiconductor layer EP.

[0022] An element isolation portion STI is formed in the semiconductor substrate SUB. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB to reach a predetermined depth from the upper surface of the semiconductor substrate SUB, and an insulating film buried inside the trench. The insulating film is, for example, a silicon oxide film.

[0023] An n-type drift region NLD, a p-type impurity region PLD, and an n-type buried region NBL are formed in the semiconductor substrate SUB. The drift region NLD is formed to a predetermined depth from the upper surface of the semiconductor substrate SUB and is located above the impurity region PLD and the buried region NBL. The impurity region PLD is located above the buried region NBL. The impurity region PLD and the buried region NBL are formed in the semiconductor substrate SUB at a position deeper than the element isolation part STI.

[0024] Furthermore, a body region PB, a well region HPW1, a well region HNW, and a well region HPW2 are formed in the semiconductor substrate SUB. The body region PB, the well region HPW1, the well region HNW, and the well region HPW2 are formed from the upper surface of the semiconductor substrate SUB to a position deeper than the element isolation part STI. The body region PB and the well region HPW1 are in contact with the impurity region PLD. The buried region NBL is in contact with the well region HNW.

[0025] A gate insulating film GI is formed on the semiconductor substrate SUB. The gate insulating film GI is, for example, a silicon oxide film. A gate electrode GE is formed on the gate insulating film GI. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE. The sidewall spacers SW include, for example, a silicon oxide film and a silicon nitride film formed on the silicon oxide film. An insulating film IF1 is formed on the upper surface of the semiconductor substrate SUB so as to cover a part of the gate electrode GE and the sidewall spacers SW. The insulating film IF1 is, for example, a silicon oxide film.

[0026] A source region NS is formed in the body region PB. As shown in FIG. 2, a high-concentration diffusion region PR is also formed in the body region PB. A drain region ND is formed in the drift region NLD. A part of the drain region ND and the drift region NLD are covered with an insulating film IF1, but the other part of the drain region ND is exposed from the insulating film IF1.

[0027] The gate electrode GE is formed on a portion of the semiconductor substrate SUB located between the source region NS and the drain region ND in the X direction. A portion of the body region PB located between the source region NS and the drain region ND and below the gate electrode GE functions as a channel region of the MISFET 1Q.

[0028] High-concentration diffusion regions PR are formed in the well regions HPW1 and HPW2. An n-type high-concentration diffusion region (impurity region) NR is formed in the well region HNW. The impurity concentrations of the source region NS, the drain region ND, and the high-concentration diffusion region NR are higher than the impurity concentration of the drift region NLD. The impurity concentration of the high-concentration diffusion region PR is higher than the impurity concentrations of the well regions HPW1 and HPW2.

[0029] A silicide film SI is formed on a portion of the semiconductor substrate SUB exposed from the insulating film IF1. That is, the silicide film SI is formed on each of the upper surfaces of a part of the gate electrode GE, the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR. The source region NS and the heavily doped diffusion region PR formed in the body region PB are electrically connected by the same silicide film SI. The silicide film SI is, for example, a cobalt silicide (CoSi2) film, a nickel silicide (NiSi) film, or a nickel platinum silicide (NiPtSi) film.

[0030] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB. The interlayer insulating film IL is, for example, a silicon oxide film. A plurality of holes CH1 are formed in the interlayer insulating film IL. A plug PG is formed inside each of the plurality of holes CH1. The plug PG includes, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film includes, for example, a titanium film and a titanium nitride film, and the conductive film is, for example, a tungsten film.

[0031] The plurality of holes CH1 are formed so as to reach the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR. Although not shown here, a plurality of wirings connected to the plurality of plugs PG are formed on the interlayer insulating film IL. A predetermined potential is supplied to the source region NS, the drain region ND, the heavily doped diffusion region PR, and the heavily doped diffusion region NR from the plurality of wirings.

[0032] The drain region ND and drift region NLD are each made conductive as n-type impurity regions and fixed at the same potential. The well region HPW1, impurity region PLD, body region PB, heavily doped diffusion region PR formed in well region HPW1, and heavily doped diffusion region PR formed in body region PB are each made conductive as p-type impurity regions and fixed at the same potential. The well region HPW2, semiconductor layer EP, support substrate SS, and heavily doped diffusion region PR formed in well region HPW2 are each made conductive as p-type impurity regions and fixed at the same potential.

[0033] The heavily doped diffusion region NR, the well region HNW, and the buried region NBL are each conductive as n-type impurity regions and fixed at the same potential. The buried region NBL and the well region HNW electrically isolate the multiple MISFETs 1Q from the semiconductor substrate SUB, thereby improving the noise immunity of the multiple MISFETs 1Q.

[0034] Although not shown here, a hole CH1 and a plug PG are also formed on the upper surface of the gate electrode GE on which the silicide film SI is formed. When the MISFET 1Q is in operation, a gate potential is supplied to the gate electrode GE, a drain potential is supplied to the drain region ND, and a source potential is supplied to the source region NS.

[0035] The dummy gate electrode DGE is formed on the element isolation portion STI where the body region PB and the well region HPW1 are in contact. A silicide film SI is also formed on the upper surface of the dummy gate electrode DGE, but the hole CH1 and the plug PG are not formed on the upper surface of the dummy gate electrode DGE. Therefore, the dummy gate electrode DGE is not electrically connected to any wiring, and no potential is supplied to the dummy gate electrode DGE. In other words, the dummy gate electrode DGE is in an electrically floating state.

[0036] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

[0037] As shown in FIG. 5, a semiconductor substrate SUB is prepared. The semiconductor substrate SUB may be a single-layer p-type silicon substrate, but in the first embodiment, the semiconductor substrate SUB includes a support substrate SS and a semiconductor layer EP. First, the support substrate SS is prepared. The support substrate SS is made of p-type silicon. Next, the semiconductor layer EP, which is a p-type silicon layer, is formed on the support substrate SS by epitaxial growth.

[0038] Next, a buried region NBL is formed in the semiconductor substrate SUB by photolithography and ion implantation. Note that after the buried region NBL is formed in the support substrate SS, the semiconductor layer EP may be formed on the support substrate SS.

[0039] As shown in Figure 6, an element isolation portion STI is formed in a semiconductor substrate SUB. First, a trench is formed in the semiconductor substrate SUB by photolithography and anisotropic etching so as to reach a predetermined depth from the upper surface of the semiconductor substrate SUB. Next, an insulating film such as a silicon oxide film is formed on the semiconductor substrate SUB so as to fill the interior of the trench. Next, the insulating film located outside the trench is removed by polishing using a CMP method so as to leave the insulating film filled inside the trench.

[0040] 7, the impurity region PLD, the drift region NLD, the well region HPW1, the well region HPW2, and the well region HNW are sequentially formed in the semiconductor substrate SUB by photolithography and ion implantation. The order in which these are formed does not matter.

[0041] 8, first, a gate insulating film GI is formed on a semiconductor substrate SUB, for example, by thermal oxidation. Next, a conductive film CF1 is formed on the gate insulating film GI and the element isolation portion STI, for example, by a film formation process using a CVD method. The conductive film CF1 is, for example, a polycrystalline silicon film doped with n-type impurities.

[0042] 9, first, a resist pattern RP1 is formed on the conductive film CF1. The resist pattern RP1 has openings that open a part of the conductive film CF1 located on the gate insulating film GI, the boundary between the element isolation part STI and the semiconductor substrate SUB, and a part of the conductive film CF1 located on the element isolation part STI.

[0043] Next, an anisotropic etching process is performed using the resist pattern RP1 as a mask to selectively remove the conductive film CF1 exposed from the resist pattern RP1, thereby forming a gate pattern GP and a dummy gate pattern DGP from the conductive film CF1. The dummy gate pattern DGP is located at least on the element isolation part STI.

[0044] As shown in FIG. 9, the resist pattern RP1 also has openings that open multiple locations in the conductive film CF1 located on the gate insulating film GI, and multiple gate patterns GP are formed by the anisotropic etching process.

[0045] 10 is a cross-sectional view taken along line A1-A3, showing the state after the anisotropic etching process. As shown in FIG. 10, the well regions HPW1, HNW, and HPW2 are covered with the dummy gate pattern DGP and the resist pattern RP1. Therefore, the body region PB is not formed in the well regions HPW1, HNW, and HPW2 by oblique ion implantation, which will be described later.

[0046] 11, the body region PB is formed by performing oblique ion implantation using the resist pattern RP1 as a mask. In this oblique ion implantation, ions are implanted from a direction tilted at an angle of, for example, 20 degrees or more and 45 degrees or less with respect to a direction (Z direction) perpendicular to the upper surface of the semiconductor substrate SUB.

[0047] The body region PB is formed in a portion of the semiconductor substrate SUB located between the gate pattern GP and the dummy gate pattern DGP in a plan view, and in a portion of the semiconductor substrate SUB located between the plurality of gate patterns GP in a plan view. The body region PB is also formed in a portion of the semiconductor substrate SUB located under each gate pattern GP. Thereafter, the resist pattern RP1 is removed by ashing.

[0048] The opening widths W3 of the multiple openings in the resist pattern RP1 are all the same. The opening width W3 is the width in the direction in which the multiple gate patterns GP and dummy gate patterns DGP are adjacent to each other, that is, the width in the X direction. Therefore, after the anisotropic etching process of FIG. 9, the shortest distances between the multiple gate patterns GP are all the same, and the shortest distances between the gate patterns GP and the dummy gate patterns DGP are also the same.

[0049] Then, since the oblique ion implantation is performed using the same resist pattern RP1, the body regions PB are formed in a self-aligned manner, and therefore, the width of the portion where the body regions PB and the gate patterns GP overlap each other in a plan view becomes constant under each gate pattern GP.

[0050] That is, by performing the anisotropic etching process for the conductive film CF1 and the ion implantation for the body regions PB using the same resist pattern RP1, it is possible to suppress variations in the channel lengths of the plurality of MISFETs 1Q.

[0051] As shown in FIG. 12, first, a resist pattern RP2 is formed to cover a part of the gate pattern GP located on the gate insulating film GI, the body region PB, and a part of the dummy gate pattern DGP located on the element isolation part STI.

[0052] Next, anisotropic etching is performed using the resist pattern RP2 as a mask to selectively remove the gate pattern GP and the dummy gate pattern DGP exposed from the resist pattern RP2, forming a gate electrode GE from the gate pattern GP and a dummy gate electrode DGE from the dummy gate pattern DGP, and then removing the resist pattern RP2 by ashing.

[0053] As shown in FIG. 13, sidewall spacers SW are formed on each side surface of the gate electrode GE and the dummy gate electrode DGE. First, a stacked film including, for example, a silicon oxide film and a silicon nitride film is formed on the semiconductor substrate SUB by a film formation process using, for example, a CVD method so as to cover the gate electrode GE and the dummy gate electrode DGE. Next, the stacked film is anisotropically etched to form sidewall spacers SW from the stacked film remaining on each side surface of the gate electrode GE and the dummy gate electrode DGE. Note that the anisotropic etching also removes the gate insulating film GI exposed from the gate electrode GE.

[0054] As shown in FIG. 14, first, a resist pattern RP3 having an opening that exposes the well region HPW1 is formed. Although not shown, the resist pattern RP3 also has openings that expose a portion of the body region PB and the well region HPW2. Next, ion implantation is performed using the resist pattern RP3 as a mask to form high-concentration diffusion regions PR in the well region HPW1, the body region PB, and the well region HPW2 (see FIGS. 2 and 3). Thereafter, the resist pattern RP3 is removed by ashing.

[0055] As shown in FIG. 15, first, a resist pattern RP4 is formed having openings that expose a portion of the body region PB and a portion of the drift region NLD. Although not shown, the resist pattern RP4 also has openings that expose the well region HNW. Next, ion implantation is performed using the resist pattern RP4 as a mask to form a source region NS in the body region PB, a drain region ND in the drift region NLD, and a heavily doped diffusion region NR in the well region HNW (see FIG. 3). The drain region ND is formed in the semiconductor substrate SUB at a position away from each gate electrode GE. The resist pattern RP4 is then removed by ashing.

[0056] Either the ion implantation in Fig. 14 or the ion implantation in Fig. 15 may be performed first. After these ion implantations, the semiconductor substrate SUB is subjected to a heat treatment to activate the impurities contained in each impurity region.

[0057] 16, first, an insulating film IF1 is formed on the upper surface of the semiconductor substrate SUB by a film formation process using, for example, a CVD method so as to cover the gate electrode GE, the dummy gate electrode DGE, and the sidewall spacers SW. Next, the insulating film IF1 is patterned by photolithography and anisotropic etching. As a result, the insulating film IF1 remains on a part of the drain region ND, on the drift region NLD, on the sidewall spacers SW, and on a part of the upper surface of the gate electrode GE.

[0058] Next, a silicide film SI is formed by salicide technology on the upper surfaces of the gate electrode GE, the dummy gate electrode DGE, the drain region ND, the source region NS, and the heavily doped diffusion region PR that are exposed from the insulating film IF1. Although not shown, the silicide film SI is also formed on the upper surface of the heavily doped diffusion region NR.

[0059] Thereafter, the semiconductor device shown in FIGS. 3 and 4 is manufactured through the following manufacturing steps.

[0060] First, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB by a film formation process using, for example, a CVD method. Next, a plurality of holes CH1 are formed in the interlayer insulating film IL by photolithography and anisotropic etching. Each of the plurality of holes CH1 reaches each of the silicide films SI formed on the upper surfaces of the source region NS, the drain region ND, the heavily doped diffusion region PR, the heavily doped diffusion region NR, and the gate electrode GE.

[0061] Next, plugs PG are formed inside each of the holes CH1. To form the plugs PG, a barrier metal film is first formed inside the holes CH1 and on the interlayer insulating film IL by, for example, sputtering. The barrier metal film includes, for example, a titanium film and a titanium nitride film. Next, a conductive film, such as a tungsten film, is formed on the barrier metal film by, for example, CVD. Next, the conductive film and the barrier metal film formed outside the holes CH1 are removed by polishing, for example, using CMP.

[0062] <Main features of the first embodiment> The main feature of the first embodiment is that oblique ion implantation for the body region PB is performed in a state where a dummy gate pattern DGP is formed as shown in FIG.

[0063] As shown in Figure 17, in oblique ion implantation, there are ions IJ1 that are directly implanted into the drift region NLD and ions IJ2 that are reflected or scattered by the resist pattern RP1 and then implanted into the drift region NLD. Therefore, if the opening width of the resist pattern RP1 changes, the implantation position of the ions IJ2 changes, and the impurity profile of the body region PB changes. As described above, the portion of the body region PB located under the gate pattern GP functions as the channel region of the MISFET 1Q. However, if the opening width of the resist pattern RP1 changes, the impurity profile of the channel region changes, and the threshold voltage of the MISFET 1Q changes.

[0064] 18 shows the relationship between the opening width of the resist pattern RP1 and the fluctuation amount of the threshold voltage (Vth) of the MISFET 1Q. As shown in FIG. 18, the opening width W3 is, for example, 0.65 μm or more and 1.0 μm or less, and is used for the resist pattern RP1 described in FIG. 11. The opening width W4 is smaller than the opening width W3, for example, less than 0.65 μm. The opening width W5 is larger than the opening width W3, for example, wider than 1.0 μm. The opening widths W3, W4, and W5 are each widths in the X direction.

[0065] In the case of the opening width W4, some of the implanted ions IJ1 and IJ2 are blocked by the upper surface of the resist pattern RP1. As a result, the amount of ions implanted into the channel region decreases, and the threshold voltage decreases. In the case of the opening width W3, the ions IJ1 and IJ2 reach the channel region more easily than in the case of the opening width W4, so the threshold voltage increases. In the case of the opening width W5, fewer ions IJ2 can reach the channel region than in the case of the opening width W3, so the threshold voltage decreases. A MISFET 1Q with a reduced threshold voltage is formed as a semiconductor element in which leakage current flows more easily than other MISFETs 1Q, which may reduce the reliability of the semiconductor device.

[0066] As shown in FIG. 1, in the first embodiment, a dummy gate electrode DGE is formed further outside of the MISFET 1Q (outermost MISFET 1Q) that is arranged outermost in the X direction among the multiple MISFETs 1Q. The dummy gate electrode DGE and the dummy gate pattern DGP that forms the basis of the dummy gate electrode DGE do not function as semiconductor elements. Therefore, in reality, the dummy gate electrode DGE and the dummy gate pattern DGP do not need to be formed. However, performing the oblique ion implantation of FIG. 11 without the dummy gate pattern DGP is almost synonymous with forming the body region PB of the outermost MISFET 1Q with the opening width W5 of FIG. 18.

[0067] In the first embodiment, a dummy gate electrode DGE is formed further outside the outermost MISFET 1Q. In other words, as shown in FIG. 11, a dummy gate pattern DGP is formed further outside the gate pattern GP for the outermost MISFET 1Q. Therefore, oblique ion implantation can be performed with the opening width W3 of FIG. 18. This ensures a sufficient amount of ions implanted into the channel region and suppresses a decrease in threshold voltage, thereby ensuring sufficient reliability of the semiconductor device.

[0068] Furthermore, the opening widths W3 of the multiple openings in the resist pattern RP1 are all the same. Therefore, the widths of the portions where the body region PB and the gate pattern GP overlap each other in a plan view are constant under each gate pattern GP. This makes it possible to suppress variations in the channel lengths of the multiple MISFETs 1Q and also suppress variations in the impurity profiles of the channel regions of the multiple MISFETs 1Q.

[0069] 2, the source regions NS are formed so as to be spaced apart from each other in the Y direction. It is preferable that variations in the impurity profiles are suppressed for the channel regions between the source regions NS and the drain regions ND.

[0070] 11, it is preferable that the width of the dummy gate pattern DGP in the Y direction is larger than the width of the drain region ND to be formed in a later manufacturing process. Finally, it is preferable that the width W1 of the dummy gate electrode DGE in the Y direction is larger than the width W2 of the drain region ND, as shown in FIG.

[0071] The width W2 of the drain region ND can also be expressed as follows using the source region NS. As shown in FIG. 2, the multiple source regions NS include a source region NS1 located at one outermost position in the Y direction and a source region NS2 located at the other outermost position in the Y direction. In other words, the multiple source regions NS include a source region NS1 and a source region NS2 that are furthest from each other in the Y direction. The source region NS1 has an outermost end NS1e that is furthest from the source region NS2 in the Y direction. The source region NS2 has an outermost end NS2e that is furthest from the source region NS1 in the Y direction. In the Y direction, the width of the dummy gate electrode DGE is greater than the distance from the outermost end NS1e to the outermost end NS2e.

[0072] (Variation 1) A semiconductor device according to Modification 1 of Embodiment 1 will be described below with reference to Fig. 19. In the following description, differences from Embodiment 1 will be mainly described, and descriptions of points that overlap with Embodiment 1 will be omitted.

[0073] Fig. 19 shows a manufacturing process subsequent to Fig. 11 and performed instead of the manufacturing process of Fig. 12. In the first embodiment, as shown in Fig. 12, a part of the dummy gate pattern DGP is processed using a resist pattern RP2 to form a dummy gate electrode DGE. In the first modification, as shown in Fig. 19, the dummy gate pattern DGP is entirely removed using a resist pattern RP5.

[0074] 19, first, a resist pattern RP5 is formed to cover a part of the gate pattern GP located on the gate insulating film GI, the body region PB, and a part of the element isolation portion STI exposed from the dummy gate pattern DGP. In order to completely remove the dummy gate pattern DGP and to prevent etching of the semiconductor substrate SUB, the end of the resist pattern RP5 is positioned on a part of the element isolation portion STI located between the dummy gate pattern DGP and the body region PB.

[0075] Next, anisotropic etching is performed using the resist pattern RP5 as a mask to selectively remove the gate pattern GP and dummy gate pattern DGP exposed from the resist pattern RP5, and a gate electrode GE is formed from the gate pattern GP. Since the dummy gate pattern DGP is completely removed, no dummy gate electrode DGE is formed. Thereafter, the resist pattern RP5 is removed by ashing.

[0076] In this way, the dummy gate pattern DGP may be removed after the body region PB is formed. The subsequent manufacturing steps are the same as those shown in FIGS.

[0077] (Variation 2) 20 to 22, a semiconductor device according to Modification 2 of Embodiment 1 will be described below. In the following description, differences from Embodiment 1 will be mainly described, and descriptions of points that overlap with Embodiment 1 will be omitted.

[0078] In the first embodiment, the dummy gate electrode DGE is formed on the element isolation part STI. In the second modification, as shown in Fig. 20, the dummy gate electrode DGE is formed not only on the element isolation part STI but also on the gate insulating film. In order to form the dummy gate electrode DGE in this manner, a dummy gate pattern DGP is formed on the element isolation part STI and the gate insulating film.

[0079] 21 shows a manufacturing process corresponding to the manufacturing process of FIGS. 9 and 11. As shown in FIG. 21, a resist pattern RP1 is formed on the conductive film CF1 so as to open a part of the conductive film CF1 located on the gate insulating film GI. Unlike in the first embodiment, the resist pattern RP1 of the second modification covers the boundary between the element isolation portion STI and the semiconductor substrate SUB and the conductive film CF1 located on the element isolation portion STI. Note that the opening width W3 of the resist pattern RP1 in the second modification is also the same as the opening width W3 in the first embodiment.

[0080] Next, an anisotropic etching process is performed using the resist pattern RP1 as a mask to selectively remove the conductive film CF1 exposed from the resist pattern RP1, thereby forming a gate pattern GP and a dummy gate pattern DGP from the conductive film CF1. The dummy gate pattern DGP is located on the gate insulating film GI and the element isolation portion STI so as to straddle the boundary between the element isolation portion STI and the semiconductor substrate SUB. Next, oblique ion implantation is performed using the resist pattern RP1 as a mask to form a body region PB. The body region PB is also formed in a portion of the semiconductor substrate SUB located below the dummy gate pattern DGP.

[0081] 21, a step may occur between the upper surface of the semiconductor substrate SUB (the upper surface of the gate insulating film GI) and the upper surface of the element isolation portion STI. When such a step occurs, the symmetry between the implantation positions of the ions IJ1 and IJ2 implanted from above the dummy gate pattern DGP toward the gate pattern GP and the implantation positions of the ions IJ1 and IJ2 implanted from above the gate pattern GP toward the dummy gate pattern DGP is likely to be shifted. In other words, a difference is likely to occur between the ion implantation amount near the gate pattern GP and the ion implantation amount near the dummy gate pattern DGP.

[0082] As in variant example 2, since the dummy gate pattern DGP is also located on the gate insulating film, the influence of the above-mentioned step does not need to be taken into consideration, improving the symmetry of the implantation positions of ions IJ1 and IJ2 and making it possible to uniformize the amount of ions implanted into the channel region.

[0083] Furthermore, since the above-mentioned step difference does not occur, the conditions for the ion implantation performed between the gate pattern GP and the dummy gate pattern DGP are the same as the conditions for the ion implantation performed between the multiple gate patterns GP, and therefore the impurity profile in the channel region can be made uniform in the multiple MISFETs 1Q.

[0084] Next, the difference between the second modification and the first embodiment will be described with respect to the width in the X direction of the source region NS located between the gate pattern GP and the dummy gate pattern DGP in plan view.

[0085] In the first embodiment, the width of the source region NS in the X direction is mainly determined by the distance between the gate pattern GP and the element isolation part STI. Therefore, if the formation position of the gate pattern GP varies, the distance between the gate pattern GP and the element isolation part STI also varies, which may reduce the width of the source region NS in the X direction.

[0086] The width in the X direction of the source region NS located between the gate pattern GP and the dummy gate pattern DGP in plan view may be smaller than the width in the X direction of the source region NS located between the multiple gate patterns GP in plan view. Therefore, in a MISFET 1Q using a source region NS located between the gate pattern GP and the dummy gate pattern DGP in plan view, there is a risk that the parasitic resistance will increase and the on-current will decrease compared to other MISFETs 1Q.

[0087] 2, a heavily doped diffusion region PR is formed between adjacent source regions NS in the Y direction. Similar to the source region NS described above, the heavily doped diffusion region PR located between the gate pattern GP and the dummy gate pattern DGP in plan view may have a reduced width in the X direction. Therefore, in a MISFET 1Q using a source region NS located between the gate pattern GP and the dummy gate pattern DGP in plan view, the resistance of the body region PB may increase and the on-breakdown voltage may decrease compared to other MISFETs 1Q.

[0088] Fig. 22 shows a manufacturing process corresponding to the manufacturing process of Fig. 15. As shown in Fig. 22, a dummy gate pattern DGP is also located on the gate insulating film.

[0089] In the second modification, the widths of the source region NS and the heavily doped diffusion region PR in the X direction are mainly determined by the distance between the gate pattern GP and the dummy gate pattern DGP. Even if the formation positions of the gate pattern GP and the dummy gate pattern DGP vary, the distance between the gate pattern GP and the dummy gate pattern DGP is constant.

[0090] That is, in the second modification, the width in the X direction of the source region NS located between the gate pattern GP and the dummy gate pattern DGP in a planar view is the same as the width in the X direction of the source region NS located between the multiple gate patterns GP in a planar view. Therefore, in the MISFET 1Q using the source region NS located between the gate pattern GP and the dummy gate pattern DGP in a planar view, the parasitic resistance is unlikely to increase and the on-current is unlikely to decrease.

[0091] In addition, in the second modification, the width in the X direction of the heavily doped diffusion region PR located between the gate pattern GP and the dummy gate pattern DGP in a planar view is the same as the width in the X direction of the heavily doped diffusion region PR located between the plurality of gate patterns GP in a planar view. Therefore, in the MISFET 1Q using the source region NS located between the gate pattern GP and the dummy gate pattern DGP in a planar view, the resistance of the body region PB is unlikely to increase and the on-breakdown voltage is unlikely to decrease.

[0092] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0093] 1Q MISFET CF1 conductive film CH1 hole DGE Dummy gate electrode DGP Dummy Gate Pattern EP semiconductor layer GE gate electrode GI gate insulating film GP Gate Pattern HPW1, HPW2 p-type well regions HNW n-type well region IJ1, IJ2 ions IF1 insulating film IL Interlayer insulating film NBL n-type buried region ND n-type drain region NLD n-type drift region NR n-type heavily doped diffusion region NS, NS1, NS2 n-type source regions NS1e, NS2e outermost end PB p-type body region PG plug PLD p-type impurity region PR p-type high concentration diffusion region RP1, RP2, RP3, RP4, RP5 resist patterns SI silicide film SS support board STI element isolation section SUB Semiconductor substrate SW Sidewall Spacer

Claims

1. (a) providing a semiconductor substrate; (b) forming an isolation region in the semiconductor substrate after the step (a); (c) after the step (b), forming a gate insulating film on the semiconductor substrate; (d) after the step (c), forming a first conductive film on the gate insulating film and the element isolation portion; (e) after the step (d), forming a first resist pattern on the first conductive film, the first resist pattern having a first opening that opens a part of the first conductive film located on the gate insulating film; (f) after the step (e), performing an anisotropic etching process using the first resist pattern as a mask to selectively remove the first conductive film exposed from the first resist pattern, thereby forming a first gate pattern and a dummy gate pattern from the first conductive film; (g) after the step (f), performing oblique ion implantation using the first resist pattern as a mask to form a first body region of the first conductivity type in a portion of the semiconductor substrate located between the first gate pattern and the dummy gate pattern in a plan view; (h) removing the first resist pattern after the step (g); Equipped with the dummy gate pattern is located at least on the element isolation portion, The method for manufacturing a semiconductor device, wherein the first body region is also formed in a portion of the semiconductor substrate located under the first gate pattern.

2. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (e), the first resist pattern has a second opening that exposes another part of the first conductive film located on the gate insulating film, In the step (f), a second gate pattern is also formed from the remaining first conductive film, After the step (f), the second gate pattern is located on the gate insulating film; In the step (g), a second body region of the first conductivity type is formed in a portion of the semiconductor substrate located between the first gate pattern and the second gate pattern in a plan view; the second body region is also formed in another portion of the semiconductor substrate located under the first gate pattern and in a portion of the semiconductor substrate located under the second gate pattern; a shortest distance between the first gate pattern and the dummy gate pattern in a direction in which the second gate pattern, the first gate pattern, and the dummy gate pattern are adjacent to each other is the same as the shortest distance between the first gate pattern and the second gate pattern.

3. 2. The method for manufacturing a semiconductor device according to claim 1, (i) after the step (h), forming a second resist pattern that covers a portion of the first gate pattern located on the gate insulating film, the first body region, and a portion of the dummy gate pattern located on the element isolation portion; (j) after the step (i), performing an anisotropic etching process using the second resist pattern as a mask to selectively remove the first gate pattern and the dummy gate pattern exposed from the second resist pattern, and forming a first gate electrode from the remaining first gate pattern and a dummy gate electrode from the remaining dummy gate pattern; (k) removing the second resist pattern after the step (j); Further provided with The method for manufacturing a semiconductor device, wherein the dummy gate electrode is located at least on the element isolation portion.

4. 4. The method for manufacturing a semiconductor device according to claim 3, (l) after the step (k), forming a first source region of a second conductivity type opposite to the first conductivity type in the first body region, and forming a first drain region of the second conductivity type in the semiconductor substrate; Further provided with the first gate electrode, the dummy gate electrode, and the first drain region extend in a first direction in a plan view, the first gate electrode is formed on a portion of the semiconductor substrate located between the first source region and the first drain region in a second direction intersecting the first direction in a plan view; a width of the dummy gate electrode in the first direction being greater than a width of the first drain region;

5. 5. The method for manufacturing a semiconductor device according to claim 4, In the step (l), a plurality of the first source regions are formed in the first body region so as to be spaced apart from each other in the first direction; the plurality of first source regions include one first source region and another first source region that are furthest apart from each other in the first direction, the one first source region has a first outermost end farthest from the other first source region in the first direction, the other first source region has a second outermost end farthest from the one first source region in the first direction, a width of the dummy gate electrode in the first direction being greater than a distance from the first outermost end to the second outermost end;

6. 5. The method for manufacturing a semiconductor device according to claim 4, the semiconductor device includes a MISFET, the MISFET has the first gate electrode, the first source region, and the first drain region; a portion of the first body region located between the first source region and the first drain region and located under the first gate electrode functions as a channel region of the MISFET; In the method for manufacturing a semiconductor device, when the MISFET is in operation, a gate potential is supplied to the first gate electrode, and the dummy gate electrode is in an electrically floating state.

7. 5. The method for manufacturing a semiconductor device according to claim 4, (m) forming a first well region of the first conductivity type in the semiconductor substrate before the step (c); Further provided with the first well region is in contact with the element isolation portion and extends in the first direction and the second direction so as to surround at least the first gate electrode, the first source region, the first drain region, the first body region, the element isolation portion, and the dummy gate electrode in a planar view.

8. 8. The method for manufacturing a semiconductor device according to claim 7, (n) before the step (c), forming a first impurity region of the first conductivity type in the semiconductor substrate at a position deeper than the element isolation part; Further provided with the first well region is formed from the upper surface of the semiconductor substrate to a position deeper than the element isolation part, and is in contact with the first impurity region; The method for manufacturing a semiconductor device, wherein the first body region is formed from the upper surface of the semiconductor substrate to a position deeper than the element isolation part and is in contact with the first impurity region.

9. 5. The method for manufacturing a semiconductor device according to claim 4, In the step (e), the first resist pattern has a second opening that exposes another part of the first conductive film located on the gate insulating film, In the step (f), a second gate pattern is also formed from the remaining first conductive film, In the step (g), a second body region of the first conductivity type is formed in a portion of the semiconductor substrate located between the first gate pattern and the second gate pattern in a plan view; the second body region is also formed in another portion of the semiconductor substrate located under the first gate pattern and in a portion of the semiconductor substrate located under the second gate pattern; a shortest distance between the first gate pattern and the dummy gate pattern in the second direction is the same as a shortest distance between the first gate pattern and the second gate pattern; In the step (i), the second resist pattern also covers the other portion of the first gate pattern located on the gate insulating film, the second body region, and a portion of the second gate pattern located on the gate insulating film; in the step (j), the first gate pattern and the second gate pattern exposed from the second resist pattern are selectively removed, the first gate electrode and the second gate electrode are formed from the remaining first gate pattern, and a third gate electrode is formed from the remaining second gate pattern; In the step (l), a second source region of the second conductivity type is formed in the second body region, and a second drain region of the second conductivity type is formed in the semiconductor substrate; the second gate electrode, the third gate electrode, and the second drain region extend in the first direction; the second gate electrode is formed on a portion of the semiconductor substrate located between the first drain region and the second source region in the second direction; the third gate electrode is formed on a portion of the semiconductor substrate located between the second drain region and the second source region in the second direction; a width of the dummy gate electrode in the first direction being larger than a width of the second drain region;

10. 2. The method for manufacturing a semiconductor device according to claim 1, The step (b) comprises: (b1) forming a trench in the semiconductor substrate; (b2) forming an insulating film on the semiconductor substrate so as to fill the trench; (b3) removing the insulating film located outside the trench so as to leave the insulating film embedded in the interior of the trench; The method for manufacturing a semiconductor device comprising the steps of:

11. 2. The method for manufacturing a semiconductor device according to claim 1, (o) after the step (h), forming a third resist pattern that covers a portion of the first gate pattern located on the gate insulating film, the first body region, and a portion of the element isolation portion exposed from the dummy gate pattern; (p) after the step (o), performing an anisotropic etching process using the third resist pattern as a mask to selectively remove the first gate pattern and the dummy gate pattern exposed from the third resist pattern, thereby forming a first gate electrode from the first gate pattern; The method for manufacturing a semiconductor device further comprises:

12. 2. The method for manufacturing a semiconductor device according to claim 1, the element isolation portion surrounds the gate insulating film, the first gate pattern, and the first body region in a plan view.

13. 2. The method for manufacturing a semiconductor device according to claim 1, the first gate pattern is located on the gate insulating film; the dummy gate pattern is located on the gate insulating film and the element isolation portion so as to straddle the boundary between the element isolation portion and the semiconductor substrate; The method for manufacturing a semiconductor device, wherein the first body region is also formed in a portion of the semiconductor substrate located under the dummy gate pattern.

14. 4. The method for manufacturing a semiconductor device according to claim 3, The method for manufacturing a semiconductor device, wherein the dummy gate electrode is formed on the element isolation portion and on the gate insulating film.

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