Semiconductor device

Abstract

To increase reliability of a semiconductor device.SOLUTION: A protection cell ESD1a has a MISFET group 1QA configured with a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA configured with a plurality of p-type MISFETs 2Q. The MISFET group 1QA and the pair of MISFET groups 2QA are electrically connected to power supply wiring and ground wiring, respectively, so as to electrically short the power supply wiring and the ground wiring. The pair of MISFET groups 2QA output a signal for making the plurality of MISFETs 1Q on-state to each gate electrode of the plurality of MISFETs 1Q. The MISFET group 1QA is provided between the pair of MISFET groups 2QA.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a protection cell for an ESD protection circuit. [Background technology]

[0002] Semiconductor devices equipped with ESD (Electro-Static Discharge) protection circuits are used to protect various circuits formed within the semiconductor device from damage caused by static electricity. The ESD protection circuit includes, for example, a detection circuit, an inverter, and a discharge circuit. When the detection circuit detects ESD current flowing through a power supply line, the detection circuit outputs a detection signal to the inverter. In response to the detection signal, the inverter outputs a drive signal to each gate electrode of multiple MISFETs (Metal Insulator Semiconductor Field Effect Transistors) that make up the discharge circuit. When each MISFET in the discharge circuit is turned on, the ESD current is discharged from the power supply line to the ground line.

[0003] For example, Patent Document 1 discloses an ESD protection circuit having an RC timer as a detection circuit, an inverter, and an n-channel transistor as a discharge circuit. In Patent Document 1, the planar layout of the ESD protection circuit shows the RC timer, the inverter, and the n-channel transistor arranged in order along one direction. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2016 / 203648 Summary of the Invention [Problem to be solved by the invention]

[0005] As semiconductor devices become more miniaturized, wiring is becoming thinner and thinner. In the wiring connecting the inverter and the gate electrodes of each MISFET constituting the discharge circuit, the wiring resistance increases due to the thinner and thinner wiring. Furthermore, as semiconductor devices become more miniaturized, the gate insulating film of the MISFET is becoming thinner, resulting in an increase in the gate capacitance of the MISFET.

[0006] Such increases in wiring resistance and gate capacitance cause RC delays in the drive signal, resulting in problems such as reduced gate drive power and slower on-state speeds for some of the MISFETs in the discharge circuit. In other words, the ESD withstand voltage decreases as the clamping performance of the ESD protection circuit decreases. As a result, the reliability of the semiconductor device decreases.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] In one embodiment, a semiconductor device includes a protection cell, a power supply wiring for supplying a power supply potential, and a ground wiring for supplying a ground potential, the protection cell having a first MISFET group and a pair of second MISFET groups, the first MISFET group and the pair of second MISFET groups being electrically connected to the power supply wiring and the ground wiring, respectively, so as to electrically short-circuit the power supply wiring and the ground wiring, the pair of second MISFET groups output a signal to a first gate electrode of each of a plurality of first MISFETs included in the first MISFET group to turn on the plurality of first MISFETs, and the first MISFET group is disposed between the pair of second MISFET groups.

[0010] In one embodiment, a semiconductor device includes an analog IP, a protection cell adjacent to the analog IP, a power supply wiring for supplying a power supply potential to the analog IP, and a ground wiring for supplying a ground potential to the analog IP. The protection cell has a first MISFET group and a pair of second MISFET groups, the first MISFET group and the pair of second MISFET groups are electrically connected to the power supply wiring and the ground wiring, respectively, so as to electrically short-circuit the power supply wiring and the ground wiring, the pair of second MISFET groups output a signal to each first gate electrode of a plurality of first MISFETs included in the first MISFET group to turn on the plurality of first MISFETs, and the first MISFET group is disposed between the pair of second MISFET groups. [Effects of the Invention]

[0011] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is an equivalent circuit diagram showing the ESD protection circuit in the first embodiment and the study example. [Figure 4] FIG. 4 is an equivalent circuit diagram showing the ESD protection circuit according to the first embodiment. [Figure 5] FIG. 5 is an equivalent circuit diagram showing the ESD protection circuit in the study example. [Figure 6] FIG. 6 is a plan view showing a protection cell in the study example. [Figure 7] FIG. 7 is a plan view showing the protection cell according to the first embodiment. [Figure 8] FIG. 8 is a plan view showing the power supply wiring and the ground wiring formed above the protection cell in the first embodiment. [Figure 9] FIG. 9 is a plan view showing a plurality of wirings formed above the protection cell according to the first embodiment. [Figure 10] FIG. 10 is a plan view showing the power supply wiring and the ground wiring formed above the protection cell in the first embodiment. [Figure 11] FIG. 11 is a plan view showing the protection cell according to the first embodiment. [Figure 12] FIG. 12 is a plan view showing the power supply wiring and the ground wiring formed above the protection cell in the first embodiment. [Figure 13] FIG. 13 is a plan view showing the power supply wiring and the ground wiring formed above the protection cell in the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a protection cell according to the first embodiment. [Figure 15] FIG. 15 is a plan view showing the power supply wiring and the ground wiring formed above the protection cell in the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing the power supply wiring and the ground wiring according to the first embodiment. [Figure 17] FIG. 17 is a plan view showing the MISFET according to the first embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing the MISFET according to the first embodiment. [Figure 19] FIG. 19 is a plan view showing a protection cell and an analog IP according to the second embodiment. [Figure 20] FIG. 20 is a plan view showing the power supply wiring and the ground wiring formed above the protection cell and the analog IP according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, depth, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that a surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0015] (Embodiment 1) <Plane layout of semiconductor device> The planar layout of the semiconductor device 100 according to the first embodiment will be described below with reference to FIGS.

[0016] 1, the semiconductor device 100 is a semiconductor chip and includes a core region CR and an outer peripheral region OR surrounding the core region CR in a plan view. The core region CR includes a plurality of circuits. The plurality of circuits include, for example, logic circuits constituting a CPU or SRAM, analog IPs (Intellectual Property), and nonvolatile memory cells. Note that IP refers to a circuit function block with a specific role. Examples of analog IPs include a PLL (Phase Locked Loop), a TRNG (True Random Number Generator), an oscillator, a temperature sensor, an analog-to-digital converter, and a digital-to-analog converter.

[0017] The peripheral region OR is provided with a plurality of protection cells ESD1, a plurality of protection cells ESD2, and a plurality of I / O (Input / Output) signal cells IOC. The plurality of protection cells ESD1 and the plurality of protection cells ESD2 each include a plurality of MISFETs for configuring an ESD protection circuit. The protection cells ESD1 configure an ESD protection circuit for a plurality of circuits provided in the core region CR. The protection cells ESD2 configure an ESD protection circuit for the I / O signal cells IOC.

[0018] The semiconductor device 100 has a rectangular planar shape, with sides 10a and 10b extending along the X direction and sides 10c and 10d extending along the Y direction. Sides 10a, 10b, 10c, and 10d form the outer edge of the peripheral region OR. The peripheral region OR is an area provided between the core region CR and sides 10a, 10b, 10c, and 10d. The protection cell ESD2 is provided between the protection cell ESD1 or the I / O signal cell IOC and sides 10a, 10b, 10c, and 10d.

[0019] 2, the outer periphery region OR is provided with a plurality of power supply wirings such as power supply wiring LVcc1 and power supply wiring LVcc2, and a plurality of ground wirings such as ground wiring LVss1 and ground wiring LVss2. The power supply wiring LVcc1, power supply wiring LVcc2, ground wiring LVss1, and ground wiring LVss2 surround the core region CR in plan view and are provided so as to overlap with the protection cell ESD1 or the protection cell ESD2 in plan view.

[0020] The power supply wiring LVcc1 supplies a power supply potential to a plurality of circuits provided in the core area CR. The ground wiring LVss1 supplies a ground potential to a plurality of circuits provided in the core area CR. The power supply wiring LVcc2 supplies a power supply potential to the I / O signal cells IOC. The power supply potential supplied from the power supply wiring LVcc2 is higher than the power supply potential supplied from the power supply wiring LVcc1. The ground wiring LVss2 supplies a ground potential to the I / O signal cells IOC.

[0021] Incidentally, as will be described in detail later, the power supply wiring LVcc1, power supply wiring LVcc2, ground wiring LVss1, and ground wiring LVss2 are respectively wiring M13 formed in the global wiring layer among the multilayer wiring layers.

[0022] Also, in the outer peripheral region OR, there are power supply wiring LVcc1, power supply wiring LVcc2, ground wiring LVss1, and ground wiring LVss2 that go around above the plurality of protection cells ESD1 and the plurality of I / O signal cells IOC, and power supply wiring LVcc1, power supply wiring LVcc2, ground wiring LVss1, and ground wiring LVss2 respectively provided above the plurality of protection cells ESD2. These wirings are electrically connected to each other by, for example, wiring M14 formed in the wiring layer above wiring M13.

[0023] <ESD protection circuit> Hereinafter, the ESD protection circuit 50 included in the semiconductor device 100 in Embodiment 1 will be described with reference to FIG. 3.

[0024] As shown in FIG. 3, a power supply potential is supplied from a power supply terminal TVcc1 connected to the power supply wiring LVcc1 to a plurality of circuits in the core region CR, and a ground potential is supplied from a ground terminal TVss1 connected to the ground wiring LVss1. A power supply potential is supplied from a power supply terminal TVcc2 connected to the power supply wiring LVcc2 to the I / O signal cell IOC, and a ground potential is supplied from a ground terminal TVss2 connected to the ground wiring LVss2.

[0025] The ESD protection circuit 50 includes a detection circuit SPC, an inverter INV, and a discharge circuit B-MOS. The discharge circuit B-MOS includes a MISFET group 1QA composed of a plurality of n-type MISFETs 1Q. The inverter INV includes a MISFET group 2QA composed of a plurality of p-type MISFETs 2Q and a MISFET group 3QA composed of a plurality of n-type MISFETs 3Q. The detection circuit SPC is a time constant circuit that detects a positive surge voltage and is configured by, for example, an integration circuit including a resistance element and a capacitance element.

[0026] The detection circuit SPC, inverter INV (MISFET group 2QA, MISFET group 3QA) and discharge circuit B-MOS (MISFET group 1QA) for the protection cell ESD1 are electrically connected to the power supply wiring LVcc1 and the ground wiring LVss1, respectively, so as to electrically short-circuit the power supply wiring LVcc1 and the ground wiring LVss1.

[0027] The detection circuit SPC, inverter INV, and discharge circuit B-MOS for the protection cell ESD2 are electrically connected to the power supply wiring LVcc2 and the ground wiring LVss2, respectively, so as to electrically short-circuit the power supply wiring LVcc2 and the ground wiring LVss2.

[0028] When the detection circuit SPC detects an ESD current flowing through the power supply wiring LVcc1 or LVcc2, the detection circuit SPC outputs a detection signal to the inverter INV. In response to the detection signal, the MISFET group 2QA of the inverter INV outputs a signal to the gate electrode of each of the multiple MISFETs 1Q that make up the discharge circuit B-MOS, to turn on the multiple MISFETs 1Q. As a result, the ESD current is discharged from the power supply wiring LVcc1 or LVcc2 to the ground wiring LVss1 or LVss2, as shown in the "discharge path" in Figure 3.

[0029] When the detection circuit SPC does not detect an ESD current, the MISFET group 3QA of the inverter INV outputs a signal to the gate electrode of each of the plurality of MISFETs 1Q to turn the plurality of MISFETs 1Q into an OFF state.

[0030] For example, when a steep high voltage is applied to the power supply terminal TVcc1 or TVcc2, an ESD current flows from the power supply wiring LVcc1 or LVcc2 to the ground wiring LVss1 or LVss2 via the ESD protection circuit 50. This makes it possible to prevent the circuits to be protected, such as the multiple circuits in the core region CR and the I / O signal cell IOC, from being destroyed by the steep high voltage.

[0031] <Examples and problems> 5 and 6, a semiconductor device that is an example of a study conducted by the present inventors will be described below. FIG. 5 shows details of the discharge circuit B-MOS in FIG. 3. FIG. 6 shows a planar layout of a protection cell ESD1a for constituting the ESD protection circuit 50. Note that the protection cell ESD1a is one of the multiple protection cells ESD1 shown in FIG. 1 that is arranged along the side 10a.

[0032] 5 and 6, the MISFET group 1QA is made up of a plurality of MISFETs 1Q connected in parallel to one another. As shown in Fig. 6, the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, and the detection circuit SPC are arranged in this order in the direction from the core region CR toward the side 10a.

[0033] The detection circuit SPC is electrically connected to the gate electrodes of the plurality of MISFETs 2Q and the plurality of MISFETs 3Q via wiring M1 and wiring M2. The drain regions of the plurality of MISFETs 2Q and the plurality of MISFETs 3Q are electrically connected to the gate electrodes of the plurality of MISFETs 1Q via wiring M1 and wiring M2. The wiring M1 is formed in the lowest wiring layer of the multi-layer wiring layer, and the wiring M2 is formed in the wiring layer one layer above the wiring M1.

[0034] In recent years, with the miniaturization of semiconductor devices, wiring has become thinner and thinner. In particular, wiring such as wiring M1 and wiring M2 formed in a wiring layer close to a MISFET needs to be made thinner and thinner to accommodate the miniaturization of the MISFET, resulting in an increase in wiring resistance.

[0035] As described above, when discharging an ESD current, the MISFET group 2QA outputs a signal to the gate electrode of each of the MISFETs 1Q to turn on the MISFETs 1Q. However, as the wiring M1 and wiring M2 become thinner and thinner, the wiring resistance increases, making it more likely that an RC delay will occur in the output signal from the MISFET group 2QA. The greater the distance from the MISFET group 2QA, the greater the wiring resistance, resulting in a larger signal delay.

[0036] That is, among the multiple MISFETs 1Q, the MISFETs 1Q that are far from the MISFET group 2QA have reduced gate driving power or are turned on more slowly. This makes it difficult to adequately protect the multiple circuits provided in the core region CR from ESD current, resulting in a problem of reduced reliability of the semiconductor device 100. Note that the same problem occurs not only in the protection cell ESD1 but also in the protection cell ESD2, making it difficult to adequately protect the I / O signal cell IOC.

[0037] <Protection Cell of First Embodiment> The protection cells ESD1 and ESD2 according to the first embodiment will be described below with reference to FIGS. 1, 4, and 7 to 18. FIG.

[0038] 1 includes protection cells ESD1a arranged along side 10a, protection cells ESD1b arranged along side 10b, protection cells ESD1c arranged along side 10c, and protection cells ESD1d arranged along side 10d. The multiple protection cells ESD2 shown in FIG. 1 include protection cells ESD2a arranged along side 10a, protection cells ESD2b arranged along side 10b, protection cells ESD2c arranged along side 10c, and protection cells ESD2d arranged along side 10d.

[0039] 7 shows the planar layout of protection cell ESD1a and protection cell ESD2d. Note that the planar layout of protection cell ESD1b is the same as the planar layout of protection cell ESD1a rotated 180 degrees in plan view. The planar layout of protection cell ESD2c is the same as the planar layout of protection cell ESD2d rotated 180 degrees in plan view.

[0040] The planar layout of the protective cell ESD2 is the same as that of the protective cell ESD1, but the thickness of the gate insulating film of each MISFET provided in the protective cell ESD2 is thicker than the thickness of the gate insulating film of each MISFET provided in the protective cell ESD1.

[0041] 7, in the first embodiment, the position at which the MISFET group 2QA is provided is different from that in the study example. In the first embodiment, the protection cell ESD1a and the protection cell ESD2d have a pair of MISFET groups 2QA. The MISFET group 1QA is adjacent to the pair of MISFET groups 2QA and is provided between the pair of MISFET groups 2QA.

[0042] Furthermore, in the direction from the core region CR toward the side 10a, the MISFET group 1QA, the MISFET group 3QA, and the detection circuit SPC are provided in this order. In other words, the MISFET group 1QA is provided between the core region CR and the MISFET group 3QA. The MISFET group 3QA is provided between the MISFET group 1QA and the detection circuit SPC.

[0043] The MISFET group 1QA is arranged in a rectangular shape in plan view. The pair of MISFET groups 2QA are provided along the long sides of the MISFET group 1QA, and the MISFET group 3QA is provided along the short sides of the MISFET group 1QA. The detection circuit SPC is provided along the short sides of the MISFET group 1QA, with the MISFET group 3QA interposed therebetween.

[0044] The MISFET 1Q has an n-type gate electrode GEn formed on a semiconductor substrate via a gate insulating film, and an n-type impurity region NSD formed in the semiconductor substrate. The impurity region NSD forms a source region or a drain region of the MISFET 1Q. A p-type impurity region PR1 is formed in the semiconductor substrate. The impurity region PR1 surrounds the multiple MISFETs 1Q in plan view. The MISFET group 1QA consists of multiple MISFETs 1Q connected in parallel to each other.

[0045] The MISFET 2Q has a p-type gate electrode GEp formed with a gate insulating film on a semiconductor substrate, and a p-type impurity region PSD formed in the semiconductor substrate. The impurity region PSD constitutes the source region or drain region of the MISFET 2Q. An n-type impurity region NR1 is formed in the semiconductor substrate. The impurity region NR1 surrounds the multiple MISFETs 2Q in plan view. The MISFET group 2QA consists of multiple MISFETs 2Q connected in parallel to each other.

[0046] The MISFET 3Q has an n-type gate electrode GEn with a gate insulating film formed on a semiconductor substrate, and an n-type impurity region NSD formed in the semiconductor substrate. The impurity region NSD forms a source region or a drain region of the MISFET 3Q. A p-type impurity region PR2 is formed in the semiconductor substrate. The impurity region PR2 surrounds the multiple MISFETs 3Q in plan view. The MISFET group 3QA consists of multiple MISFETs 3Q connected in parallel to each other.

[0047] In the first embodiment, the case where MISFET1Q is n-type, MISFET2Q is p-type, and MISFET3Q is n-type is exemplified. However, when MISFET1Q is p-type, p-type MISFET2Q and n-type MISFET3Q are used. In that case, the conductivity types of the components included in MISFET group 1QA, MISFET group 2QA, and MISFET group 3QA are reversed, for example, impurity region NSD becomes a p-type impurity region.

[0048] A plurality of wirings M1 and a plurality of wirings M2 are used to connect the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA and the detection circuit SPC. The wirings M1 are formed in the lowest wiring layer of the multilayer wiring layer, and the wirings M2 are formed in the wiring layer one layer above the wirings M1.

[0049] The detection circuit SPC is electrically connected to the gate electrode GEp of each of the plurality of MISFETs 2Q and the gate electrode GEn of each of the plurality of MISFETs 3Q via wiring M1 and wiring M2. The drain regions of each of the plurality of MISFETs 2Q and the plurality of MISFETs 3Q are electrically connected to the gate electrode GEn of each of the plurality of MISFETs 1Q via wiring M1 and wiring M2.

[0050] To make the drawing easier to understand, only the wiring M1 and wiring M2 used to connect the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, and the detection circuit SPC are shown. That is, some of the multiple wirings M1 and multiple wirings M2 are electrically connected to the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, or the detection circuit SPC so that the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, or the detection circuit SPC is electrically connected to the power supply wiring LVcc1, the power supply wiring LVcc2, the ground wiring LVss1, or the ground wiring LVss2.

[0051] In the study example, the problem was that the further the distance from MISFET group 2QA, the greater the wiring resistance, resulting in greater signal delay, as shown in Figures 5 and 6. For example, the wiring path for MISFET 1Q, which is the farthest from MISFET group 2QA, is roughly the sum of the length of the long side of MISFET group 1QA and half the length of the short side of MISFET group 1QA.

[0052] 7, in the first embodiment, the MISFET group 2QA is provided along the long side of the MISFET group 1QA. Therefore, the wiring path of the MISFET 1Q, which is farthest from the MISFET group 2QA, is approximately half the length of the short side of the MISFET group 1QA.

[0053] 4 and 5, the equivalent circuit of the ESD protection circuit 50 of the first embodiment is the same as the equivalent circuit of the ESD protection circuit 50 of the study example, but the distribution of wiring resistance is different between the first embodiment and the study example. In the first embodiment, the wiring resistance between the gate electrode GEn of each of the multiple MISFETs 1Q connected in parallel and the MISFET group 2QA is equalized to a low value. Therefore, in the first embodiment, the signal delay from the MISFET group 2QA to the gate electrode GEn of the MISFET 1Q can be significantly reduced compared to the study example.

[0054] As described above, according to the first embodiment, the problems of reduced gate drive power and slower on-state speed can be suppressed in some MISFETs 1Q of the MISFET group 1QA. Therefore, the clamping performance of the ESD protection circuit 50 can be improved, and the multiple circuits and I / O signal cells IOC provided in the core region CR can be adequately protected from ESD current. This means that the ESD resistance of the semiconductor device 100 has been improved, and it can also be said that higher reliability than conventional devices has been ensured.

[0055] Although the first embodiment reduces the wiring resistance between the MISFET group 2QA of the inverter INV and the discharge circuit B-MOS (MISFET group 1QA), the wiring resistance between the detection circuit SPC and the MISFET group 2QA of the inverter INV increases slightly. However, the number of MISFETs 2Q included in the MISFET group 2QA is much smaller than the number of MISFETs 1Q included in the MISFET group 1QA. Furthermore, the total gate width of the multiple MISFETs 2Q included in the MISFET group 2QA is approximately several tens of micrometers to several hundred micrometers, which is much smaller than the total gate width of the multiple MISFETs 1Q included in the MISFET group 1QA. Therefore, the gate capacitance of the entire MISFET group 2QA is small. Therefore, the increase in the wiring resistance between the detection circuit SPC and the MISFET group 2QA does not significantly affect the clamping performance of the ESD protection circuit 50.

[0056] On the other hand, the total gate width of the multiple MISFETs 1Q included in the MISFET group 1QA is approximately several thousand μm, and the gate capacitance of the entire MISFET group 1QA is much larger than the gate capacitance of the entire MISFET group 2QA. Therefore, reducing the wiring resistance between the MISFET group 2QA and the MISFET group 1QA has a significant impact on the clamping performance of the ESD protection circuit 50. Therefore, the first embodiment can significantly improve the clamping performance of the ESD protection circuit 50.

[0057] 8 shows a planar layout of the power supply wiring LVcc1, the power supply wiring LVcc2, the ground wiring LVss1, and the ground wiring LVss2 provided above the protection cell ESD1a. The power supply wiring LVcc1, the power supply wiring LVcc2, the ground wiring LVss1, and the ground wiring LVss2 are each a wiring M13 formed in a wiring layer above the wiring M1 and the wiring M2 in the multilayer wiring layer.

[0058] The protection cell ESD1a is used in an ESD protection circuit 50 for multiple circuits provided in the core region CR. Therefore, in order to quickly discharge in the discharge circuit B-MOS, it is preferable that the wiring paths between the discharge circuit B-MOS and the power supply wiring LVcc1 and ground wiring LVss1 are as short as possible. Therefore, it is preferable that the power supply wiring LVcc1 and ground wiring LVss1 are arranged so that the power supply wiring LVcc1 and ground wiring LVss1 overlap as much as possible with the MISFET group 1QA of the protection cell ESD1a in a plan view.

[0059] Therefore, of the two short sides of the MISFET group 1QA, the one short side opposite to the one adjacent to the MISFET group 2QA is placed near the power supply wiring LVcc1 and the ground wiring LVss1. Also, the one short side of the MISFET group 1QA is placed near the power supply wiring LVcc2 and the ground wiring LVss2.

[0060] 9 shows a planar layout of the wirings M3 to M12 provided above the protection cell ESD1a. The wirings M3 to M12 are each formed in a wiring layer between the wirings M13 and M2 in a multi-layer wiring layer.

[0061] The wirings M3 to M12 extend in a direction intersecting the extending direction of the power supply wiring LVcc1 and the ground wiring LVss1, which are the wiring M13, and are electrically connected to the power supply wiring LVcc1 and the ground wiring LVss1, respectively.

[0062] As described above, some of the multiple wirings M1 and multiple wirings M2 are electrically connected to the power supply wiring LVcc1 and the ground wiring LVss1 via these wirings M3 to M12. Using such some of the wirings M1 and M2 and the wirings M3 to M12, the detection circuit SPC, MISFET group 2QA, MISFET group 3QA, and MISFET group 1QA are electrically connected to the power supply wiring LVcc1 and the ground wiring LVss1, respectively, so as to electrically short-circuit the power supply wiring LVcc1 and the ground wiring LVss1.

[0063] FIG. 10 shows a planar layout of the power supply wiring LVcc1, the power supply wiring LVcc2, the ground wiring LVss1, and the ground wiring LVss2 provided above the protection cell ESD2d.

[0064] The protection cell ESD2d is used in the ESD protection circuit 50 for the I / O signal cell IOC. Therefore, in order to quickly discharge in the discharge circuit B-MOS, it is preferable that the wiring paths between the discharge circuit B-MOS and the power supply wiring LVcc2 and ground wiring LVss2 are as short as possible. Therefore, it is preferable that the power supply wiring LVcc2 and ground wiring LVss2 are arranged so that the power supply wiring LVcc2 and ground wiring LVss2 overlap as much as possible with the MISFET group 1QA of the protection cell ESD2d in a plan view.

[0065] Therefore, of the two short sides of the MISFET group 1QA, the one short side opposite to the one adjacent to the MISFET group 2QA is placed near the power supply wiring LVcc2 and the ground wiring LVss2. Also, the one short side of the MISFET group 1QA is placed near the power supply wiring LVcc1 and the ground wiring LVss1.

[0066] Although not shown, above the protective cell ESD2d, wirings M3 to M12 are also formed for the same purpose as in Fig. 9. These wirings M3 to M12 extend in a direction intersecting the extension direction of the power supply wiring LVcc2 and the ground wiring LVss2, which are wiring M13, and are electrically connected to the power supply wiring LVcc2 and the ground wiring LVss2. Therefore, in the protective cell ESD2d as well, the detection circuit SPC, MISFET group 2QA, MISFET group 3QA, and MISFET group 1QA are electrically connected to the power supply wiring LVcc2 and the ground wiring LVss2, respectively, via wirings M1 to M12 so as to electrically short-circuit the power supply wiring LVcc2 and the ground wiring LVss2.

[0067] 11 shows the planar layout of protection cell ESD1c and protection cell ESD2a. Note that the planar layout of protection cell ESD1d is the same as the planar layout of protection cell ESD1c rotated 180 degrees in plan view. The planar layout of protection cell ESD2b is the same as the planar layout of protection cell ESD2a rotated 180 degrees in plan view.

[0068] 11, in protection cells ESD1c and ESD2a, the wiring relationship between MISFET group 1QA, MISFET group 2QA, MISFET group 3QA, and detection circuit SPC is the same as in protection cells ESD1a and ESD2d. Also, in protection cells ESD1c and ESD2a, the layout relationship between MISFET group 1QA, MISFET group 2QA, MISFET group 3QA, and detection circuit SPC is the same as in protection cells ESD1a and ESD2d.

[0069] That is, in the protection cells ESD1c and ESD2a, the MISFET group 1QA is adjacent to a pair of MISFET groups 2QA and is provided between the pair of MISFET groups 2QA. Furthermore, the MISFET group 1QA, the MISFET group 3QA, and the detection circuit SPC are provided in this order in the direction from the core region CR toward the side 10c. In other words, the MISFET group 1QA is provided between the core region CR and the MISFET group 3QA. The MISFET group 3QA is provided between the MISFET group 1QA and the detection circuit SPC.

[0070] In addition, in the protection cells ESD1c and ESD2a, the layout shape of the MISFET group 1QA in a plan view is rectangular. The pair of MISFET groups 2QA are provided along the long sides of the MISFET group 1QA, and the MISFET group 3QA is provided along the short sides of the MISFET group 1QA. The detection circuit SPC is provided along the short sides of the MISFET group 1QA, with the MISFET group 3QA interposed therebetween.

[0071] FIG. 12 shows a planar layout of the power supply wiring LVcc1, the power supply wiring LVcc2, the ground wiring LVss1, and the ground wiring LVss2 provided above the protection cell ESD1c.

[0072] To enable the discharge circuit B-MOS to discharge quickly, it is preferable that the wiring paths between the discharge circuit B-MOS and the power supply wiring LVcc1 and ground wiring LVss1 are as short as possible. Therefore, it is preferable that the power supply wiring LVcc1 and ground wiring LVss1 are arranged so that the power supply wiring LVcc1 and ground wiring LVss1 overlap as much as possible with the MISFET group 1QA of the protection cell ESD1c in a plan view.

[0073] Therefore, of the two short sides of the MISFET group 1QA, the one short side opposite to the one adjacent to the MISFET group 2QA is placed near the power supply wiring LVcc1 and the ground wiring LVss1. Also, the one short side of the MISFET group 1QA is placed near the power supply wiring LVcc2 and the ground wiring LVss2.

[0074] Although not shown, above the protection cell ESD1c, wirings M3 to M12 are also formed for the same purpose as in Fig. 9. These wirings M3 to M12 extend in a direction intersecting the extension direction of the power supply wiring LVcc1 and ground wiring LVss1, which are wiring M13, and are electrically connected to the power supply wiring LVcc1 and ground wiring LVss1. Therefore, in the protection cell ESD1c as well, the detection circuit SPC, MISFET group 2QA, MISFET group 3QA, and MISFET group 1QA are electrically connected to the power supply wiring LVcc1 and ground wiring LVss1, respectively, via wirings M1 to M12 so as to electrically short-circuit the power supply wiring LVcc1 and ground wiring LVss1.

[0075] FIG. 13 shows a planar layout of the power supply wiring LVcc1, the power supply wiring LVcc2, the ground wiring LVss1, and the ground wiring LVss2 provided above the protection cell ESD2a.

[0076] To quickly discharge the discharge circuit B-MOS, it is preferable that the wiring paths between the discharge circuit B-MOS and the power supply wiring LVcc2 and ground wiring LVss2 are as short as possible. Therefore, it is preferable that the power supply wiring LVcc2 and ground wiring LVss2 are arranged so that the power supply wiring LVcc2 and ground wiring LVss2 overlap as much as possible with the MISFET group 1QA of the protection cell ESD2a in a plan view.

[0077] Therefore, of the two short sides of the MISFET group 1QA, the one short side opposite to the one adjacent to the MISFET group 2QA is placed near the power supply wiring LVcc2 and the ground wiring LVss2. Also, the one short side of the MISFET group 1QA is placed near the power supply wiring LVcc1 and the ground wiring LVss1.

[0078] <Cross-sectional structure of the protection cell> Fig. 14 is a cross-sectional view taken along the line AA shown in Fig. 11 and Fig. 12. As an example of the cross-sectional structures of the protection cell ESD1 and the protection cell ESD2, the cross-sectional structure of the protection cell ESD1c will be described.

[0079] As shown in FIG. 14, the semiconductor device 100 includes a semiconductor substrate SUB, a plurality of transistors, and a multi-layer wiring layer formed on the semiconductor substrate SUB.

[0080] The semiconductor substrate SUB has an upper surface and a lower surface and is made of p-type silicon. An element isolation portion STI is formed in the semiconductor substrate SUB. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB to reach a predetermined depth from the upper surface of the semiconductor substrate SUB, and an insulating film buried inside the trench. The insulating film is, for example, a silicon oxide film.

[0081] An n-type well region DNW is formed in the semiconductor substrate SUB. A ground wiring LVss1 is electrically connected to the semiconductor substrate SUB. The well region DNW serves to electrically separate the ground wiring LVss1 from the ground wiring LVss2. When, for example, a region in which a protection cell ESD1 is formed is used as a region in the semiconductor substrate SUB for electrical connection to the ground wiring LVss1, the well region DNW is not formed in the region in which the protection cell ESD1 is formed.

[0082] In the well region DNW, p-type well regions PW1, PW2, and PW3 are formed. Gate electrodes GEn are formed on the well regions PW1, PW2, and PW3, respectively, with gate insulating films interposed therebetween. The gate electrodes GEn are, for example, n-type polycrystalline silicon films.

[0083] An n-type impurity region NSD is formed in each of the well regions PW1, PW2, and PW3. A p-type impurity region PR1 is formed in the well region PW1, a p-type impurity region PR2 is formed in the well region PW2, and a p-type impurity region PR3 is formed in the well region PW3.

[0084] MISFET1Q has a gate insulating film and a gate electrode GEn formed on a well region PW1, and an impurity region NSD formed in the well region PW1 as a source region or a drain region. A portion of the well region PW1 located between the source region and the drain region and covered by the gate electrode GEn functions as a channel region of MISFET1Q. A ground potential is supplied to the well region PW1 via an impurity region PR1 electrically connected to a ground wiring LVss1 or a ground wiring LVss2.

[0085] 7 and 11, the layout shape of the MISFET group 1QA in a plan view is rectangular. In other words, the planar shape of the well region PW1 in which the MISFET group 1QA is formed is rectangular. In yet other words, the region surrounded by the impurity region PR1 in a plan view is the region in which the MISFET group 1QA is arranged, and is rectangular.

[0086] MISFET3Q has a gate insulating film and a gate electrode GEn formed on a well region PW2, and an impurity region NSD formed in the well region PW2 as a source region or a drain region. A portion of the well region PW2 located between the source region and the drain region and covered by the gate electrode GEn functions as a channel region of MISFET2Q. A ground potential is supplied to the well region PW2 via an impurity region PR2 electrically connected to a ground wiring LVss1 or a ground wiring LVss2.

[0087] The integrator circuit of the detection circuit SPC is mainly composed of a capacitance element and a resistance element. These capacitance element and resistance element can be formed by appropriately combining a well region PW3, a gate insulating film and a gate electrode GEn formed on the well region PW3, and an impurity region NSD formed in the well region PW3. The resistance element may be formed of a barrier metal film included in wiring of a damascene structure or a dual damascene structure, which will be described later.

[0088] Although not shown in FIG. 14, the MISFET group 2QA (MISFET2Q) in FIG. 11 will be described below. An n-type well region is formed in the well region DNW in which the MISFET group 2QA is formed. A gate electrode GEp is formed on the n-type well region via a gate insulating film. A p-type impurity region PSD and an n-type impurity region NR1 are formed in the n-type well region. MISFET 2Q has a gate insulating film and gate electrode GEp formed on the n-type well region, and has the impurity region PSD as a source region or a drain region. A portion of the n-type well region that is located between the source region and the drain region and is covered by the gate electrode GEp functions as a channel region of MISFET 2Q. A power supply potential is supplied to the n-type well region via the impurity region NR1 electrically connected to a power supply wiring LVcc1 or a power supply wiring LVcc2.

[0089] The multilayer wiring layer is formed on a semiconductor substrate SUB and has multiple wiring layers. In the example of Fig. 14, the multilayer wiring layer is composed of a first wiring layer to a fourteenth wiring layer. Wires M1 to M14 are formed in the first wiring layer to the fourteenth wiring layer, respectively. The first wiring layer to the fifth wiring layer are local wiring layers, the sixth wiring layer to the twelfth wiring layer are semi-global wiring layers, and the thirteenth wiring layer and the fourteenth wiring layer are global wiring layers.

[0090] The thickness of each of the wirings M13 and M14 is greater than the thickness of each of the wirings M6 to M12, and the line width of each of the wirings M13 and M14 is greater than the line width of each of the wirings M6 to M12. The thickness of each of the wirings M6 to M12 is greater than the thickness of each of the wirings M1 to M5, and the line width of each of the wirings M6 to M12 is greater than the line width of each of the wirings M1 to M5.

[0091] The wirings M1 to M14 are each wirings of a damascene structure or a dual damascene structure, and are composed of, for example, a barrier metal film including a tantalum film and a tantalum nitride film, and a copper film formed on the barrier metal film and having a thickness greater than that of the barrier metal film.

[0092] 3, 4, and 5, the power supply terminal TVcc1, the ground wiring LVss1, the power supply wiring LVcc2, and the ground terminal TVss2 are each formed by a part of the wiring formed in the layer above the wiring M14 (not shown). The wiring formed in the layer above the wiring M14 is mainly formed of a patterned aluminum alloy film.

[0093] 15 and 16, the connection relationship between the power supply wiring LVcc1, power supply wiring LVcc2, ground wiring LVss1, and ground wiring LVss2 that run around above the multiple protection cells ESD1 and the multiple I / O signal cells IOC, and the power supply wiring LVcc1, power supply wiring LVcc2, ground wiring LVss1, and ground wiring LVss2 that are respectively provided above the protection cell ESD2 will be described below.

[0094] 16 is a cross-sectional view taken along line BB in FIG.

[0095] 16, the power supply wiring LVcc2 located above the protection cell ESD1c is electrically connected to the power supply wiring LVcc2 located above the protection cell ESD2c by the wiring M14. Similarly, the power supply wiring LVcc1 and the ground wiring LVss1 can be connected from above the protection cell ESD1c or the I / O signal cell IOC to above the protection cell ESD2c by the wiring M14.

[0096] Moreover, above the protection cell ESD1c or the I / O signal cell IOC, the ground wiring LVss2 is arranged on the outer periphery of the power supply wiring LVcc1, the ground wiring LVss1, and the power supply wiring LVcc2. No other wiring exists between the ground wiring LVss2 located above the protection cell ESD1c or the I / O signal cell IOC and the ground wiring LVss2 located above the protection cell ESD2c. Therefore, these ground wirings LVss2 may be integrated or may be electrically connected via wiring M14.

[0097] In the first embodiment, an example is given in which the multilayer wiring layer is composed of the first to fourteenth wiring layers, but the number of wiring layers in the multilayer wiring layer is not limited to 14 layers, and may be more than 14 layers or less than 14 layers.

[0098] <Detailed structure of each MISFET> 17 and 18, the detailed structures of the multiple MISFETs included in the semiconductor device 100, such as MISFET1Q, MISFET2Q, MISFET3Q, the MISFETs provided in the core region CR, and the MISFETs provided in the I / O signal cells IOC, will be described below.

[0099] In the first embodiment, the channel region of each of the multiple MISFETs included in the semiconductor device 100 is three-dimensionally covered by the gate electrodes of the multiple MISFETs. As such a MISFET, a FIN-FET structure or a GAA (Gate All Around) structure using nanowires or nanosheets can be applied.

[0100] 17 and 18, a case will be described in which the plurality of MISFETs included in the semiconductor device 100 have a FIN-FET structure. Here, the plurality of MISFETs 1Q included in the MISFET group 1QA will be exemplified.

[0101] 17 and 18, the semiconductor substrate SUB is provided with a plurality of protruding portions 20 that are parts of the semiconductor substrate SUB. The plurality of protruding portions 20 extend in the X direction and are spaced apart from one another in the Y direction. Element isolation portions STI are formed on the semiconductor substrate SUB located between the plurality of protruding portions 20. In other words, the spaces between the plurality of protruding portions 20 correspond to trenches formed in the semiconductor substrate SUB, and the element isolation portions STI are formed inside the trenches. The position of the upper surface of the element isolation portion STI is lower than the position of the upper surfaces of the protruding portions 20.

[0102] The gate electrode GEn extends in the Y direction and is formed so as to cover the top surface and both side surfaces of at least one of the multiple protrusions 20. The gate insulating film GI is formed between the gate electrode GEn and the protrusion 20. The well region PW1 is formed in the semiconductor substrate SUB including the protrusion 20. The impurity region NSD is formed in the protrusion 20 (in the well region PW1) exposed from the gate electrode GEn.

[0103] In the case of a FIN-FET structure, a well region PW1 located between two impurity regions NSD that become the source region or the drain region and covered with the gate electrode GEn becomes the channel region of the MISFET1Q.

[0104] Since the MISFET has a three-dimensional structure like a FIN-FET, more MISFETs can be arranged in the same area compared to a planar structure, ensuring a large drive current. This allows for the miniaturization of the semiconductor device 100 to be promoted.

[0105] On the other hand, in order to increase the speed of MISFETs, the thickness of the gate insulating film GI is being reduced. In the case of the MISFETs provided in the protective cell ESD1 and the core region CR, the thickness of the gate insulating film GI is, for example, 1 nm or more and 4 nm or less. In the case of the MISFETs provided in the protective cell ESD2 and the I / O signal cell IOC, the thickness of the gate insulating film GI is thicker than that of the protective cell ESD1, for example, 3 nm or more and 6 nm or less.

[0106] The gate insulating film GI is, for example, a silicon oxide film or a laminated film of a silicon oxide film and a high-dielectric-constant film. The high-dielectric-constant film is an insulating film having a higher dielectric constant than a silicon nitride film, such as a hafnium oxide film (HfO2 film) or a hafnium silicate film (HfSiO film).

[0107] As the gate insulating film becomes thinner and its dielectric constant becomes higher, the gate capacitance tends to increase. As the gate capacitance increases, signal delays tend to occur between the MISFET group 2QA and the MISFET group 1QA (see FIG. 4). However, by employing the protection cells ESD1 and ESD2 of the first embodiment, the wiring resistance can be significantly reduced and the signal delay can be significantly suppressed, thereby making it possible to suitably accommodate thinner gate insulating films.

[0108] Furthermore, in the FIN-FET structure, forming the protrusion 20 imposes constraints on the manufacturing process, making it difficult to form multiple protrusions 20 extending in different directions. The gate electrode needs to extend in a direction intersecting the extension direction of the protrusion 20 so as to cover the top and both side surfaces of the protrusion 20. Therefore, as shown in FIGS. 7 and 11, even if the orientations of the protection cells ESD1 and ESD2 are different, the extension direction of the gate electrode is fixed to the Y direction. In the first embodiment, even if the extension direction of the gate electrode is fixed, signal delay can be suppressed.

[0109] As described above, in the first embodiment, the case where the multiple MISFETs included in the semiconductor device 100 have a three-dimensional structure such as a FIN-FET structure has been described. However, even if the multiple MISFETs have a planar structure, by using the protection cells ESD1 and ESD2 of the first embodiment, the clamping performance of the ESD protection circuit 50 can be improved, and the reliability of the semiconductor device 100 can be improved.

[0110] (Embodiment 2) 19 and 20, the semiconductor device according to the second embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0111] In the first embodiment, the protection cell ESD1 and the protection cell ESD2 are provided in the outer periphery region OR. In the second embodiment, a case will be described in which the protection cell ESD1 or the protection cell ESD2 is provided in the core region CR.

[0112] As shown in FIG. 19 , the core area CR is provided with multiple circuits, including an analog IP 60. Specific examples of the analog IP 60 have been described above. Because the analog IP 60 is susceptible to noise, dedicated power supply and ground voltages are often provided for the analog IP 60 to prevent noise propagation from the power supply voltage commonly used by the semiconductor chip and the circuit area to which the ground voltage is supplied. Therefore, unlike other circuits, the analog IP 60 shown in FIG. 19 is supplied with power supply and ground potentials from power wiring and ground wiring provided exclusively for the analog IP 60. Depending on the specifications of the analog IP 60, power wiring LVcc1 and ground wiring LVss1, or power wiring LVcc2 and ground wiring LVss2, may be used as wiring for supplying the power supply and ground potentials.

[0113] In the second embodiment, a power supply wiring LVcc2 and a ground wiring LVss2 are used as wirings for supplying a power supply potential and a ground potential to the analog IP 60, and a protection cell ESD2d is used as the ESD protection circuit 50. As shown in FIG.

[0114] 19 and 20, the protective cell ESD2d is provided adjacent to the analog IP 60. The power supply wiring LVcc2 and the ground wiring LVss2 are formed in the 13th wiring layer so as to overlap with the analog IP 60 and the protective cell ESD2d in plan view.

[0115] Although not shown, the power supply wiring LVcc2 and the ground wiring LVss2 are electrically connected to the analog IP60 and the protective cell ESD2d by wiring M1 to wiring M12. The power supply terminal TVcc2 and the ground terminal TVss2 for the analog IP60 are formed by part of wiring formed in the upper layer of wiring M14 formed immediately above the power supply wiring LVcc2 and the ground wiring LVss2 shown in FIG.

[0116] In this way, in the second embodiment, the analog IP 60 can be protected from ESD current by the protection cell ESD2d provided exclusively for the analog IP 60.

[0117] Note that protection cell ESD2a, protection cell ESD2b, or protection cell ESD2c can be used instead of protection cell ESD2d depending on the planar layout shape of the analog IP 60 or the space available around the analog IP 60. Furthermore, when power supply wiring LVcc1 and ground wiring LVss1 are used as wiring for supplying power supply potential and ground potential to the analog IP 60, protection cell ESD1a, protection cell ESD1b, protection cell ESD2c, or protection cell ESD1d can also be used.

[0118] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0119] 100 Semiconductor device Sides 10a, 10b, 10c, and 10d 20 Protrusion 50 ESD protection circuit 60 Analog IP 1Q, 2Q, 3Q MISFET 1QA, 2QA, 3QA MISFET group B-MOS discharge circuit (MISFET group 1QA) CR Core Area DNW n-type well region ESD1, ESD1a, ESD1b, ESD1c, ESD1d Protection cells for core area Protection cells for ESD2, ESD2a, ESD2b, ESD2c, ESD2d I / O signal cells INV Inverter (MISFET group 2QA, 3QA) IOC I / O signal cell GEn, Gep gate electrodes GI gate insulating film LVcc1 Power supply wiring for the core area Power wiring for LVcc2 I / O signal cells LVss1 Ground wiring for core area Ground wiring for LVss2 I / O signal cells M1 to M14 wiring OR outer area PR1, PR2, RP3 p-type impurity regions PSD p-type impurity region (source region, drain region) PW1, PW2, PW3 p-type well regions NR1 n-type impurity region NSD n-type impurity region (source region, drain region) SPC detection circuit STI element isolation section SUB Semiconductor substrate TVcc1, TVcc2 power supply terminal TVss1, TVss2 ground terminal

Claims

1. a core region in which a plurality of circuits are provided; an outer peripheral region surrounding the core region in a plan view; a protection cell provided in the peripheral region and constituting an ESD protection circuit; a power supply wiring for supplying a power supply potential; a ground wiring for supplying a ground potential; Equipped with the protection cell has a first MISFET group constituted by a plurality of first MISFETs of a first conductivity type, and a pair of second MISFET groups constituted by a plurality of second MISFETs of a second conductivity type opposite to the first conductivity type, the first MISFET group and the pair of second MISFET groups are electrically connected to the power supply wiring and the ground wiring, respectively, so as to electrically short-circuit the power supply wiring and the ground wiring; the pair of second MISFET groups outputs a signal to a first gate electrode of each of the plurality of first MISFETs to turn on the plurality of first MISFETs; The semiconductor device, wherein the first MISFET group is provided between the pair of second MISFET groups.

2. 2. The semiconductor device according to claim 1, the protection cell further includes a third MISFET group configured by a plurality of third MISFETs of the first conductivity type; the third MISFET group is electrically connected to the power supply wiring and the ground wiring so as to electrically short-circuit the power supply wiring and the ground wiring, respectively; the third MISFET group outputs a signal to a first gate electrode of each of the plurality of first MISFETs to turn the plurality of first MISFETs into an off state; The first MISFET group is provided between the core region and the third MISFET group.

3. 3. The semiconductor device according to claim 2, the first MISFET group has a rectangular layout shape in plan view; the pair of second MISFET groups are provided along a long side of the first MISFET group, The third MISFET group is provided along a short side of the first MISFET group.

4. 4. The semiconductor device according to claim 3, the protection cell further includes a detection circuit capable of detecting an ESD current to the power supply line; the detection circuit is electrically connected to the power supply wiring and the ground wiring so as to electrically short-circuit the power supply wiring and the ground wiring, respectively; the detection circuit is electrically connected to a second gate electrode of each of the plurality of second MISFETs and a third gate electrode of each of the plurality of third MISFETs; The semiconductor device, wherein the detection circuit is provided along the short side of the first MISFET group.

5. 5. The semiconductor device according to claim 4, the third MISFET group is provided between the first MISFET group and the detection circuit, the detection circuit is provided along the short side of the first MISFET group via the third MISFET group.

6. 6. The semiconductor device according to claim 5, further comprising a plurality of first wirings used to connect the first MISFET group, the second MISFET group, the third MISFET group, and the detection circuit; the power supply wiring and the ground wiring are formed in a wiring layer above the plurality of first wirings, and are provided in the outer periphery region so as to overlap the protection cell in a plan view; a thickness of each of the power supply wiring and the ground wiring is greater than a thickness of each of the plurality of first wirings;

7. 2. The semiconductor device according to claim 1, the first gate electrode of each of the plurality of first MISFETs extends in a first direction in plan view.

8. 8. The semiconductor device according to claim 7, a channel region of each of the plurality of first MISFETs is three-dimensionally covered by the first gate electrode of each of the plurality of first MISFETs.

9. 9. The semiconductor device according to claim 8, a semiconductor substrate; a plurality of protrusions that are part of the semiconductor substrate, extend in a second direction intersecting the first direction in a plan view, and are spaced apart from each other in the first direction; an isolation portion formed on the semiconductor substrate and positioned between the plurality of protrusions; and the position of the upper surface of the element isolation portion is lower than the position of the upper surface of the protrusion portion; the first gate electrode is formed to cover the top surface and both side surfaces of at least one of the plurality of protruding portions.

10. 8. The semiconductor device according to claim 7, a first side along the first direction; a second side extending along a second direction intersecting the first direction in a plan view; a plurality of said protection cells; Further provided with the first side and the second side constitute an outer edge of the outer periphery region, the plurality of protection cells include a first protection cell provided between the first side and the core region, and a second protection cell provided between the second side and the core region, the first MISFET group has a rectangular layout shape in plan view; a long side of the first MISFET group of the first protection cell is aligned along the second direction; a long side of the first MISFET group of the second protection cell extending along the first direction;

11. 11. The semiconductor device according to claim 10, a plurality of the first protection cells are provided between the first side and the core region; a plurality of the second protection cells are provided between the second side and the core region.

12. 11. The semiconductor device according to claim 10, A plurality of the power supply wirings; A plurality of the ground wirings; Further provided with a first power supply wiring among the plurality of power supply wirings supplies a power supply potential to the plurality of circuits provided in the core region; a first ground wiring among the plurality of ground wirings supplies a ground potential to the plurality of circuits provided in the core region; the first MISFET group and the pair of second MISFET groups of the first protection cell are electrically connected to the first power supply wiring and the first ground wiring, respectively, so as to electrically short-circuit the first power supply wiring and the first ground wiring; the first MISFET group and the pair of second MISFET groups of the second protection cell are electrically connected to the first power supply wiring and the first ground wiring, respectively, so as to electrically short-circuit the first power supply wiring and the first ground wiring.

13. 13. The semiconductor device according to claim 12, a plurality of I / O signal cells provided in the peripheral region; the plurality of protection cells further include a third protection cell provided between the first side and the first protection cell, and a fourth protection cell provided between the second side and the second protection cell, a long side of the first MISFET group of the third protection cell is aligned along the first direction, a long side of the first MISFET group of the fourth protection cell is aligned along the second direction; a second power supply wiring among the plurality of power supply wirings supplies a power supply potential to the plurality of I / O signal cells; a second ground wiring among the plurality of ground wirings supplies a ground potential to the plurality of I / O signal cells; the first MISFET group and the pair of second MISFET groups of the third protection cell are electrically connected to the second power supply wiring and the second ground wiring, respectively, so as to electrically short-circuit the second power supply wiring and the second ground wiring; the first MISFET group and the pair of second MISFET groups of the fourth protection cell are electrically connected to the second power supply wiring and the second ground wiring, respectively, so as to electrically short-circuit the second power supply wiring and the second ground wiring.

14. 14. The semiconductor device according to claim 13, a gate insulating film thickness of each of the plurality of first MISFETs and the plurality of second MISFETs included in the third protection cell and the fourth protection cell is thicker than a gate insulating film thickness of each of the plurality of first MISFETs and the plurality of second MISFETs included in the first protection cell and the second protection cell.

15. 8. The semiconductor device according to claim 7, a first side along the first direction; a second side extending along a second direction intersecting the first direction in a plan view; a plurality of said protection cells; a first I / O signal cell provided in the outer periphery region and between the first side and the core region; a second I / O signal cell provided in the outer periphery region and between the second side and the core region; Further provided with the first side and the second side constitute an outer edge of the outer periphery region, the plurality of protection cells include a third protection cell provided between the first side and the first I / O signal cell, and a fourth protection cell provided between the second side and the second I / O signal cell; the first MISFET group has a rectangular layout shape in plan view; a long side of the first MISFET group of the third protection cell is aligned along the first direction, a long side of the first MISFET group of the fourth protection cell extending along the second direction.

16. 16. The semiconductor device according to claim 15, A plurality of the power supply wirings; A plurality of the ground wirings; Further provided with a second power supply wiring among the plurality of power supply wirings supplies a power supply potential to the first I / O signal cell and the second I / O signal cell; a second ground wiring among the plurality of ground wirings supplies a ground potential to the first I / O signal cell and the second I / O signal cell; the first MISFET group and the pair of second MISFET groups of the third protection cell are electrically connected to the second power supply wiring and the second ground wiring, respectively, so as to electrically short-circuit the second power supply wiring and the second ground wiring; the first MISFET group and the pair of second MISFET groups of the fourth protection cell are electrically connected to the second power supply wiring and the second ground wiring, respectively, so as to electrically short-circuit the second power supply wiring and the second ground wiring.

17. Analog IP and a protection cell that is provided adjacent to the analog IP and that constitutes an ESD protection circuit; a power supply wiring for supplying a power supply potential to the analog IP; a ground wiring for supplying a ground potential to the analog IP; Equipped with the protection cell has a first MISFET group constituted by a plurality of first MISFETs of a first conductivity type, and a pair of second MISFET groups constituted by a plurality of second MISFETs of a second conductivity type opposite to the first conductivity type, the first MISFET group and the pair of second MISFET groups are electrically connected to the power supply wiring and the ground wiring, respectively, so as to electrically short-circuit the power supply wiring and the ground wiring; the pair of second MISFET groups outputs a signal to a first gate electrode of each of the plurality of first MISFETs to turn on the plurality of first MISFETs; The semiconductor device, wherein the first MISFET group is provided between the pair of second MISFET groups.

18. 18. The semiconductor device according to claim 17, the protection cell further includes a third MISFET group configured by a plurality of third MISFETs of the first conductivity type; the third MISFET group is electrically connected to the power supply wiring and the ground wiring so as to electrically short-circuit the power supply wiring and the ground wiring, respectively; the third MISFET group outputs a signal to a first gate electrode of each of the plurality of first MISFETs to turn the plurality of first MISFETs into an off state; the first MISFET group has a rectangular layout shape in plan view; the pair of second MISFET groups are provided along a long side of the first MISFET group, The third MISFET group is provided along a short side of the first MISFET group.

19. 19. The semiconductor device according to claim 18, the protection cell further includes a detection circuit capable of detecting an ESD current to the power supply line; the detection circuit is electrically connected to the power supply wiring and the ground wiring so as to electrically short-circuit the power supply wiring and the ground wiring, respectively; the detection circuit is electrically connected to a second gate electrode of each of the plurality of second MISFETs and a third gate electrode of each of the plurality of third MISFETs; The semiconductor device, wherein the detection circuit is provided along the short side of the first MISFET group.

20. 20. The semiconductor device according to claim 19, further comprising a plurality of first wirings used to connect the first MISFET group, the second MISFET group, the third MISFET group, and the detection circuit; the power supply wiring and the ground wiring are formed in a wiring layer above the plurality of first wirings so as to overlap the analog IP and the protection cell in a plan view; a thickness of each of the power supply wiring and the ground wiring is greater than a thickness of each of the plurality of first wirings;

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