Display device and array substrate

Abstract

To prevent occurrence of disconnection in a display device and an array substrate.SOLUTION: A display device comprises: a display part; and an inspection part having first wiring 41 including a first line L1 extending in an X direction and a second line obliquely intersecting the first line L1 and second wiring 42 provided in an upper layer of the first wiring 41 and including, in a planar view, a third line L31 orthogonal to the first line L1, and performing display inspection of the display part. The second line L2 includes: a connection part L22 connected to the first line L1 by obliquely intersecting it; a first part L21 arranged from one end of the connection part L22 so as to be aligned with the third line L31; and a second part L23 arranged from the other end in a direction opposite to the first part L21 so as to be aligned with the third line L31. A widened portion C1 of the third line L31, which becomes wider toward the connection part L22 side, is located, in the planar view, at an intersection PA1 where the third line L31 and the first line L1 intersect each other.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a display device and an array substrate. [Background technology]

[0002] Japanese Patent Application Laid-Open No. 2001-67020 (Patent Document 1) describes a matrix array substrate in which the lower layer signal line wiring is made sufficiently wide at the intersections between the signal lines and the scanning lines to absorb variations in the outline positions of the upper layer signal line wiring, thereby preventing short circuits from occurring between the upper layer signal line wiring and the scanning lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-67020 Summary of the Invention [Problem to be solved by the invention]

[0004] In display devices and array substrates, it is desirable to prevent the occurrence of disconnections. [Means for solving the problem]

[0005] A display device according to one embodiment includes a display unit, first wiring including first lines extending in a first direction and second lines diagonally intersecting the first lines, and an inspection unit configured to inspect the display of the display unit. The first wiring is disposed above the first wiring and includes third lines that, in a plan view, are perpendicular to the first lines extending in the first direction. The second lines include a connection portion that diagonally intersects the first lines, a first portion extending from one end of the connection portion to the third line, and a second portion extending from the other end of the connection portion to the third line in a direction opposite to the first portion. The third lines include a wide portion that increases in width toward the connection portion. The wide portion is located at an intersection of the third line and the first line in a plan view.

[0006] An array substrate according to one embodiment includes an inspection unit for inspecting display, the inspection unit having first wiring including a first line extending in a first direction and a second line diagonally intersecting the first line, and second wiring provided in a layer above the first wiring and including a third line perpendicular to the first line extending in the first direction in a plan view. The second line includes a connection portion diagonally intersecting the first line, a first portion extending from one end of the connection portion to be aligned with the third line, and a second portion extending from the other end of the connection portion to be aligned with the third line in a direction opposite to the first portion. The third line includes a wide portion whose width increases toward the connection portion. The wide portion is located at the intersection of the third line and the first line in a plan view. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing a schematic configuration example of a liquid crystal display device. [Figure 2] FIG. 2 is a view showing a part of the cross section taken along the line AA in FIG. [Figure 3] FIG. 3 is an enlarged plan view of the vicinity of the terminal area. [Figure 4] FIG. 4 is a view showing a cross section taken along the line BB in FIG. [Figure 5]FIG. 5 is a diagram showing an equivalent circuit corresponding to FIG. [Figure 6] FIG. 6 is a schematic plan view showing a part of an example structure of the inspection circuit. [Figure 7] FIG. 7 is a view showing a cross section taken along line CC in FIG. [Figure 8] FIG. 8 is a diagram for explaining the structure around the connection portion of the first wiring and the second wiring. [Figure 9] FIG. 9 is a schematic plan view showing an example of the structure of an inspection circuit of a comparative example. [Figure 10] FIG. 10 is a view showing a cross section taken along the line DD in FIG. [Figure 11] FIG. 11 is a schematic plan view showing a modified example of the inspection circuit. [Figure 12] FIG. 12 is a diagram showing a modified example of the first wiring. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings.

[0009] It should be noted that the present disclosure is merely an example, and any modifications that a person skilled in the art can easily conceive of while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure.

[0010] In addition, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but this is merely an example and does not limit the interpretation of the present disclosure. In this specification and each drawing, elements similar to elements shown in previous drawings may be assigned the same reference numerals, and detailed explanations may be omitted as appropriate.

[0011] In the present embodiment, a liquid crystal display device having a liquid crystal display element is disclosed as an example of a display device. However, the embodiment does not preclude application of the technical ideas disclosed in the embodiment to display devices having other types of display elements, such as organic electroluminescence display elements, micro LEDs, or mini LEDs. Furthermore, the technical ideas disclosed in the embodiment can also be applied to array substrates and electronic devices having sensor elements, such as capacitance sensors and optical sensors.

[0012] <Overall configuration of liquid crystal display device> FIG. 1 is a plan view showing a schematic configuration example of a liquid crystal display device 1. As shown in FIG.

[0013] As shown in Figure 1, the X, Y, and Z directions are defined. The X, Y, and Z directions are perpendicular to each other, but may intersect at an angle other than a perpendicular angle. Viewing the liquid crystal display device 1 or its components parallel to the Z direction is called a "planar view." The direction indicated by the Z arrow is sometimes called "upward," and the opposite direction is sometimes called "downward."

[0014] As shown in FIG. 1, the liquid crystal display device 1 includes a TFT substrate 100 (array substrate, second substrate) and a counter substrate 200 (first substrate). In the liquid crystal display device 1, the TFT substrate 100 and the counter substrate 200 are arranged to overlap each other. In a plan view, the counter substrate 200 has a first rectangular shape, and the TFT substrate 100 has a second rectangular shape. The long sides of the TFT substrate 100 and the counter substrate 200 are aligned in the Y direction, and the short sides are aligned in the X direction. The length of the TFT substrate 100 in the Y direction is longer than the length of the counter substrate 200. In other words, in a plan view, three of the four sides of the rectangular shape of the TFT substrate 100 are aligned, and one side protrudes from one side of the counter substrate 200. The TFT substrate 100 and the counter substrate 200 are bonded together by a sealant 150 provided around the periphery of the counter substrate 200, and liquid crystal is sealed inside. A display region 20 is formed in the region surrounded by the sealant 150 and where the liquid crystal is sealed. In the display region 20, scanning lines 11 extend in the horizontal X direction and are arranged in the Y direction. In addition, in the display region 20, video signal lines 12 extend in the Y direction and are arranged in the X direction. Areas surrounded by the scanning lines 11 and the video signal lines 12 form pixels 13.

[0015] A terminal region 30 is formed in a portion where the TFT substrate 100 protrudes from the counter substrate 200. A flexible wiring substrate 500 is connected to the terminal region 30. Power, scanning signals, video signals, clock signals, etc. are supplied from the flexible wiring substrate 500 to the display region 20. The display region 20 and the flexible wiring substrate 500 are connected by second wiring 42, the details of which will be described later. Since the flexible wiring substrate 500 is connected to the terminal region 30 in this way, the area of the terminal region 30 can be reduced, and the frame can also be made smaller. A driver IC (not shown) is mounted on the flexible wiring substrate 500.

[0016] FIG. 2 is a view showing a part of the cross section taken along the line AA in FIG. The display region 20 and the terminal region 30 are formed at the same time. Therefore, the cross sections of the display region 20 and the terminal region 30 have similar configurations. An example of the basic layer configuration of the display region 20 will be described using FIG. 2. The display region 20 and the terminal region 30 are formed by the same process. The cross section of the display region 20 shown in FIG. 2 is for a liquid crystal display device 1 that is an IPS (In Plane Switching) type.

[0017] 2, the TFT substrate 100 is generally made of glass, but if a flexible display device is desired, the TFT substrate 100 is made of a resin such as polyimide. An underlayer 101 made of a laminated film of silicon oxide (SiO) and silicon nitride (SiN) is formed on the TFT substrate 100. The role of the underlayer 101 is to prevent impurities from the TFT substrate 100 from contaminating the semiconductor layer 102.

[0018] A semiconductor layer 102 is formed on an underlayer 101. The semiconductor layer 102 is made of polycrystalline silicon (poly-Si). Because poly-Si has high mobility, peripheral circuits such as a scanning line driving circuit can be formed simultaneously. The semiconductor layer 102 is not limited to polycrystalline silicon. For example, amorphous silicon (a-Si) or an oxide semiconductor such as IGZO (Indium Gallium Zinc Oxide) may also be used as the semiconductor layer 102. In addition, semiconductor layers SC1 and SC2 (see FIG. 6) of the inspection circuit 40 in the terminal region 30, which will be described later, are also formed simultaneously using the semiconductor layer 102.

[0019] A gate insulating film 103 is formed to cover the semiconductor layer 102. The gate insulating film 103 is, for example, a SiO film formed by CVD using TEOS (tetraethoxysilane) as a raw material. A gate electrode 104 is formed on the gate insulating film 103. The gate electrode 104 is formed of, for example, MoW or the like, and is formed simultaneously with the above-mentioned scanning line 11 (see FIG. 1). In addition, a portion of the terminal wiring (signal terminal 31 and inspection terminal 32 described later) in the terminal region 30 is also formed simultaneously with the gate electrode 104 using the same material. In addition, like the gate electrode 104, the first wiring 41 of the inspection circuit 40 in the terminal region 30 described later is also formed using the same material and in the same process as the scanning line 11. In this way, the metal layer formed using the same material and in the same process as the scanning line 11 is referred to as the gate layer.

[0020] After patterning the gate electrode 104, ion implantation of phosphorus (P), boron (B), or the like is performed to impart conductivity to the semiconductor layer 102 except for the area below the gate electrode 104. In the semiconductor layer 102, the area directly below the gate electrode 104 becomes a channel portion, and the other areas become a drain region 1021 or a source region 1022.

[0021] Thereafter, the interlayer insulating film 105 is formed. The interlayer insulating film 105 is formed of SiO, SiN, or a laminated film of SiO and SiN. Through holes 120 and 121 are formed in the interlayer insulating film 105 and the gate insulating film 103, enabling connection between the drain electrode 106 and the drain region 1021 and connection between the source electrode 107 and the source region 1022. In this embodiment, the drain electrode 106, the source electrode 107, and the video signal line 12 (not shown in FIG. 2) are formed simultaneously. In addition, a portion of the terminal wiring, such as a third line (see FIG. 6) described later in the terminal region 30, is also formed simultaneously with the drain electrode 106, etc. In this way, the metal layer formed with the same material and in the same process as the video signal line 12 is referred to as the drain layer. The drain electrode 106 and the source electrode 107 are formed, for example, from a material in which aluminum (Al) or an aluminum alloy is sandwiched between titanium (Ti), or from a material in which aluminum is sandwiched between MoW or the like.

[0022] An organic passivation film 108 is formed from a transparent resin such as acrylic to cover the drain electrode 106 and the source electrode 107. The organic passivation film 108 is formed to a thickness of 2 μm to 4 μm. This allows the organic passivation film 108 to function as a planarizing film. A through-hole 130 is formed in the organic passivation film 108, allowing connection between the source electrode 107 and a pixel electrode 111, which will be described later.

[0023] A common electrode 109 is formed on the organic passivation film 108 using a transparent conductive oxide film such as ITO (Indium Tin Oxide). The common electrode 109 is formed in common to each pixel. A capacitive insulating film 110 made of SiN is formed to cover the common electrode 109. A pixel electrode 111 is formed on the capacitive insulating film 110 using a transparent conductive oxide film such as ITO. The ITO constituting the common electrode 109 or pixel electrode 111 forms a terminal wiring or a part of a terminal in the terminal region 30.

[0024] An alignment film 112 is formed to cover the pixel electrodes 111. This is to initially align the liquid crystal molecules 301. The pixel electrodes 111 are formed in a stripe or comb shape. When a signal voltage is applied to the pixel electrodes 111, electric lines of force are generated between the pixel electrodes 111 and the common electrode 109, which is formed flat underneath, as shown by the arrows in Figure 2, causing the liquid crystal molecules 301 to rotate, thereby controlling the amount of light passing through the liquid crystal layer 300.

[0025] As shown in FIG. 2, a counter substrate 200 is disposed above a liquid crystal layer 300. The counter substrate 200 is generally made of glass, but if a flexible display device is desired, the counter substrate 200 is made of a resin such as polyimide. A color filter 201 and a black matrix 202 are formed below the counter substrate 200. An overcoat film 203 is formed below the color filter 201 and the black matrix 202, covering the color filter 201 and the black matrix 202. A columnar spacer 210 is formed below the overcoat film 203. The columnar spacer 210 maintains a constant distance between the TFT substrate 100 and the counter substrate 200. An alignment film 204 is formed to cover the underside of the overcoat film 203.

[0026] 3 is an enlarged plan view of the vicinity of the terminal region 30. As shown in Fig. 3, the peripheries of the TFT substrate 100 and the counter substrate 200 are bonded together with a sealant 150. The display region 20 is formed inside the area surrounded by the sealant 150. In the terminal region 30, signal terminals 31 (see Fig. 4, etc.) for connection to the flexible wiring substrate 500 and inspection terminals 32 for inspecting the display region 20 are formed.

[0027] In the display area 20, video signal lines 12 extend in the Y direction. There are a large number of video signal lines 12. Therefore, a selection circuit 60 is provided to reduce the number of wires in the terminal area 30. The selection circuit 60 is a switching circuit formed of TFTs. For example, by configuring the selection circuit 60 so that it can select one of the red, green, and blue pixels within one frame and transmit a signal sequentially, the number of wires can be reduced to one-third.

[0028] The wiring from the selection circuit 60 passes through the diagonal wiring region 50 and is connected to the inspection circuit 40. The inspection circuit 40 is also a switching circuit made up of many TFTs. The inspection circuit 40 switches so that the signal from the signal terminal 31 or the inspection terminal 32 can be connected to each wiring in the diagonal wiring region 50. The inspection process is performed using the inspection terminal 32 before the flexible wiring substrate 500 is connected.

[0029] In this embodiment, as shown in Fig. 3, the inspection circuit 40 is covered by the counter substrate 200. Therefore, the inspection circuit 40, which has many TFTs, is protected by the counter substrate 200 and the sealant 150. The diagonal wiring region 50 extends to the terminal region 30 via the inspection circuit 40 and connects to signal terminals 31 (see Fig. 4, etc.) formed in the terminal region 30. A flexible wiring substrate 500 is connected to the signal terminals 31. In Fig. 3, the driver IC is not mounted in the terminal region 30 but is mounted on the flexible wiring substrate 500.

[0030] When the driver IC is mounted on the terminal area 30 of the TFT substrate 100, it is called COG (Chip On Glass), and when the driver IC is mounted on the flexible wiring substrate 500, it is called COF (Chip On Film). The video signals supplied to each video signal line 12 are arranged by the driver IC. That is, the driver IC converts video signals supplied serially from the outside into parallel signals and supplies the converted video signals to the display area 20 of the liquid crystal display device 1. Therefore, in the case of a COF such as the liquid crystal display device 1 of this embodiment, the number of terminals is significantly greater than in the case of a COG. For example, while the number of terminals in the case of a COG is approximately 300, in the case of a COF, the number of terminals becomes approximately 1500 to 1800, which is 5 to 6 times that number.

[0031] Fig. 4 is a diagram showing the cross section BB of Fig. 3. As shown in Fig. 4, the peripheries of the TFT substrate 100 and the counter substrate 200 are bonded together with a sealant 150. Liquid crystal is sealed in a liquid crystal layer 300 surrounded by the TFT substrate 100, the counter substrate 200, and the sealant 150. On the TFT substrate 100 side, video signal lines 12, selection circuits 60, diagonal wiring regions 50, inspection circuits 40, second wiring 42, and signal terminals 31 are formed.

[0032] 4, the video signal lines 12, the selection circuit 60, the diagonal wiring region 50, the inspection circuit 40, and a portion of the second wiring 42 are covered with an organic passivation film 108 and further protected by a sealant 150 and an opposing substrate 200 provided on the sealant 150. Since the inspection circuit 40 is provided and protected under the sealant 150, the reliability of the inspection circuit 40 can be ensured. On the TFT substrate 100, the second wiring 42 extends from the inspection circuit 40 toward the signal terminal 31. In the Z direction, the signal terminal 31 is connected to the flexible wiring substrate 500 via an anisotropic conductive film (ACF) 501. The second wiring 42 may be covered by a capacitive insulating film 110 made of SiN or the organic passivation film 108, as shown in FIG. 2, or may be exposed.

[0033] FIG. 5 is a diagram showing an equivalent circuit corresponding to FIG. 3. For convenience of explanation, FIG. 5 shows only a part of the equivalent circuit. As shown in FIG. 5, video signal lines 12 extend in the Y direction from a selection circuit 60 on the display area 20 side. The selection circuit 60 has many switches 61 made of TFTs. As described above, the selection circuit 60 is configured to transmit a signal three times during one frame, which makes it possible to reduce the number of wires on the terminal area 30 side of the selection circuit 60 to one-third.

[0034] The diagonal wiring region 50 connects the selection circuit 60 and the inspection circuit 40. For example, by reducing the number of wires on the terminal region 30 side of the selection circuit 60 to one-third, the pitch of the signal terminals 31 can be made smaller than the wire pitch in the selection circuit 60. Therefore, diagonal wiring 51 is formed between the selection circuit 60 and the inspection circuit 40. Compared to when the wires extend in the Y direction, the wire pitch in the diagonal wiring 51 area is smaller. As a result, it is difficult to ensure wire spacing in the diagonal wiring 51 area. For this reason, the wiring in the diagonal wiring 51 area is multilayered. That is, in the diagonal wiring region 50, through holes 90 and 91 are formed in every other diagonal wiring 51, and the wiring is transferred, for example, from the drain layer to the gate layer.

[0035] The inspection circuit 40 is a circuit that inspects a large number of wirings for breaks and shorts. In the diagonal wiring area 50, a plurality of diagonal wirings 51 extending from each switch 61 in the selection circuit 60 are arranged. In the inspection circuit 40, an inspection switch 40a is provided for each diagonal wiring 51. The inspection switch 40a is a switch that switches so that the diagonal wiring 51 is connected to either the first wiring 41 or the second wiring 42. The first wiring 41 is connected to an inspection terminal 32 that is used during inspection performed before the flexible wiring substrate 500 is connected. The second wiring 42 is connected to a signal terminal 31 to which the flexible wiring substrate 500 is connected.

[0036] 3, a plurality of test terminals 32 are provided on the left and right of the group of signal terminals 31. The first wirings 41 connected to these test terminals 32 extend in the X direction and are arranged in the Y direction in the test circuit 40. The diagonal wirings 51 in the diagonal wiring area 50 are connected to any of the first wirings 41 via the test switches 40a. When testing, the inputs to the test terminals 32 are switched sequentially to test for breaks and the like in the diagonal wirings 51 and the video signal lines 12 beyond them.

[0037] 3 to 5, in the inspection process during manufacturing of the liquid crystal display device 1, it is possible to inspect for breaks, short circuits, etc. in the wiring extending from the inspection circuit 40 to the display area 20 side.

[0038] <Test circuit structure> Next, the structure of the inspection circuit 40 will be described with reference to Figs. 6 to 8. Fig. 6 is a schematic plan view showing a part of an example structure of the inspection circuit 40. Fig. 7 is a view showing a cross section taken along CC in Fig. 6. Fig. 8 is a view for explaining the structure around the connection portion L22 of the first wiring 41 and the second wiring 42 included in the inspection circuit 40.

[0039] As shown in FIG. 6, the inspection circuit 40 includes a first wiring 41 and a second wiring 42. The first wiring includes a first line L1 extending in a first direction, which in this embodiment is the X direction, and a second line L2 diagonally intersecting the first line L1. The second wiring 42 is provided in a layer above the first wiring 41 and includes third lines L31, L32, L33, and L34 that intersect perpendicularly with the first line L1 extending in the X direction in a plan view. The second wiring 42 further includes third lines L35 and L36. The third line L35 (51) is arranged alongside the third line L34 in the X direction and is arranged above the first line L1 shown in FIG. 6 to extend in the Y direction. Therefore, the third line L35 is arranged across the second line L2 from the third line L34 closest to the connection portion L22, and does not intersect with the first line L1 in a plan view. The third line L36 is arranged alongside the third line L31 in the X direction, and is arranged to extend in the Y direction below the first line L1 shown in Fig. 6. Therefore, the third line L36 is arranged across the second line L2 from the third line L31 closest to the connection portion L22, and does not intersect with the first line L1 in a plan view.

[0040] The test circuit 40 is a transistor including semiconductor layers SC1 and SC2. The semiconductor layer SC1 is disposed below the third line L34 and the third line L35. In a plan view, the semiconductor layer SC1 overlaps with a portion of the third line L34, a portion of the third line L35, and a portion of the second line L2. In a plan view, a contact hole 71 is provided in the portion of the third line L34 that overlaps with the semiconductor layer SC1. In a plan view, a contact hole 72 is provided in the portion of the third line L35 that overlaps with the semiconductor layer SC1.

[0041] Furthermore, the semiconductor layer SC2 is disposed below the third line L31 and the third line L36. In a plan view, the semiconductor layer SC2 overlaps with part of the third line L31, part of the third line L36, and part of the second line L2. In a plan view, a contact hole 81 is provided in the part of the third line L31 that overlaps with the semiconductor layer SC2. In a plan view, a contact hole 82 is provided in the part of the third line L36 that overlaps with the semiconductor layer SC2.

[0042] 6, in the inspection circuit 40, the third line L34 is connected to the source layer of the semiconductor layer SC1 via a contact hole 71, the third line L35 is connected to the drain layer of the semiconductor layer SC1 via a contact hole 72, the third line L36 is connected to the source layer of the semiconductor layer SC2 via a contact hole 82, and the third line L31 is connected to the drain layer of the semiconductor layer SC2 via a contact hole 81. The second line L2 serves as the gate layer for each of the semiconductor layers SC1 and SC2. The first line L1 is connected to an inspection terminal 32 that performs a display inspection of the display area 20.

[0043] The second line L2 includes a connection portion L22 that connects to the first line L1 at an oblique angle, a first portion L21 that extends from one end of the connection portion L22 to the third line L34, and a second portion L23 that extends from the other end of the connection portion L22 to the third line L31. The longitudinal direction of the connection portion L22 intersects with the extension direction of the first line L1 at a predetermined angle. In this embodiment, in a plan view, the extension directions of the first portion L21 and the second portion L23 of the second line L2 are parallel to the extension directions of the third lines L34 and L31, respectively. The intersection point CP between the center line of the first line L1 and the center line of the connection portion L22 of the second line L2 is shown.

[0044] In this embodiment, of the multiple third lines, four third lines L31, L32, L33, and L34 are shown as examples, and other third lines unnecessary for the explanation are omitted from the illustrations. The third lines L31, L32, L33, and L34 are arranged parallel to the X direction and extend in the Y direction. The third lines L31, L32, and L33 are arranged to the right of the second line L2. The third line L31 is arranged closest to the second line L2, followed by the third lines L32 and L33. The third line L34 is arranged to the left of the second line L2 and closest to the second line L2. Although not shown in the illustrations, a third line without a wide portion, which will be described later, is also arranged to the left of the third line L34. The third lines not shown in the figure have a configuration similar to that of the third lines L32 and L33, and are arranged on the left side of the third line L34.

[0045] The two third lines L31 and L34, which are arranged on either side of the intersection point CP, each include a wide portion C1 and a wide portion C2. More specifically, the third line L31 includes a wide portion C1 at the intersection with the first line L1 in a plan view, the wide portion C1 increasing in width toward the connection portion L22. For example, if the width of the portion of the third line L31 other than the wide portion C1 in the X direction is width W31, the width of the wide portion C1 is width W32 (>W31). In other words, the wide portion C1 protrudes toward the intersection point CP by a distance D1. Furthermore, if the width of the portion other than the wide portion C1 in the Y direction is width W11, the width of the wide portion C1 is width W12 (>W11). Thus, the wide portion C1 is wider than the width of the other portions of the third line L31 in both the X and Y directions. The wide portion C2 of the third line L34 has the same configuration as the wide portion C1 except that it is arranged to face the wide portion C1, and therefore detailed description thereof will be omitted. The two wide portions C1 and C2 are arranged to face each other with the connection portion L22 in between.

[0046] Only the third line L31 closest to the connection portion L22 includes the wide portion C1, and only the third line L34 closest to the connection portion L22 includes the wide portion C2. In other words, the third lines L32, L33, etc. that are not adjacent to the connection portion L22 do not have wide portions at the portions where they intersect with the first line L1.

[0047] As shown in FIG. 8 , the first wiring 41 is configured such that the first line L1 and the second line L2 are connected by a connection portion L22. Therefore, in a plan view, the first wiring 41 has a triangular recess P1 formed at a portion where the connection portion L22 of the second line L2 intersects with the first line L1. The recess P1 is provided closer to the intersection point CP than the distance D2 between the second portion L23 of the second line L2 and the first line L1. In other words, the recess P1 is located farther from the intersection point PA1 than the distance D2 between the second portion L23 of the second line L2 and the third line L31. The intersection point PA1 is the portion where the first line L1 and the third line L31 intersect in a plan view. Therefore, the portion where the first line L1 and the connection portion L22 intersect, including the intersection point CP, is located at a distance D2 or more from the intersection point PA1. This suppresses the influence of the connection portion L22 on the intersection point PA1. That is, in the first wiring 41, the occurrence of variations in the shape of the first lines L1 can be suppressed.

[0048] As shown in FIG. 7, the shape of the first line L1 is consistent. In the shape of the first line L1, for example, the side surfaces SI1 and SI2 are symmetrical with respect to the center line VL. Furthermore, the side surfaces SI1 and SI2 each have a low angle with respect to the bottom surface B1. That is, the shape of the first line L1 is a low tapered shape that gradually widens downward. This facilitates the formation of the gate insulating film 103 on the first line L1 without variation. Furthermore, the third line L31 on the gate insulating film 103 without variation. Therefore, the liquid crystal display device 1 can prevent breaks in the third line L31.

[0049] Furthermore, for example, if variations in the shape of the first line L1 occur due to some reason in the manufacturing process, the shape of the gate insulating film 103 formed on the first line L1 may also vary. Even in such a case, the third line L31 has a wide portion C1. That is, for example, when the third line L31 is formed from the bottom to the top in FIG. 8 along the Y direction, the width of the third line L31 widens before and after the intersection PA1, that is, from slightly before reaching the first line L1 to slightly after passing the first line L1. In this embodiment, the width of the third line L31 changes from width W31 to width W32 (>W31). Having the wide portion C1 in this way improves the likelihood of the third line L31 becoming disconnected. Therefore, the liquid crystal display device 1 can prevent the third line L31 from becoming disconnected.

[0050] <Structure and Comparison of Inspection Circuits of Comparative Examples> Next, a structural example of an inspection circuit of a comparative example will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a schematic plan view showing a structural example of an inspection circuit of a comparative example. Fig. 10 is a view showing a cross section taken along line DD of Fig. 9. In Fig. 9, semiconductor layers SC1 and SC2, a plurality of third lines, and other elements not necessary for the explanation are omitted.

[0051] <<Inspection circuit structure of comparative example>> As shown in FIG. 9, the inspection circuit 40A includes a first wiring 41A and a second wiring 42A. The first wiring 41A includes a first line L1A, a first portion L21A, and a second portion L23A. The first line L1A extends in the X direction. One end of the first portion L21A is connected to the first line L1A. The first portion L21A extends upward in the Y direction from the position where it is connected to the first line L1A. The second portion L23A is disposed a predetermined distance away from the first portion L21A in the X direction. One end of the second portion L23A is connected to the first line L1A. The second portion L23A extends downward in the Y direction from the position where it is connected to the first line L1A. In the first line L1A, the portion where the first portion L21A and the second portion L23A are connected and the portion between them are referred to as a connection portion L22A.

[0052] The second wiring 42A has third lines L31A, L32A, L33A, and L34A. The third lines L31A, L32A, L33A, and L34A are arranged side by side in parallel to the X direction so as to extend in the Y direction. The third lines L31A, L32A, and L33A are provided on the right side of the second portion L23A. The third line L31A is arranged closest to the second portion L23A, followed by the third lines L32A and L33A. The third line L34A is arranged on the left side of the first portion L21A.

[0053] <<Comparison with comparative examples>> As shown in region R1, the second portion L23A and the third line L31A are spaced a distance D3 apart in the X direction. However, the inspection circuit 40A shown in FIG. 9 does not have the recess P1 that the inspection circuit 40 of the present embodiment shown in FIG. 8 has. Therefore, compared to the case of FIG. 8, the connection portion L22A and the intersection PA2 are located closer to each other. The intersection PA2 is the portion where the first line L1A and the third line L31A intersect in a plan view. For example, if the distance D3 and the distance D2 of FIG. 8 are the same, the second portion L23A and the third line L31A are closer to each other by the recess P1 of the present embodiment. Therefore, when the third line L31A is formed, the intersection PA2 may be affected by the connection portion L22A, resulting in variations in the shape of the formed third line L31A.

[0054] For example, as shown in FIG. 10, variations occur in the shape of the third line L31A. The side surface SI3 forms a low angle with respect to the bottom surface B2, while the side surface SI4 forms a high angle with respect to the bottom surface B2. This also causes variations in the shape of the gate insulating film 103 formed on the first line L1A. For example, in the gate insulating film 103, the side surface SI5 formed on the side surface SI3 forms a low angle with respect to the bottom surface B2, while the side surface SI6 formed on the side surface SI4 forms a high angle with respect to the bottom surface B2. In other words, the gate insulating film 103 has a low tapered shape on the left side of FIG. 10, but a high tapered shape on the right side. When the gate insulating film 103 is formed with a high tapered shape, for example, deterioration in the adhesion of the third line L31A may cause a break in the third line L31A formed on the gate insulating film 103.

[0055] For example, when the third line L31A is formed, a gap S occurs in the third line L31A above a highly tapered portion of the gate insulating film 103. In this case, the third line L31A is divided into a third line L31A1 portion and a third line L31A2 portion, causing a break in the third line L31A. Similarly, if the shape of the first line L1A varies for some reason during the manufacturing process, a break may also occur in the third line L31A.

[0056] In contrast, as shown in FIG. 8, in the liquid crystal display device 1 of this embodiment, the connection portion L22 of the second line L2 intersects with the first line L1, thereby separating the connection portion L22 from the intersection portion PA1. Additionally, the wide portion C1 of the third line L31 closest to the connection portion L22 improves the likelihood of the third line L31. Therefore, the liquid crystal display device 1 can prevent the occurrence of a disconnection in the third line L31 in the inspection circuit 40. The same applies to the third line L34. Furthermore, the wide portion C1 of only the third line L31 closest to the connection portion L22 eliminates the need to increase the pitch between the third lines L31, L32, and L33 of the second wiring 42, thereby preventing the area of the second wiring 42 from expanding in the X direction.

[0057] <Modification of the inspection circuit> FIG. 11 is a schematic plan view showing a modified example of the inspection circuit 40. In FIG. 11, the semiconductor layers SC1 and SC2, the plurality of third lines, and other elements not necessary for the explanation are omitted. As shown in FIG. 11, in the inspection circuit 40, the third line L31 is provided with a wide portion C1, but the third line L34 is not provided with a wide portion C1. The other configurations are the same as those shown in FIG. 8. In this way, the liquid crystal display device 1 may be configured such that the wide portion is provided only on one of the third lines in the inspection circuit 40, the third line facing the connection portion L22.

[0058] <Modification of the first wiring> FIG. 12 illustrates a modified example of the first wiring 41. In FIG. 12, the semiconductor layers SC1 and SC2, the third lines, and other elements not necessary for the explanation are omitted. As illustrated in FIG. 12, the connection portion L22 connecting the first line L1 and the second line L2 is not clearly defined in the first wiring 41, as compared to the case illustrated in FIG. 8 and other figures. That is, in this modification, the connection portion L22 illustrated in FIG. 8 and other figures is provided with a coupling region P2 coupling the first line L1 to the connection portion L22. The coupling region P2 is, for example, a region including a recess P1, and couples the first line L1 to the coupling portion L22. Because the first wiring 41 is formed in this manner, even if variations occur in the shape of the first line L1 at the intersection PA1, the wide portion C1 of the third line L31 allows the liquid crystal display device 1 to prevent disconnection of the third line L31. [Industrial Applicability]

[0059] The present invention can be used in display devices and array substrates. [Explanation of symbols]

[0060] 1 LCD display device 11 scan lines 12 Video signal line 13 pixels 20 Display area 30 terminal area 31 Signal terminal 32 Inspection terminal 40 Inspection circuit 41,41A 1st wiring 42,42A Second wiring 50 Diagonal wiring area 51 Diagonal wiring 60 Selection circuit 71, 72, 81, 82 contact holes 100 TFT substrates 102 Semiconductor layer 103 Gate insulating film 104 gate electrode 111 pixel electrode 150 Sealing material 200 Opposing substrate 300 LCD layer 500 Flexible wiring board B1,B2 Bottom C1, C2 wide part CP intersection D1, D2, D3 distance L1, L1A 1st line L2 Second Line L31~L34, L31A~L34A 3rd line L21,L21A 1st part L22, L22A connection L23,L23A 2nd part P1 recess PA1, PA2 intersection R1 area SC1, SC2 semiconductor layer SI1~SI6 Side W11, W12, W31, W32 width

Claims

1. A display unit; an inspection unit that inspects the display of the display unit, the inspection unit having first wiring including first lines extending in a first direction and second lines diagonally intersecting the first lines, and second wiring including third lines that are provided in a layer above the first wiring and are perpendicular to the first lines extending in the first direction in a plan view; Equipped with the second line includes a connection portion that is connected to the first line so as to diagonally intersect therewith, a first portion that is arranged from one end of the connection portion so as to be aligned with the third line, and a second portion that is arranged from the other end of the connection portion so as to be aligned with the third line in a direction opposite to the first portion, the third line includes a wide portion whose width increases toward the connection portion, the wide portion is located at an intersection where the third line and the first line intersect in a plan view; Display device.

2. In a plan view, a direction in which the first portion of the second line extends and a direction in which the second portion of the second line extends are parallel to a direction in which the third line extends. The display device according to claim 1 .

3. the second wiring includes two of the third lines with the connection portion interposed therebetween, each of the two third lines includes the wide portion; The two wide portions are arranged to face each other with the connection portion therebetween. The display device according to claim 2 .

4. the second wiring includes a plurality of the third lines, the third lines are arranged side by side in the first direction, Only the third line closest to the connection portion includes the wide portion. The display device according to claim 2 .

5. the first line is connected to an inspection terminal for inspecting the display of the display unit; The display device according to claim 4 .

6. a first substrate having a first rectangular shape in a plan view; a second substrate having a second rectangular shape in a plan view, one of four sides of the first rectangular shape being protruding, the first substrate and the second substrate are provided so as to overlap each other, a periphery of the first substrate is bonded to the second substrate via a sealing material; the display unit is formed in an area surrounded by the sealing material, The inspection unit is provided under the sealing material on the second substrate. The display device according to claim 4 .

7. an inspection unit for inspecting a display, the inspection unit having first wiring including first lines extending in a first direction and second lines diagonally intersecting the first lines, and second wiring including third lines provided in a layer above the first wiring and orthogonal to the first lines extending in the first direction in a plan view; the second line includes a connection portion that diagonally intersects the first line, a first portion that is arranged from one end of the connection portion to be aligned with the third line, and a second portion that is arranged from the other end of the connection portion to be aligned with the third line in a direction opposite to the first portion, the third line includes a wide portion whose width increases toward the connection portion, the wide portion is located at an intersection where the third line and the first line intersect in a plan view; Array board.

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