Display device and array substrate

Abstract

To prevent disconnection from occurring to a semiconductor layer.SOLUTION: A liquid crystal display device includes: a semiconductor layer OS; a signal line SE provided on the semiconductor layer OS; an insulation part IP1 provided beside the signal line SE; an insulation part IP2 provided on the insulation part IP1 and the signal line SE; and a protection layer PL provided on the insulation part IP2. In a planar view, a first area AR1 provided with the protection layer PL includes a second area AR2 where the signal line SE is connected to the semiconductor layer OS, and a third area AR3 which is disposed in the surroundings of the second area AR2 and in which the semiconductor layer OS is covered with the insulation part IP1.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a display device and an array substrate. [Background technology]

[0002] Japanese Patent Publication No. 6776060 (Patent Document 1) describes a display device having a switching element including a semiconductor layer and a signal line, with a conductive protective layer provided between the semiconductor layer and the signal line, and the semiconductor layer and the signal line being electrically connected via the protective layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6776060 Summary of the Invention [Problem to be solved by the invention]

[0004] In display devices and array substrates, it is desirable to prevent breaks in the semiconductor layers. [Means for solving the problem]

[0005] A display device according to one embodiment includes a semiconductor layer, a signal line provided on the semiconductor layer, a first insulating portion provided on a side of the signal line, a second insulating portion provided on the first insulating portion and on the signal line, and a protective layer provided on the second insulating portion. In a plan view, a first region in which the protective layer is provided includes a second region in which the signal line is connected to the semiconductor layer, and a third region disposed around the second region and in which the semiconductor layer is covered by the first insulating portion.

[0006] An array substrate according to one embodiment includes a semiconductor layer, a signal line provided on the semiconductor layer, a first insulating portion provided on a side of the signal line, a second insulating portion provided on the first insulating portion and on the signal line, and a protective layer provided on the second insulating portion. In a plan view, a first region in which the protective layer is provided includes a second region in which the signal line is connected to the semiconductor layer, and a third region disposed around the second region, in which the semiconductor layer is covered by the first insulating portion. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an exploded perspective view showing a schematic configuration example of a display device. [Figure 2] FIG. 2 is a plan view showing a schematic configuration of the display panel. [Figure 3] FIG. 3 is a plan view showing an example of a planar layout of sub-pixels. [Figure 4] FIG. 4 is a schematic plan view illustrating a protective layer provided in a subpixel. [Figure 5] FIG. 5 is a schematic cross-sectional view taken along line AA in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line BB in FIG. 4 before the protective layer is formed. [Figure 7] FIG. 7 is a schematic cross-sectional view taken along line BB in FIG. 4 after the protective layer has been formed. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line CC in FIG. [Figure 9] FIG. 9 is a flowchart showing an example of forming a protective layer. [Figure 10] FIG. 10 is a cross-sectional view showing an example of the configuration of a display device of a comparative example. [Figure 11] FIG. 11 is a plan view schematically showing another example of the protective layer. [Figure 12] FIG. 12 is a plan view schematically showing another example of the protective layer. [Figure 13] FIG. 13 is a plan view schematically showing another example of the protective layer. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings.

[0009] It should be noted that the present disclosure is merely an example, and any modifications that a person skilled in the art can easily conceive of while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure.

[0010] In addition, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but this is merely an example and does not limit the interpretation of the present disclosure. In this specification and each drawing, elements similar to elements shown in previous drawings may be assigned the same reference numerals, and detailed explanations may be omitted as appropriate.

[0011] In the present embodiment, a liquid crystal display device having a liquid crystal display element is disclosed as an example of a display device. However, the embodiment does not preclude application of the technical ideas disclosed in the embodiment to display devices having other types of display elements, such as organic electroluminescence display elements, micro LEDs, or mini LEDs. Furthermore, the technical ideas disclosed in the embodiment can also be applied to array substrates and electronic devices having sensor elements, such as capacitance sensors and optical sensors.

[0012] <Overall configuration of liquid crystal display device> FIG. 1 is an exploded perspective view showing a schematic configuration example of a liquid crystal display device 1. As shown in FIG.

[0013] As shown in Figure 1, the X, Y, and Z directions are defined. The X, Y, and Z directions are perpendicular to each other, but may intersect at an angle other than a perpendicular angle. Viewing the liquid crystal display device 1 or its components parallel to the Z direction is called a "planar view." The direction indicated by the Z arrow is sometimes called "upward," and the opposite direction is sometimes called "downward."

[0014] 1, a liquid crystal display device 1 includes a display panel 2 and a backlight 3. For example, the backlight 3 may be configured as a side-edge type backlight including a light guide LG facing the display panel 2 and a plurality of light-emitting elements LS arranged at positions facing the side surfaces of the light guide LG. However, the backlight 3 is not limited to this, and backlights of various configurations that can supply the light necessary for image display may be used.

[0015] The planar shapes of the display panel 2 and the light guide LG are, for example, rectangular shapes with short sides along the X direction and long sides along the Y direction, but are not limited to rectangular shapes and may be other shapes.

[0016] The display panel 2 is a light-transmitting liquid crystal panel and includes, for example, an array substrate SUB1, a counter substrate SUB2 facing the array substrate SUB1, and a liquid crystal layer LC sealed between the array substrate SUB1 and the counter substrate SUB2. The display panel 2 thus configured has, for example, a rectangular display area DA.

[0017] The liquid crystal display device 1 further includes an optical sheet group 4, and polarizing plates 5 and 6. The optical sheet group 4 is disposed between the light guide LG and the display panel 2. For example, the optical sheet group 4 includes a diffusion sheet DF that diffuses the light emitted from the light guide LG, and a prism sheet PR1 and a prism sheet PR2, each of which has a large number of prisms formed thereon.

[0018] The polarizing plate 5 is disposed between the optical sheet group 4 and the array substrate SUB1. On the other hand, the polarizing plate 6 is disposed above the counter substrate SUB2. Here, the polarization axes of the polarizing plate 5 and the polarizing plate 6 are in a crossed Nicol relationship, i.e., perpendicular to each other.

[0019] The liquid crystal display device 1 configured in this manner can be used in various types of devices, such as head-mounted displays, in-vehicle devices, smartphones, tablet terminal devices, mobile phones, personal computers, television receivers, and game devices.

[0020] <Display panel configuration> Next, the configuration of the display panel 2 will be described. FIG. 2 is a plan view showing a schematic configuration of the display panel 2. As shown in FIG.

[0021] 2, the display panel 2 has a display area DA and a peripheral area SA around the display area DA. For example, as shown in FIG. 2, the lower side of the array substrate SUB1 protrudes in the Y direction further than the counter substrate SUB2. As a result, the array substrate SUB1 has a mounting area MA that does not overlap with the counter substrate SUB2 in a plan view. This mounting area MA constitutes part of the peripheral area SA.

[0022] In the display area DA, a plurality of pixels PX are arranged in a matrix. Each pixel PX includes a plurality of subpixels. For example, in FIG. 2, the pixel PX includes a red subpixel SPR, a green subpixel SPG, and a blue subpixel SPB. However, the pixel PX is not limited to this configuration, and may be configured to include subpixels of other colors, such as white.

[0023] As shown in Fig. 2, the display panel 2 includes a plurality of scanning lines G, a plurality of signal lines S (video lines), a scan driver GD1, a scan driver GD2, and a selector circuit ST. The plurality of scanning lines G extend in the X direction and are aligned in the Y direction. In contrast, the plurality of signal lines S extend in the Y direction and are aligned in the X direction. Each of the plurality of scanning lines G is connected to the scan driver GD1 or the scan driver GD2. Meanwhile, each of the plurality of signal lines S is connected to the selector circuit ST.

[0024] Next, as shown in Fig. 2, a controller CT is mounted in the mounting area MA. Furthermore, a terminal portion T is provided in the mounting area MA, and a flexible substrate F is connected to this terminal portion T. The controller CT may be mounted on the flexible substrate F. The controller CT is configured by, for example, an IC chip or a circuit element.

[0025] Various types of signals transmitted from an electronic device in which the liquid crystal display device 1 is implemented are output to the controller CT via an integrated circuit mounted on the flexible substrate F. The controller CT receives these signals and supplies a video signal to the selector circuit ST, while controlling the scan driver GD1, the scan driver GD2, and the selector circuit ST.

[0026] Each of the scan driver GD1 and the scan driver GD2 sequentially supplies scan signals to a plurality of scan lines G. On the other hand, the selector circuit ST sequentially supplies video signals input from the controller CT to the signal lines S.

[0027] Each pixel PX includes a pixel electrode PE, a switching element SW (thin film transistor), and a common electrode CE to which a common potential is supplied. The switching element SW is connected to the pixel electrode PE, the scanning line G, and the signal line S.

[0028] For example, when the switching element SW is composed of a thin film transistor (field effect transistor), the gate of the thin film transistor is electrically connected to the scanning line G. In addition, the source of the thin film transistor is electrically connected to the signal line S, while the drain of the thin film transistor is electrically connected to the pixel electrode PE.

[0029] When a scanning signal is supplied to the scanning line G, the thin film transistor turns on, and the video signal supplied to the signal line S is supplied to the pixel electrode PE. Meanwhile, the common electrode CE is formed across multiple sub-pixels, and when a video signal is supplied to the pixel electrode PE, a potential difference is generated between the pixel electrode PE and the common electrode CE. The electric field generated thereby acts on the liquid crystal layer LC, thereby controlling the alignment direction of the multiple liquid crystal molecules that make up the liquid crystal layer LC.

[0030] For example, in the so-called "vertical electric field method," in which a pixel electrode PE is formed on the array substrate and a common electrode CE is formed on the opposing substrate, and the liquid crystal layer LC is sandwiched between the pixel electrode PE and the common electrode CE, the orientation direction of the multiple liquid crystal molecules that make up the liquid crystal layer LC is controlled by the vertical electric field generated between the pixel electrode PE and the common electrode CE.

[0031] On the other hand, in the so-called "horizontal electric field method," for example, pixel electrodes PE and common electrodes CE are formed on an array substrate, and the horizontal electric field (fringe electric field) leaking from slits provided in the common electrode CE is utilized. The horizontal electric field leaking from the slits controls the orientation direction of multiple liquid crystal molecules that make up the liquid crystal layer LC arranged above the array substrate.

[0032] As described above, there are two methods for controlling the alignment direction of liquid crystal molecules: the "vertical electric field method" and the "horizontal electric field method." For example, the "horizontal electric field method" has the advantage of being able to provide a wider viewing angle than the "vertical electric field method." In this embodiment, the "horizontal electric field method" is adopted, and the scanning lines G, signal lines S, scanning drivers GD1 and GD2, selector circuits ST, switching elements SW, pixel electrodes PE, and common electrodes CE are formed on the array substrate SUB1.

[0033] <Plane layout configuration of sub-pixels> Next, the planar layout configuration of the sub-pixels will be described. FIG. 3 is a plan view showing an example of a planar layout of sub-pixels.

[0034] 3, the subpixels are subpixels SPR, SPG, and SPB. A red color filter CFR is arranged in the subpixel SPR, a green color filter CFG is arranged in the subpixel SPG, and a blue color filter CFB is arranged in the subpixel SPB.

[0035] As shown in Fig. 3, the subpixels SPR, SPG, and SPB are arranged in this order in the X direction. Furthermore, the subpixels SPR, SPB, and SPG are arranged in this order in the Y direction. As a result, the subpixels SPR are arranged in a diagonal direction intersecting the X and Y directions. Similarly, the subpixels SPG are arranged in a diagonal direction, and the subpixels SPB are also arranged in a diagonal direction.

[0036] The color filters CFR, CFG, and CFB are arranged in a dot shape (island shape) relative to the subpixels SPR, SPG, and SPB.

[0037] Gaps GP1 are formed between color filters CFR and CFG that are adjacent in the Y direction, between color filters CFG and CFB, and between color filters CFB and CFR, for example.

[0038] The planar layout of the subpixels SPR, SPG, and SPB and the color filters CFR, CFG, and CFB is not limited to the planar layout shown in FIG.

[0039] For example, the subpixels SPR may be arranged in the Y direction, the subpixels SPG may be arranged in the Y direction, and the subpixels SPB may be arranged in the Y direction, with the columns of the subpixels SPR, the columns of the subpixels SPG, and the columns of the subpixels SPB arranged in order in the X direction.

[0040] As described above, the liquid crystal display device 1 according to the present embodiment has a so-called "COA (Color Filter on Array) structure" in which the color filters CFR, CFG, and CFB are all disposed on the array substrate SUB1. According to the "COA structure," the color filters and sub-pixels are provided on the same array substrate SUB1. Therefore, the "COA structure" makes it possible to realize a high-definition liquid crystal display device 1 without being affected by misalignment between the array substrate SUB1 and the counter-substrate SUB2.

[0041] Fig. 4 is a schematic plan view illustrating a protective layer PL provided in a sub-pixel. Note that Fig. 4 does not show an opening region formed in the sub-pixel, a slit provided in the opening region, a conductive film TML, insulating layers IL1 to IL7, etc., which will be described later with reference to Fig. 5.

[0042] 4 shows a gate electrode GE1 (first gate electrode) and a gate electrode GE2 (second gate electrode) extending in the X direction, and two source electrodes SE extending in the Y direction and intersecting these gate electrodes GE1 and GE2. The gate electrodes GE1 and GE2 form the above-mentioned scanning lines G. The source electrodes SE form the above-mentioned signal lines S.

[0043] The source electrode SE includes a contact portion PLG1 (first contact portion). The contact portion PLG1 is connected to the semiconductor layer OS, which is a thin-film transistor. The semiconductor layer OS constitutes the switching element SW described above. In this way, the contact portion PLG1 has a function of electrically connecting the semiconductor layer OS and the source electrode SE.

[0044] A portion of the upper surface of the source electrode SE is covered with a protective layer PL. The protective layer PL has a rectangular shape in a plan view, as shown in FIG. 4, for example. A first region AR1 in which the protective layer PL is provided includes a second region AR2 in which the semiconductor layer OS and the source electrode SE are connected, and a third region AR3 that is disposed around the second region AR2 and in which the semiconductor layer OS is covered with an insulating portion IP1 (not shown in FIG. 4). By making the protective layer PL rectangular, dimensional control becomes easier, and the manufacturing process of the liquid crystal display device 1 can be facilitated. The shape of the protective layer PL is not limited to a rectangular shape. The protective layer PL is made of a translucent conductive material such as ITO (Indium Tin Oxide). A method for forming the protective layer PL will be described later.

[0045] The semiconductor layer OS extends so as to intersect with the gate electrodes GE1 and GE2. The semiconductor layer OS is provided above the gate electrode GE1 and includes a portion provided below the gate electrode GE2. The semiconductor layer OS is connected to the relay electrode RE (first electrode) at the contact portion PLG2. That is, the contact portion PLG2 (second contact portion) has the function of electrically connecting the semiconductor layer OS and the relay electrode RE. The relay electrode RE is made of, for example, a translucent conductive material such as ITO.

[0046] 4, a common electrode CE is provided so as to overlap in plan with the entire elements, such as the gate electrodes GE1 and GE2 and the source electrode SE. A slit (not shown) is provided in the common electrode CE in an opening region (not shown). A contact portion PLG3 (third contact portion) is provided on the relay electrode RE. The contact portion PLG3 electrically connects the pixel electrode PE and the relay electrode RE.

[0047] Here, for example, when a potential difference is generated between the common electrode CE and the pixel electrode PE, the electric field generated leaks out from a slit (not shown) provided in the common electrode CE. As a result, the horizontal electric field leaking out from the slit (not shown) controls the alignment direction of a plurality of liquid crystal molecules constituting the liquid crystal layer disposed above the array substrate SUB1. In other words, the slit (not shown) provided in the common electrode CE has the function of applying a horizontal electric field to the liquid crystal layer to control the alignment direction of a plurality of liquid crystal molecules. In this manner, the planar layout configuration of the sub-pixels is realized.

[0048] <Cross-sectional structure of sub-pixel> Next, the cross-sectional structure of the sub-pixel will be described.

[0049] Fig. 5 is a schematic cross-sectional view taken along line AA in Fig. 4. Note that Fig. 5 is a schematic cross-sectional view and does not accurately reflect the cross-section taken along line AA in Fig. 4. For example, Fig. 5 shows the conductive film TML and insulating layers IL1 to IL7, but these conductive films TML and insulating layers IL1 to IL7 are not shown in Fig. 4.

[0050] 5, an insulating layer IL1 is formed on a light-transmitting glass substrate 10. An insulating layer IL2 is then formed on this insulating layer IL1. In this embodiment, the glass substrate 10 is made of glass, but is not limited to this and may be made of a resin material such as polyimide resin. The insulating layers IL1 and IL2 are made of inorganic insulating films such as silicon nitride films and silicon oxide films.

[0051] 5, a gate electrode GE1 of a thin film transistor (field effect transistor) serving as a switching element is formed on the insulating layer IL2. This gate electrode GE1 functions as a scanning line G. The gate electrode GE1 is made of, for example, a metal material. The gate electrode GE1 may have a single-layer structure made of a single metal material, or may have a multi-layer structure in which different types of metal materials are stacked.

[0052] Next, an insulating layer IL3 is formed on the insulating layer IL2 so as to cover the gate electrode GE1. A semiconductor layer OS is then formed on this insulating layer IL3. The insulating layer IL3 is made of an inorganic insulating film such as a silicon nitride film or a silicon oxide film. On the other hand, the semiconductor layer OS is made of an amorphous silicon film or an oxide semiconductor film.

[0053] The semiconductor layer OS functions as a channel of the thin film transistor. That is, a channel is formed in the semiconductor layer OS based on a gate voltage applied to the gate electrode GE1. For example, when a gate voltage equal to or greater than a threshold voltage is applied to the gate electrode GE1, a channel is formed in the semiconductor layer OS. On the other hand, when a gate voltage less than the threshold voltage is applied to the gate electrode GE1, the channel formed in the semiconductor layer OS disappears.

[0054] This makes it possible to control the on / off operation of the thin film transistor based on the gate voltage applied to the gate electrode GE1.

[0055] For example, the semiconductor layer OS is preferably formed of an oxide semiconductor film, because a thin film transistor using an oxide semiconductor film as a channel has advantages of higher electron mobility and extremely low off-leakage current than a thin film transistor using an amorphous silicon film as a channel.

[0056] Next, as shown in FIG. 5, an insulating layer IL4 is formed on the insulating layer IL3 so as to cover the semiconductor layer OS. A gate electrode GE2 is then formed on the insulating layer IL4. The insulating layer IL4 is made of, for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film. Meanwhile, the gate electrode GE2 is made of, for example, a metal material. Thus, the thin-film transistor has gate electrodes GE1 and GE2 arranged to sandwich the semiconductor layer OS from above and below. In this configuration, for example, a channel can be formed on the lower surface of the semiconductor layer OS by applying a gate voltage equal to or greater than a threshold voltage to the gate electrode GE1 arranged below the semiconductor layer OS, and a channel can also be formed on the upper surface of the semiconductor layer OS by applying a gate voltage equal to or greater than a threshold voltage to the gate electrode GE2 arranged above the semiconductor layer OS.

[0057] In other words, in the thin film transistor of this embodiment, channels can be formed on both the upper and lower surfaces of the semiconductor layer OS, thereby improving the current driving force of the thin film transistor. However, the configuration of the thin film transistor is not limited to this, and the gate electrode GE2 may be omitted.

[0058] Next, an insulating layer IL5 is formed on the insulating layer IL4 so as to cover the gate electrode GE2. Then, a source electrode SE is formed on the insulating layer IL5. This source electrode SE functions as a signal line S. Furthermore, the source electrode SE and the signal line S are narrower than the width of the semiconductor layer OS. The insulating layer IL5 is made of, for example, an inorganic insulating film such as a silicon nitride film or a silicon oxide film. On the other hand, the source electrode SE is made of, for example, a metal material.

[0059] Here, as shown in FIG. 5, a contact hole CH1 is formed in the insulating layer IL4 and the insulating layer IL5, penetrating these insulating layers and reaching the semiconductor layer OS. The insulating layer IL4 and the insulating layer IL5 form an insulating part IP1 (first insulating part). The cross-sectional shape of the contact hole CH1 is, for example, an inverse tapered shape that narrows toward the semiconductor layer OS. In this contact hole CH1, the source electrode SE is electrically connected to the semiconductor layer OS via a contact part PLG1. The cross-sectional shape of the source electrode SE including the contact part PLG1 is, for example, a tapered shape that widens toward the semiconductor layer OS.

[0060] Next, an insulating layer IL6 is formed on the insulating layer IL5 so as to cover the source electrode SE. This insulating layer IL6 is also composed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film. The insulating layer IL6 constitutes an insulating portion IP2 (second insulating portion). Then, as shown in FIG. 5, a contact hole CH2 is formed penetrating the insulating layer IL6, the insulating layer IL5, and the insulating layer IL4 to reach the semiconductor layer OS. At this time, a relay electrode RE is formed from inside the contact hole CH2 over the insulating layer IL6. In FIG. 5, a contact hole CH1 is formed at one end of the semiconductor layer OS, and a contact hole CH2 is formed at the other end of the semiconductor layer OS.

[0061] In addition to the relay electrode RE, a protective layer PL is provided on the insulating layer IL6. The protective layer PL is disposed at a distance from the relay electrode RE. The protective layer PL is provided, for example, in a floating state on the insulating layer IL6. Here, "floating" means that it is not electrically connected to other components. Therefore, in the liquid crystal display device 1, the provision of the protective layer PL can prevent electrical influence on other conductive components. Furthermore, by arranging the protective layer PL in a floating state, a process such as forming a contact hole is unnecessary, thereby simplifying the manufacturing process. The protective layer PL may be unintentionally electrically connected to the source electrode SE through a gap formed in the insulating layer IL6. The protective layer PL may also be electrically connected to the source electrode SE using, for example, a contact hole. This is because even if the protective layer PL is connected to the source electrode SE, the electrical influence is negligible.

[0062] Next, an insulating layer IL7 is formed on the insulating layer IL6 so as to fill the inside of the contact hole CH2 and cover the relay electrode RE formed on a part of the insulating layer IL6 and the protective layer PL. The insulating layer IL7 is also made of an inorganic insulating film such as a silicon nitride film or a silicon oxide film.

[0063] This forms a contact portion PLG2 having a relay electrode RE connected to the semiconductor layer OS in the contact hole CH2 and an insulating layer IL7 covering the relay electrode RE. The relay electrode RE includes the contact portion PLG2. The contact portion PLG2 penetrates the insulating portions IP1 and IP2 and is electrically connected to the semiconductor layer OS. As a result, the relay electrode RE is electrically connected to the semiconductor layer OS via the contact portion PLG2. In other words, the relay electrode RE is electrically connected to the drain of the thin-film transistor.

[0064] The protective layer PL is provided above the contact portion PLG1 included in the source electrode SE. The protective layer PL closes the gap GP2 formed between the insulating portion IP2 (insulating layer IL6) formed on the source electrode SE and the insulating portion IP2 formed on the insulating portion IP1. The protective layer PL will be described in detail later.

[0065] As shown in FIG. 5, color filters CFB and CFG are formed on the insulating layer IL7. This achieves a "COA structure" in this embodiment. Next, an organic insulating film 100A is formed to cover the color filters CFB and CFG. The organic insulating film 100A is made of an organic material such as acrylic resin. A contact hole CH3 is formed in the organic insulating film 100A and the insulating layer IL7, penetrating the organic insulating film 100A and the insulating layer IL7 and reaching the relay electrode RE. Multiple types of components are embedded in the contact hole CH3 to form a contact portion PLG3 (third contact portion). In this way, the pixel electrode PE is electrically connected to the semiconductor layer OS (drain side) via the relay electrode RE at the contact portion PLG3. The contact portion PLG3 is connected to the relay electrode RE above the second gate electrode GE2.

[0066] Next, the internal and external configuration of the contact part PLG3 will be described.

[0067] 5, a relay electrode RE is provided on an insulating layer IL6, and an insulating layer IL7 is disposed so as to cover this relay electrode RE. Color filters CFB and CFG are provided on the insulating layer IL7. In order to flatten the unevenness caused by the color filters CFB and CFG, an organic insulating film 100A is provided so as to cover the color filters CFB and CFG.

[0068] As shown in FIG. 5, a contact hole CH3 is formed in the organic insulating film 100A, penetrating the organic insulating film 100A and the insulating layer IL7 to reach the relay electrode RE. A pixel electrode PE made of a translucent conductive material such as ITO is formed on the inner wall of the contact hole CH3. As shown in FIG. 5, the pixel electrode PE is electrically connected to the relay electrode RE at the bottom of the contact hole CH3. Furthermore, a capacitive insulating film CI is formed in the contact hole CH3 and in contact with the pixel electrode PE and the inner wall of the contact hole CH3. The capacitive insulating film CI is made of, for example, a silicon nitride film. Next, a conductive film TML in contact with the capacitive insulating film CI, a common electrode CE in contact with the conductive film TML, and an organic insulating film 100B in contact with the common electrode CE and filling the contact hole CH3 are formed in the contact hole CH3.

[0069] Here, a capacitance is formed by the pixel electrode PE, the capacitance insulating film CI, and the common electrode CE. When a potential difference is generated between the pixel electrode PE and the common electrode CE, an electric field is induced between the pixel electrode PE and the common electrode CE. The common electrode CE has a slit (not shown), through which the electric field leaks out of the capacitance. The orientation direction of the liquid crystal molecules is controlled based on the electric field leaking from the slit.

[0070] The common electrode CE is made of a translucent conductive material such as ITO. In order to reduce the resistance of the common electrode CE, a conductive film TML is provided in contact with the common electrode CE. In other words, the conductive film TML has the function of reducing the resistance of the common electrode CE.

[0071] 5, a liquid crystal layer LC is disposed above the organic insulating film 100A on which the contact portion PLG3 is formed, with an alignment film 200A interposed therebetween, and a spacer SP is provided above the contact portion PLG3. A glass substrate 20 is then disposed above the liquid crystal layer LC with an alignment film 200B and an overcoat film OC interposed therebetween. In this manner, the cross-sectional structure of the sub-pixel is realized.

[0072] <Sub-pixel operation> Next, the operation of the sub-pixel will be briefly described.

[0073] For example, when a scanning signal is supplied to gate electrodes GE1 and GE2 of a thin-film transistor, which is one of the components of a subpixel, a gate voltage equal to or greater than the threshold voltage is applied to each of the gate electrodes GE1 and GE2. This causes a channel to form on both the upper and lower surfaces of the semiconductor layer OS sandwiched between the gate electrodes GE1 and GE2. This electrically connects the source and drain of the thin-film transistor, turning it on. At this time, for example, when a video signal is supplied to the source electrode SE of the thin-film transistor, this video signal is transmitted to the relay electrode RE, which is electrically connected to the drain of the semiconductor layer OS, via the turned-on thin-film transistor. The video signal is then transmitted from the relay electrode RE to the pixel electrode PE via the contact portion PLG3.

[0074] A capacitor consisting of a pixel electrode PE, a common electrode CE, and a capacitive insulating film CI is formed inside and outside the contact portion PLG3, and a video signal is supplied to the pixel electrode PE constituting the capacitor. As a result, a potential difference occurs between the pixel electrode PE and the common electrode CE, and an electric field generated based on this potential difference leaks out through a slit in the common electrode CE. The horizontal electric field leaking out from the slit controls the alignment direction of multiple liquid crystal molecules constituting the liquid crystal layer LC arranged above the array substrate SUB1. As a result, the transmission and blocking of light from the liquid crystal layer LC is controlled in the subpixels. This control is performed for all subpixels arranged in the display area, and an image is displayed in the display area DA.

[0075] <Protective layer explanation> Next, the protective layer PL will be described. Fig. 6 is a schematic cross-sectional view taken along line BB in Fig. 4 before the protective layer PL is formed. Fig. 7 is a schematic cross-sectional view taken along line BB in Fig. 4 after the protective layer PL is formed.

[0076] 6, a configuration example used to explain the protective layer PL of the liquid crystal display device 1 includes a semiconductor layer OS, a source electrode SE provided on the semiconductor layer OS, an insulating portion IP1 provided on each side of the source electrode SE, an insulating portion IP2 provided on the insulating portion IP1 and the source electrode SE, and a protective layer PL (see FIG. 7) provided on the insulating portion IP2. The semiconductor layer OS, the source electrode SE, the insulating portion IP1, the insulating portion IP2, and the protective layer PL are provided, for example, on an array substrate SUB1 (see FIG. 1) not shown in FIG. 6.

[0077] The cross section of the source electrode SE in the width direction, including the contact portion PLG1, has a tapered shape that widens toward the semiconductor layer OS. The angle AN1 of the tapered portion of the source electrode SE relative to the semiconductor layer OS is, for example, 70 degrees. The angle AN1 may be greater than or equal to 70 degrees and less than 90 degrees. In other words, the angle AN1 is the angle at which an abnormality (gap GP2) occurs in the insulating portion IP2 (insulating layer IL6) formed on the insulating portion IP1. When the angle AN1 is a highly tapered shape greater than or equal to 70 degrees and less than 90 degrees, the opposing insulating portion IP1 may also be highly tapered, greater than or equal to 70 degrees and less than 90 degrees, like the source electrode SE. When the source electrode SE and the insulating portion IP1 are both highly tapered in this manner, a gap GP2 may be formed between the insulating portion IP2A formed on the source electrode SE and the insulating portion IP2B formed on the insulating portion IP1.

[0078] 7, the protective layer PL is formed so as to cover the insulating portion IP2 (insulating layer IL6). The first region AR1 in which the protective layer PL is provided includes a second region AR2 in which the source electrode SE is connected to the semiconductor layer OS, and a third region AR3 that is arranged around the second region AR2 and in which the semiconductor layer OS is covered by the insulating portion IP1. Therefore, the protective layer PL covers the gap GP2 formed between the insulating portion IP2A formed on the source electrode SE and the insulating portion IP2B formed on the insulating portion IP1. The third region AR3 includes a region that includes at least the gap GP2 in a plan view.

[0079] FIG. 8 is a schematic cross-sectional view taken along line CC in FIG. As shown in FIG. 8, the cross-sectional shape of the source electrode SE in the width direction is tapered toward the semiconductor layer OS, and the opposing insulating portion IP1 is also tapered like the source electrode SE, as in the cases of FIGS. 6 and 7. Meanwhile, the angle AN2 of the tapered portion of the source electrode SE and the insulating portion IP1 relative to the semiconductor layer OS is, for example, 60 degrees. When the angle AN2 is, for example, a low taper shape less than 60 degrees but not less than 0 degrees, the opposing insulating portion IP1 may also be formed with a low taper like the source electrode SE. When both the source electrode SE and the insulating portion IP1 are formed with a low taper in this way, no gap GP2 is formed between the source electrode SE and the insulating portion IP2 formed on the insulating portion, and the insulating layer IL6 is formed so that they are connected.

[0080] Even when the insulating portion IP2 is formed in this manner, the first region AR1 in which the protective layer PL is provided includes the second region AR2 and the third region AR3. That is, as shown in Figures 7 and 8, the shape of the insulating layer IL6 formed in the third region AR3 changes depending on the cross-sectional shape of the source electrode SE and the cross-sectional shape of the insulating portion IP1 facing the shape of the source electrode SE. The protective layer PL can protect the first region AR1 whether the insulating portion IP2 is formed with a gap GP2 or is formed continuously.

[0081] Furthermore, the cross-sectional shapes of the source electrode SE and the opposing insulating portion IP1 may vary during the manufacturing process. For example, the contact hole CH1 is circular in plan view. Therefore, it may be difficult to accurately form a low taper around the circular contact portion PLG1. It is also possible to increase the cross-sectional shape of the source electrode SE to increase volume and reduce resistance. As such, the cross-sectional shapes of the source electrode SE and the insulating portion IP1 may be highly tapered, either unintentionally or intentionally. Even when a gap GP2 may occur, the protective layer PL can protect the semiconductor layer OS. Regarding the third region AR3 included in the first region AR1 protected by the protective layer PL, it is desirable to determine or estimate the expected size of the gap GP2 in advance and set the size of the third region AR3 so that the gap GP2 is included.

[0082] <Example of protective layer formation> Next, an example of forming the protective layer PL will be described. Fig. 9 is a flowchart showing an example of forming the protective layer PL. Note that, hereinafter, among the steps of forming the entire liquid crystal display device 1, steps related to forming the protective layer PL will be described in detail.

[0083] After the glass substrate 10, insulating layer IL1, insulating layer IL2, gate electrode GE1, insulating layer IL3, semiconductor layer OS, insulating layer IL4, gate electrode GE2, insulating layer IL5, and contact hole CH1 have been formed, a source electrode SE is formed (ST101). The source electrode SE is formed so as to pass over the contact hole CH1 along the Y-axis direction. The source electrode SE includes a contact portion PLG1. The contact portion PLG1 is formed in the contact hole CH1. The source electrode SE is electrically connected to the semiconductor layer OS via the contact portion PLG1. An insulating portion IP1 constituted by the insulating layer IL4 and the insulating layer IL5 is formed on the side of the source electrode SE and on the semiconductor layer OS where the source electrode SE is not formed.

[0084] Next, an insulating layer IL6 (insulating portion IP2) is formed (ST102). The insulating layer IL6 is formed on the insulating layer IL5 and on the source electrode SE. For example, as shown in FIG. 6, the insulating layer IL6 is formed on the insulating layer IL5 and on the source electrode SE. The insulating layer IL6 is formed differently depending on the cross-sectional shape of the source electrode SE and the cross-sectional shape of the insulating layer IL5 adjacent to the source electrode SE. For example, as shown in FIG. 6, in the insulating layer IL6, a gap GP2 is formed between the insulating portion IP2A formed on the source electrode SE and the insulating portion IP2B formed on the insulating portion IP1. Furthermore, for example, as shown in FIG. 8, the insulating layer IL6 is formed so as to be continuous over the source electrode SE and the insulating portion IP1.

[0085] Next, a contact hole CH2 is formed (ST103). As shown in Fig. 5, the contact hole CH2 is formed so as to penetrate the insulating layer IL4, the insulating layer IL5, and the insulating layer IL6 and expose the upper surface of the semiconductor layer OS. The position where the contact hole CH2 is formed is shown in Figs. 4 and 5, for example.

[0086] Next, a transparent conductive film is formed (ST104). The region where the transparent conductive film is formed includes at least a relay region where the relay electrode RE is formed and a first region AR1 where the protective layer PL is formed. The transparent conductive film is formed, for example, on the insulating layer IL6 and on the entire inner surface of the contact hole CH2. The transparent conductive film is made of a translucent conductive material such as ITO.

[0087] Next, the relay electrode RE and the protective layer PL are formed (ST105). For example, first, a resist is applied to the entire surface of the transparent conductive film. Next, the relay region where the relay electrode RE is formed and the region other than the first region AR1 where the protective layer PL is formed are exposed to light. The exposure reduces the solubility of the resist in the relay region and the region other than the first region AR1. The resist in the region with reduced solubility is removed by development. As a result, the transparent electrode film is exposed in the region other than the relay region and the first region AR1. Next, an etching solution is used to remove the transparent electrode film in the relay region where the resist is applied and the region other than the first region AR1. At this time, the protective layer PL is formed in the first region AR1 with the resist applied. Therefore, for example, even if a gap GP2 is formed in the insulating layer IL6 as shown in FIG. 7, it is possible to prevent the etching solution from passing through the gap GP2 and penetrating into the semiconductor layer OS. Next, the resist applied to the relay region and the first region AR1 is removed. As a result, for example, the relay electrode RE and the protective layer PL are formed on the insulating layer IL5 as shown in Fig. 5. The subsequent steps of forming the insulating layer IL7 and the like will not be described again.

[0088] In the liquid crystal display device 1, the provision of the protective layer PL that protects the first region AR1 can prevent the etchant used in forming the relay electrode RE from penetrating into the semiconductor layer OS. Therefore, the liquid crystal display device 1 can avoid a situation in which the semiconductor layer OS is partially removed, and can prevent disconnections from occurring in the semiconductor layer OS.

[0089] <Differences from comparative examples> Fig. 10 is a diagram showing a configuration example of a display device as a comparative example in which a protective layer PL is not provided. As shown in Fig. 10, this configuration example has the same configuration as that shown in Fig. 7 (i.e., Fig. 6) except that a protective layer PL is not provided.

[0090] As shown in FIG. 10, a gap GP2 is formed between the insulating portion IP2A formed on the source electrode SE and the insulating portion IP2B formed on the insulating portion IP1. Because the protective layer PL is not provided when the relay electrode RE is formed, the etching solution penetrates onto the semiconductor layer OS, as shown by the arrow ARW in the figure. As a result, the semiconductor layer OS is partially lost. This may result in a disconnection of the semiconductor layer OS.

[0091] The liquid crystal display device 1 of this embodiment is provided with a protective layer PL, which can prevent the etching solution from penetrating onto the semiconductor layer OS and causing a break in the semiconductor layer OS.

[0092] <Other examples of protective layer PL> The protective layer PL may be configured so that an etching agent does not penetrate into the semiconductor layer OS when the relay electrode RE is formed. For this reason, for example, the protective layer PL may be configured as follows.

[0093] <Modification of the shape of the protective layer PL in plan view> FIG. 11 is a plan view schematically illustrating another example of the protective layer PL. As shown in FIG. 11, the protective layer PL is formed in a circular shape in plan view. The protective layer PL includes a first region AR1. Therefore, the protective layer PL prevents the etchant from penetrating into the semiconductor layer OS when the relay electrode RE is formed. Even when the protective layer PL is formed in this manner, the liquid crystal display device 1 can prevent disconnections from occurring in the semiconductor layer OS. Because the protective layer PL is formed in a circular shape, a greater distance can be secured between adjacent source electrodes SE than in the case where the protective layer PL is rectangular. Therefore, a wider positional misalignment margin can be secured for the protective layer PL, reducing the possibility of short-circuiting of the source electrodes SE.

[0094] Furthermore, in a plan view, the shape of the protective layer PL is not limited to the rectangular or circular shape described above. For example, the shape of the first region AR1 may be a polygonal shape such as a triangular, pentagonal, or trapezoidal shape. Note that the circular shape may be considered to include an elliptical shape.

[0095] Fig. 12 is a plan view schematically showing another example of the protective layer PL. As shown in Fig. 12, the shape of the protective layer PL in plan view is a combined shape that combines a polygonal shape and a circular shape. Fig. 12 also shows a fourth region AR4 in which the source electrode SE and the semiconductor layer OS are connected and the semiconductor layer OS is drawn out as wiring from the connection region. As shown in Fig. 12, the first region AR1 protected by the protective layer PL includes the fourth region AR4.

[0096] The protective layer PL protects the first region AR1. Even when the protective layer PL is formed in this manner, the liquid crystal display device 1 can prevent disconnections from occurring in the semiconductor layer OS. Furthermore, the first region AR1 protected by the protective layer PL includes the fourth region AR4 in a plan view. Therefore, the protective layer PL can also prevent the etching solution from penetrating into the wiring portion of the semiconductor layer OS when the relay electrodes RE are formed. Therefore, the liquid crystal display device 1 can more reliably prevent disconnections from occurring in the semiconductor layer OS.

[0097] 13 is a plan view schematically illustrating another example of the protective layer PL. As shown in FIG. 13, the first region AR1 is configured not to include the fifth region AR5. The fifth region AR5 is a part of the second region AR2 and the third region AR3 on the opposite side to the side where the semiconductor layer OS is drawn out as wiring. For example, the fifth region AR5 is the region opposite the fourth region AR4 in a plan view. In other words, the fifth region AR5 is the region of the first region AR1 that is farthest from the fourth region AR4.

[0098] Even if the fifth region AR5 is excluded from the first region AR1 in this way, the wiring portion of the semiconductor layer OS is protected by the protective layer PL. This prevents the etching solution from penetrating into the wiring portion of the semiconductor layer OS when forming the relay electrode RE. Even if the protective layer PL is formed to protect the first region AR1 excluding the fifth region AR5, the liquid crystal display device 1 can prevent disconnections from occurring in the semiconductor layer OS. Therefore, the liquid crystal display device 1 can increase the tolerance for the formation accuracy of the protective layer PL in a planar view. This makes it easier to form the protective layer PL. [Industrial Applicability]

[0099] The present invention can be used in display devices and array substrates. [Explanation of symbols]

[0100] 1 LCD display device 2 Display panel 3. Backlight 4 Optical sheets 5,6 Polarizing plate 10,20 Glass substrate 100A, 100B Organic insulating film 200A, 200B alignment film AN1,AN2 Angle AR1 1st area AR2 2nd area AR3 3rd area AR4 4th area AR5 5th area ARW Arrow CE common electrode CFB, CFG, CFR color filters CH1, CH2, CH3 contact holes CI Capacitive insulating film CT controller DA display area DF Diffusion Sheet F Flexible board G scan line GD1, GD2 scan driver GE1, GE2 gate electrodes GP1, GP2 gap IL1,IL2,IL3,IL4,IL5,IL6,IL7 insulating layer IP1, IP2 insulation LC liquid crystal layer LG light guide LS light-emitting element MA implementation area OC overcoat film OS semiconductor layer PE pixel electrode PL protective layer PLG1, PLG2, PLG3 contact part PR1, PR2 prism sheet PX pixels RE relay electrode S signal line SA surrounding area SE source electrode SP Spacer SPB, SPG, SPR subpixels ST selector circuit SUB1 array board SUB2 opposing substrate SW Switching element T terminal section TML conductive film

Claims

1. a semiconductor layer; a signal line provided on the semiconductor layer; a first insulating portion provided on a side of the signal line; a second insulating portion provided on the first insulating portion and on the signal line; a protective layer provided on the second insulating portion; Equipped with In a plan view, the first region in which the protective layer is provided includes a second region in which the signal line is connected to the semiconductor layer, and a third region that is disposed around the second region and in which the semiconductor layer is covered by the first insulating portion. Display device.

2. the signal line includes a first contact portion connected to the semiconductor layer; a cross section of the signal line including the first contact portion in a width direction thereof has a tapered shape whose width increases toward the semiconductor layer; The display device according to claim 1 .

3. In the cross section, the angle of the portion forming the tapered shape with respect to the semiconductor layer is equal to or greater than 70 degrees and less than 90 degrees. The display device according to claim 2 .

4. a gap is formed between the second insulating portion formed on the signal line and the second insulating portion formed on the first insulating portion; The protective layer covers the gap. The display device according to claim 1 .

5. the protective layer is provided on the second insulating portion so as not to be electrically connected to the second insulating portion; The display device according to claim 1 .

6. The shape of the protective layer in a plan view is any one of a polygonal shape, a circular shape, and a combined shape of the polygonal shape and the circular shape. The display device according to claim 1 .

7. Further, a first electrode is provided on the second insulating portion, the first electrode and the protective layer are provided on the second insulating portion and spaced apart from each other; the protective layer and the first electrode are made of indium tin oxide; The display device according to claim 1 .

8. the first electrode includes a second contact portion connected to the semiconductor layer; the second contact portion penetrates the first insulating portion and the second insulating portion and is connected to the semiconductor layer; The display device according to claim 7 .

9. Further, the pixel electrode includes a first gate electrode, a second gate electrode, and a pixel electrode; the semiconductor layer includes a portion provided above the first gate electrode and below the second gate electrode; the pixel electrode includes a third contact connected to the first electrode above the second gate electrode; the signal line is connected to a source electrode of the semiconductor layer; The display device according to claim 8 .

10. a semiconductor layer; a signal line provided on the semiconductor layer; a first insulating portion provided on a side of the signal line; a second insulating portion provided on the first insulating portion and on the signal line; a protective layer provided on the second insulating portion; Equipped with In a plan view, the first region in which the protective layer is provided includes a second region in which the signal line is connected to the semiconductor layer, and a third region that is disposed around the second region and in which the semiconductor layer is covered by the first insulating portion. Array board.

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