Method for forming reduced diameter microvias

Abstract

To provide a method and a non-transitory computer-readable medium for forming microvias for packaging applications.SOLUTION: A method includes depositing 110 a conductive seed layer 210 on a substrate 200, depositing 120 a first dielectric layer 220, patterning 130 the first dielectric layer 220 to form at least one via 230 having a diameter D, depositing 140 a conductive material 240 in the via 230 to form a pillar, depositing 150 the first dielectric layer 220 and the seed layer 210, and depositing 160 a second dielectric layer 250.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure generally relate to methods for forming microvias with reduced diameter and / or increased alignment, and more particularly, to methods for forming copper pillars in redistribution layer (RDL) polymer dielectrics. [Background technology]

[0002]

[0002] RDL polymer dielectrics are used to redistribute high density I / Os emanating from chips onto package substrates. Multilayer RDLs are used to interconnect two or more chips. Using semi-additive processes (SAP), copper traces are fabricated in a planar, two-dimensional fashion. Successive layers are interconnected vertically by microvias.

[0003]

[0003] While line widths and spacings continue to shrink to <20 μm, scaling microvias is currently one of the biggest bottlenecks facing the industry. Scaling copper lines without reducing via diameter reduces the wiring density per layer, which increases the number of layers and increases the manufacturing costs of packages.

[0004]

[0004] Industry standard dielectrics are typically epoxy dielectrics filled with silica fillers. Such composite materials are typically used for their thermomechanical and electrical performance. While such smooth-surfaced composite dielectrics enable the fabrication of fine lines, forming small vias using any subtractive process, such as etching / laser, poses significant challenges due to potential non-uniformities in the bulk material.

[0005]

[0005] Microvias are typically formed by laser drilling. However, the diameter of laser-drilled microvias is limited to 20 μm diameter for manufacturing reasons. Laser-drilled vias are difficult to scale down below the 20 μm node, primarily due to cost and throughput reasons.

[0006]

[0006] Therefore, there is a need for new methods of forming microvias, particularly microvias with reduced diameter and improved placement accuracy. Summary of the Invention

[0007] One or more embodiments of the present disclosure are directed to a method of forming a microvia. The method includes depositing a conductive seed layer on a substrate. A first dielectric layer is deposited. The first dielectric layer is patterned to form at least one via having a diameter. A conductive material is deposited in the at least one via to form at least one conductive pillar having a height. The first dielectric layer and the conductive seed layer are removed from the substrate. A second dielectric layer is deposited around the at least one conductive pillar.

[0008] An additional embodiment of the present disclosure is directed to a method of forming a microvia. The method includes depositing a copper seed layer on a substrate. A first copper layer is deposited on the copper seed layer. The first copper layer is patterned to form a first copper line. A first dielectric layer is deposited on the first copper line. The first dielectric layer is photosensitive. The first dielectric layer is patterned to form a via having a diameter. The via is positioned above the first copper line. Copper material is deposited in the via to form a copper pillar. The first dielectric layer and the copper seed layer are removed from the substrate. A second dielectric layer is deposited around and above the copper pillar. The second dielectric layer includes a silica-filled epoxy. The second dielectric layer is planarized to expose the top of the copper pillar. A second copper layer is deposited on the second dielectric layer and the copper pillar. The second copper layer is patterned to form a second copper line.

[0009]

[0009] A further embodiment of the present disclosure is directed to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform the following operations: depositing a copper seed layer on a substrate; depositing a first dielectric layer; patterning the first dielectric layer to form a via having a diameter; depositing copper material in the via to form a copper pillar; etching the first dielectric layer and the copper seed layer from the substrate; and depositing a second dielectric layer around at least one conductive pillar.

[0010]

[0010] In order that the features of the present disclosure set forth above may be understood in detail, a more particular description of the present disclosure briefly summarized above will be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the present disclosure may admit of other equally effective embodiments, and therefore the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0011] [Figure 1] 1 illustrates an exemplary processing method according to one or more embodiments of the present disclosure. [Figure 2]

[0012] 1 illustrates an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 3]

[0013] 1 illustrates an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 4]

[0014] 1 illustrates an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figure 5]

[0015] 1 illustrates an exemplary substrate during processing in accordance with one or more embodiments of the present disclosure. [Figures 6A-6C]

[0016] 1 illustrates an exemplary device formed in accordance with one or more embodiments of the present disclosure. [Figure 7]

[0017] 1 illustrates a processing system in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0018] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0019] The term "substrate," as used herein and in the appended claims, refers to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that when reference is made to a substrate, it may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, when reference is made to deposition on a substrate, it may refer to both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0014]

[0020] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam (e-beam) cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in this disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015]

[0021] One or more embodiments of the present disclosure are directed to methods for forming microvias. Some embodiments of the present disclosure provide microvias with reduced diameters compared to known processes. Some embodiments of the present disclosure provide microvias with improved placement accuracy.

[0016]

[0022] Some embodiments of the present disclosure advantageously provide microvias with reduced diameters. In some embodiments, the microvia diameter is 20 μm or less, 10 μm or less, or 5 μm or less. In some embodiments, the microvia diameter is 0.05 μm, 0.1 μm, 0.2 μm, 0.5 μm, 1 μm, or 2 μm or more. Without being bound by theory, the reduced diameter allows for higher wiring density (IO / mm / layer) within the RDL without the need for an increased number of RDLs.

[0017]

[0023] Some embodiments of the present disclosure advantageously utilize equipment and / or processes that are well known in the art. Examples include, but are not limited to, physical vapor deposition (PVD), lithography, electrolytic copper deposition (ECD), and etching / chemical mechanical planarization (CMP). Without being bound by theory, it is believed that the use of known equipment and processes reduces the resistance to adoption and increases the potential use of existing hardware.

[0018]

[0024] Some embodiments of the present disclosure advantageously provide microvias with improved overlay accuracy. Without being bound by theory, the improved overlay accuracy seen in some embodiments allows for smaller capture pads. In some embodiments, capture pads are not used (i.e., via-in-line processes).

[0019]

[0025] Some embodiments of the present disclosure advantageously provide semiconductor chipsets with a reduced number of RDL layers. Without being bound by theory, the reduction in RDL layers reduces the manufacturing costs of the final semiconductor chipset.

[0020]

[0026] 1 and 2, an exemplary method 100 for forming microvias is illustrated, as is an exemplary substrate being processed. For the avoidance of doubt, the method illustrated in FIG. 1 includes several operations within dashed boxes. These operations are optional. Furthermore, it is within the scope of this disclosure that some, all, or none of the optional steps may be performed.

[0021]

[0027] The method begins in operation 110 by depositing a conductive seed layer 210 on a substrate 200. In some embodiments, the substrate 200 is silicon. The substrate is shown in FIG. 2A, and the substrate with the conductive seed layer is shown in FIG. 2B. Lettered electronic devices in the figures are used to indicate the electronic device at various times during processing. Alternative electronic devices are formed by alternative or optional processes and are indicated with a prime (e.g., B'). As used in this regard, a "conductive" seed layer refers to a seed layer of a conductive material. The term "conductive" seed layer should not be understood to convey anything regarding the electrical properties of the "conductive" seed layer. In some embodiments, the conductive seed layer 210 comprises copper. In some embodiments, the conductive seed layer 210 is continuous. In some embodiments, the conductive seed layer 210 has an average thickness in the range of 50 nm to 500 nm. In some embodiments not shown, a barrier layer is deposited on the substrate before depositing the conductive seed layer 210.

[0022]

[0028] In some embodiments, method 100 continues with optional operation 310. For reference, a substrate 200 processed by optional operations 310 and 320 is shown in FIG. 3 and is labeled device B″. Those skilled in the art will recognize that electronic devices of the same base letter can be substituted for any of the described methods. For example, the device labeled B″ can be substituted for the device labeled B in FIG. 2. In optional operation 310, a first conductive layer 350 is deposited on the conductive seed layer 210.

[0023]

[0029] In operation 320, first conductive layer 350 is patterned by removing portions of first conductive layer 350 to form conductive feature 360. In some embodiments, in operation 320, first conductive layer 350 is patterned by removing portions of first conductive layer 350 to form conductive feature 360. Those skilled in the art would recognize this as a subtractive patterning process. Alternatively, in some embodiments not shown, first conductive layer 350 may be deposited by a patterning process, and conductive feature 360 may be formed on first conductive layer 350. Those skilled in the art would recognize this as a semi-additive process (SAP). In some embodiments, conductive feature 360 is a conductive line, trace, or capture pad. In some embodiments, first conductive layer 350 and conductive feature 360 comprise copper.

[0024]

[0030] As used in this regard, a "capture pad" is a pad of conductive material to which a via and / or pillar is expected to connect. Traditionally, imprecision in the laser drilling process has necessitated larger capture pads to ensure that the via / pillar makes contact with the conductive line. As discussed above, some embodiments of the present disclosure provide microvias with improved overlay accuracy, allowing for smaller or no capture pads. In some embodiments, the vias are formed to contact the conductive line without a capture pad.

[0025]

[0031] In some embodiments, via 230 is formed within a tolerance of a predetermined xy location on substrate 200. In some embodiments, the tolerance is 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 0.5 μm or less, or 0.25 μm or less from the predetermined xy location. In some embodiments, the tolerance is 50% or less, 20% or less, 10% or less, 5% or less, or 1% or less of the via diameter D from the predetermined xy location.

[0026]

[0032] The method 100 continues, at operation 120, by depositing a first dielectric layer 220. The first dielectric layer 220 may be deposited by any suitable method, including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on coating, hot roll lamination, vacuum lamination, etc.

[0027]

[0033] In some embodiments, first dielectric layer 220 comprises a photosensitive dielectric material. In some embodiments, first dielectric layer 220 comprises a negative photoresist or a positive photoresist. In some embodiments, first dielectric layer 220 comprises a chemically amplified resist.

[0028]

[0034] In some embodiments not shown, a planarization layer is deposited before the first dielectric layer 220. Without being bound by theory, it is believed that the first dielectric layer may not self-level or planarize over features in the substrate (e.g., conductive feature 360). Thus, in some embodiments, a planarization layer is deposited over the substrate, including any conductive features, to provide a level surface for the deposition of the first dielectric layer 220. In some embodiments, the planarization layer comprises a dielectric layer. In some embodiments, the planarization layer comprises a parylene layer.

[0029]

[0035] Method 100 continues in operation 130 by patterning first dielectric layer 220 to form at least one via 230 having a diameter D. In those embodiments in which first dielectric layer 220 comprises a photosensitive dielectric material, first dielectric layer 220 may be patterned by a photolithography process. In some embodiments, operation 130 also removes any planarization layer exposed at the bottom of via 230.

[0030]

[0036] Unlike conventional laser drilling, in photolithography processes, the diameter D of via 230 is limited primarily by the resolution of the lithography process. As previously mentioned, the reduced diameter provided by some embodiments enables higher wiring density in packaging applications.

[0031]

[0037] In some embodiments, the diameter D of the via 230 is 20 μm or less, 15 μm or less, 10 μm or less, 8 μm or less, 5 μm or less, 3 μm or less, 1 μm or less, or 0.5 μm or less. In some embodiments, the diameter D of the via 230 is in the range of 0.5 μm to 1 μm, 0.5 μm to 3 μm, 0.5 μm to 5 μm, 0.5 μm to 10 μm, 0.5 μm to 20 μm, 1 μm to 3 μm, 1 μm to 5 μm, 1 μm to 10 μm, 1 μm to 20 μm, 3 μm to 5 μm, 3 μm to 10 μm, or 3 μm to 20 μm.

[0032]

[0038] The method 100 continues at operation 140 by depositing a conductive material 240 in the via 230 to form a pillar. In some embodiments, the conductive material includes copper. In some embodiments, the height H of the pillar is less than or equal to the thickness T of the first dielectric layer 220. In some embodiments, the height H of the pillar is greater than the thickness of the first dielectric material. In these embodiments, the overburden deposited outside of the via 230 may be removed. Any suitable removal process may be used, including, but not limited to, planarization.

[0033]

[0039] The method 100 continues at operation 150 by depositing a first dielectric layer 220 and a seed layer 210. The removal process may be performed by any suitable process.

[0034]

[0040] In some embodiments, the first dielectric layer 220 is removed by a wet etching process. In some embodiments, the wet etching process includes the use of an organic stripper. In some embodiments, the organic stripper includes N-methylpyrrolidone (NMP). In some embodiments, the wet etching process includes the use of an inorganic stripper. In some embodiments, the inorganic stripper may include a hydroxide and an amine. In some embodiments, the inorganic stripper includes sodium hydroxide or potassium hydroxide and tetramethylammonium hydroxide. In some embodiments, the wet etching process is performed at a temperature ranging from 20° C. to 50° C. In some embodiments, the wet etching process utilizes an external force, including, but not limited to, ultrasonication or air agitation. Without being bound by theory, it is believed that the external force in some embodiments improves mass flow and / or reaction rate to improve removal of the first dielectric layer 220.

[0035]

[0041] In some embodiments, the seed layer 210 is removed by a wet etching process. In some embodiments, the wet etching process relies on the oxidation-reduction reaction of the seed layer 210. In some embodiments, the wet etching process includes the use of ferric chloride.

[0036]

[0042] In some embodiments, the first dielectric layer 220 and / or the seed layer 210 are removed by a dry etching process. In some embodiments, the dry etching process includes the use of a plasma. In some embodiments, the plasma is formed from oxygen and argon. In some embodiments, the plasma is formed from halogen and / or hydrogen gas.

[0037]

[0043] In some embodiments, if a barrier layer is present, the barrier layer may also be removed by operation 150. In some embodiments, if a planarization layer is present, the planarization layer may also be removed by operation 150.

[0038]

[0044] In some embodiments, the method 100 further includes performing an ashing process. In some embodiments, the ashing process is performed after removing the first dielectric layer 220 and the seed layer 210. In some embodiments, the ashing process removes any organic residue from the substrate 200. In some embodiments, the ashing process includes exposing the substrate to a plasma generated from a mixture of O and argon. In some embodiments, the plasma has a power in the range of 250 W to 300 W, or 280 W. In some embodiments, the substrate is exposed to the plasma for a period in the range of 2 minutes to 5 minutes.

[0039]

[0045] In some embodiments, a bias power is provided to the plasma. In some embodiments, the bias power allows for shorter reaction times. Without being bound by theory, it is believed that the bias power provides directionality to the plasma species (ions, electrons, radicals, etc.) and helps impart momentum to the plasma species. It is believed that the increased bombardment energy increases the reaction rate and increases the removal rate of the dielectric layer residue.

[0040]

[0046] The method 100 continues, at operation 160, by depositing a second dielectric layer 250. In some embodiments, the second dielectric layer 250 comprises a redistribution layer (RDL) dielectric. In some embodiments, the RDL dielectric comprises a polymer dielectric. In some embodiments, the polymer dielectric comprises a filler. In some embodiments, the second dielectric layer 250 comprises a silica-filled epoxy.

[0041]

[0047] The second dielectric layer 250 may be formed by any suitable process. In some embodiments, the second dielectric layer 250 is deposited by dry film lamination. In some embodiments, the second dielectric layer 250 is initially flowable upon deposition. In some embodiments, the second dielectric layer may be cured.

[0042]

[0048] For example, in some embodiments, the silica-filled epoxy is deposited by dry film lamination under vacuum at a temperature ranging from 90°C to 130°C. Without being bound by theory, it is believed that at these temperatures, the epoxy in the dielectric becomes flowable and conforms around underlying features (e.g., lines / capture pads), and the lamination pressure flattens the film onto the top surface. Additionally, the vacuum environment ensures that there are no voids between the dielectric and the substrate / lines / pads. In some embodiments, after lamination, the second dielectric layer is cured at 180°C for a period ranging from 30 to 60 minutes. In some embodiments, the curing temperature ranges from 150°C to 200°C.

[0043]

[0049] In some embodiments, the method continues with optional operation 410. For reference, substrate 200 processed by optional operation 410 is shown in FIG. 4. In some embodiments, the thickness of second dielectric layer 250 is not tightly controlled during deposition in operation 160. In these embodiments, the thickness of second dielectric layer 250 may exceed height H of the pillars of conductive material 240. In optional operation 410, second dielectric layer 250 is planarized to expose the tops of conductive material 240. In some embodiments, the planarization process may be performed by CMP or an etch-back process.

[0044]

[0050] After optional operation 410, the top surfaces of the pillars and the second dielectric layer 250 are substantially coplanar. As used in this regard, "substantially coplanar" material has a surface within + / - 50 nm.

[0045]

[0051] In some embodiments, method 100 continues with optional operations 510 and 520. For reference, FIG. 5 shows substrate 200 being processed by optional operations 510 and 520. In optional operation 510, a second conductive layer 550 is deposited on second dielectric layer 250 and conductive pillars. In some embodiments, in operation 520, second conductive layer 550 is patterned by removing portions of first conductive layer 550 to form conductive features 560. Those skilled in the art would recognize this as a subtractive patterning process. Alternatively, in some embodiments not shown, second conductive layer 550 may be deposited by a patterning process, and conductive features 560 may be formed on second conductive layer 550. Those skilled in the art would recognize this as a semi-additive process (SAP). In some embodiments, conductive features 560 are conductive lines, traces, or capture pads. In some embodiments, second conductive layer 550 and conductive features 560 comprise copper.

[0046]

[0052] Referring to Figures 6A-6C, related embodiments of completed devices are illustrated. In Figure 6A, device 610 includes at least two pillars 620A, 620B connecting two first copper wires 630A, 630B to one second copper wire 640. Alternatively, in Figure 6B, device 650 includes at least two pillars 660A, 660B connecting one first copper wire 670 to two second copper wires 680A, 680B. Finally, in Figure 6C, the embodiments of Figures 6A and 6B are combined to connect multiple first copper wires to multiple second copper wires in a "daisy chain" fashion.

[0047]

[0053] Referring to FIG. 7 , a further embodiment of the present disclosure is directed to a processing system 900 for performing the methods described herein. FIG. 7 illustrates a system 900 that may be used to process substrates according to one or more embodiments of the present disclosure. The system 900 may be referred to as a cluster tool. The system 900 includes a central transfer station 910 with a robot 912 therein. The robot 912 is shown as a single blade robot, although one skilled in the art will recognize that other robot 912 configurations are within the scope of the present disclosure. The robot 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0048]

[0054] At least one pre-clean / buffer chamber 920 is connected to the central transfer station 910. The pre-clean / buffer chamber 920 may include one or more of a heater, a radical source, or a plasma source. The pre-clean / buffer chamber 920 may be used as a holding area for individual semiconductor substrates or for cassettes of wafers for processing. The pre-clean / buffer chamber 920 may perform a pre-clean process, pre-heat substrates for processing, or may simply be a staging area for a processing sequence. In some embodiments, there are two pre-clean / buffer chambers 920 connected to the central transfer station 910.

[0049]

[0055] 7, the pre-clean chamber 920 may act as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 that move substrates from cassettes to the pre-clean / buffer chamber 920. A robot 912 may then move the substrates from the pre-clean / buffer chamber 920 to other chambers in the system 900.

[0050]

[0056] A first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured as a deposition chamber and may be fluidly coupled to one or more reactive gas sources to provide one or more flows of reactive gas to the first processing chamber 930. Substrates may be moved in and out of the processing chamber 930 by a robot 912 passing through an isolation valve 914.

[0051]

[0057] Processing chambers 940 may also be connected to the central transfer station 910. In some embodiments, the processing chambers 940 include patterning chambers and are fluidly coupled to one or more reactive gas sources to provide a flow of reactive gas to the processing chambers 940 to perform isotropic etch processes. Substrates may be moved in and out of the processing chambers 940 by a robot 912 passing through an isolation valve 914.

[0052]

[0058] In some embodiments, a processing chamber 960 is connected to the central transfer station 910 and configured to act as an etching or removal chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0053]

[0059] In some embodiments, each of processing chambers 930, 940, and 960 is configured to perform a different portion of a processing method. For example, processing chamber 930 may be configured to perform a deposition process, processing chamber 940 may be configured to perform a patterning process, and processing chamber 960 may be configured to perform an etch / removal process. A skilled artisan will recognize that the number and arrangement of individual processing chambers in a tool can vary, and the embodiment shown in FIG. 7 represents just one possible configuration.

[0054]

[0060] In some embodiments, processing system 900 includes one or more metrology stations. For example, a metrology station may be located in the pre-clean / buffer chamber 920, in the central transfer station 910, or in any of the individual processing chambers 930, 940, 960. A metrology station may be located anywhere in system 900 that allows a substrate to be measured without removing the substrate from system 900.

[0055]

[0061] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, or 960. In some embodiments, there are multiple controllers 950 connected to individual chambers or stations, and a main control processor is coupled to each of the individual processors to control the system 900. The controller 950 may be one of any form of general-purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial environment to control various chambers and sub-processors.

[0056]

[0062] At least one controller 950 may have a processor 952, a memory 954 coupled to the processor 952, input / output devices 956 coupled to the processor 952, and support circuits 958 for communication between various electronic components. The memory 954 may include one or more of temporary memory (e.g., random access memory) and non-temporary memory (e.g., storage).

[0057]

[0063] The processor's memory 954 or computer-readable medium may be one or more of readily available memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The memory 954 may hold a set of instructions operable by the processor 952 to control parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. The circuits may include, for example, cache, power supplies, clock circuits, input / output circuits, subsystems, etc.

[0058]

[0064] The processes may generally be stored in memory as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be implemented in hardware. Thus, the processes may be implemented in software and executed by a computer system in hardware (e.g., an application-specific integrated circuit or other type of hardware implementation) or a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber to perform the processes.

[0059]

[0065] In some embodiments, the controller 950 has one or more configurations for executing individual processes or sub-processes to implement the method. The controller 950 may be connected to and configured to operate intermediate components to implement the functions of the method. For example, the controller 950 may be connected to and configured to control one or more gas valves, actuators, motors, slit valves, vacuum controls, etc.

[0060]

[0066] The controller 950 in some embodiments has one or more configurations selected from the following: a configuration for moving substrates on a robot between multiple processing chambers and a metrology station; a configuration for loading and / or unloading substrates from the system; a configuration for depositing a conductive seed layer on a substrate; a configuration for depositing a first copper layer; a configuration for patterning the first copper layer; a configuration for depositing a first dielectric layer; a configuration for patterning the first dielectric layer; a configuration for depositing a conductive material in vias; a configuration for removing the first dielectric layer; a configuration for depositing a second dielectric layer; a configuration for planarizing the second dielectric layer; a configuration for depositing a second copper layer; and / or a configuration for patterning the second copper layer.

[0061]

[0067] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0062]

[0068] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a microvia, comprising: depositing a conductive seed layer on a substrate; depositing a first dielectric layer; patterning the first dielectric layer to form at least one via having a diameter; depositing a conductive material in the at least one via to form at least one conductive pillar having a height; removing the first dielectric layer and the conductive seed layer from the substrate; depositing a second dielectric layer around the at least one conductive pillar; A method comprising:

2. depositing a first conductive layer on the conductive seed layer before depositing the first dielectric layer; patterning the first conductive layer to form first conductive lines or capture pads; The method of claim 1 further comprising:

3. The method of claim 1 , further comprising performing an ashing process after removing the first dielectric layer and the conductive seed layer.

4. depositing the second dielectric layer having a thickness greater than the height of the at least one conductive pillar; planarizing the second dielectric layer to expose a top of the at least one conductive pillar; The method of claim 1 further comprising:

5. depositing a second conductive layer over the second dielectric layer and the at least one conductive pillar; patterning the second conductive layer to form second conductive lines or capture pads; The method of claim 1 further comprising:

6. The method of claim 1 , wherein the conductive seed layer and the conductive material comprise copper.

7. 10. The method of claim 1, wherein the first dielectric layer comprises a photosensitive dielectric and patterning at least one via in the first dielectric layer comprises a photolithography process.

8. The method of claim 7 , wherein the photosensitive dielectric material comprises a positive photoresist.

9. The method of claim 7 , wherein the photosensitive dielectric material comprises a negative photoresist.

10. The method of claim 1 , wherein the second dielectric layer comprises a RDL polymer dielectric.

11. The method of claim 10 , wherein the RDL polymer dielectric comprises a silica-filled epoxy.

12. The method of claim 1 , wherein the diameter of the at least one via is less than or equal to 20 μm.

13. The method of claim 12 , wherein the diameter of the at least one via is in the range of 1 μm to 20 μm.

14. 2. The method of claim 1, wherein the at least one via is formed within a predetermined xy location tolerance, the tolerance being 0.5 μm or less from the predetermined xy location.

15. The method of claim 1 , wherein the at least one via is formed to contact a conductive line without a capture pad.

16. 1. A method of forming a microvia, comprising: depositing a copper seed layer on a substrate; depositing a first copper layer on the copper seed layer; patterning the first copper layer to form a first copper line; depositing a first dielectric layer on the first copper line, the first dielectric layer being photosensitive; patterning the first dielectric layer to form a via having a diameter, the via being positioned above the first copper line; depositing a copper material in the via to form a copper pillar; removing the first dielectric layer and the copper seed layer from the substrate; depositing a second dielectric layer around and over the copper pillar, the second dielectric layer comprising a silica-filled epoxy; planarizing the second dielectric layer to expose the tops of the copper pillars; depositing a second copper layer over the second dielectric layer and the copper pillars; patterning the second copper layer to form second copper lines; A method comprising:

17. 17. The method of claim 16, wherein the diameter of the via is greater than or equal to 1 μm and less than or equal to 20 μm.

18. 17. The method of claim 16, wherein the via is formed within a predetermined xy location tolerance, the tolerance being 0.5 μm or less from the predetermined xy location.

19. 17. The method of claim 16, wherein at least two copper pillars are formed to connect two first copper wires to one second copper wire or one first copper wire to two second copper wires.

20. 1. A non-transitory computer-readable medium containing instructions that, when executed by a controller of a processing system, cause the processing system to: depositing a copper seed layer on the substrate; depositing a first dielectric layer; patterning the first dielectric layer to form a via having a diameter; depositing a copper material in the via to form a copper pillar; etching the first dielectric layer and the copper seed layer from the substrate; depositing a second dielectric layer around the copper pillar; A non-transitory computer-readable medium for implementing the above.

Images