Manufacturing method for semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics, a semiconductor device with stable electric characteristics, a semiconductor device with high reliability, and a manufacturing method for the semiconductor device.SOLUTION: The method includes forming a semiconductor layer 108 including metal oxide, forming a gate insulating layer 110 including an oxide on the semiconductor layer, and forming a metal oxide layer on the gate insulating layer. After the metal oxide layer is formed, a heating process is performed and after the heating process is performed, the metal oxide layer is removed. After the metal oxide layer is removed, a gate electrode 112 overlapping with a part of the semiconductor layer is formed on the gate insulating layer. Then, a first element is supplied through the gate insulating layer to a region (low-resistance region 108n) of the semiconductor layer that does not overlap with the gate electrode. As the first element, phosphorus, boron, magnesium, aluminum, silicon, and the like are given. The process performed after the metal oxide layer is removed is preferably performed at the temperature less than or equal to the temperature of the heating process.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. and a method for producing the same.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the semiconductor device include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, Input devices (e.g., touch sensors), input / output devices (e.g., touch panels), etc. These driving methods and manufacturing methods can be cited as examples. refers to any device that can function by utilizing the properties of semiconductors. [Background technology]

[0003] Oxide semiconductors using metal oxides have attracted attention as semiconductor materials that can be used in transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the indium ratio relative to the gallium ratio, the field effect mobility (simply mobility) A semiconductor device with improved resistance, or sometimes referred to as μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed by sputtering or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. Utilizing some of the production equipment for transistors that use polycrystalline silicon and amorphous silicon, with some modifications This allows for reduced capital investment. has a higher field effect mobility than amorphous silicon, so it is possible to A high-performance display device can be realized.

[0005] Furthermore, Patent Document 2 discloses that the source and drain regions are formed with aluminum, boron, gallium, etc. A small number of elements selected from the group consisting of aluminum, indium, titanium, silicon, germanium, tin, and lead A thin film using an oxide semiconductor film having a low resistance region containing at least one dopant A film transistor is disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-228622 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with stable electrical characteristics. An object of one embodiment is to provide a highly reliable semiconductor device.

[0008] Note that the description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. From the description of the section, it is possible to extract other issues. [Means for solving the problem]

[0009] One embodiment of the present invention is to form a semiconductor layer containing a metal oxide, and then form a gate electrode containing the oxide on the semiconductor layer. a gate insulating layer is formed, a metal oxide layer is formed on the gate insulating layer, and after forming the metal oxide layer After the heat treatment, the metal oxide layer is removed. After that, a gate electrode is formed on the gate insulating layer so as to overlap a part of the semiconductor layer, and a semiconductor that supplies a first element to a region where the gate electrode does not overlap via a gate insulating layer; A method for fabricating the device.

[0010] The first element may be, for example, phosphorus, boron, magnesium, aluminum, or silicon. be.

[0011] The metal oxide layer preferably has an aluminum oxide film. Preferably, the metal oxide layer and the semiconductor layer have the same metal oxide.

[0012] The steps performed after removing the metal oxide layer are each performed at a temperature equal to or lower than the temperature of the heat treatment. It is preferable to do so.

[0013] The gate insulating layer includes a first layer on the semiconductor layer, a second layer on the first layer, and a third layer on the second layer. The deposition rate of the first layer is preferably lower than the deposition rate of the second layer. It is preferable that the deposition rate of the third layer is lower than the deposition rate of the second layer. [Effects of the Invention]

[0014] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. A semiconductor device can be provided.

[0015] The description of these effects does not preclude the existence of other effects. However, it is not necessary to have all of these effects. , it is possible to extract effects other than these. [Brief explanation of the drawings]

[0016] [Figure 1] 1A is a top view illustrating an example of a transistor, and FIGS. 1B and 1C are cross-sectional views illustrating an example of a transistor. [Figure 2] FIG. 1 is a cross-sectional view illustrating an example of a transistor. [Figure 3] 1A is a top view illustrating an example of a transistor, and FIGS. 1B and 1C are cross-sectional views illustrating an example of a transistor. [Figure 4] FIG. 1 is a cross-sectional view illustrating an example of a transistor. [Figure 5] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 9] FIG. 1 is a top view illustrating an example of a display device. [Figure 10] FIG. 1 is a cross-sectional view showing an example of a display device. [Figure 11] FIG. 1 is a cross-sectional view showing an example of a display device. [Figure 12] FIG. 1 is a cross-sectional view showing an example of a display device. [Figure 13] FIG. 1 is a cross-sectional view showing an example of a display device. [Figure 14] 1A is a block diagram showing an example of a display device, and FIGS. 1B and 1C are circuit diagrams showing an example of a display device. [Figure 15] 1A, 1B, and 1C are circuit diagrams showing an example of a display device, and FIG. 1B is a timing chart of the display device. [Figure 16] FIG. 2 is a diagram showing an example of a display module. [Figure 17] 1A and 1B are diagrams illustrating examples of electronic devices. [Figure 18] 1A and 1B are diagrams illustrating examples of electronic devices. [Figure 19] 1A and 1B are diagrams illustrating examples of electronic devices. [Figure 20] 1A and 1B are diagrams illustrating examples of electronic devices. [Figure 21] FIG. 3 is a cross-sectional view showing a transistor of a comparative sample according to Example 1. [Figure 22] 4 is a graph showing electrical characteristics of the transistor according to Example 1. [Figure 23] 4 is a graph showing electrical characteristics of the transistor according to Example 1. [Figure 24] 4 is a graph showing the reliability evaluation results of the transistor according to Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0017] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents described.

[0018] In the configuration of the invention described below, the same parts or parts having similar functions are designated by the same reference numerals. The same reference numerals are used in common among different drawings, and the repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be added.

[0019] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in reality for ease of understanding. Therefore, the disclosed invention may not necessarily represent the position, size, range, etc. Furthermore, the present invention is not limited to the position, size, range, etc. disclosed in the drawings.

[0020] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." Alternatively, for example, the term "insulating film" can be changed to " The term "insulating layer" may be changed to "insulating layer."

[0021] In this specification, the channel length direction of a transistor is the direction of the length between the source region and the drain region. The channel length direction is one of the directions parallel to the line connecting the two points at the shortest distance. , which corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the on state. The channel width direction is the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and channel width direction are not fixed. There are cases where this happens.

[0022] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is in an off state (non- The drain current when the device is in the on state (also called the on-state or off-state). Unless otherwise specified, for n-channel transistors, the voltage between the gate and source, V gs Gashi Threshold voltage V th (For p-channel transistors, V th (higher than) This refers to

[0023] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. In this embodiment, a transistor will be specifically used as a semiconductor device. explain.

[0024] In the semiconductor device of one embodiment of the present invention, a semiconductor layer containing a metal oxide is formed, and an oxide film is formed on the semiconductor layer. forming a gate insulating layer containing a metal oxide; forming a metal oxide layer on the gate insulating layer; After forming the metal oxide layer, a heat treatment is performed, and after the heat treatment, the metal oxide layer is removed. After removing the semiconductor layer, a gate electrode is formed on the gate insulating layer so as to overlap a part of the semiconductor layer. A first element is supplied to a region of the conductor layer that is not overlapped with the gate electrode through the gate insulating layer. It is formed by adding (also called adding or injecting)

[0025] In one embodiment of the present invention, after forming a semiconductor layer, a gate insulating layer, and a metal oxide layer, a gate insulating layer is formed. Before forming the electrode, a heat treatment is performed. Oxygen can be supplied.

[0026] The metal oxide layer is preferably formed in an atmosphere containing oxygen. During the deposition of the semiconductor layer, oxygen can be supplied into the gate insulating layer and further into the semiconductor layer.

[0027] It is preferable that the metal oxide layer is difficult to permeate oxygen. The oxygen is prevented from being released to the metal oxide layer side, and the oxygen is supplied to the semiconductor layer. Therefore, oxygen vacancies (V O :oxygen vaca This can compensate for the loss of charge (ncy), improving the reliability of the transistor. .

[0028] For example, an aluminum oxide film can be used as the metal oxide layer.

[0029] Alternatively, the metal oxide layer and the semiconductor layer preferably contain the same metal oxide.

[0030] When the metal oxide layer is conductive, the metal oxide layer is processed into an island shape and left as it is, and the gate electrode is formed on the island. However, depending on the material and processing method of the metal oxide layer, For example, if the metal oxide layer is deformed, the metal oxide layer may be damaged. This reduces the coverage of the layer formed on the material layer.

[0031] Furthermore, even if the metal oxide layer has insulating properties, the metal oxide layer may be left as is and the gate may be removed. When used as a part of a transistor insulating layer, the reliability of the transistor may be reduced. Depending on the film quality of the metal oxide layer, the interface between the previously formed gate insulating layer and the metal oxide layer may Or, there is a risk that a defect level may be formed in the vicinity thereof.

[0032] Here, gate bias heat (Gat The GBT stress test is performed under the applied bias temperature. This is a type of rapid test that detects, in a short time, changes in transistor characteristics that occur over a long period of use. Among them, the gate is positive with respect to the source potential and drain potential. The test is called PBTS (Positive Bias Test) and is held at high temperature while applying a potential of Temperature Stress) test, applying a negative voltage to the gate, The test is called NBTS (Negative Bias Temperature Test). It is also called a PBT Stress test, which is performed under the irradiation of light such as white LED light. The S test and NBTS test were performed using PBTIS (Positive Bias Temperature Standards) Perature Illumination Stress Test, NBTIS (Ne gative Bias Temperature Illumination Str This is called the ESS test.

[0033] In an n-type transistor using a metal oxide as the semiconductor layer, when the transistor is in the on state, When the gate is placed in the state where current flows, a positive potential is applied to the gate. The amount of variation in threshold voltage is one of the important items to pay attention to as an index of transistor reliability. This becomes:

[0034] When a metal oxide layer is present between the gate electrode and the gate insulating layer, The amount of variation in the threshold voltage during the PBTS test of a transistor is larger than when the There is (see Example 1).

[0035] Therefore, in one embodiment of the present invention, after the heat treatment, the metal oxide layer is completely removed. By removing the metal oxide layer, the reliability of the transistor can be improved.

[0036] The metal oxide layer is preferably removed by wet etching. By using a gate insulating layer, the gate insulating layer is prevented from being etched simultaneously with the metal oxide layer. This can prevent the thickness of the gate insulating layer from being reduced, and can be made uniform.

[0037] Then, a gate electrode is formed, and the first element is supplied to the semiconductor layer using the gate electrode as a mask. By doing so, a pair of low resistance regions can be formed in the semiconductor layer. A channel forming region overlapping with the gate electrode and a pair of low resistance regions sandwiching the channel forming region. and a region.

[0038] The first element may be, for example, phosphorus, boron, magnesium, aluminum, or silicon. be.

[0039] Note that the above-described heat treatment is performed relatively quickly because oxygen is sufficiently supplied from the gate insulating layer to the semiconductor layer. On the other hand, after removing the metal oxide layer, Compared to when a metal oxide layer was provided, oxygen is more easily released from the semiconductor layer and gate insulating layer. For example, oxygen contained in the channel formation region of the semiconductor layer or the gate insulating layer Therefore, the metal oxide layer is removed, and the metal may diffuse into the low resistance region or the gate electrode. The subsequent steps are preferably carried out at a temperature equal to or lower than the temperature of the heat treatment described above. This can prevent oxygen vacancies from being formed in the semiconductor layer. If the oxygen vacancy is small and the carrier density is low, the off-state current of the transistor can be significantly reduced. This also improves the reliability of the transistor.

[0040] Generally, to reduce the resistance of silicon, heat treatment is required after supplying impurities. On the other hand, the semiconductor layer containing the metal oxide has a low resistance when the first element is supplied. Therefore, there is no need to perform heat treatment to reduce the resistance. Even if a step of forming a pair of low resistance regions in the semiconductor layer is subsequently performed, oxygen vacancies are sufficiently reduced. The channel forming region has an extremely low carrier density, and the source region and the It is possible to form a semiconductor layer having both a gate electrode and a drain region, and the semiconductor layer has excellent electrical characteristics. As a result, a highly reliable semiconductor device can be realized.

[0041] In one embodiment of the present invention, the first element can also be supplied to the gate insulating layer. In practice, by using the gate electrode as a mask, the gate insulating layer is mainly The first element is supplied to the portion overlapping the low resistance region, and the first element is supplied to the portion overlapping the channel formation region of the semiconductor layer. Therefore, after the first element is supplied, the heating process is performed. When the gate insulating layer is removed, oxygen is supplied to the channel forming region, and the channel forming region is On the other hand, oxygen is supplied from the gate insulating layer to the low-resistance region. This also shows that oxygen deficiency is sufficiently reduced and the electrical resistance is not easily increased. A channel forming region with extremely low carrier density and a source region and a drain region with extremely low electrical resistance are formed. It is possible to form a semiconductor layer that has both an insulating region and a high-performance semiconductor layer, which has excellent electrical properties and is highly reliable. Therefore, a highly reliable semiconductor device can be realized.

[0042] [Configuration example 1] FIG. 1A shows a top view of a transistor 100. FIG. 1B shows the top view of the transistor 100 shown in FIG. FIG. 1C shows a cross-sectional view of the area between the dashed line A1 and A2 in FIG. The dashed line A1-A2 is the channel length direction, and the dashed line B1-B The two directions correspond to the channel width direction. Some elements (such as the gate insulating layer) are omitted. In the subsequent drawings, some of the components are omitted, as in FIG. 1(A).

[0043] The transistor 100 includes an insulating layer 103, an island-shaped semiconductor layer 108, a gate insulating layer 110, a gate The semiconductor device has a port electrode 112 and an insulating layer 118 .

[0044] The insulating layer 103 is provided on the substrate 102. The semiconductor layer 108 is formed on the insulating layer 103. The gate insulating layer 110 is formed on the upper surface of the insulating layer 103 and the semiconductor layer 108. The gate electrode 112 is provided on the gate insulating layer 110. The gate electrode 112 has a portion overlapping the semiconductor layer 108 via the gate insulating layer 110. The insulating layer 118 is formed on the upper surface of the gate insulating layer 110 and on the upper surface and It is installed to cover the side.

[0045] The transistor 100 is a top-gate transistor having a gate electrode 112 on the semiconductor layer 108. This is a transistor.

[0046] As shown in FIGS. 1A and 1B, the transistor 100 includes a conductive layer 12 on an insulating layer 118. The conductive layer 120a and the conductive layer 120b may be formed of the conductive layer 120a and the conductive layer 120b. One functions as a source electrode and the other functions as a drain electrode. and conductive layer 120b are formed by openings provided in insulating layer 118 and gate insulating layer 110, respectively. The opening 141a or the opening 141b is electrically connected to the low resistance region 108n, which will be described later. To be continued.

[0047] The semiconductor layer 108 is a semiconductor layer containing a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. It is preferable that

[0048] The semiconductor layer 108 has a region overlapping with the gate electrode 112 and a pair of low-resistance regions sandwiching the region. The region of the semiconductor layer 108 that overlaps with the gate electrode 112 is a transistor. The pair of low resistance transistors 100 function as a channel forming region where the channel of the transistor 100 can be formed. Resistive regions 108n function as the source and drain regions of transistor 100.

[0049] The low resistance region 108n is a region having a lower resistance than the channel formation region. Regions with high carrier density, regions with higher oxygen vacancy density than the channel formation region, channel-shaped It can also be called a region with a higher impurity concentration than the growth region, or a region that is n-type.

[0050] The low resistance region 108n is a region containing one or more impurity elements. Examples of elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Sodium, magnesium, silicon, and rare gases (helium, neon, argon, crypto The pair of low resistance regions 108n may include boron, phosphorus, aluminum, etc. Preferably, the material contains aluminum, magnesium, or silicon, and preferably contains boron or phosphorus. It is more preferable to

[0051] The impurities contained in the low resistance region 108n may be removed by the influence of heat during the manufacturing process. Some of the impurity elements may diffuse into the channel formation region. The concentration of the impurity element in the low resistance region 108n is preferably one-tenth or less of the concentration of the impurity element in the low resistance region 108n. It is preferable that the difference is 1 / 100 or less.

[0052] The gate insulating layer 110 is in contact with the channel forming region of the semiconductor layer 108 and is connected to the gate electrode 1. The gate insulating layer 110 has an area overlapping the pair of low resistance regions 12 of the semiconductor layer 108. It has a region that is in contact with 108n and does not overlap with gate electrode 112.

[0053] When the semiconductor layer 108 includes a metal oxide, the gate insulating layer 110 preferably includes an oxide. In particular, the gate insulating layer 110 is preferably an oxide film that can release oxygen when heated. Desirable.

[0054] The gate insulating layer 110 containing oxide is provided on the upper surface of the semiconductor layer 108, and the semiconductor layer 108 is heated. By performing the treatment, oxygen released from the gate insulating layer 110 is supplied to the semiconductor layer 108. This makes it possible to compensate for oxygen vacancies in the semiconductor layer 108, improving reliability. It is possible to realize a transistor with high performance.

[0055] In one embodiment of the present invention, the gate electrode 112 is formed and an impurity element is supplied to the semiconductor layer 108. Before this, a heat treatment is performed to supply oxygen from the gate insulating layer 110 to the semiconductor layer 108. On the other hand, a transistor, a semiconductor device or a display device having the transistor, etc. Depending on the configuration, the formation of the gate electrode 112 and the supply of impurity elements to the semiconductor layer 108 In some cases, a further heat treatment is performed after the above process. There is a risk that oxygen contained in the formed region may diffuse into the low resistance region 108n or the gate electrode 112. In addition, there is a possibility that oxygen is supplied from the gate insulating layer 110 to the low-resistance region 108n. When oxygen is supplied to the low resistance region 108n, the carrier density decreases and the electrical resistance increases. It may rise.

[0056] Therefore, in the gate insulating layer 110, the region in contact with the pair of low resistance regions 108n, i.e. Preferably, the impurity element is contained in a region that does not overlap with the gate electrode 112. In the region of the gate insulating layer 110 that does not overlap with the gate electrode 112, the impurity concentration is higher than the region of the edge layer 110 that overlaps the gate electrode 112 and lower than the low resistance region 108n It is preferable that the oxide film capable of releasing oxygen by heating has a region where the temperature is as low as possible. By supplying impurity elements, the amount of oxygen released can be reduced. Therefore, the region of the gate insulating layer 110 in contact with the low resistance region 108n contains the above-mentioned impurity element. If the gate insulating layer 110 is in a low-resistance region 108n, oxygen is less likely to be supplied to the low-resistance region 108n. The low resistance region 108n can maintain a low electrical resistance.

[0057] By adopting such a structure, oxygen vacancies are sufficiently reduced, and a chip with an extremely low carrier density can be obtained. a channel forming region and a source region and a drain region with extremely low electrical resistance; A semiconductor device with excellent electrical characteristics and high reliability can be realized.

[0058] The insulating layer 103 and the gate insulating layer 110 that are in contact with the channel forming region of the semiconductor layer 108 are The insulating layer 103 and the gate insulating layer 110 each preferably contain an oxide. An oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film is used. This allows the insulating film to be formed by heat treatment or the like in the manufacturing process of the transistor 100. The oxygen desorbed from the layer 103 and the gate insulating layer 110 is transported to the channel forming region of the semiconductor layer 108. By supplying oxygen, oxygen vacancies in the semiconductor layer 108 can be reduced.

[0059] FIG. 2 shows an enlarged cross-sectional view of a region P surrounded by a dashed line in FIG. 1(B).

[0060] The gate insulating layer 110 has a region 110d containing the above-described impurity element. is located at least at or near the interface between the gate insulating layer 110 and the low resistance region 108n. The region 110d is a region where the semiconductor layer 108 and the gate electrode 112 are not provided. In the region, at least the interface between the gate insulating layer 110 and the insulating layer 103 or its vicinity As shown in FIGS. 1B, 1C, and 2, the region 110d is It is preferable that the insulating layer 104 is not provided in a portion in contact with the channel formation region of the semiconductor layer 108. .

[0061] The insulating layer 103 has the above-mentioned impurity element at or near the interface where it contacts the gate insulating layer 110. 2, the region 103d has an insulating layer 103d. It may also be provided at or near the interface where 103 and low resistance region 108n come into contact. At this time, the impurity concentration of the region 103d overlapping with the low resistance region 108n is The concentration is lower than that of the portion in contact with the gate insulating layer 110 .

[0062] Here, the impurity concentration in the low resistance region 108n is higher the closer it is to the gate insulating layer 110. It is preferable that the concentration gradient be such that the concentration of the low-resistance region 108n is high. Since the resistance becomes lower toward the upper portion, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be reduced. In addition, the concentration can be reduced uniformly throughout the low resistance region 108n. Since the total amount of impurity elements in the low resistance region 108n can be reduced compared to when the low resistance region 108n is fabricated Keep the amount of impurities that can diffuse into the channel formation region due to the influence of heat during the process low. can be done.

[0063] The impurity concentration in the region 110d becomes higher as it approaches the low-resistance region 108n. It is preferable to have a concentration gradient such that the oxide film capable of releasing oxygen by heating is used. In the gate insulating layer 110, the region 110d containing the impurity element described above has a high conductivity compared to the other regions. Therefore, the low resistance region of the gate insulating layer 110 can suppress the release of oxygen compared to the low resistance region of the gate insulating layer 110. The region 110d located at or near the interface with the region 108n is a blocking region for oxygen. This layer functions as a blocking layer and can effectively reduce the amount of oxygen supplied to the low resistance region 108n. do.

[0064] The impurity element is supplied to at least the semiconductor layer 108 using the gate electrode 112 as a mask. Furthermore, it is preferable to supply the impurity element to the gate insulating layer 110 as well. This allows the region 110d to be formed in a self-aligned manner at the same time as the low resistance region 108n is formed. It can be formed.

[0065] 2 and the like, the portion of the gate insulating layer 110 with a high impurity concentration is Region 110d is shown as a gate insulating layer to exaggerate its location at or near the interface. Although the hatched pattern is only shown near the semiconductor layer 108 in 110, In this case, the gate insulating layer 110 contains the above impurity elements throughout its entire thickness.

[0066] The impurity elements can be supplied by plasma ion doping or ion implantation. These methods are preferred because the depth of ions to be doped can be easily adjusted. This makes it easier to target the region including the silicon dioxide film 10 and the semiconductor layer 108 and add ions thereto.

[0067] The supply conditions of the impurity element are as follows: The impurity concentration at or near the interface between the gate insulating layer 108 and the gate insulating layer 110 is the highest. This allows the semiconductor layer 108 and the gate insulating layer to be formed in a single process. The impurity element can be supplied to both the low resistance region and the layer 110 at an appropriate concentration. By supplying impurity elements at a high concentration to the upper part of 108n to reduce the resistance, a low resistance region 10 The contact resistance between the gate insulating layer 18n and the source electrode or the drain electrode can be reduced. By forming a region with a high concentration of impurity elements in a portion close to the low resistance region 108n of the semiconductor device 10, The oxygen diffusibility in this portion is reduced, and the oxygen in the gate insulating layer 110 moves toward the low resistance region 108n. This can further suppress the diffusion of the particles.

[0068] The low resistance region 108n and the region 110d each have an impurity concentration of 1×10 19 atom s / cm 3 More than 1×10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atom s / cm 3 5x10 or more 22 atoms / cm 3 Less than 1×10, more preferably 20 at oms / cm 3 More than 1×10 22 atoms / cm 3 It is preferred to include a region that is: The low-resistance region 108n has a lower impurity concentration than the region 110d of the gate insulating layer 110. It is preferable that the low resistance region 108n has a high resistance portion, because this can lower the electrical resistance of the low resistance region 108n.

[0069] The concentration of impurities contained in the low resistance region 108n and the region 110d is determined by, for example, the secondary ion mass Analysis method (SIMS: Secondary Ion Mass Spectrometry) ) and X-ray Photoelectron Spectroscopy (XPS). When XPS analysis is used, the analysis can be performed by other analytical methods such as XPS. can be achieved by combining ion sputtering from the front or back side with XPS analysis. , the concentration distribution in the depth direction can be known.

[0070] When an element that easily bonds with oxygen is used as the impurity element, the impurity element is In other words, the impurity element removes oxygen from the semiconductor layer 108. As a result, oxygen vacancies are generated in the semiconductor layer 108, and the oxygen vacancies are bonded to hydrogen in the film. Furthermore, the impurity elements in the semiconductor layer 108 are stable in an oxidized state. Since it exists in the A low resistance region 108n can be realized.

[0071] When an element that easily bonds with oxygen is used as an impurity element, the gate The impurity element is also present in the insulating layer 110 in a state of being bonded to oxygen. The impurity element is bonded to the metal and stabilized, so that the region containing the impurity element retains almost no oxygen even after heating. This results in a state where almost no oxygen is desorbed, making it difficult for oxygen to diffuse into other layers. The supply of oxygen from the gate insulating layer 110 to the low resistance region 108n is suppressed, and the channel Therefore, the resistance of the low-resistance region 108n can be increased. This prevents the formation of oxygen vacancies in the channel formation region, resulting in good electrical properties and A highly reliable transistor can be realized.

[0072] The impurity element is stabilized by bonding with oxygen in the semiconductor layer 108 and the gate insulating layer 110. It is preferable to use an element, for example, an element whose oxide can exist in a solid state under standard conditions. It is preferable to use the following. Particularly preferable elements are rare gases and typical non-metallic elements other than hydrogen. boron, typical metal elements, and transition metal elements, in particular boron, phosphorus, aluminum, Magnesium and silicon are preferred.

[0073] For example, when boron is used as the impurity element, the low resistance region 108n and the region 110d The boron contained in the material can exist in a state of being bonded to oxygen. This can be seen in the XPS analysis as follows: This can be confirmed by observing the spectral peaks due to B2O3 bonds. In the analysis, a spectral peak was observed due to the existence of elemental boron. The peak intensity is so low that it is not visible or is buried in the background noise at the lower limit of measurement. and becomes smaller.

[0074] The insulating layer 118 functions as a protective layer to protect the transistor 100. The gate insulating layer 110 has a function of preventing oxygen that may be released from the gate insulating layer 110 from diffusing to the outside. For example, inorganic insulating materials such as oxides or nitrides can be used. More specific examples include silicon nitride, silicon nitride oxide, silicon oxynitride, and silicon oxide. Aluminum, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium aluminium An inorganic insulating material such as laminate can be used.

[0075] [Configuration example 2] FIG. 3A shows a top view of the transistor 100A. FIG. 3(C) shows a cross-sectional view of the area between the dashed line A1 and A2 in FIG. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1- The B2 direction corresponds to the channel width direction.

[0076] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 is connected to the semiconductor layer 108 and the gate electrode 112. There is an overlapping area.

[0077] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode The gate electrode 112 functions as a second gate electrode (also referred to as a top gate electrode). A part of the insulating layer 103 functions as a first gate insulating layer. A portion of the gate insulating layer 110 functions as a second gate insulating layer.

[0078] The portion of the semiconductor layer 108 that overlaps with at least one of the gate electrode 112 and the conductive layer 106 , which functions as a channel forming region. The portion of the gate electrode 112 of the semiconductor substrate 8 that overlaps with the gate electrode 112 is sometimes called a channel forming region. The portion that does not overlap with the port electrode 112 but overlaps with the conductive layer 106 (the portion including the low-resistance region 108n) Channels can also be formed.

[0079] 3C, the conductive layer 106 is formed between the gate insulating layer 110 and the insulating layer 103. The gate electrode 112 may be electrically connected to the insulating film 114 through an opening 142 formed in the insulating film 114. This allows the conductive layer 106 and the gate electrode 112 to be applied with the same potential.

[0080] The conductive layer 106 is made of the same material as the gate electrode 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. This is preferable because it allows

[0081] As shown in FIGS. 3A and 3C, the gate electrode 1 It is preferable that the conductive layer 106 and the semiconductor layer 108 protrude outward beyond the edge of the semiconductor layer 108. At this time, as shown in FIG. 3(C), the entire semiconductor layer 108 in the channel width direction is The gate electrode 112 and the conductive layer 106 are covered with the gate insulating layer 110 and the insulating layer 103. The composition is as follows.

[0082] With this configuration, the semiconductor layer 108 is heated by an electric field generated by the pair of gate electrodes. In this case, the conductive layer 106 and the gate electrode 112 are electrically surrounded. It is preferable to apply the same potential to the semiconductor layer 108. Since an electric field for the purpose can be effectively applied, the on-current of the transistor 100A can be increased. This also makes it possible to miniaturize the transistor 100A.

[0083] Note that the gate electrode 112 and the conductive layer 106 may not be connected to each other. A constant potential is applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A is applied to the other. At this time, the transistor 100A is turned on by a potential applied to one electrode. It is also possible to control the threshold voltage when driven by the other electrode.

[0084] [Application example] Next, as an application example, a semiconductor device according to one embodiment of the present invention including a transistor and a capacitor will be described. 4. Specifically, the semiconductor layer 108c containing impurities is An example in which a transistor and a capacitor are formed on the same surface using a metal oxide film as one electrode will be described. do.

[0085] The capacitor 130A shown in FIG. 4A is a capacitor element 130A of the transistor 100 (FIGS. 1A to 1C). It is set up alongside.

[0086] The capacitor element 130A shown in FIG. 4B is a capacitor element of the transistor 100A (FIGS. 3A to 3C). ) and is placed alongside.

[0087] The capacitive element 130A is disposed between the semiconductor layer 108c and the conductive layer 120b and functions as a dielectric. The gate insulating layer 110 and the insulating layer 118 are provided.

[0088] The semiconductor layer 108c is provided on the same plane as the semiconductor layer 108. For example, 8c is a metal oxide film formed by processing the same metal oxide film as the semiconductor layer 108, and then forming a low-resistance region 108n. The impurity element can be supplied to form the SiO 2 layer.

[0089] By using such a structure, a capacitor element can be formed at the same time as a transistor without increasing the manufacturing process. 130A can be produced.

[0090] The capacitance element 130B shown in FIG. 4C is a capacitance element of the transistor 100A (FIGS. 3A to 3C). ) and is placed alongside.

[0091] The capacitive element 130B is disposed between the conductive layer 106c and the semiconductor layer 108c and functions as a dielectric. The insulating layer 103 is provided.

[0092] The conductive layer 106c is provided on the same surface as the conductive layer 106. The same conductive film as the layer 106 can be processed to form the layer 106 .

[0093] The capacitance element 130B can have a thinner dielectric than the capacitance element 130A, so that the capacitance element 130B can have a larger capacitance. It can be a capacitive element of a capacitor.

[0094] [Components of semiconductor device] Next, the components included in the semiconductor device of this embodiment will be described in detail. The description of components that have already been described may be omitted.

[0095] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, single crystal semiconductors made of silicon or silicon carbide are Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates The substrate 102 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a substrate having a semiconductor element formed thereon may be used as the substrate 102. It's fine.

[0096] In addition, a flexible substrate is used as the substrate 102, and the transistor 100 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100 or the like. The release layer may be removed from the substrate 102 after a semiconductor device is partially or entirely completed thereon. The transistor 100 can be separated and transferred to another substrate. can be transferred onto substrates with poor heat resistance or flexible substrates.

[0097] The insulating layer 103 is formed, for example, by using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. In order to improve the interface characteristics with the semiconductor layer 108, the insulating layer 1 In step 03, at least a region in contact with the semiconductor layer 108 is preferably formed of an oxide insulating film. It is also preferable to use a film that releases oxygen when heated for the insulating layer 103. .

[0098] The insulating layer 103 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide Any of these may be used, and the layer may be provided as a single layer or a multilayer.

[0099] In addition, the insulating layer 103 may have a layer other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When a film is used, the surface in contact with the semiconductor layer 108 is pretreated with oxygen plasma or the like. It is preferable to carry out the oxidation of the surface or the vicinity of the surface.

[0100] A gate electrode 112, a conductive layer 106 functioning as a gate electrode, and a source electrode and a drain electrode are provided. The conductive layers 120a and 120b, which function as drain electrodes, are made of chromium, copper, aluminum, or the like. Aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel a metal element selected from the group consisting of zinc, iron, and cobalt, an alloy containing the above-mentioned metal element, or Each of these can be formed using an alloy or the like that combines the above-mentioned metal elements.

[0101] The gate electrode 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are provided with I n-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-T i-Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide Oxide conductors (OC) or metal oxides are used. It is also possible to do so.

[0102] In addition, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. When the metal oxide is heated, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. Conductive metal oxides can be called oxide conductors (OCs). .

[0103] The gate electrode 112 and the conductive layer 106 are each made of the above-mentioned oxide conductor (metal oxide ) and a conductive film containing a metal or an alloy. By using a conductive film containing an alloy, the wiring resistance can be reduced. The side of the electrode 112 that contacts the gate insulating layer 110 or the side of the conductive layer 106 that contacts the insulating layer 103 It is preferable to use a conductive film containing an oxide conductor for the insulating film.

[0104] The gate electrode 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b are Among the above-mentioned metal elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is preferable that the material has one or more selected from the following. In particular, tantalum nitride It is preferable to use a tantalum nitride film. The tantalum nitride film is electrically conductive and does not react with copper, oxygen, or Since it has a high barrier property against hydrogen and releases little hydrogen from itself, the semiconductor layer 1 The conductive film is suitable as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[0105] The gate insulating layer 110 may be a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, acid Zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film The insulating layer may include one or more of a silicon oxide film, a cerium oxide film, and a neodymium oxide film. The gate insulating layer 110 is not limited to a single layer, but may have a laminated structure of two or more layers. stomach.

[0106] At least the region of the gate insulating layer 110 that is in contact with the semiconductor layer 108 is made of an oxide insulating film. It is preferable that the oxygen content of the silicon dioxide film is in excess of the stoichiometric composition. In other words, the gate insulating layer 110 is an insulating film that can release oxygen. For example, the gate insulating layer 110 can be formed in an oxygen atmosphere, and the gate insulating layer 110 after the film formation can be formed in an oxygen atmosphere. The insulating layer 110 may be subjected to a heat treatment in an oxygen atmosphere, a plasma treatment, or the like. The gate insulating layer 110 is formed by depositing an oxide film on the gate insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the 10.

[0107] Furthermore, as the gate insulating layer 110, a material having a dielectric constant lower than that of silicon oxide or silicon oxynitride is used. A material with high conductivity, such as hafnium oxide, can also be used. By increasing the thickness, leakage current due to tunnel current can be suppressed. Hafnium is preferred because it has a higher dielectric constant than amorphous hafnium oxide.

[0108] The semiconductor layer 108 preferably includes an oxide semiconductor. Alternatively, the semiconductor layer 108 includes The silicon may be amorphous silicon or crystalline silicon. Examples include silicon (low-temperature polysilicon, single crystal silicon, etc.).

[0109] The semiconductor layer 108 is made of, for example, indium and M (M is gallium, aluminum, silicon, etc.). Ni, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium one or more selected from aluminum, tantalum, tungsten, and magnesium) and zinc In particular, M is aluminum, gallium, yttrium, and tin.

[0110] In particular, the semiconductor layer 108 is made of indium (In), gallium (Ga), and zinc (Zn It is preferable to use an oxide containing IGZO (also referred to as IGZO).

[0111] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form the In-M-Zn oxide film, The atomic ratio of the metal elements in the sputtering target used is In:M:Zn=1:1. :1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn =1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:1:3, In:M: Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, I n:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6 , In:M:Zn=5:2:5, etc.

[0112] When a target containing polycrystalline oxide is used as a sputtering target, the crystal This is preferable because it is easy to form the semiconductor layer 108 having the desired properties. The atomic ratio of 108 is the atomic ratio of the metal elements contained in the sputtering target. For example, the sputtering temperature for the semiconductor layer 108 is When the target composition is In:Ga:Zn=4:2:4.1 [atomic ratio], the deposited semiconductor The composition of the conductor layer 108 may be approximately In:Ga:Zn=4:2:3 [atomic ratio]. be.

[0113] When the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, the ratio of In When the atomic ratio is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more. Also, the atomic ratio of In:Ga:Zn=5:1:6 or When describing it as being close to the atomic ratio of Ga, when the atomic ratio of In is 5, the atomic ratio of Ga is 0.1. The atomic ratio of Zn is greater than or equal to 5 and less than or equal to 7. When describing that the numerical ratio is In:Ga:Zn=1:1:1 or close to it, When the atomic ratio is 1, the atomic ratio of Ga is greater than 0.1 and less than 2, and the atomic ratio of Zn is This includes cases where the ratio is greater than 0.1 and less than or equal to 2.

[0114] In the semiconductor layer 108, if the atomic ratio of In is higher than the atomic ratio of M (for example, Ga), This is preferable because it can increase the field effect mobility of the transistor. In this case, if the atomic ratio of M (e.g., Ga) is higher than the atomic ratio of In, oxygen vacancies are likely to be formed. Well, that's desirable.

[0115] The semiconductor layer 108 may also have a plurality of metal oxide layers stacked together. For example, the layer 8 may have two or more metal oxide layers with different crystallinity.

[0116] For example, the first metal oxide film to be formed has an atomic ratio of In to M (e.g., Ga). An In-M-Zn oxide film with a higher atomic ratio is formed, and the second metal oxide film is formed later. Then, an In-M-Zn oxide film in which the atomic ratio of M (e.g., Ga) is higher than the atomic ratio of In is obtained. This increases the field effect mobility of the transistor and The oxygen vacancies in the conductor layer 108 can be suppressed, and the electrical characteristics and reliability of the transistor can be improved. can.

[0117] Alternatively, by using the same sputtering target and varying the deposition conditions, It is preferable to form a plurality of metal oxide layers continuously without any gaps.

[0118] For example, the oxygen flow rate during the deposition of the first metal oxide film is set to be equal to the oxygen flow rate during the deposition of the second metal oxide film. The oxygen flow rate is set to be smaller than that during the formation of the first metal oxide film. The condition is set such that oxygen is not flowed during the deposition of the second metal oxide film. In addition, the first metal oxide film can be more effectively supplied than the second metal oxide film. On the other hand, the second layer provided on the upper side has low crystallinity and high electrical conductivity. The second metal oxide film is made to have higher crystallinity than the first metal oxide film, thereby Damage caused during processing of the gate insulating layer 8 and during deposition of the gate insulating layer 110 can be suppressed.

[0119] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%, preferably Preferably, it is 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is preferably set to 50% or more and 100% or less. Alternatively, it is 60% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably The ratio is preferably 90% or more and 100% or less, typically 100%. The conditions of pressure, temperature, power, etc. during film formation may be different between the first metal oxide film and the second metal oxide film. By keeping the conditions other than the element flow rate ratio the same, the time required for the film formation process can be shortened. Therefore, it is preferable.

[0120] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0121] The oxygen vacancies formed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancies, When a carrier source is generated in the semiconductor layer 108, the This causes a change in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage. In the semiconductor layer 108, it is preferable that the oxygen vacancies are as small as possible.

[0122] Therefore, in one aspect of the present invention, the insulating film near the semiconductor layer 108, specifically, the semiconductor The gate insulating layer 110 above the layer 108 and the insulating layer 103 below are formed by oxidation. The insulating layer 103 and the gate insulating layer 11 are formed by heat or the like during the manufacturing process. By transferring oxygen from the silicon dioxide to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 are reduced. This makes it possible to

[0123] Metal oxides applicable to the semiconductor layer will be described below.

[0124] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). For example, zinc oxynitride (ZnON) Any nitrogen-containing metal oxide may be used for the semiconductor layer.

[0125] In this specification and the like, CAAC (c-axis aligned crystal ), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

[0126] For example, the semiconductor layer is made of CAC (Cloud-Aligned Composite)-O S can be used.

[0127] CAC-OS or CAC-metal oxide is a material that has the function of conductivity in some parts. The material has an insulating function in part and a semiconductor function in the whole. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a material, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0128] In addition, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region are formed at the nanoparticle level in the material. The conductive and insulating regions may be separated by a thin film. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0129] In addition, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are The peripheral region is 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. The following sizes may be dispersed in the material:

[0130] In addition, CAC-OS or CAC-metal oxide has different band gaps. For example, CAC-OS or CAC-metal oxidized de is a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. In this configuration, when carriers flow, In the narrow gap component, carriers mainly flow. The component having a wide gap acts complementary to the component having a narrow gap. Carriers also flow into the wide-gap component in conjunction with the component with a wide gap. AC-OS or CAC-metal oxide is placed in the channel formation region of the transistor. When used, the transistor has a high current driving force in the on state, i.e., a large on-current. Furthermore, high field-effect mobility can be obtained.

[0131] That is, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite It can also be called a matrix composite.

[0132] Oxide semiconductors (metal oxides) are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (ca xis aligned crystalline oxide semiconductor tor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide de semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and amorphous and oxide semiconductors.

[0133] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0134] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. In addition, the distortion may have a lattice arrangement such as a pentagon or a heptagon. In CAAC-OS, clear grain boundaries are observed even near the strain. It is difficult to confirm the grain boundary due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high SiO2 content in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is because distortion can be tolerated by, for example, adjusting the distortion.

[0135] The CAAC-OS also includes a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element M , zinc, and oxygen layers (hereinafter referred to as (M, Zn) layers) are stacked. It is also called a layered structure. Indium and element M are mutually substitutable. When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) layer and Also, when indium in the In layer is replaced with element M, the (In,M) layer It can also be expressed as:

[0136] CAAC-OS is a metal oxide with high crystallinity. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having the CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0137] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0138] Indium gallium oxide, a type of metal oxide containing indium, gallium, and zinc, is In the case of IGZO, the nanocrystals mentioned above provide a stable structure. In particular, IGZO tends to have difficulty growing crystals in the atmosphere. Small crystals (e.g., crystals of a few mm or a few cm) are more likely to be formed than large crystals (here, crystals of a few mm or a few cm). , the nanocrystals mentioned above) may be structurally more stable.

[0139] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has voids or low density areas. The e-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0140] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-lik The crystalline structure may have two or more of e-OS, nc-OS, and CAAC-OS.

[0141] The metal oxide film functioning as a semiconductor layer is heated by either an inert gas or an oxygen gas. The metal oxide film can be formed by using both of the oxygen flow rate ratio and the oxygen flow rate ratio. However, in order to obtain a transistor with high field effect mobility, In this case, the oxygen flow rate ratio (oxygen partial pressure) during the deposition of the metal oxide film is 0% or more and 3% or less. 0% or less is preferable, 5% or more and 30% or less is more preferable, and 7% or more and 15% or less is even more preferable. preferable.

[0142] The metal oxide preferably has an energy gap of 2 eV or more, and more preferably 2.5 eV or more. It is more preferable that the energy is 3 eV or more, and even more preferable that the energy is 3 eV or more. By using metal oxides with a wide energy gap, the off-state current of transistors can be reduced. This can be done.

[0143] [Example of manufacturing method] Next, a method for manufacturing a transistor of one embodiment of the present invention will be described with reference to FIGS. Here, a method for manufacturing the transistor 100A shown in Configuration Example 2 will be described. FIG. 8 shows the channel length direction and the channel width direction at each stage of the manufacturing process of the transistor. The cross sections are shown side by side.

[0144] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. , Chemical Vapor Deposition (CVD) method, Vacuum evaporation, Pulsed Laser Deposit (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be a plasma-enhanced chemical vapor deposition (PECVD) method. There are methods such as VD (Plasma Enhanced CVD) and thermal CVD. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). c CVD) method.

[0145] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are formed by spin coating, de-coating, Dip, spray coating, inkjet, dispensing, screen printing, offset printing Brush, doctor knife, slit coat, roll coat, curtain coat, knife coat, etc. It can be formed by the method described above.

[0146] Furthermore, when processing thin films that constitute semiconductor devices, photolithography or the like is used. Alternatively, nanoimprinting, sandblasting, lift-off, and other methods can be used. The thin film may be processed by a method such as a film formation method using a shielding mask such as a metal mask. Alternatively, island-shaped thin films may be formed directly by the above method.

[0147] There are two typical photolithography methods: A resist mask is formed on the thin film, and the thin film is processed by etching or the like. The other method is to remove the mask after forming a photosensitive thin film. This is a method in which the thin film is developed and processed into a desired shape.

[0148] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), g Uses light from ultraviolet rays (wavelength 436 nm), h rays (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure technology. Using extreme ultraviolet (EUV) and X-rays, Also, instead of light used for exposure, an electron beam can be used. However, it is preferable to use X-rays or electron beams, since they allow extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required. It is essential.

[0149] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. etc. can be used.

[0150] First, as shown in FIG. 5(A), a conductive film is formed on a substrate 102 and processed by etching. In this way, the conductive layer 106 functioning as a gate electrode is formed.

[0151] Next, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 5(A)).

[0152] The structure of the insulating layer 103 will be described in more detail with reference to FIGS. 6A and 6B.

[0153] The insulating layer 103 shown in FIG. 6A is made up of an insulating layer 103a and an insulating layer 103b on the insulating layer 103a. The insulating layer 103b has a three-layer structure, and an insulating layer 103c on the insulating layer 103b.

[0154] The insulating layer 103 shown in FIG. 6B is made up of an insulating layer 103e and an insulating layer 103 on the insulating layer 103e. a, an insulating layer 103b on the insulating layer 103a, and an insulating layer 103c on the insulating layer 103b. The insulating layer 103 shown in FIG. 6(B) has a four-layer structure. 3, with an insulating layer 103e added.

[0155] The insulating layer 103a and the insulating layer 103b are nitride insulating films formed under different film forming conditions. Preferably, the insulating layer 103c is an insulating oxide film. The insulating layer 103a and the insulating layer 103b are formed under different conditions. The insulating layer 103e, the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c are preferably It is preferable that the insulating layers are formed successively without being exposed to the air. The insulating layer 103a, the insulating layer 103b, and the insulating layer 103c are each formed by a plasma CVD method. It is more preferable to form

[0156] The insulating layer 103e, the insulating layer 103a, and the insulating layer 103b are each made of silicon nitride. nitride insulating films such as silicon nitride film, silicon nitride oxide film, aluminum nitride film, and hafnium nitride film The insulating layer 103c can be formed using a silicon oxide film, a silicon oxynitride film, or Silicon nitride oxide film, aluminum oxide film, hafnium oxide film, yttrium oxide film, acid Zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film An oxide insulating film such as a silicon oxide film, a cerium oxide film, or a neodymium oxide film can be used.

[0157] For example, the insulating layer 103e, the insulating layer 103a, and the insulating layer 103b may each be made of plastic. A silicon nitride film is formed by the plasma CVD method, and a silicon nitride film is formed as the insulating layer 103c by the plasma CVD method. It is preferable to form a silicon oxynitride film by using a silicon oxynitride film.

[0158] The insulating layer 103a is preferably a film with high breakdown voltage and low stress. By using a film with low stress, warping of the substrate can be suppressed. This makes it easy to transport the material even when using a mold, thereby shortening the manufacturing time and improving the manufacturing yield. In addition, the insulating layer 103a is thicker than the insulating layer 103e and the insulating layer 103b. This makes it possible to increase productivity of the insulating layer 103.

[0159] The insulating layer 103e and the insulating layer 103b each prevent the diffusion of impurities from the substrate 102 side. It is preferable that the film is dense and can block the dust.

[0160] Specifically, the insulating layer 103e has a blocking effect against the metal elements contained in the conductive layer 106. For example, when copper is used for the conductive layer 106, it is desirable that the copper has a high conductivity. In order to prevent the diffusion of the conductive material, it is preferable to provide an insulating layer 103e. When the layer 106 is formed using a metal element that is difficult to diffuse into the insulating layer 103, 103e may not be provided.

[0161] It is desirable that the insulating layer 103b releases a small amount of hydrogen and has a high blocking property against hydrogen. When hydrogen is released from the insulating layer 103, it bonds with oxygen in the semiconductor layer 108 and becomes water. As a result of the oxygen being released, oxygen vacancies may be formed in the semiconductor layer 108. When hydrogen enters the electron vacancy, it forms a donor, increasing the carrier density. By suppressing the release of hydrogen from the transistor, fluctuations in transistor characteristics are suppressed, improving reliability. It can be done.

[0162] For example, the pressure and / or power during the deposition of the insulating layer 103a may be adjusted to the same value as that during the deposition of the insulating layer 103b. By lowering the film formation conditions, the stress of the insulating layer 103a is made smaller than the stress of the insulating layer 103b. In addition, the insulating layer 103b can be made to have a higher blocking ability against hydrogen than the insulating layer 103a. It is possible to make a film with high locking properties.

[0163] The insulating layer 103c is a layer that contacts the semiconductor layer 108. The insulating layer 103c has defects on the surface. It is an extremely dense film with little adhesion, making it difficult for impurities such as water in the air to be adsorbed onto its surface. It is preferable.

[0164] The deposition gas used to deposit each layer constituting the insulating layer 103 is a source gas containing a deposition gas. The deposition gas includes source gases as well as rare gases such as argon, helium, and nitrogen. The ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply referred to as By reducing the flow rate, the deposition rate can be reduced, resulting in a dense film with fewer defects. It can be filmed.

[0165] The insulating layer 103a is formed under conditions where the flow rate ratio of the deposition gas is higher than that of the insulating layer 103b. This increases the deposition rate of the insulating layer 103a and the deposition rate of the insulating layer 103. Productivity can be increased.

[0166] The insulating layer 103b and the insulating layer 103e each have a lower deposition rate than the insulating layer 103a. It is preferable that the insulating layer 103b and the insulating layer 103c are formed under the condition of a low flow rate ratio. As the edge layer 103e, a dense film with few defects can be formed.

[0167] Here, the boundary between the insulating layer 103a and the insulating layer 103b, and the boundary between the insulating layer 103e and the insulating layer 103 The boundary between a and b may be unclear, so in Figs. 6(A) and 6(B), The boundary between the insulating layers 103a and 103b is shown by a dashed line. Since the degree of the change is different, the cross section of the insulating layer 103 is observed by a transmission electron microscope (TEM). In the Displacement Electron Microscope (DEM) image, these boundaries Similarly, the difference between the insulating layer 103e and the insulating layer The boundary with 103a can sometimes also be observed.

[0168] After the insulating layer 103 is formed, treatment for supplying oxygen to the insulating layer 103 may be performed. Examples of the treatment that supplies oxygen include plasma treatment under an oxygen atmosphere, heat treatment in a vacuum, treatment using a plasma ion doping method, and treatment using an ion implantation method Examples include theory.

[0169] Next, a metal oxide film is formed on the insulating layer 103 and processed to form an island-shaped semiconductor layer 108. (Figure 5(B)).

[0170] The metal oxide film can be formed by a sputtering method using a metal oxide target. preferable.

[0171] When forming a metal oxide film, it is preferable to use oxygen gas. When forming the film, in addition to oxygen gas, inert gas (e.g., helium gas, argon gas, It is also possible to mix gases such as fluorine gas and fluorine gases into the metal oxide film. The higher the ratio of oxygen gas in the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the more easily the crystallization of the metal oxide film will progress. On the other hand, the oxygen flow rate is low. The lower the thickness, the lower the crystallinity of the metal oxide film, and the larger the on-state current of the transistor. can.

[0172] The conditions for forming the metal oxide film are that the substrate temperature is between room temperature and 200° C., preferably between 100° C. and 200° C. For example, the substrate temperature may be set to be above room temperature but below 140°C. In addition, the substrate temperature is set to room temperature or is not intentionally heated. By forming a metal oxide film in a low temperature state, the crystallinity can be reduced.

[0173] In addition, before forming the metal oxide film, water, hydrogen, and organic compounds adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a treatment for removing components or a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced pressure atmosphere. Alternatively, the plasma treatment may be carried out in an atmosphere containing oxygen. When plasma treatment is performed in an atmosphere containing nitrogen oxide (N2O) gas, the surface of the insulating layer 103 After such treatment, the surface of the insulating layer 103 is It is preferable to form the metal oxide film continuously without exposing it to the atmosphere.

[0174] Metal oxide films can be processed using either wet etching or dry etching, or both. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 is etched. It may be aged and thinned.

[0175] After forming the metal oxide film or processing it into the semiconductor layer 108, the metal oxide film or the semiconductor layer Heat treatment may be performed to remove hydrogen and water from the SiO 2 film. The temperature of the heat treatment is typically Generally, temperatures between 150°C and the strain point of the substrate, between 250°C and 450°C, or between 300°C and The maximum temperature can be 450°C or less.

[0176] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After the heating, the substrate may be heated in an atmosphere containing oxygen. It is preferable that the mixture does not contain water. The heat treatment may be carried out using an electric furnace, an RTA device, or the like. By using an RTA device, the heat treatment time can be shortened.

[0177] Next, a gate insulating layer 110 and a metal oxide layer 111 are formed on the insulating layer 103 and the semiconductor layer 108. 14 is laminated to form a film (FIG. 5(C)).

[0178] Before forming the gate insulating layer 110, the surface of the semiconductor layer 108 is subjected to plasma treatment. This is preferable to remove impurities such as water adsorbed on the surface of the semiconductor layer 108. The impurities present at the interface between the semiconductor layer 108 and the gate insulating layer 110 can be reduced. In particular, the shape of the semiconductor layer 108 can be reduced. If the surface of the semiconductor layer 108 is exposed to the atmosphere during the period from the formation of the semiconductor layer 108 to the formation of the gate insulating layer 110, The plasma treatment is preferably carried out using, for example, oxygen, ozone, nitrogen, nitrous oxide (NO The plasma treatment can be carried out in an atmosphere containing oxygen. Furthermore, when the N2O plasma treatment is performed, the surface of the semiconductor layer 108 After the plasma treatment, the surface of the semiconductor layer 108 is exposed to the atmosphere. It is preferable to deposit the gate insulating layer 110 successively without exposing it to radiation.

[0179] The gate insulating layer 110 may be, for example, a silicon oxide film or a silicon oxynitride film. The oxide film is preferably formed by plasma CVD. Alternatively, the film may be formed by using a plasma CVD method.

[0180] A more detailed configuration of the gate insulating layer 110 will be described with reference to FIG.

[0181] The gate insulating layer 110 shown in FIG. 6(C) is made up of an insulating layer 110a and an insulating layer 110b on the insulating layer 110a. The insulating layer 110b has a three-layer structure, and an insulating layer 110c on the insulating layer 110b.

[0182] The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are formed by using different acidic materials under different film forming conditions. In this case, the insulating layer 110a, the insulating layer 110b, and the insulating film The insulating layer 110c is preferably deposited successively in the same deposition apparatus. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are formed by plasma CVD. It is preferable to form a silicon oxynitride film.

[0183] The insulating layer 110a is a layer that is in contact with the semiconductor layer 108. When the insulating layer 110a is formed, the semiconductor In order to reduce damage to the insulating layer 110a, the deposition rate (also referred to as deposition rate) of the insulating layer 110a is It is preferable that the temperature (temperature) is low.

[0184] The insulating layer 110a is preferably formed under lower power conditions than the insulating layer 110b. This makes it possible to minimize damage to the semiconductor layer 108.

[0185] It is also desirable that the insulating layer 110a has low defects and releases only a small amount of hydrogen and water. This can prevent oxygen vacancies from being formed in the semiconductor layer .

[0186] In order to increase the productivity of the gate insulating layer 110, it is preferable that the deposition rate of the insulating layer 110b is high. Furthermore, compared to the insulating layer 110a and the insulating layer 110c, the insulating layer 110b It is preferable that the thickness is large.

[0187] The insulating layer 110c has few defects on its surface, and impurities such as water contained in the air are adsorbed to its surface. It is preferable that the film is extremely dense and resistant to cracking.

[0188] The deposition gas used to deposit each layer constituting the gate insulating layer 110 includes a source gas containing a deposition gas. The deposition gas includes argon, helium, nitrogen, etc. in addition to the source gas. The ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter referred to as the "flow rate of the deposition gas") may be any dilution gas. By reducing the flow rate, the deposition rate can be reduced, resulting in a dense film with fewer defects. A film can be formed.

[0189] For example, a silicon oxynitride film is formed using a deposition agent containing silicon, such as silane or disilane. and a raw material gas containing an oxidizing gas such as oxygen, ozone, nitrous oxide, or nitrogen dioxide. can be used.

[0190] The insulating layer 110a is formed under conditions where the flow rate ratio of the deposition gas is lower than that of the insulating layer 110b. This allows the insulating layer 110a to be formed as a dense film with few defects. It is possible.

[0191] The insulating layer 110b has a deposition rate higher than that of the insulating layer 110a and / or the insulating layer 110c. It is preferable that the insulating layer 110b be formed under conditions where the flow rate ratio of the reactive gas is high. This can increase the film formation rate and improve productivity of the gate insulating layer 110.

[0192] The insulating layer 110c, like the insulating layer 110a, has a higher flow rate of deposition gas than the insulating layer 110b. It is preferable that the insulating layer 110c is formed under the condition of a low amount ratio. a and insulating layer 110b are formed on the semiconductor layer 108. During the film formation, the semiconductor layer 108 receives little damage. The insulating layer 110a can be formed under higher power conditions than the insulating layer 110b. By depositing the film at a relatively high power, a dense film with few surface defects can be formed as the insulating layer 110c. A film can be formed.

[0193] Here, the boundary between the insulating layer 110a and the insulating layer 110b, and the boundary between the insulating layer 110b and the insulating layer 110 The boundaries between the two points c and the point d may be unclear, so in Fig. 6(C) these boundaries are The insulating layer 110a and the insulating layer 110b have different film densities. In a TEM image of a cross section of the gate insulating layer 110, these boundaries are contrasted. Similarly, the difference in the boundary between the insulating layer 110b and the insulating layer 110c can be observed. The world may also be observed.

[0194] The metal oxide layer 114 is made of a material that is difficult for oxygen and hydrogen to permeate. 14 is the diffusion of oxygen contained in the gate insulating layer 110 to the side opposite to the semiconductor layer 108. The metal oxide layer 114 has a function of preventing hydrogen and water from entering the gate insulating layer 1 from the outside. The metal oxide layer 114 has a function of suppressing diffusion to the gate electrode 10 side. It is preferable to use a material that is less permeable to oxygen and hydrogen than the insulating layer 110 .

[0195] The metal oxide layer 114 can be either an insulating layer or a conductive layer.

[0196] The metal oxide layer 114 may be made of an insulating material having a higher dielectric constant than silicon oxide. For example, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. A film or the like can be used.

[0197] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). ), or silicon-containing indium tin oxide (ITSO), can also be used.

[0198] The metal oxide layer 114 may be formed of an oxide material containing one or more of the same elements as those of the semiconductor layer 108. In particular, an oxide semiconductor material applicable to the semiconductor layer 108 is preferably used. At this time, it is preferable that the metal oxide layer 114 is formed by the same sputtering method as the semiconductor layer 108. By applying a metal oxide film formed using a ring target, equipment can be standardized. Therefore, it is preferable.

[0199] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When a metal oxide material is used, the composition (content) of gallium is higher than that of the semiconductor layer 108. The use of such a material is preferred because it can further enhance the blocking property against oxygen. At this time, the semiconductor layer 108 contains a material having a higher indium content than the metal oxide layer 114. By using such a material, the field-effect mobility of the transistor 100 can be increased.

[0200] The metal oxide layer 114 is preferably formed using a sputtering device. When forming an oxide film using a tartering device, it is necessary to form it in an atmosphere containing oxygen gas. Therefore, oxygen can be suitably supplied into the gate insulating layer 110 and the semiconductor layer 108.

[0201] The metal oxide layer 114 is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form the film by sputtering in an atmosphere containing oxygen. Oxygen can be supplied to the gate insulating layer 110 when the metal oxide layer 114 is formed.

[0202] The metal oxide layer 114 is formed by an oxide target containing the same metal oxide as that for the semiconductor layer 108. When the film is formed by a sputtering method using a fluorine atom, the above-mentioned method can be used. .

[0203] For example, by using oxygen as the deposition gas and a reactive sputtering method using a metal target, For example, if aluminum is used as the metal target, a metal oxide layer 114 may be formed. When used, an aluminum oxide film can be formed.

[0204] When the metal oxide layer 114 is formed, the ratio of the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus is The higher the oxygen flow rate ratio (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the greater the gate insulating layer 1 The oxygen supplied in the 10 can be increased. The oxygen flow ratio or oxygen partial pressure can be increased, for example, to 5 0% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or less, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure to 0% and to make the oxygen partial pressure as close to 100% as possible.

[0205] In this way, the metal oxide layer 114 is formed by sputtering in an atmosphere containing oxygen. By this, oxygen is supplied to the gate insulating layer 110 when the metal oxide layer 114 is formed. In addition, oxygen can be prevented from being released from the gate insulating layer 110. This allows a large amount of oxygen to be trapped in the gate insulating layer 110. As a result, a large amount of oxygen can be supplied to the semiconductor layer 108. This reduces oxygen vacancies in the O8, resulting in highly reliable transistors.

[0206] Next, heat treatment is performed to supply oxygen from the gate insulating layer 110 to the semiconductor layer 108. The heat treatment is preferably carried out in an atmosphere containing at least one of nitrogen, oxygen, and rare gas. The heating can be carried out at a temperature of 00°C or higher and 400°C or lower.

[0207] After forming the metal oxide layer 114, a heat treatment is performed before forming the gate electrode 112. Therefore, oxygen can be effectively supplied from the gate insulating layer 110 to the semiconductor layer 108 .

[0208] Next, the metal oxide layer 114 is removed (FIG. 5(D)). The subsequent steps are preferably carried out at a temperature equal to or lower than the temperature of the heat treatment. This makes it possible to suppress the desorption of oxygen from the semiconductor layer 108, and oxygen deficiency can be prevented from occurring in the semiconductor layer 108. Therefore, the reliability of the transistor can be improved. Cut.

[0209] There is no particular limitation on the method for removing the metal oxide layer 114. However, if wet etching is used, the metal oxide layer 114 can be removed. This can prevent the gate insulating layer 110 from being etched simultaneously with the metal oxide layer 114 . This prevents the thickness of the gate insulating layer 110 from decreasing, and The film thickness can be made uniform.

[0210] After removing the metal oxide layer 114, the gate insulating layer 110 and a portion of the insulating layer 103 are etched. By this, an opening 142 is formed that reaches the conductive layer 106. The gate electrode 112 and the conductive layer 106 are electrically connected in the opening 142. The opening 142 may be formed before the metal oxide layer 114 is formed.

[0211] Next, a conductive film 112f that will become the gate electrode 112 is formed on the gate insulating layer 110 (FIG. 5(E)). The conductive film 112f is formed by sputtering using a metal or alloy sputtering target. It is preferable to form the conductive film by sputtering. 112f and the conductive layer 106 are connected.

[0212] Next, a part of the conductive film 112f is etched to form the gate electrode 112 (FIG. 7(A) ).

[0213] In this manner, the gate insulating layer 110 is formed on the top and side surfaces of the semiconductor layer 108 and the insulating layer 10 By covering the semiconductor layer 3, the semiconductor layer 3 is prevented from being exposed to the etching process for forming the gate electrode 112. This can prevent the conductive layer 108 and the insulating layer 103 from being partially etched and thinned. do.

[0214] Next, using the gate electrode 112 as a mask, the gate insulating layer 110 and the semiconductor layer 108 are doped with impurities. A process for supplying the material element 140 is performed to form the low resistance region 108n, the region 110d, and the region 10 3d is formed (FIGS. 7B and 7C). The semiconductor layer 108 and the gate insulating layer 110 In the region overlapping with the gate electrode 112, the gate electrode 112 acts as a mask and the impurity source The element 140 is not supplied.

[0215] The impurity element 140 is preferably supplied by plasma ion doping or ion implantation. These methods can be used to measure the concentration profile in the depth direction by using the ion acceleration voltage. The plasma ion doping method can be controlled with high precision by adjusting the pressure and dose. By using this method, productivity can be improved. By using this, the purity of the impurity element to be supplied can be increased.

[0216] In the supplying process of the impurity element 140, the interface between the semiconductor layer 108 and the gate insulating layer 110, Alternatively, a portion of the semiconductor layer 108 near the interface, or a portion of the gate insulating layer 110 near the interface It is preferable to control the processing conditions so that the area close to the As a result, the optimum concentration of impurities can be introduced into both the semiconductor layer 108 and the gate insulating layer 110 in a single process. The element 140 can be provided.

[0217] The impurity elements 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and arsenic. Impurity elements 140 include aluminum, magnesium, silicon, and rare gases. As the catalyst, boron, phosphorus, aluminum, magnesium, or silicon is preferably used. Preferably, boron or phosphorus is used.

[0218] As a source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, B2H6 gas or BF3 gas can be typically used. In addition, when supplying phosphorus, PH3 gas can be typically used. Alternatively, a mixed gas obtained by diluting these source gases with a rare gas may be used.

[0219] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, and S i2H6, F2, HF, H2, (C5H5)2Mg, and rare gases can be used. The ion source is not limited to a gas, and may be a solid or liquid that is heated and vaporized.

[0220] The supply of the impurity element 140 depends on the composition, density, thickness, and the like of the gate insulating layer 110 and the semiconductor layer 108. This can be controlled by setting conditions such as acceleration voltage and dose, taking into account the above. .

[0221] The method of supplying the impurity element 140 is not limited, and may be, for example, a plasma treatment or a thermal treatment by heating. In the case of the plasma treatment method, the impurity element to be supplied is By generating plasma in a gas atmosphere containing impurities and performing plasma treatment, The plasma generating device can be a dry etching device. Use equipment such as ashing equipment, plasma CVD equipment, and high-density plasma CVD equipment. can be done.

[0222] In one embodiment of the present invention, the impurity element 140 is introduced into the semiconductor layer 108 through the gate insulating layer 110. This allows the semiconductor layer 108 to be fused when the impurity element 140 is supplied. Therefore, the decrease in crystallinity can be prevented, and the increase in electrical resistance due to the decrease in crystallinity can be prevented. This is particularly suitable for such cases.

[0223] In the step of supplying the impurity element 140, the gate insulating layer 110 overlaps with the gate electrode 112. The impurity element 140 is supplied to the undoped portion of the gate insulating layer 110. The amount of oxygen released by heating varies between the portion overlapping with the port electrode 112 and the portion not overlapping with the port electrode 112. Therefore, when the heat treatment is performed after the step of supplying the impurity element 140, Even in this case, the supply of oxygen from the gate insulating layer 110 to the low-resistance region 108n can be suppressed. Therefore, the increase in the electrical resistance of the low resistance region 108n can be suppressed.

[0224] Next, an insulating layer 118 is formed to cover the gate insulating layer 110 and the gate electrode 112 (FIG. 8( A)).

[0225] When the insulating layer 118 is formed by plasma CVD, if the film formation temperature is too high, the low resistance region The impurities contained in the region 108n etc. diffuse to the peripheral region including the channel forming region of the semiconductor layer 108. There is a risk that the insulating layer 118 may be dispersed, or the electrical resistance of the low resistance region 108n may increase. The film temperature is, for example, 150°C or higher and 400°C or lower, preferably 180°C or higher and 360°C or lower. The temperature is preferably 200° C. or higher and 250° C. or lower, and more preferably 200° C. or higher and 250° C. or lower. By forming the film at high temperature, even transistors with short channel lengths can have good electrical characteristics. It can be granted.

[0226] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 11 8 and a portion of the gate insulating layer 110 are etched to reach the low resistance region 108n. An opening 141a and an opening 141b are formed.

[0227] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is then processed into a desired shape to form the conductive layers 120a and 120b. (Figure 8(B)).

[0228] Through the above steps, the transistor 100A can be manufactured. When the photodiode 100A is applied to the pixels of a display device, a protective insulating layer, a planarizing layer, a surface It is only necessary to add a step of forming one or more of the display element and the wiring.

[0229] In the method for manufacturing a semiconductor device of this embodiment, a semiconductor layer, a gate insulating layer, and a metal oxide layer are formed. After forming the gate insulating layer, heat treatment is performed before forming the gate electrode. By providing a metal oxide layer that is difficult to permeate, oxygen is effectively supplied from the gate insulating layer to the semiconductor layer. This reduces oxygen vacancies in the channel formation region of the semiconductor layer, The reliability of the transistor can be improved. This removes the metal oxide layer, thereby preventing any troubles caused by processing or remaining of the metal oxide layer. Therefore, it is possible to suppress the deterioration of the transistor characteristics, and to realize semiconductor devices with excellent electrical characteristics and high reliability. This makes it possible to achieve this position.

[0230] This embodiment mode can be combined with other embodiment modes as appropriate. In the case where multiple configuration examples are shown in one embodiment, the configuration examples may be combined as appropriate. It is possible to do this.

[0231] (Embodiment 2) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 3 will be used to explain.

[0232] The semiconductor device of one embodiment of the present invention has favorable electrical characteristics; therefore, when used in a display device, For example, the transistor of one embodiment of the present invention can The present invention can be applied to a transistor included in one or both of a pixel and a driver circuit of the display device. can.

[0233] The semiconductor device of one embodiment of the present invention is a display device or a module including the display device. As a module having the display device, a flexible Flexible printed circuit board (hereinafter referred to as FPC (Fiber-Core Printed Circuit) or TCP (Tape Carrier Package) Module with a connector attached, COG (Chip On Glass) method or Modules with integrated circuits (ICs) mounted using COF (Chip On Film) methods, etc. Examples include ru.

[0234] [Top view of the display device] FIG. 9A is a top view of a display device 700. The display device 700 is formed by a sealing material 712. The device has a first substrate 701 and a second substrate 705 bonded together. The pixel portion 702, the source driver 703, and the area sealed with the second substrate 705 and the sealing material 712 are The pixel portion 702 includes a plurality of display elements. will be established.

[0235] The FPC 716 is connected to the portion of the first substrate 701 that does not overlap with the second substrate 705. A PC terminal portion 708 is provided. The FPC 716 connects the FPC terminal portion 708 and the signal The pixel section 702, the source driver 704, and the gate driver 706 are connected via a line 710. Various signals are supplied to each of these.

[0236] There may be provided a plurality of gate drivers 706. The source drivers 704 are each formed separately on a semiconductor substrate or the like and packaged. The IC chip may be mounted on the first substrate 701 or on an FPC. It can be implemented in 716.

[0237] Transistors included in the pixel portion 702, the source driver 704, and the gate driver 706 The transistor of one embodiment of the present invention can be applied to the above-described semiconductor device.

[0238] Examples of the display element provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. In addition, LEDs (Light Emitting Diodes) can be used as light emitting elements. iode), OLED (Organic LED), QLED (Quantum-dot) Examples of self-luminous light-emitting elements include LEDs and semiconductor lasers. MEMS (Micro Electro Mechanical Systems) Systems), microcapsules, electrophoresis, electrowetting Use a display element that uses the electronic powder method or the electronic liquid powder method. It is also possible.

[0239] A display device 700A shown in FIG. 9B is a display device using a flexible resin substrate instead of the first substrate 701. of a display device that can be used as a flexible display, to which the layer 743 is applied. Here is an example.

[0240] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in the region P1 in FIG. 9B, the display device 700A includes a pixel section 702 and a resin layer The pair of gate drivers 706 are connected to the pixel section. The gate drivers 706 are provided on both sides of the pixel section 702. and is provided along an arc-shaped contour.

[0241] The resin layer 743 has a protruding shape at the portion where the FPC terminal portion 708 is provided. In addition, a part of the resin layer 743 including the FPC terminal portion 708 is located on the back side in the region P2 in FIG. 9(B). By folding back a part of the resin layer 743, the FPC 716 can be attached to the pixel section 7 The display device 700A can be mounted on the back of the display device 02. This allows for space saving in electronic devices.

[0242] An IC 717 is mounted on an FPC 716 connected to the display device 700A. 17 has a function as, for example, a source driver. The source driver 704 includes at least a protection circuit, a buffer circuit, a demultiplexer circuit, etc. The configuration may include at least one.

[0243] The display device 700B shown in FIG. 9C is suitable for use in electronic devices having large screens. The display device 700B is a display device that can be used in, for example, a television device, a monitor device, Personal computers (including laptops and desktops), tablets, It can be suitably used for digital signage and the like.

[0244] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate drivers 722. It has.

[0245] The plurality of source driver ICs 721 are attached to FPCs 723, respectively. One terminal of each of the FPCs 723 is connected to the first board 701, and the other terminal is connected to the printed board 702. The FPC 723 is bent to connect the printed circuit board 724 to the display. The display device 700B can be mounted on the back side of the base part 702 so that the display device 700B can be mounted on the electronic device. This allows for space savings for the equipment.

[0246] On the other hand, the gate driver 722 is formed on the first substrate 701. It is possible to realize electronic devices in a picture frame.

[0247] By adopting such a configuration, a large-sized and high-resolution display device can be realized. Diagonal size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more It can also be applied to display devices with resolutions such as 4K2K or 8K4K. This makes it possible to realize a display device with extremely high resolution.

[0248] [Cross-sectional structure of the display device] 10 and 11 show a display device having a liquid crystal element as a display element. 3 shows a display device having an EL element as a display element. 9(B) and 9(C) are cross-sectional views taken along the dashed line QR in FIG. 1 is a cross-sectional view taken along dashed dotted line ST shown in FIG.

[0249] The display device 700 shown in FIGS. 10 to 12 and the display device 700A shown in FIG. The wiring section 711, the pixel section 702, the source driver 704, and the FPC terminal section 708 are The wiring portion 711 has a signal line 710. The pixel portion 702 has a transistor. 11 shows a case where the capacitor 790 is not provided. The source driver 704 includes a transistor 752.

[0250] The transistors 750 and 752 are formed by oxidizing a semiconductor layer in which a channel is formed. For example, the transistors exemplified in the first embodiment are The display device can be applied to a semiconductor layer made of silicon (amorphous silicon). The semiconductor device may have a transistor using silicon, polycrystalline silicon, or single crystal silicon. .

[0251] The transistor used in this embodiment is a highly purified oxide semiconductor in which the formation of oxygen vacancies is suppressed. The transistor has a conductor film. The off-state current of the transistor can be reduced. This allows the holding time of the electric signal to be extended, and the writing interval of the image signal, etc. to be set longer. Since the frequency of refresh operations can be reduced, power consumption can be reduced.

[0252] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using this, the switching transistor in the pixel section and the driver used in the driver circuit section The transistors can be formed on the same substrate. Since there is no need to use semiconductor devices formed from silicon wafers, etc., The number of points can be reduced. In addition, in the pixel area, transistors that can be driven at high speed can be used. By using this, high quality images can be provided.

[0253] The capacitor 790 shown in FIGS. 10 and 12 has the same semiconductor layer as the transistor 750. The lower electrode is formed by processing the film, and the resistance is reduced. and an upper electrode formed by processing a conductive film. Two insulating films covering the transistor 750 are provided between the capacitor element 79. 0 is a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes.

[0254] The capacitor 790 shown in FIG. 13 has the same first gate electrode as the transistor 750. The lower electrode is formed by processing a film, and the lower electrode is formed by processing the same metal oxide film as the semiconductor layer. The top electrode has a low resistance region, similar to the low resistance region of transistor 750. In addition, a first gate of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor 790 is formed by It is a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. The external electrodes are obtained by processing the same film as the source and drain electrodes of the transistor. The wiring is connected.

[0255] A planarization insulating film 77 is formed over the transistor 750, the transistor 752, and the capacitor 790. 0 is provided.

[0256] The transistor 750 included in the pixel portion 702 and the transistor included in the source driver 704 For example, one of the two may be a top gate type. A transistor of the first type may be used as one of the first and second gate electrodes, and a bottom-gate transistor may be used as the other. The same applies to the gate driver 706 as described above.

[0257] The signal line 710 is connected to the same conductor as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by resistance and enables display on a large screen.

[0258] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 780, and a The wiring 760 is connected to the FPC 71 through an anisotropic conductive film 780. 6. Here, the wiring 760 is electrically connected to the terminals of the transistors 750 and 6. The source electrode and drain electrode 752 are formed from the same conductive film.

[0259] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used. When a flexible substrate is used for the first substrate 701, Between the substrate 701 of the first embodiment and the transistor 750 and the like, an insulating layer having a barrier property against water and hydrogen is provided. It is preferred to provide an edge layer.

[0260] On the second substrate 705 side, there are a light-shielding film 738, a colored film 736, and an insulating film 73 in contact with these. 4 and are provided.

[0261] 10, 11, and 12, there are provided between the first substrate 701 and the second substrate 705: A spacer 778 is provided to adjust the distance between the two substrates. The substrate 701 and the second substrate 705 are bonded together with a sealant 712 .

[0262] The display device 700 shown in FIG. 10 includes a vertical electric field type liquid crystal element 775. The conductive layer 772 includes a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 772 is provided on the second substrate 705 side and functions as a common electrode. The gate electrode is electrically connected to the source electrode or the drain electrode of the transistor 750. An electrode layer 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0263] The conductive layer 772 may be made of a material that is transparent to visible light or a material that is reflective to visible light. Examples of materials that are transparent to visible light include It is recommended to use oxide materials containing indium, zinc, tin, etc. As the material, for example, a material containing aluminum, silver, or the like may be used.

[0264] When the conductive layer 772 is made of a material that is reflective to visible light, the display device 700 is a reflective type. On the other hand, when a material that transmits visible light is used for the conductive layer 772, In the case of a reflective LCD, a polarizing plate is installed on the viewing side. On the other hand, in the case of a transmission type liquid crystal display device, a pair of polarizing plates is provided to sandwich the liquid crystal element. .

[0265] The display device 700 shown in FIG. 11 is a horizontal electric field (FFS) display device. d) Switching mode) liquid crystal element 775 is used. A conductive layer 774 functioning as a common electrode is provided on the conductive layer 7 with an insulating layer 773 interposed therebetween. The orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the liquid crystal layer 772 and the conductive layer 774. This can be done.

[0266] In FIG. 11, a storage capacitor is formed by a stacked structure of a conductive layer 772, an insulating layer 773, and a conductive layer 774. Therefore, it is not necessary to provide a separate capacitance element, and the aperture ratio can be increased. It is possible.

[0267] Although not shown in FIGS. 10 and 11, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members, Light sources such as a backlight and a sidelight can be provided as appropriate.

[0268] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, or a polymer dispersed liquid crystal. , polymer network type liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. .

[0269] The liquid crystal element modes are TN (Twisted Nematic) mode, VA (V Vertical Alignment mode, IPS (In-Plane Switching hing mode, FFS mode, ASM (Axially Symmetric al Ignition Micro-cell mode, OCB (Optical Compensation ECB (Electrically Birefringence) mode Controlled Birefringence mode, VA-IPS mode, A host mode can be used.

[0270] In addition, as a driving method of the liquid crystal element, a time-dependent additive color mixture method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the colored film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors of red (R), green (G), and blue (B). Therefore, the aperture ratio of the pixel and the definition of the display device can be increased.

[0271] The display device 700 shown in FIG. 12 and the display device 700A shown in FIG. The light-emitting element 782 includes a conductive layer 772, an EL layer 786, and a conductive film 788. The L layer 786 comprises a luminescent material.

[0272] Luminescent materials include fluorescent materials, phosphorescent materials, and thermoluminescent materials. Substances that exhibit activated delayed fluorescence (thermally activated delayed fluorescence) d delayed fluorescence (TADF) materials), inorganic compounds (quantum Dot materials, etc. can be used.

[0273] The display device 700 shown in FIG. 12 and the display device 700A shown in FIG. 13 have a planarization insulating film 77 An insulating film 730 is provided on the light-emitting element 782 to cover a part of the conductive layer 772. This is a top-emission light-emitting element having a conductive film 788 that transmits visible light. The light emitting element 782 may have a bottom emission structure that emits light to the conductive layer 772 side, or a bottom emission structure that emits light to the conductive layer 772 side. A dual emission structure in which light is emitted to both the 772 side and the conductive film 788 side may be used. stomach.

[0274] In FIG. 12, the colored film 736 is provided at a position overlapping the light emitting element 782, and the light blocking film 738 are provided in a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. As shown in FIG. 1, a side-by-side EL layer 786 is formed in each subpixel of each color. When a color-coded method (also called a color-coded method) is used, the colored film 736 does not need to be provided.

[0275] In FIG. 13, the EL layer 786 of the light-emitting element 782 is formed by the insulating film 730 and the conductive layer 77 The EL layer 786 is formed in an island shape on the substrate 2 so that each sub-pixel emits a different color. By using the color film 736, a color display can be realized without using the color film 736. A protective layer 741 is provided to cover the light emitting element 782. The protective layer 741 is formed to protect the light emitting element 782 from water. The protective layer 741 has a function of preventing impurities such as silicon dioxide from diffusing. It is also preferable that the insulating film has a laminated structure including at least one inorganic insulating film and at least one organic insulating film. is more preferable.

[0276] The display device 700A shown in FIG. 13 includes a support substrate instead of the first substrate 701 shown in FIG. 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated. The transistor 750 , the capacitor 790 , and the like are provided over the insulating layer 744 .

[0277] The support substrate 745 is a substrate that contains organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The resin layer 743 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The support substrate 745 is bonded to the support substrate 745 by an adhesive layer 742. The resin layer 743 It is preferably thinner than the carrier substrate 745 .

[0278] 12. In addition, the display device 700A shown in FIG. 13 has a protective substrate instead of the second substrate 705 shown in FIG. The protective layer 740 is attached to the sealing film 732. The protective layer 740 may be a glass substrate or a resin film. As a result, optical components such as polarizing plates and scattering plates, input devices such as touch sensors, or A configuration in which two or more layers are stacked may also be applied.

[0279] 13 also shows a bendable region P2. The region P2 is formed by the support substrate 745 In addition to the adhesive layer 742, there are also portions where no inorganic insulating films such as the insulating layer 744 are provided. In addition, in the region P2, a resin layer 746 is provided to cover the wiring 760. The inorganic insulating film is not provided in the possible region P2 as much as possible, and the conductive layer containing a metal or an alloy is provided. By using a laminated structure consisting of only layers containing organic materials, cracks do not occur when the material is bent. Furthermore, by not providing the support substrate 745 in the region P2, an extremely small The radius of curvature allows a portion of the display device 700A to bend.

[0280] The display device of this embodiment may have an input device such as a touch sensor. The display device according to the embodiment may have a function as a touch panel.

[0281] Sensor types include capacitance, resistive film, surface acoustic wave, infrared, and optical. Various methods can be used, such as pressure-sensitive or pressure-sensitive methods, or a combination of two or more of these. They may also be used in combination.

[0282] The touch panel is a so-called in-cell type touch panel, in which the input device is formed inside a pair of substrates. touch panel, an input device formed on a display device, so-called on-cell type touch panel, or There are also so-called out-cell type touch panels that are attached to a display device.

[0283] This embodiment mode can be combined with other embodiment modes as appropriate.

[0284] (Embodiment 3) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. and explain.

[0285] The semiconductor device of one embodiment of the present invention has favorable electrical characteristics; therefore, when used in a display device, For example, the transistor of one embodiment of the present invention can The present invention can be applied to a transistor included in one or both of a pixel and a driver circuit of the display device. can.

[0286] The display device shown in FIG. 14A includes a pixel portion 502, a driver circuit portion 504, and a protective circuit 506. and a terminal portion 507. Note that the protection circuit 506 may not be provided.

[0287] The transistors included in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also be formed using the transistor of one embodiment of the present invention. may be applied.

[0288] The pixel unit 502 is made up of a plurality of pixels arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The LCD device has a plurality of pixel circuits 501 for driving the display elements.

[0289] The driver circuit unit 504 includes a gate driver that outputs scan signals to the scan lines GL_1 to GL_X. 504a, a source driver 504 that supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a has at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may also be configured using a shift register or the like.

[0290] The terminal unit 507 inputs power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for

[0291] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, indicates various wirings such as the data line DL which is the wiring between the source driver 504b and the pixel circuit 501. is connected to.

[0292] The gate driver 504a and the source driver 504b are based on the same base as the pixel section 502. It may be formed directly on the board, or on a separate substrate, and may be COG or TAB (Tape The structure is mounted on a substrate on which the pixel part is formed by automated bonding. It may also be composed.

[0293] The plurality of pixel circuits 501 shown in FIG. 14(A) may be, for example, The configuration shown in FIG.

[0294] The pixel circuit 501 shown in FIG. 14B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 includes a data line DL_n, a scanning line GL_m, and a The voltage supply line VL and the like are connected.

[0295] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential ( A common potential may be applied to the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row. One of the poles may be given a different potential.

[0296] The pixel circuit 501 shown in FIG. 14C includes transistors 552 and 554 and a capacitor 562. and a light-emitting element 572. The pixel circuit 501 includes a data line DL_n, a scanning line GL _m, a potential supply line VL_a, a potential supply line VL_b, etc. are connected to the electrodes.

[0297] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. The other terminal is supplied with a low power supply potential VSS. The current flowing through the light emitting element 572 is controlled in accordance with the potential, and thus the light emitting element 572 emits light. The luminance of these light sources is controlled.

[0298] This embodiment mode can be combined with other embodiment modes as appropriate.

[0299] (Fourth embodiment) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. and explain.

[0300] The pixels of the display device of this embodiment have a memory for correcting the gradation (luminance value). The transistor according to one embodiment of the present invention can be used as a transistor included in the pixel. .

[0301] [Pixel circuit] 15A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M1 The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. 1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0302] The transistor M1 has a gate connected to a wiring G1, one of a source and a drain connected to a wiring S1, and the other connected to a wiring S2. The gate of the transistor M2 is connected to the wiring G. 2, one of the source and drain is the wiring S2, the other is the other electrode of the capacitor C1, and the circuit 401 and connect to each other.

[0303] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal elements. A semiconductor device, a MEMS device, or the like can be applied.

[0304] The node connecting the transistor M1 and the capacitor C1 is N1, and the transistor M2 and the circuit 401 are The node connecting these is defined as N2.

[0305] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the potential of the node N2 In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via capacitor M1, a voltage is applied to the node N1 by capacitive coupling via capacitor C1. This allows the potential of the node N2 to be changed in accordance with the change in the potential of the node N1.

[0306] Here, one or both of the transistors M1 and M2 may be The transistor using an oxide semiconductor, which is exemplified in , can be used. The extremely small off-current allows the potentials of the nodes N1 and N2 to be maintained for a long period of time. In addition, when the period for which the potential of each node is held is short (specifically, when the frame In cases where the system frequency is 30 Hz or more, a transistor using a semiconductor such as silicon is used. A printer may also be used.

[0307] [Drive method] An example of an operation method of the pixel circuit 400 will be described with reference to FIG. 1 is a timing chart relating to the operation of the pixel circuit 400. Therefore, various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, and The influence of the threshold voltage of the capacitor is not taken into account.

[0308] In the operation shown in FIG. 15B, one frame period is divided into a period T1 and a period T2. Period T1 is a period during which a potential is written to node N2, and period T2 is a period during which a potential is written to node N1. It is between.

[0309] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the wiring S1 is supplied with a fixed potential V ref and the first data is supplied to the wiring S2. Potential V w supply.

[0310] The node N1 is connected to the line S1 via the transistor M1. ref is given. In addition, the node N2 is supplied with a first data potential V w is given. Therefore, the potential difference V across the capacitor C1 w -V ref is maintained.

[0311] In the period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns on the transistor M2 is applied to the wiring G2. A potential that turns off the transistor M2 is applied to the line S1. d ata A predetermined constant potential is applied to the wiring S2, or the wiring S2 is set in a floating state. do.

[0312] The node N1 is supplied with a second data potential V data is given. At this time, the second data potential V data Depending on node N2 That is, the potential of the first data potential V w and potential In FIG. 15(B), the potential dV is a positive value. However, the second data potential V data is the potential V ref It may be lower.

[0313] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. If the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes equal to the second data Voltage V data The potential is close to

[0314] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the pixel circuit 401 can be generated, the gradation can be corrected within the pixel circuit 400. This makes it possible to do so.

[0315] In addition, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when using liquid crystal elements, overdriving is possible. It is possible to realize drive, etc.

[0316] [Pixel circuit with liquid crystal element] The pixel circuit 400LC shown in FIG. 15C includes a circuit 401LC. , a liquid crystal element LC, and a capacitor C2.

[0317] One electrode of the liquid crystal element LC is connected to the node N2 and one electrode of the capacitor C2. The poles are at potential V com2 The other electrode of the capacitor C2 is connected to a wiring to which a potential V c om1 Connect with the wiring given.

[0318] The capacitor C2 functions as a storage capacitor. If unnecessary, the capacitor C2 can be omitted. do.

[0319] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, By using a liquid crystal material with a high driving voltage, high-speed display can be achieved. In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the temperature and the deterioration state of the liquid crystal element LC.

[0320] [Pixel circuit having a light-emitting element] The pixel circuit 400EL shown in FIG. 15D includes a circuit 401EL. , a light-emitting element EL, a transistor M3, and a capacitor C2.

[0321] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the One of the inputs is at potential V H The other is a wiring to which the voltage is applied, and the other is one electrode of the light-emitting element EL. The other electrode of the capacitor C2 is connected to a potential V com It is connected to the wiring that gives The other electrode of the light element EL is connected to a potential V L Connect with the wiring given.

[0322] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. It functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0323] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, the transistor M3 may be connected to the cathode side. H and potential V L The value of can be changed as appropriate.

[0324] The pixel circuit 400EL applies a high potential to the gate of the transistor M3. Since a large current can be passed through the EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or wiring S2, the transistor M3 and the It is also possible to correct variations in the electrical characteristics of the light elements EL.

[0325] The circuit is not limited to the circuits illustrated in FIGS. 15(C) and 15(D), and may include additional transistors and capacitors. It may also be configured to add a quantity.

[0326] This embodiment mode can be combined with other embodiment modes as appropriate.

[0327] (Embodiment 5) In this embodiment, a display module of one embodiment of the present invention will be described with reference to FIGS. .

[0328] The display module 6000 shown in FIG. 16(A) includes an upper cover 6001 and a lower cover 600 2, a display device 6006 connected to an FPC 6005, a frame 6009, a printer The power supply 6010 includes a power board 6010 and a battery 6011.

[0329] A display device manufactured using the transistor of one embodiment of the present invention is used as the display device 6006. The display device 6006 can realize a highly reliable display module. can be done.

[0330] The upper cover 6001 and the lower cover 6002 are configured to fit the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0331] The display device 6006 may have a function as a touch panel.

[0332] The frame 6009 has a function of protecting the display device 6006 and a function of operating the printed circuit board 6010. It may also have a function of blocking generated electromagnetic waves, a function as a heat sink, and the like.

[0333] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. It includes a processing circuit, a battery control circuit, etc. The power supply may be a battery 6011.

[0334] FIG. 16(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. be.

[0335] The display module 6000 includes a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The area surrounded by the upper cover 6001 and the lower cover 6002 has a portion 6016. The light guide region has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b).

[0336] The display device 6006 is connected to a printed circuit board 6010 and a battery 6012 via a frame 6009. The display device 6006 and the frame 6009 are provided so as to overlap with the light guide unit 601. 7a, and fixed to the light guide portion 6017b.

[0337] Light 6018 emitted from the light emitting unit 6015 is guided to the display device 6006 by the light guiding unit 6017a. The light passes through the upper part of the light guide part 6017b and reaches the light receiving part 6016. When the light 6018 is blocked by a detection object such as a glass, a touch operation is detected. This can be done.

[0338] A plurality of light emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-emitting units 6016 are provided at positions facing the light-emitting units 6015. Information on the position where the operation was performed can be obtained.

[0339] The light emitting unit 6015 may be a light source such as an LED element, and in particular, may be a light source that emits infrared light. It is preferable to use a light source that emits light. A photoelectric element that receives light and converts it into an electrical signal can be used. Preferably, it is capable of receiving infrared light. A photodiode such as a photodiode can be used.

[0340] The light 6018 is transmitted through the light guide portions 6017a and 6017b. The light receiving unit 6016 can be disposed below the display device 6006, and external light is received by the light receiving unit 6016. In particular, it can absorb visible light and infrared light, preventing the touch sensor from malfunctioning. By using a resin that is permeable to light, malfunction of the touch sensor can be more effectively suppressed.

[0341] This embodiment mode can be combined with other embodiment modes as appropriate.

[0342] (Embodiment 6) In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 17 to 20. do.

[0343] The electronic devices of this embodiment include the semiconductor device of one embodiment of the present invention. The transistor of one embodiment of the present invention can be used as a transistor in a display device used in a display portion. The transistor of one embodiment of the present invention has stable and favorable electrical characteristics and high reliability. Therefore, the reliability of the display device and the electronic device can be improved. Such transistors can be used in a variety of electronic devices.

[0344] The display unit of the electronic device of this embodiment can display, for example, full high definition, 4K2K, 8K4K, It is possible to display images with a resolution of 16K8K or higher.

[0345] Examples of electronic devices include television sets, desktop or notebook PCs, etc. Personal computers, computer monitors, digital signage, pachinko machines, etc. In addition to electronic devices with relatively large screens such as large game consoles, digital cameras, Digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals Examples include audio equipment, sound reproduction devices, etc.

[0346] The electronic device of this embodiment is mounted on the inner or outer wall of a house or building, or the interior of a car. It can be incorporated along the curved surface of the interior or exterior.

[0347] The electronic device of this embodiment may have an antenna. This allows the display of images, information, etc. on the display unit. If a secondary battery is included, the antenna may be used for contactless power transmission.

[0348] The electronic device of this embodiment includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, Distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared) It may be possible.

[0349] The electronic device of this embodiment can have various functions. For example, Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar - Functions to display date or time, etc., and to run various software (programs) Functions, wireless communication functions, and functions for reading programs or data recorded on recording media etc.

[0350] The electronic device 6500 shown in FIG. 17A is a mobile phone that can be used as a smartphone. It is an information terminal.

[0351] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, and a button 65 04, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0352] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 6502. Cut.

[0353] FIG. 17B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0354] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. A display panel 6511, an optical member 6512, a touch panel 6513, and a protective member 6510 are arranged in a space surrounded by the display panel 6511, the optical member 6512, and a touch panel 6513. The sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. .

[0355] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The cable 6513 is fixed by an adhesive layer (not shown).

[0356] In the area outside the display portion 6502, a part of the display panel 6511 is folded back. The FPC6515 is connected to the folded part. C6516 is mounted on the FPC6515. connected to a child.

[0357] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, extremely lightweight electronic devices can be realized. Because it is thin, it is possible to install a large-capacity battery 6518 while keeping the thickness of the electronic device small. In addition, a part of the display panel 6511 is folded back and the FPC 6515 is attached to the back of the pixel area. By arranging the connection portion, an electronic device with a narrow frame can be realized.

[0358] FIG. 18A shows an example of a television device. The television device 7100 includes a housing 71 The display unit 7000 is built into the housing 71. This shows a configuration that supports 01.

[0359] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 7000. Cut.

[0360] The television device 7100 shown in FIG. 18A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or the display unit 700. The display unit 7000 may be provided with a touch sensor, and the television can be operated by touching the display unit 7000 with a finger or the like. The remote control operator 7111 may operate the remote control operator 7100. The remote control device 7111 may have a display unit that displays information output from the remote control device 7111. The channel and volume can be controlled using the operation keys or touch panel. , the image displayed on the display unit 7000 can be manipulated.

[0361] The television device 7100 includes a receiver, a modem, and the like. It is also possible to receive general television broadcasts via wired or wireless connection via a modem. By connecting to a wired communication network, it can be transmitted in one direction (sender to receiver) or two directions. It is also possible to communicate information in two directions (between a sender and a receiver, or between receivers). do.

[0362] FIG. 18(B) shows an example of a notebook personal computer. The computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and a 213, an external connection port 7214, etc. The display unit 7000 is incorporated in the housing 7211. It is being eaten.

[0363] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 7000. Cut.

[0364] 18(C) and (D) show an example of digital signage.

[0365] The digital signage 7300 shown in FIG. 18C includes a housing 7301, a display unit 7000, and and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a control switch, connection terminals, various sensors, a microphone, etc. do.

[0366] FIG. 18(D) shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit 7000 provided along the curved surface of a pillar 7401. It has.

[0367] 18C and 18D, the display portion 7000 includes a transistor of one embodiment of the present invention. A display device that

[0368] The larger the display unit 7000, the more information can be displayed at once. The wider the part 7000, the more noticeable it is, and for example, the more effective the advertisement. Cut.

[0369] By applying a touch panel to the display unit 7000, images or videos can be displayed on the display unit 7000. It is also preferable because it not only shows route information but also allows users to operate it intuitively. When used to provide information such as traffic information, intuitive operation is required. Usability can be improved.

[0370] Also, as shown in FIG. 18(C) and FIG. 18(D), a digital signage 7300 or The digital signage 7400 is an information terminal device 731 such as a smartphone owned by a user. 1 or information terminal 7411 via wireless communication. The advertisement information displayed on the display unit 7000 is transmitted to the information terminal 7311 or the information terminal 741. 1. Also, the information terminal 7311 or the information terminal 741 By operating 1, the display on the display unit 7000 can be switched.

[0371] In addition, the digital signage 7300 or the digital signage 7400 is equipped with an information terminal 7 311 or the screen of the information terminal 7411 is used as a control means (controller) to play games. This allows an unspecified number of users to participate in the game at the same time and enjoy it. It is possible.

[0372] FIG. 19(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. Figure.

[0373] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button The camera 8000 has a detachable lens 8006 attached thereto. The camera 8000 may be configured such that the lens 8006 and the housing are integrated. good.

[0374] The camera 8000 can be operated by pressing the shutter button 8004 or by using a touch panel. An image can be captured by touching the display unit 8002.

[0375] The housing 8001 has a mount with electrodes, and is equipped with a finder 8100 and a strobe. Devices etc. can be connected.

[0376] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0377] The housing 8101 has a mount that engages with the mount of the camera 8000. The finder 8100 displays the images received from the camera 8000. The information can be displayed on the display unit 8102.

[0378] The button 8103 has a function such as a power button.

[0379] The display unit 8002 of the camera 8000 and the display unit 8102 of the finder 8100 are A display device including the transistor of one embodiment of the present invention can be applied. The camera 8000 may have a built-in camera.

[0380] FIG. 19B is a diagram showing the appearance of the head mounted display 8200.

[0381] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820 3, a display unit 8204, a cable 8205, etc. The mounting unit 8201 also has a battery It has a built-in Teri 8206.

[0382] A cable 8205 supplies power from a battery 8206 to the main body 8203. 3 is equipped with a wireless receiver etc., and can display received video information on a display unit 8204 The main body 8203 is also equipped with a camera, and information on the movements of the user's eyes and eyelids is used as an input means. It can be used as follows.

[0383] In addition, the attachment part 8201 has a function of attaching a device to a position where the device is in contact with the user, which is designed to flow in accordance with the movement of the user's eyeball. A plurality of electrodes capable of detecting a current may be provided, and the device may have a function of recognizing a line of sight. The device may also have a function of monitoring the pulse of the user based on the current flowing through the electrodes. The mounting part 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the user's head movement may be The display unit 8204 may have a function of changing the image displayed on the display unit 8204 according to the occasion.

[0384] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 8204. Cut.

[0385] 19(C), (D), and (E) are diagrams showing the appearance of the head-mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, and It has a band-shaped fixture 8304 and a pair of lenses 8305.

[0386] The user can view the display on the display unit 8302 through the lens 8305. By arranging the display unit 8302 in a curved manner, the user can feel a high sense of presence. In addition, different images displayed in different areas of the display unit 8302 can be projected onto the lens 83 By viewing through the 05, it is possible to perform 3D display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but two display units 8302 may be provided, and one of the display units 8302 may be provided. One display may be provided per eye.

[0387] A display device including the transistor of one embodiment of the present invention can be applied to the display portion 8302. A display device with extremely high resolution can be manufactured using the transistor of one embodiment of the present invention. For example, as shown in FIG. 19(E), a lens 8305 is used to enlarge the display. In other words, even when the display unit 8302 is used, the pixels are hardly visible to the user. This allows the user to view highly realistic images.

[0388] The electronic devices shown in FIGS. 20A to 20F include a housing 9000, a display portion 9001, a speaker 9002, and a touch panel 9003. 9003, operation keys 9005 (including the power switch or operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including the ability to measure flow, humidity, gradient, vibration, odor or infrared), It has models such as 9008.

[0389] The electronic devices shown in FIGS. 20A to 20F have various functions. Functions for displaying information (still images, videos, text images, etc.) on the display, touch panel function, Functions that display calendars, dates, or times, etc., and various software (programs) Therefore, the function of controlling the processing, the wireless communication function, the program recorded on the recording medium, or The electronic device can have the function of reading and processing data. The electronic device may have a variety of functions, but is not limited to these. Also, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external or built into the camera), and the function of displaying the captured image on the display unit. It may be possible.

[0390] The electronic devices shown in FIGS. 20A to 20F will be described in detail below.

[0391] 20A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 includes: For example, it can be used as a smartphone. A portable information terminal 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple surfaces. 9 shows an example in which three icons 9050 are displayed. 51 can also be displayed on another surface of the display unit 9001. An example of the information 9051 is Notifications of incoming emails, SNS messages, phone calls, etc., email and SNS subject lines, sender names , date and time, remaining battery power, antenna reception strength, etc. An icon 9050 or the like may be displayed in the position where is displayed.

[0392] 20B is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 includes: The display unit 9001 has a function of displaying information on three or more surfaces. 9 shows an example in which information 9053 and information 9054 are displayed on different surfaces. When the mobile information terminal 9102 is stored in the breast pocket of the clothes, The user can also check the information 9053 displayed in a position that can be observed from above. The user can check the display without taking the mobile information terminal 9102 out of his pocket, and can, for example, receive a call. You can determine whether or not it is possible.

[0393] FIG. 20C is a perspective view showing a wristwatch-type mobile information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. By making the mobile information terminal 9200 communicate with, for example, a wirelessly enabled headset, Therefore, hands-free calling is also possible. The terminal 9006 can transmit data to and from other information terminals and can also charge the device. Charging can also be performed by wireless power supply.

[0394] 20(D), (E), and (F) are perspective views showing a foldable mobile information terminal 9201. FIG. 20(D) shows the portable information terminal 9201 in an unfolded state, and FIG. 20(F) shows the portable information terminal 9201 in a folded state. Folded state, Figure 20(E) is in the process of changing from Figure 20(D) to Figure 20(F) The portable information terminal 9201 is highly portable when folded, and can be easily expanded. When opened, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 201 is made up of three housings 900 connected by hinges 9055. For example, the display unit 9001 has a curvature radius of 0.1 mm or more and 150 mm or less. Can be bent downwards.

[0395] This embodiment mode can be combined with other embodiment modes and examples as appropriate. [Example]

[0396] In this example, a transistor was fabricated using a method for fabricating a transistor according to one embodiment of the present invention. The results of the evaluation will be explained below. Two types of samples were prepared.

[0397] As Sample A to which one embodiment of the present invention is applied, the transistors shown in FIGS. 3A to 3C are A laminated structure corresponding to the structure of 100A was formed. Specifically, a conductive layer 1 was formed on a substrate 102. 06, insulating layer 103, semiconductor layer 108, gate insulating layer 110, gate electrode 112, insulating layer Further, the insulating layer 118, the conductive layer 120a, and the conductive layer 120b were formed. A planarizing film (not shown) was formed over the layer 120a and the conductive layer 120b.

[0398] For comparative sample B, a stacked structure corresponding to the structure of the transistor shown in FIG. 21 shows cross sections of the transistor in the channel length direction and the channel width direction. Specifically, a conductive layer 106, an insulating layer 103, a semiconductor layer 108, a gate insulating layer 109, a gate insulating layer 110, a gate insulating layer 111, a gate insulating layer 112, a gate insulating layer 113, a gate insulating layer 114, a gate insulating layer 115, a gate insulating layer 116, a gate insulating layer 117, a gate insulating layer 118, a gate insulating layer 119 ... 110, a metal oxide layer 114, a gate electrode 112, an insulating layer 118, a conductive layer 120a, and The conductive layer 120b was formed. Furthermore, the insulating layer 118, the conductive layer 120a, and the conductive layer 120b were formed. A planarizing film (not shown) was formed on b.

[0399] In Sample A to which one embodiment of the present invention is applied, as described in Embodiment 1, the gate insulating layer 1 After forming a metal oxide layer 114 on the substrate 10 and performing a heat treatment, the metal oxide layer 114 is completely removed. On the other hand, in the comparative sample B, the metal oxide layer 114 was removed after the heat treatment. I didn't leave.

[0400] A specific method for manufacturing a transistor will be described below with reference to FIGS.

[0401] First, a tungsten film having a thickness of about 100 nm is formed on a glass substrate (corresponding to the substrate 102) by spat. The conductive layer 106 was formed by forming it by a pulverizing method and processing it (FIG. 5(A)).

[0402] Next, an insulating layer 103 was formed on the substrate 102 and the conductive layer 106 (FIGS. 5A and 6A). In this embodiment, as the insulating layer 103, as shown in FIG. a, an insulating layer 103b on the insulating layer 103a, and an insulating layer 103c on the insulating layer 103b. As the insulating layer 103a, a silicon nitride film having a thickness of about 240 nm was formed. b is a silicon nitride film having a thickness of about 60 nm, and The silicon oxynitride films were formed by plasma CVD.

[0403] Next, an IGZO film with a thickness of about 40 nm is formed on the insulating layer 103 and processed to form a semiconductor. The IGZO film was formed by sputtering. A metal oxide target with a ratio of In:Ga:Zn=1:1:1 was used, and the oxygen flow rate was 5 After the IGZO film was formed, it was heated for 3 hours in a nitrogen atmosphere. Heat treatment was carried out at 50°C for 1 hour, followed by heating at 350°C in a mixed atmosphere of oxygen and nitrogen. Heat treatment was carried out for 1 hour.

[0404] Next, plasma treatment was performed for 20 seconds in an atmosphere containing N2O gas, and then the insulating A gate insulating layer 110 was formed on the layer 103 and the semiconductor layer 108 (FIG. 5C and FIG. 6). In this embodiment, as the gate insulating layer 110, as shown in FIG. 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. As the insulating layer 110a, a silicon oxynitride film having a thickness of about 5 nm was formed. The insulating layer 110b is a silicon oxynitride film having a thickness of about 140 nm, and the insulating layer 110c is a silicon oxynitride film having a thickness of about 140 nm. A silicon oxynitride film with a thickness of approximately 5 nm was formed on each of the insulating layers by plasma CVD. The layer 110a and the insulating layer 110c are formed under conditions in which the film formation rate is lower than that of the insulating layer 110b. was formed.

[0405] Next, a metal oxide layer 114 is formed on the gate insulating layer 110 by oxidizing a silicon dioxide gas in an oxygen-containing atmosphere. An aluminum oxide film with a thickness of about 5 nm was formed by sputtering (Fig. 5(C)). By forming the metal oxide layer 114 in an atmosphere containing oxygen, the metal oxide layer 114 in the gate insulating layer 110 The substrate temperature during the deposition of the aluminum oxide film was 170°C. After forming the aluminum oxide film, the substrate was heated at 350°C for 1 minute in a mixed atmosphere of oxygen and nitrogen. Heat treatment was carried out for 1 hour.

[0406] Here, in the sample A, after removing the metal oxide layer 114 entirely (FIG. 5(D)), On the other hand, in the comparative sample B, the metal oxide layer 114 was not removed, and the next step was carried out. It progressed to the point.

[0407] Next, a conductive film was formed on the gate insulating layer 110 of the sample A and on the metal oxide layer 114 of the comparative sample B. As the film 112f, a molybdenum film having a thickness of about 100 nm was formed by sputtering ( 5(E)), and processing was performed to form a gate electrode 112 (FIG. 7(A)).

[0408] Next, boron (B) was supplied using a plasma ion doping device (FIG. 7(B) and In this step, the gate electrode 112 is used as a mask to remove the semiconductor layer 108 and Boron was provided to the gate insulating layer 110 (and also to the metal oxide layer 114 in the comparative sample B). The gas used to supply boron was B2H6 gas, and the acceleration voltage was 40 kV. The amount of noise is 2 x 10 15 ions / cm 2 It was decided.

[0409] Next, on the gate insulating layer 110 and the gate electrode 112, an insulating layer 118 having a thickness of about 30 A 0 nm silicon oxynitride film was formed by plasma CVD (Fig. 8(A)).

[0410] Next, openings were made in parts of the gate insulating layer 110 and the insulating layer 118. In the comparative sample B, A portion of the oxide layer 114 was also opened. Then, a molybdenum film having a thickness of about 100 nm was sputtered. The conductive layer 120a and the conductive layer 120b were formed by forming and processing the conductive layer 120a and the conductive layer 120b. Figure 8(B)).

[0411] Thereafter, an acrylic film having a thickness of about 1.5 μm is formed as a flattening film (not shown), and nitrogen is The mixture was subjected to a heat treatment at 250°C for 1 hour in an atmosphere.

[0412] In this manner, each sample was prepared.

[0413] Next, the Id-Vg characteristics of the transistors were measured for each sample. 23(A) shows the transistor of sample A, and FIG. 22(B) and FIG. 23(B) show the transistor of comparative sample B. 22(A) and 22(B) show the Id-Vg characteristics of the capacitor. The results are for a transistor with a 2 μm peak and a channel width (W) of 3 μm. 3(B) shows the results of a transistor with a channel length (L) of 3 μm and a channel width (W) of 3 μm. The result is...

[0414] The measurement conditions for the Id-Vg characteristics of the transistor are as follows: voltage ( Gate voltage (Vg) and the voltage applied to the conductive layer 106 (back gate voltage (Vbg)) The voltage was applied from -15 V to +20 V in 0.25 V steps. The voltage applied to the source electrode (Vs) is set to 0V (comm), and the voltage applied to the drain electrode is set to 0V (comm). The drain voltage (Vd) was set to 0.1V and 10V.

[0415] In Figures 22 and 23, the vertical axis represents the drain current (Id (A)) and the horizontal axis represents the gate voltage (V g(V)).

[0416] As shown in Figures 22 and 23, there is no significant difference in the Id-Vg characteristics between sample A and comparative sample B. No change was observed, and good characteristics were obtained.

[0417] Next, a stress test of the transistor was carried out for each sample.

[0418] The stress test was a gate bias thermal (GBT) stress test. The table shows the results of the PBTS test and the NBTIS test. In the PBTS test, the transistor The substrate on which the transistor is formed is kept at 60°C, and 0V is applied to the source and drain of the transistor, and 0V is applied to the gate. A voltage of 45 V was applied to the transistor and this state was maintained for 3600 seconds. The substrate on which the transistor is formed is kept at 60°C and irradiated with 10,000 lx white LED light. With this in place, apply a voltage of 0V to the source and drain of the transistor and -45V to the gate. This state was maintained for 3600 seconds.

[0419] Figure 24 shows the results of the PBTS test and NBTIS test for Sample A and Comparative Sample B. 4 shows the results for a transistor with a channel length (L) of 2 μm and a channel width (W) of 3 μm. do.

[0420] As shown in FIG. 24, compared to comparative sample B, sample A had a lower threshold voltage in the PBTS test. The amount of pressure fluctuation (ΔVth) was approximately 1 / 6, demonstrating extremely high reliability.

[0421] In this way, by removing the entire metal oxide layer 114 after the heat treatment, the deterioration of the PBTS can be reduced. A wide range of improvements was observed.

[0422] From the above, by removing the metal oxide layer 114 completely after the heat treatment, the electrical properties and It was found that a transistor with both excellent properties and reliability could be fabricated. [Explanation of symbols]

[0423] 100 transistors 100A transistor 102 Circuit Board 103 Insulating layer 103a Insulating layer 103b insulating layer 103c Insulating layer 103d area 103e Insulating layer 106 Conductive layer 106c conductive layer 108 Semiconductor layer 108c Semiconductor layer 108n low resistance region 110 Gate insulating layer 110a insulating layer 110b insulating layer 110c insulating layer 110d area 112 gate electrode 112f conductive film 114 Metal oxide layer 118 Insulating Layer 120a Conductive layer 120b conductive layer 130A Capacitive Element 130B Capacitive element 140 Impurity elements 141a opening 141b opening 142 Opening 400 pixel circuit 400EL pixel circuit 400LC pixel circuit 401 Circuit 401EL circuit 401LC circuit 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 700 Display device 700A display device 700B display unit 701 First substrate 702 pixel section 704 Source Driver 705 Second board 706 Gate Driver 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 717 IC 721 Source Driver IC 722 Gate Driver 723 FPC 724 Printed Circuit Board 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 740 protective layer 741 Protective layer 742 Adhesive layer 743 Resin layer 744 Insulation Layer 745 Support substrate 746 Resin layer 750 transistors 752 transistors 760 Wiring 770 Planarization insulating film 772 Conductive layer 773 Insulation Layer 774 Conductive Layer 775 Liquid Crystal Elements 776 Liquid Crystal Layer 778 Spacer 780 Anisotropic Conductive Film 782 Light-emitting element 786 EL layer 788 Conductive Film 790 Capacitor 6000 Display Module 6001 Top cover 6002 Lower cover 6005 FPC 6006 Display device 6009 Frame 6010 printed circuit board 6011 Battery 6015 Light-emitting part 6016 Light receiving section 6017a Light guiding section 6017b Light guiding part 6018 light 6500 Electronic equipment 6501 Housing 6502 Display section 6503 Power button 6504 Button 6505 Speaker 6506 Microphone 6507 Camera 6508 Light source 6510 Protective materials 6511 Display Panel 6512 Optical components 6513 Touch Sensor Panel 6515 FPC 6516 IC 6517 Printed Circuit Board 6518 Battery 7000 Display 7100 Television equipment 7101 Housing 7103 Stand 7111 Remote control device 7200 Notebook Personal Computer 7211 Case 7212 keyboard 7213 Pointing Device 7214 External connection port 7300 Digital Signage 7301 Housing 7303 Speaker 7311 Information terminals 7400 Digital Signage 7401 Pillar 7411 Information terminals 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8006 Lens 8100 Finder 8101 Housing 8102 Display section 8103 Button 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 8300 Head Mounted Display 8301 Housing 8302 Display section 8304 Fixtures 8305 Lens 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Icon 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal

Claims

1. Forming a first insulating layer containing silicon oxide; forming an oxide semiconductor layer containing In, Ga, and Zn in contact with an upper surface of the first insulating layer; forming a gate insulating layer containing silicon oxide above the oxide semiconductor layer; forming a metal oxide layer above the gate insulating layer; After forming the metal oxide layer, a heat treatment is performed, After the heat treatment, the metal oxide layer is removed; After removing the metal oxide layer, a gate electrode having a region overlapping with the oxide semiconductor layer is formed on the gate insulating layer; after forming the gate electrode, supplying a first element to the oxide semiconductor layer through the gate electrode and the gate insulating layer; the first element is phosphorus, boron, magnesium, aluminum, or silicon; the oxide semiconductor layer has crystallinity; A method for manufacturing a semiconductor device.

2. Forming a first insulating layer containing silicon oxide; forming an oxide semiconductor layer containing In, Ga, and Zn in contact with an upper surface of the first insulating layer; forming a gate insulating layer containing silicon oxide above the oxide semiconductor layer; forming a metal oxide layer above the gate insulating layer; After forming the metal oxide layer, a heat treatment is performed, After the heat treatment, the metal oxide layer is removed; After removing the metal oxide layer, a gate electrode having a region overlapping with the oxide semiconductor layer is formed on the gate insulating layer; after forming the gate electrode, supplying a first element to the oxide semiconductor layer through the gate electrode and the gate insulating layer; the first element is phosphorus, boron, magnesium, aluminum, or silicon; the oxide semiconductor layer has two or more metal oxide layers with different crystallinity; A method for manufacturing a semiconductor device.

3. In claim 1 or 2, The method for manufacturing a semiconductor device, wherein the metal oxide layer includes an aluminum oxide film.

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