Semiconductor device

Abstract

To provide a semiconductor device capable of achieving an off state without causing an increase in power consumption.SOLUTION: The semiconductor device includes: a power element under an on state without a voltage applied to a gate; a switching field effect transistor for applying a first voltage to a gate of the power element; and a switching field effect transistor for applying a lower voltage than the first voltage to the gate of the power element. The switching field effect transistor has a low off current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a method for driving a semiconductor device, or a semiconductor device. The present invention relates to an electronic device equipped with the device.

[0002] In addition, in this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. For example, power devices, display devices and integrated circuits that include such power devices. The circuit and the like are included in the semiconductor device. [Background technology]

[0003] Semiconductor devices used as power devices are made using silicon-based materials. Power devices are widely available. Power devices using silicon have a band gap Therefore, in recent years, the band gap has been widened. Power devices using SiC and GaN are being developed (see, for example, Patent Document 1). ). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-10142 Summary of the Invention [Problem to be solved by the invention]

[0005] HFET (heterojunction field effect transistor) is a power device that uses GaN. The HFET is made up of an AlN buffer layer, a GaN layer, and an AlGaN layer stacked on a SiC substrate. A structure in which a source electrode, a gate electrode, and a drain electrode are provided on the AlGaN layer. In addition, due to the difference in band gap between the GaN layer and the AlGaN layer, A highly concentrated two-dimensional electron gas layer is formed at the interface between the AlGaN layer and the AlGaN layer. Since the conduction band has a lower energy level than the Fermi level, in HFETs, a two-dimensional electron gas layer This is a normally-on transistor, where current flows even when no voltage is applied to the gate. This causes problems because the drive circuits and protection circuits become complicated. If the electron concentration is simply reduced to make the device normally off, the resistance of the device will increase. Therefore, it is very difficult to achieve both a normally-off state and low resistance. Attempts have been made to achieve normally-off operation by devising a device structure. This increases the complexity of the manufacturing process and increases the manufacturing costs.

[0006] In view of the above, one embodiment of the present invention is to realize an off state without increasing power consumption. It is an object of the present invention to provide a semiconductor device that can [Means for solving the problem]

[0007] One aspect of the present invention is a power element that is in an on state when no voltage is applied to the gate. a switching field effect transistor for applying a first voltage to the gate of the power element; and a switching transistor for applying a voltage lower than the first voltage to the gate of the power element. and a field effect transistor for switching the field effect transistor. The semiconductor device has a small current. A semiconductor device in which a channel region is formed of an i-type or substantially i-type oxide semiconductor layer The switching field effect transistor applies a high potential to the gate of the power element. Alternatively, a low potential is applied to obtain the on and off states of the power element.

[0008] One aspect of the present invention is an oxide semiconductor device having a first gate and a second gate, and an n-type channel region. a power MOSFET formed of a nitride semiconductor layer, and a first gate and a second gate of the power MOSFET. a switching field effect transistor for applying a positive voltage to the first gate and the second gate; A switching element for applying a negative voltage to the first gate and the second gate of the power MOSFET and a field effect transistor for switching the first gate and the second gate of the power MOSFET. The node of the port is connected to a switching field effect transistor, and the switching An oxide semiconductor in which the channel region of a field-effect transistor is made i-type or substantially i-type It is a semiconductor device formed by a layer. - Applying a high or low potential to the first gate and the second gate of the MOSFET - Obtain the on and off states of the MOSFET.

[0009] According to another aspect of the present invention, there is provided a semiconductor device including: a first field effect transistor connected to a high voltage generation source; a second field effect transistor connected to the first field effect transistor; a third field effect transistor connected to the second transistor and connected to a low voltage source; a capacitance element connected to the field effect transistor and the third field effect transistor; a power MOSFET connected to the second field effect transistor; The power MOSFET has a first gate and a second gate, and a gate electrode connected to the first gate. a first insulating layer, a second insulating layer in contact with the second gate, and a first insulating layer and a second insulating layer an oxide semiconductor layer formed between the source and drain regions and a source region and a drain region in contact with the oxide semiconductor layer; The first and second terminals function as a gate electrode, and the second gate electrode The gate is connected to the first field effect transistor and the second field effect transistor. The channel forming regions of the field effect transistor to the third field effect transistor are made i-type. The oxide semiconductor layer of the power MOSFET is an n-type. It is a semiconductor device.

[0010] The carrier concentration in the oxide semiconductor layer of a power MOSFET is 1×10 16 cm -3 1x1 or more 0 20 cm -3 Less than 1 × 10 17 cm -3 More than 1×10 20 cm -3 Below be.

[0011] Switching field effect transistor, first field effect transistor to third field effect transistor The carrier concentration of the oxide semiconductor layer of the transistor is 5×10 14 cm -3 is less than.

[0012] The first gate or the second gate of the power MOSFET is connected to the first terminal or the second terminal. It is also possible to overlap one with the other and not overlap the other. [Effects of the Invention]

[0013] According to one aspect of the present invention, a power supply that can realize an off state without increasing power consumption. It is possible to provide a device and a semiconductor device having the same. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 2] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 3] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 4] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 5] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device of one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 1 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 9] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device of one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 13] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 14] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 15] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 16] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 17] FIG. 1 is an equivalent circuit diagram illustrating a semiconductor device of one embodiment of the present invention. [Figure 18] FIG. 1 is a diagram illustrating an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. It is to be understood that the invention may be practiced in various different ways without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various changes can be made in form and detail. It should not be construed as being limited to the description of the present embodiment. In the present invention, reference numerals indicating the same objects are common among different drawings.

[0016] The size, layer thickness, or area of each component shown in the drawings of each embodiment is The figures may be exaggerated for clarity and are not necessarily limited to the scale. Not determined.

[0017] In addition, the terms "first," "second," "third," and "Nth" (N is a natural number) used in this specification refer to the structures It is added to avoid confusion of constituent elements and is not intended to limit the number. do.

[0018] Voltage is the difference between a certain potential and a reference potential (for example, ground potential). Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage difference, respectively. It is possible to do this.

[0019] Also, when it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are functionally connected, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) , wiring, electrodes, terminals, conductive layers, layers, etc.). Therefore, a predetermined connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be modified to include the connection relationships shown in the drawings or text. This also includes matters other than those in charge.

[0020] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device that is a power device will be described. explain.

[0021] The semiconductor device shown in FIG. 1 includes a power element 110 and a control circuit 100. 0 denotes a field effect transistor 102 (also referred to as a first transistor), a field effect transistor a field-effect transistor 103 (also referred to as a second transistor), a field-effect transistor 104 (also referred to as a third transistor), (also referred to as a transistor), a capacitor 105, an overvoltage detection circuit 106, a refresh control It includes a circuit 107, a high voltage source 108, and a low voltage source 109.

[0022] The control circuit 100 controls the high voltage source 108 to generate a voltage to be applied to the power element 110. The input terminal I The amount of current that flows through the power element 110 when an overvoltage is applied between N and the output terminal OUT Control.

[0023] The field effect transistor 102 has a gate connected to the overvoltage detection circuit 106 and a first terminal The first terminal is connected to a high voltage source 108, and the second terminal is connected to a power element 110. As a result, the transistor 102 detects the application of a high potential to the power element 110 connected to the second terminal. Control.

[0024] The field effect transistor 103 has a gate connected to the overvoltage detection circuit 106 and a first terminal is connected to the capacitor 105 and the second terminal of the field effect transistor 104, and the second terminal is connected to the power element 110.

[0025] The field effect transistor 103 receives the low voltage charged in the capacitor element 105 from the low voltage generating source 109. The application of a potential to the power element 110 connected to the second terminal is controlled.

[0026] The off-state current described in this specification is the current that flows through the source when the field-effect transistor is off. The current that flows between the source and drain, i.e., between the first terminal and the second terminal.

[0027] The gate of the field effect transistor 104 is connected to the refresh control circuit 107. The first terminal is connected to a low voltage source 109, and the second terminal is connected to a capacitance element 105 and a field effect transistor. The first terminal of the field effect transistor 103 is connected to the second terminal of the field effect transistor 104. The capacitor 105 connected to the power supply 101 controls charging of the low potential.

[0028] The channel regions of the field effect transistors 102 to 104 are i-type. or is formed of a substantially i-type oxide semiconductor layer. The oxide semiconductor layer has a carrier density of 5×10 14 cm -3 Less than 1x1 0 12 cm -3 less than 1×10 11 cm -3 The following is also true of donors and It is preferable that the hydrogen and oxygen vacancies that contribute to the formation of the oxide are small. 16 cm -3 The carrier density is preferably obtained by measuring the Hall effect. The carrier density of the concentration is measured by CV measurement (Capacitance-Voltage-Mechanism). The hydrogen concentration in the oxide semiconductor layer is obtained from the measurement results. The measurement is performed using secondary ion mass spectrometry (SIMS). It is obtained by spectroscopic analysis.

[0029] A field-effect transistor using an i-type or substantially i-type oxide semiconductor in the channel region The resistor 102 has an off-state current of 1×10 -16 A / μm or less, even 1×10 -19 A / The size can be reduced to less than 1 μm. However, because the band gap is wide and a large amount of thermal energy is required for electron excitation, Therefore, when a negative potential is applied to the gate electrode, In the off state, the minority carriers, holes, are essentially zero, so direct recombination occurs. Indirect recombination is unlikely to occur, and the current becomes infinitesimally small. When the transistor is in a non-conducting (off) state, the oxide semiconductor layer is regarded as an insulator. On the other hand, it is possible to design circuits by combining these two. The conductor layer is a semiconductor layer made of amorphous silicon when the field effect transistor is in a conductive state. It is expected that the current supply capacity will be higher than that of the conductor layer. The field effect transistors 102 to 104 are enhancement type transistors, and in the off state, It has a very small leakage current and is normally off, providing excellent switching characteristics.

[0030] The capacitor 105 controls the conduction (ON) of the field-effect transistor 104 intermittently. ) is an element for maintaining a low potential applied to the power element 110. 05 may be formed by a structure in which an insulating layer is sandwiched between conductors.

[0031] The overvoltage detection circuit 106 detects the voltage between the input terminal IN and the output terminal OUT by detecting the field effect. In order to control the conduction or non-conduction of the result transistor 102 and the field effect transistor 103, Specifically, when an overvoltage is applied between the input terminal IN and the output terminal OUT, When this occurs, the field effect transistor 102 is made conductive and the field effect transistor 103 is made non-conductive. , controls the application of a high potential from the high voltage source 108 to the power element 110. When no overvoltage is applied between the terminal IN and the output terminal OUT, the field effect transistor 1 02 is made non-conductive, and the field effect transistor 103 is made conductive, generating a low voltage to the power element 110. The application of a low potential charged from the power source 109 to the capacitance element 105 is controlled.

[0032] The refresh control circuit 107 controls the charging of the low potential from the low voltage generating source 109 to the capacitance element 105. A circuit that controls the conduction or non-conduction of the field effect transistor 104 to control the current. Specifically, the low voltage generated by the low voltage generating source 109 is stored in the capacitance element 105. Before the potential is discharged to the power element 110, the field effect transistor 104 is made to conduct intermittently. It is a circuit for charging at low potential.

[0033] The power element 110 is a power element that is turned on when no voltage is applied to the gate. The power element 110 is a bipolar transistor using Si, SiC, GaN, or an oxide semiconductor. FET (Field-Effect Transistor) insulator), gate turn-off thyristor, insulated gate bipolar transistor In addition, in the field effect transistor, power MOSFET (Metal Oxide Semiconductor FET), Use HFET, JFET (junction field effect transistor), etc. as appropriate. The equivalent circuit of the three-terminal power element 121 is shown in FIG. 2(A). The gates of the field effect transistors 102 and 103 are connected to the field effect transistors 102 and 103. In addition, one of the source terminal and the drain terminal of the power element 121 is set as a first terminal, and the source terminal The other of the input and drain terminals is the second terminal, and the first terminal is connected to the input terminal IN. The second terminal is connected to the output terminal OUT.

[0034] In the present embodiment, as a representative example of the power element 110, a power element 110 shown in FIG. The following description will be given using a four-terminal power MOSFET 101.

[0035] The power MOSFET 101 has four terminals, typically a first gate terminal (first gate a second gate terminal (called the second gate), and a drain terminal (called the drain The power MOSFET 101 has a gate terminal (also called a gate) and a source terminal (also called a source). A first gate and a second gate are disposed above and below the channel region. A signal for controlling the switching of the power MOSFET 101 is supplied to the gate of the power MOSFET 101 .

[0036] A power M in which a first gate 201 and a second gate 206 are arranged above and below a channel region The circuit symbol of the OSFET 101 is shown in Figure 2(C). As shown in Figure 2(C), The SFET 101 has a first gate 201, a second gate 206, and a first terminal 204A. The power MOSFET 101 has a first gate 201 and a second terminal 204B. and a second gate 206 is connected to the high voltage source 108 or the low voltage source 109. A signal (signal G shown in FIG. 2C) is input to the high voltage source 108 or the low voltage source The first terminal 204A of the power MOSFET 101 and Switching between the two terminals 204B, such as conduction or non-conduction, is controlled.

[0037] The channel region of the power MOSFET 101 is formed of an n-type oxide semiconductor layer. The n-type oxide semiconductor layer has a carrier density of 1×10 16 cm -3 More than 1×10 20 cm -3 Less than 1 × 10 17 cm -3 More than 1×10 20 cm -3 Below is In addition, in an oxide semiconductor, hydrogen and oxygen vacancies act as donors. Concentration is 1×10 16 cm -3 More than 1×10 20 cm -3 It is preferable that:

[0038] The power MOSFET 101 has an n-type oxide semiconductor layer in the channel region, The on-resistance is higher than that of a power MOSFET that has an i-type oxide semiconductor layer in the channel region. It is possible to reduce the resistance and allow a large current to flow. Since the device has an oxide semiconductor layer in the channel region, it is a depletion type device. It is a normally-on type in which current flows even when no voltage is applied. The power MOSFET has a first gate 201 and a second gate 206. It can be turned off by applying a negative voltage to the gate 201 and the second gate 206. For this reason, power MOSFETs have low on-resistance and are capable of passing large currents. On the other hand, when a positive voltage is applied to the first gate 201 and the second gate 206, The power MOSFET 101 can be turned on by applying a voltage. Since it has a first gate 201 and a second gate 206, it is a single-gate power MOS Compared to FETs, increasing the thickness of the channel region makes the threshold voltage more negative, It is possible to increase the on-current.

[0039] Next, the operation of the semiconductor device shown in FIG. 2B will be described with reference to FIGS. 3 and 4. In the explanation of FIG. 4, the dotted arrows indicate the power MOSFET 101 and each field effect transistor. The signal flow due to the conduction or non-conduction of the transistor is visualized for easy understanding. In addition, in the channel region of the power MOSFET 101 constituting the semiconductor device, The n-type oxide semiconductor layer is used, and is turned on by a high potential from a high voltage source 108. 2(A) , the low potential from the low voltage generating source 109 makes the transistor non-conductive. The operation of the semiconductor device shown in FIG. 3 is the same as that of the power MOSFET shown in FIG. 101 can be replaced with a power element 121.

[0040] FIG. 3A illustrates the operation when the power MOSFET 101 is turned on. The voltage detection circuit 106 controls the field effect transistor 102 to turn it on. The refresh control circuit 107 controls the field effect transistor 103 to be non-conductive. By making the field effect transistor 102 conductive, A high potential is applied from a high voltage source 108 to the first gate and the second gate of the power MOSFET 101. When this voltage is applied to the power MOSFET 101, the power MOSFET 101 becomes conductive.

[0041] FIG. 3B illustrates the operation when the power MOSFET 101 is made non-conductive. The overvoltage detection circuit 106 controls the field effect transistor 102 to be non-conductive, and the field effect The transistor 103 is turned on, and the field effect transistor 104 is turned on by the control of the refresh control circuit 107. As shown in FIG. 3B, the field effect transistor 104 is turned off. By making the terminal 03 conductive, the low voltage generated by the low voltage generating source 109 is charged in the capacitor element 105. A potential is applied to the first gate and the second gate of the power MOSFET 101, and the power M The OSFET 101 becomes non-conductive.

[0042] FIG. 3C illustrates the operation of charging the capacitor 105 with a low potential, which is described in FIG. 3B. The overvoltage detection circuit 106 controls the field effect transistor 102 to be non-conductive and the .... The field effect transistor 103 is turned on, and the refresh control circuit 107 controls the field effect transistor 103 to turn on. The effect transistor 104 is turned on, and a low potential is applied from the low voltage source 109 to the capacitance element 105. Charge the battery.

[0043] The charging of the capacitor 105 to a low potential as described in FIG. 3C is performed by the refresh control circuit 1 07 controls the charging from the low voltage source 109. As a result, the capacitor 105 maintains a low potential that makes the power MOSFET 101 non-conductive. During this time, the semiconductor device maintains the state shown in FIG. 3(B). Then, it intermittently changes to the state shown in FIG. 3(C). Then, the field effect transistor 104 is turned on, and the low potential is charged to the capacitor 105. For example, the operation of FIG. 3(C) can be performed once per minute, allowing enough time for charging. .

[0044] As described above, in the configuration of this embodiment, the state shown in FIG. 3(A) or the state shown in FIG. 3(B) can be achieved. 3(C) are repeated, but the period during which the state of FIG. 3(B) is maintained becomes longer.

[0045] Here, the effect of this embodiment will be described in detail with reference to FIG. The first gate and the second gate of the power MOSFET 101 in the state of FIG. a node connected to the output terminal, the field effect transistor 103, and one end of the capacitance element 105 The children are shown with solid lines, and other connections are shown with dashed lines.

[0046] When the field effect transistor 102 and the field effect transistor 104 become non-conductive, The node connected to the first gate and the second gate of the power MOSFET 101 is connected to a voltage As described above, the field effect transistor 1 The channel region of the field effect transistor 104 is made i-type or substantially i-type. Since it is made of an oxide semiconductor layer, the off-state current is extremely small. The node connected to the first gate and the second gate of the OSFET 101 is connected to a low voltage source The low potential charged from the capacitor 109 to the capacitor 105 can be maintained for a long period of time. Instead of applying a low potential to the capacitor, a low potential may be applied to the capacitor intermittently. When a low potential is applied to the first gate and the second gate of the MOSFET 101, the power M The OSFET 101 is turned off. The power MOSFET 101 can be turned off without increasing the .

[0047] In the semiconductor device shown in FIG. 2C, the first gate of the power MOSFET 101 In order to improve the retention characteristics of the potential of the node connected to the first gate and the second gate, A capacitance element 401 is separately provided at a node connected to the first gate and the second gate so that In the semiconductor device shown in FIGS. 2(A) and 2(B), A capacitance element 401 is provided at the gate of the power MOSFET 101 and the power element 121. You may do so.

[0048] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

[0049] (Embodiment 2) In this embodiment, the structure and manufacturing method of the power MOSFET 101 shown in Embodiment 1 will be described. This will be explained with reference to FIGS. 5 to 7.

[0050] FIG. 5A shows one example of a cross-sectional structure of the power MOSFET 101 according to the first embodiment. 5B shows a top view of the power MOSFET 101. corresponds to Figure 5(A).

[0051] The power MOSFET 101 shown in FIG. 5A has a first gate electrode made of a conductive layer on a substrate 200. A gate insulating layer 202 is provided on the first gate 201. An n-type oxide semiconductor layer 203 is provided on the insulating layer 202. A first terminal 204A and a second terminal 204B are provided, each of which is made of a conductive layer covering the oxide. An insulating layer 205 is formed over the semiconductor layer 203, the first terminal 204A, and the second terminal 204B. On the insulating layer 205, a first terminal 204A and a second terminal 204B are provided. A second gate 206 made of a conductive layer is formed to overlap the portion.

[0052] The substrate 200 must have at least sufficient heat resistance to withstand subsequent heat treatment. When a glass substrate is used as the substrate 200, a substrate having a distortion point of 730° C. or higher is used. The glass substrate is preferably made of, for example, aluminosilicate glass, aluminophore glass, or the like. Glass materials such as borosilicate glass and barium borosilicate glass are used. It is preferable to use a glass substrate containing more BaO than O3.

[0053] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material can be used. Alternatively, crystallized glass can be used. Furthermore, the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material It is also possible to use a material having an insulating layer formed on its surface.

[0054] Although not shown in FIG. 5A, a heat conduction layer is formed between the substrate 200 and the first gate 201. By forming an insulating layer with a high thermal conductivity, a power MOSFET 101 with high heat resistance can be fabricated. As an insulating layer with high thermal conductivity, aluminum nitride layer, aluminum nitride oxide layer, layer, silicon nitride layer, etc.

[0055] The first gate 201 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above-mentioned metal elements, or It can be formed by using an alloy combining metal elements such as manganese, ma A metallic element selected from one or more of magnesium, zirconium, and beryllium The first gate 201 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum layer containing silicon, a titanium layer on an aluminum layer, Two-layer structure with a titanium layer on a titanium nitride layer, two-layer structure with a titanium layer on a titanium nitride layer, Two-layer structure with a tungsten layer on top, and a tantalum nitride layer on top of a tungsten layer Two-layer structure: titanium layer, aluminum layer on top of titanium layer, and titanium layer on top of that. There are also three-layer structures that form an aluminum layer. Layers or layers of elements selected from stainless steel, molybdenum, chromium, neodymium, and scandium A combination of alloy layers or nitride layers may also be used.

[0056] The first gate 201 is made of indium tin oxide, indium containing tungsten oxide, or the like. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide with oxide, titanium dioxide Alternatively, a light-transmitting conductive material such as indium tin oxide may be used. Alternatively, the light-transmitting conductive material and the metal element may be laminated together.

[0057] The gate insulating layer 202 may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride layer, or a silicon nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or a stacked layer. The gate insulating layer 202 preferably contains oxygen in a portion in contact with the oxide semiconductor layer 203. It is particularly preferable to form the insulating film from a silicon oxide layer. This allows oxygen to be supplied to the oxide semiconductor layer 203, improving its characteristics.

[0058] The gate insulating layer 202 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide The gate leakage current can be reduced by using high-k materials and oxide materials. A silicon layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an alumina oxide layer. The gate insulating layer 202 may have a stacked structure with one or more of the aluminum layers. The thickness can be greater than or equal to 100 nm and less than or equal to 300 nm.

[0059] The n-type oxide semiconductor layer 203 is made of a quaternary metal oxide, In—Sn—Ga—Zn— O-based metal oxides, ternary metal oxides such as In-Ga-Zn-O-based metal oxides, and In- Sn-Zn-O metal oxide, In-Al-Zn-O metal oxide, Sn-Ga-Zn- O-based metal oxide, Al-Ga-Zn-O-based metal oxide, Sn-Al-Zn-O-based metal oxide and binary metal oxides such as In-Zn-O and Sn-Zn-O. materials, Al-Zn-O metal oxides, Zn-Mg-O metal oxides, Sn-Mg-O metals In this case, n-element metal oxides, In-Mg-O-based metal oxides, etc. can be used. The oxide is composed of n kinds of metal oxides. The oxide semiconductor layer contains the following impurities: Elements other than the metal oxides that are the main components may be contained in an amount of 1%, preferably 0.1%.

[0060] The n-type oxide semiconductor layer 203 is a ternary metal oxide, InM X Zn Y O Z (Y=0.5 to 5), where M is gallium. One or more elements selected from the group 13 elements such as (Ga), aluminum (Al), and boron (B) represents multiple elements. The contents of In, M, Zn, and O are optional, and the content of M is This includes the case where the content is zero (i.e., x=0). On the other hand, the content of In and Zn is not zero. That is, the above notation includes In-Ga-Zn-O based metal oxides and In-Zn-O based metals. metal oxide semiconductors and the like.

[0061] In addition, the metal oxide forming the n-type oxide semiconductor layer 203 has an energy gap of It is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more.

[0062] The n-type oxide semiconductor layer 203 may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single crystal structure. An oxide semiconductor having a crystal structure can be used as appropriate. An oxide semiconductor having parallel crystals can be used.

[0063] The n-type oxide semiconductor layer 203 has a carrier density of 1×10 16 cm -3 More than 1×10 20 cm -3 Less than 1 × 10 17 cm -3 More than 1×10 20 cm -3 Below is In an oxide semiconductor, hydrogen and oxygen vacancies act as donors, so the hydrogen concentration 1×10 16 cm -3 More than 1×10 20 cm -3 It is preferable that:

[0064] The thickness of the n-type oxide semiconductor layer 203 is set to a value that is negatively charged to the first gate and the second gate. When a voltage is applied, the depletion layer expands into the channel region, turning the power MOSFET 101 into a The thickness is set to a value that allows the device to be in the off state. The carrier density is 1×10 16 cm -3 1x or more 10 20 cm -3 The dielectric constant is 15, the band gap is 3.15, and the effective density of states of the conduction band is Degrees are Nc=2.8×10 19 cm -3 , the effective density of states in the valence band is Nv=1.04×10 19 cm -3 When a gate is located on one side of the oxide semiconductor layer, the maximum depletion layer width is The power MOSFET shown in FIG. Since the first gate 201 and the second gate 206 are provided, the thickness of the n-type oxide semiconductor layer 203 is The carrier density can be 1×10 17 cm -3 More than 1×10 20 cm -3 In the following cases, the maximum depletion layer width is 7 nm or more and 218 nm or more. In this case, the thickness of the n-type oxide semiconductor layer 203 is set to 14 nm or more and 436 nm or less. m or less.

[0065] The first terminal 204A and the second terminal 204B are made of aluminum, chromium, copper, tantalum, Metal elements selected from titanium, molybdenum, and tungsten, and those containing the above-mentioned metal elements The metal layer can be formed by using an alloy of the above metal elements or an alloy combining the above metal elements. Also, one or more of manganese, magnesium, zirconium, and beryllium Alternatively, a metal element selected from the group consisting of the first terminal 204A and the second terminal 204 may be used. B may have a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon a single layer structure of titanium on an aluminum layer, a two-layer structure of titanium on an aluminum layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer; a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer; Two-layer structure with a tungsten layer on a tantalum nitride layer, a titanium layer, and a There are also three-layer structures, such as an aluminum layer and a titanium layer on top of that. , aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, A layer of an element selected from scandium, or an alloy layer or nitride layer made by combining multiple elements may also be used.

[0066] The first terminal 204A and the second terminal 204B are made of indium tin oxide, tungsten oxide, or the like. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Conductive materials with transparency, such as indium tin oxide with added silicon oxide, are used. In addition, a laminate structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be formed. You can also do this.

[0067] For the insulating layer 205, the materials shown for the gate insulating layer 202 can be used as appropriate.

[0068] The second gate 206 can be made of any of the materials shown for the first gate 201 .

[0069] The power MOSFET 101 shown in FIG. 5 has an n-type oxide semiconductor layer in the channel region. Therefore, it is possible to reduce the on-resistance and allow a large current to flow. However, since it has an n-type oxide semiconductor layer in the channel region, it is a depletion type. This is a normally-on state in which current flows even when no voltage is applied to the gate. The power MOSFET shown in this embodiment has a first gate 201 and a second gate 206, and applying a negative voltage to the first gate 201 and the second gate 206 Therefore, the on-resistance is low and a large current can flow. On the other hand, the first gate 201 It can be turned on by applying a positive voltage to the second gate 206. Since the power MOSFET 101 has a first gate 201 and a second gate 206, ,By increasing the thickness of the channel region compared to single-gate power MOSFETs, This allows a large current to flow.

[0070] Also, as shown in FIG. 5(B), by connecting the power MOSFETs 101 in parallel, The transistor channel width W can be designed to be large. This allows for large current Therefore, it is possible to manufacture a power device capable of passing a current.

[0071] Next, FIG. 6 shows a cross-sectional structure of a power MOSFET different from that shown in FIG. 5. The power MOSFET 101A has a second gate 206A connected to the first terminal 204A and the second terminal 204B. It is characterized in that it overlaps one of the terminals 204B but does not overlap the other.

[0072] The power MOSFET 101A shown in FIG. 6A has a first gate electrode made of a conductive layer on a substrate 200. A gate insulating layer 202 is provided on the first gate 201. An n-type oxide semiconductor layer 203 is provided on the insulating layer 202. A first terminal 204A and a second terminal 204B are provided, each of which is made of a conductive layer and covers a part of the surface of the substrate. An insulating layer 205 is formed over the semiconductor layer 203, the first terminal 204A, and the second terminal 204B. Also, a first terminal 204A and a second terminal 204B are formed on the insulating layer 205. A second gate 206A made of a conductive layer is provided, overlapping one terminal 204B but not the other. That is, the oxide semiconductor layer 203 is formed so as to be in contact with the second gate 206A. A region 208 that does not overlap the first terminal 204A and the second terminal 204B is formed.

[0073] The second gate 206A is made of the same material and by the same manufacturing method as the second gate 206 shown in FIG. It can be formed by

[0074] The power MOSFET 101B shown in FIG. 6B has a first gate electrode made of a conductive layer on a substrate 200. A gate insulating layer 202 is provided on the first gate 201A. An n-type oxide semiconductor layer 203 is provided on the gate insulating layer 202. A first terminal 204A and a second terminal 204B are provided, each of which is made of a conductive layer and covers a part of the surface of the substrate 3. An insulating layer 20 is formed over the compound semiconductor layer 203, the first terminal 204A, and the second terminal 204B. 5 is provided on the insulating layer 205. Also, the first terminal 204A and A second gate 206A made of a conductive layer overlaps one of the two terminals 204B but not the other. That is, the oxide semiconductor layer 203 is formed so as to form the first gate 201A. The second gate 206A does not overlap with the first terminal 204A and the second terminal 204B. An offset region 209 is formed.

[0075] The first gate 201A is made of the same material and by the same manufacturing method as the first gate 201 shown in FIG. It can be formed by

[0076] The power MOSFET 101A and the power MOSFET 101B shown in FIG. 6 are n-type. Since the oxide semiconductor layer 203 is provided in the channel region, the on-resistance can be reduced. However, the n-type oxide semiconductor layer is Since the gate is in the depletion region, it is a depletion type. The power MOSFET shown in this embodiment is in a normally-on state, where a current flows even when the The first gate 201 or 201A has a second gate 206A, and the first gate Applying a negative voltage to 201 or 201A and the second gate 206A turns it off. and a positive voltage is applied to the first gate 201 or 201A and the second gate 206A. It can be turned on by applying a voltage. Therefore, the on-resistance is low and a large current can be This allows the power MOSFET to be turned off. , having a first gate 201 or 201A and a second gate 206A, Compared to a conventional gate power MOSFET, the thickness of the channel region can be increased. This allows a large current to flow. In B, a first gate 201A and a second gate 202B are formed in an n-type oxide semiconductor. 06A, the first terminal 204A, and the offset area 20 that is not covered by the second terminal 204B. 9, the drain breakdown voltage is lower than that of the power MOSFET 101 shown in FIG. It is possible to increase the voltage at the first terminal 204A or the second terminal 204B. It can be applied.

[0077] Here, a method for manufacturing the power MOSFET 101 shown in FIG. 5 will be described with reference to FIG. do.

[0078] As shown in FIG. 7A, a first gate 201 is formed on a substrate 200. Next, A gate insulating layer 202 is formed on the gate 201 .

[0079] The first gate 201 can be fabricated using a printing method, an inkjet method, or the like, thereby reducing the number of steps. Alternatively, a conductive layer can be formed by a sputtering method, a CVD method, a vapor deposition method, etc. After forming the conductive layer, the conductive layer is etched using a resist formed by a photolithography process as a mask. The first gate 201 can be formed by etching. When the end portion is tapered, the coverage of the insulating layer, the semiconductor layer, and the conductive layer to be formed later is reduced. In addition, a thermal barrier is preferably formed between the substrate 200 and the first gate 201. A highly conductive insulating layer is formed using methods such as sputtering, CVD, coating, and printing. It is preferable.

[0080] The gate insulating layer 202 is formed by a sputtering method, a CVD method, a printing method, a coating method, or the like. Alternatively, high density plasma can be generated using microwaves (for example, at a frequency of 2.45 GHz). By using CVD, a dense, high-quality gate insulating layer 202 with high dielectric strength can be formed. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Furthermore, the gate insulating layer 2 obtained by high density plasma CVD can be improved. 02 can be formed with a constant thickness, and has excellent step coverage. The thickness of the gate insulating layer 202 obtained by CVD can be precisely controlled.

[0081] Next, as shown in FIG. 7B, an n-type oxide semiconductor layer 20 The n-type oxide semiconductor layer 203 is formed by using a printing method, an inkjet method, or the like. Alternatively, the number of steps can be reduced by forming a gate insulating layer 202 on the gate insulating layer 202. N-type oxides are deposited by sputtering, CVD, coating, pulsed laser deposition, etc. After forming the semiconductor layer, the resist formed by the photolithography process is used as a mask. The oxide semiconductor layer is etched to form an island-shaped n-type oxide semiconductor layer 203. It is possible.

[0082] The carrier density of the oxide semiconductor layer is determined by the hydrogen concentration of the source gas and the target under the film formation conditions. The hydrogen concentration in the oxide semiconductor layer depends on the concentration of hydrogen and oxygen, the material to be deposited, and its composition. Alternatively, the oxygen concentration in the oxide semiconductor layer may be reduced to cause oxygen vacancies. Therefore, hydrogen or oxygen vacancies that act as a barrier can be contained in the oxide semiconductor layer. Therefore, an n-type oxide semiconductor layer can be formed.

[0083] After the oxide semiconductor layer 203 is formed, heat treatment is performed to change the oxide semiconductor layer 203 into a microcrystalline structure or a polycrystalline structure. Alternatively, the oxide semiconductor layer may have a single crystal structure. The oxide semiconductor layer may have a crystal structure in which crystals are substantially parallel.

[0084] Next, as shown in FIG. 7(C), a first terminal that functions as a source electrode and a drain electrode is formed. The first terminal 204A and the second terminal 204B are formed. 4B can be produced using printing methods, inkjet methods, etc., reducing the number of processes. Alternatively, a thin film can be formed over the gate insulating layer 202 and the oxide semiconductor layer 203 by a sputtering method. After forming a conductive layer by a CVD method, a vapor deposition method, or the like, a photolithography process is performed. The conductive layer is etched using the resist as a mask to form the first terminal 204A and the second terminal 204B. Terminal 204B can be formed.

[0085] Next, as shown in FIG. 7(D), the gate insulating layer 202, the oxide semiconductor layer 203, and the first terminal An insulating layer 205 is formed on the first terminal 204A and the second terminal 204B. Next, a second gate insulating layer 205 is formed on the insulating layer 205 in the same manner as the gate insulating layer 202. The second gate 206 can be formed in the same manner as the first gate. .

[0086] Through the above steps, a depletion-type oxide semiconductor layer having an n-type oxide semiconductor layer in a channel region is formed. In the above manufacturing process, the power MOSFET 101 can be manufactured. By changing the layout of the second gate, the power MOSFET 1 shown in FIG. 6B. The power MOSFET 101B shown in FIG. 6B can be fabricated by using the above-described method.

[0087] (Embodiment 3) In this embodiment, instead of the power MOSFET 101 shown in the first and second embodiments, The structure of a power MOSFET that can be used instead is explained using Figures 8 and 9. Reveal.

[0088] The power MOSFETs shown in FIGS. 8 and 9 have the following features compared to the power MOSFET shown in FIG. The difference is that there is no gate between the substrate 200 and the oxide semiconductor layer 213 .

[0089] The power MOSFET 111A shown in FIG. 8 includes an n-type oxide semiconductor layer 2 on a substrate 200. 13 is provided, and a first terminal 204A made of a conductive layer is provided to cover a part of the oxide semiconductor layer 213. , the second terminal 204B, the oxide semiconductor layer 213, the first terminal 204A, and the second terminal 204B. A gate insulating layer 212 is provided over the second terminal 204B, and a first insulating layer 212 is provided on the gate insulating layer 212. Gate 2 is a conductive layer that overlaps a portion of one of the first terminal 204A and the second terminal 204B. That is, the oxide semiconductor layer 213 is formed so as to be connected to the gate 211 and A region 208 that does not overlap the first terminal 204A and the second terminal 204B is formed.

[0090] As in the power MOSFET 101 shown in the second embodiment, the substrate 200 and the oxide semiconductor By forming an insulating layer with high thermal conductivity between the conductor layers 213, a power MOS with high heat resistance can be obtained. FET 111A can be fabricated. Also, the first terminal 204A and the second terminal 2 04B may be provided between the substrate 200 and the oxide semiconductor layer 213. Similarly, the first terminal 204A and the second terminal 204B do not have the region 208. A gate 211 made of an overlapping conductive layer may be provided.

[0091] The power MOSFET 111B shown in FIG. 9A has a first terminal made of a conductive layer on a substrate 200. A terminal 204A is provided, and an n-type oxide semiconductor is provided to cover the first terminal 204A made of a conductive layer. A conductive layer 213 is provided on the oxide semiconductor layer 213, and a second terminal 22 made of a conductive layer is provided to cover a part of the oxide semiconductor layer 213. A gate insulating layer 204B is provided to cover the oxide semiconductor layer 213 and the second terminal 204B. 212 is provided, and a gate 211 made of a conductive layer and a first terminal A wiring 214 is provided to connect to the first terminal 204A, and a wiring 215 is provided to connect to the second terminal 204B. It is formed so that it can be

[0092] FIG. 9(B) is a top view of the power MOSFET 111B shown in FIG. 9(A). 9(B) corresponds to the cross section of the second terminal 20 4B, and a gate 211 is disposed around a wiring 215 connected to the second terminal 204B. Also, around the gate 211, a first terminal 204A and a Wiring 214 is arranged.

[0093] That is, the first terminal 204A and the second terminal 204B do not overlap. The first terminal 204A and the second terminal 204B are provided in a region including a region that does not overlap with each other. A part (end) of the gate 211 is connected to one of the first terminal 204A and the second terminal 204B. It may be superimposed on either or both.

[0094] As in the power MOSFET 101 shown in the second embodiment, the substrate 200 and the first terminal By forming an insulating layer with high thermal conductivity between the electrode 204A and the oxide semiconductor layer 213, A power MOSFET 111B with high thermal resistance can be fabricated.

[0095] The oxide semiconductor layer 213 illustrated in FIGS. 8 and 9 is the same as the oxide semiconductor layer 203 described in Embodiment 2. The power MOSFET 11 shown in FIG. 1A and 9, the gate 211 is formed on the oxide semiconductor layer 21. Therefore, the thickness of the oxide semiconductor layer 213 is When a negative voltage is applied to 211, the depletion layer expands into the channel region, and the power MOSFET The thickness is set to a value that allows the ET111B to be turned off. In this embodiment, the number of gates is half that of the power MOSFET 101 shown in the second embodiment, the carrier density is 1×10 16 cm -3 More than 1×10 20 cm -3 In the following cases, the maximum depletion layer width is 7 nm or more. Therefore, the thickness of the n-type oxide semiconductor layer 213 is set to 7 nm or more to 677 nm or less. m or less. In addition, the carrier density can be 1×10 17 cm -3 More than 1×10 2 0 cm -3 In the following cases, the maximum depletion layer width is 7 nm or more and 218 nm or less. The thickness of the n-type oxide semiconductor layer 213 can be set to 7 nm or more and 218 nm or less. .

[0096] The method for fabricating the power MOSFET shown in FIGS. 8 and 9 is the same as that shown in FIGS. In addition, the method for fabricating the power MOSFET shown in the second embodiment can be used as appropriate. .

[0097] The power MOSFETs shown in Figs. 8 and 9 have an n-type oxide semiconductor layer in the channel region. Therefore, it is possible to reduce the on-resistance and allow a large current to flow. However, since the channel region has an n-type oxide semiconductor layer, it is a depletion type This is a normally-on state in which current flows even when no voltage is applied to the gate. In the power MOSFET shown in this embodiment, when a negative voltage is applied to the gate 211, It can be turned off by applying a positive voltage to the gate 211. Therefore, it is possible to use a power MO with low on-resistance and large current. The off state of the SFET can be realized.

[0098] (Fourth embodiment) In this embodiment, the field-effect transistors 102 to 104 shown in Embodiment 1 are The structure and manufacturing method of the resistor 104 will be described with reference to FIGS. The field effect transistors 102 to 104 may have the same structure. will be explained using the field effect transistor 102 as a representative example.

[0099] The field effect transistor 102 shown in FIG. 10 includes a gate 251 made of a conductive layer on a substrate 250. A gate insulating layer 252 is provided on the gate 251. The oxide semiconductor layer 253 is made i-type or substantially i-type. A first terminal 254A and a second terminal 254B made of a conductive layer are provided to cover a part of the surface of the substrate 53. , an insulating layer covering the oxide semiconductor layer 253, the first terminal 254A, and the second terminal 254B. 255 is provided.

[0100] The substrate 250 can be the substrate 200 described in Embodiment 2 as appropriate.

[0101] The gate 251 may be formed using the material shown in the first gate 201 in the second embodiment. can.

[0102] The gate insulating layer 252 is formed using the material for the gate insulating layer 202 described in Embodiment 2 as appropriate. The thickness of the gate insulating layer 252 can be set to 50 nm or more and 500 nm or less. By increasing the thickness of the gate insulating layer 252, it is possible to reduce the gate leakage current. can be done.

[0103] The oxide semiconductor layer 253 is formed using the metal oxide described for the oxide semiconductor layer 203 in Embodiment 2. In addition, an oxide semiconductor having an amorphous structure, a polycrystalline structure, or a single crystal structure can be used. In addition, a crystal having a c-axis that is nearly parallel to the direction perpendicular to the surface can be used. However, the oxide semiconductor layer 253 must be an i-type or is essentially i-type, so the carrier density is 5×10 14 cm -3 Less than, preferably is 1 x 10 12 cm-3 less than 1×10 11 cm -3 The following is true: It is preferable that the hydrogen and oxygen vacancies that contribute as donors are small, and the hydrogen concentration is 1×10 16 cm -3 The following is preferred:

[0104] By thoroughly removing hydrogen, the material is highly purified, oxygen vacancies are reduced, and the stoichiometric ratio is met. By using an oxide semiconductor layer that is made i-type or substantially i-type as a channel region, As a result, the off-state current of the transistor 102 is 1×10 -16 A or less. In the non-conducting state of the field-effect transistor, the oxide semiconductor layer can be regarded as an insulator. On the other hand, the oxide semiconductor layer 253 is a conductive material for a field effect transistor. In the on-state, it is expected to have a higher current supply capacity than semiconductor layers made of amorphous silicon. Therefore, the field effect transistor 102 is an enhancement type. In the off state, the device is in a normally off state with extremely low leakage current, providing excellent switching performance. It has characteristics.

[0105] The first terminal 254A and the second terminal 254B are the same as the first terminal 204A shown in the second embodiment. The materials shown for the first terminal 204A and the second terminal 204B can be used as appropriate.

[0106] The insulating layer 255 is preferably formed of an oxide insulating layer. Typical examples of oxide insulating layers include: The insulating layer may be a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. The insulating layer 205 may have a stacked structure of an oxide insulating layer and a nitride insulating layer. The insulating layer 2 may be a silicon nitride layer, a silicon nitride oxide layer, or an aluminum nitride layer. In the insulating film 55, a region in contact with the oxide semiconductor layer 253 is formed as an oxide insulating layer. This reduces oxygen deficiency in the compound semiconductor layer and satisfies the stoichiometric ratio.

[0107] It should be noted that the field effect transistor 102 can take a variety of forms and is not limited to any particular configuration. For example, a multi-gate structure with two or more gates can be applied. In this case, the gate electrodes can be arranged above and below the channel region. By arranging the gates above and below the channel region, two field-effect transistors are formed. It is also possible to configure the inverters in such a way that the inverters are connected in parallel.

[0108] Here, a method for manufacturing the field effect transistor 102 shown in FIG. 10 will be described with reference to FIG. explain.

[0109] As shown in FIG. 11(A), a gate 251 is formed on a substrate 250. Next, a gate 2 On the gate insulating layer 51, a gate insulating layer 252 is formed.

[0110] The gate 251 can be formed by the method for forming the first gate 201 shown in Embodiment 2. The gate insulating layer 252 can be formed by the method for forming the gate insulating layer 202 described in Embodiment 2. Note that when an oxide semiconductor layer is made i-type or substantially i-type, Since the gate insulating layer 252 is extremely sensitive to the interface state and the interface charge, By forming the layer using high density plasma CVD, the interface state density is reduced and the interface characteristics are improved. It is possible.

[0111] When the gate insulating layer 252 is formed, the substrate 200 is heated to form the gate insulating layer 252. It is possible to reduce the hydrogen, water, hydroxyl groups, hydrides, etc. contained in 252.

[0112] In addition, in order to reduce hydrogen, water, a hydroxyl group, hydride, and the like contained in the gate insulating layer 252, When the gate insulating layer 252 is formed by a sputtering method, hydrogen and water remaining in the treatment chamber are It is preferable to form the gate insulating layer 252 while removing hydroxyl groups, hydrides, etc. In order to remove hydrogen, water, hydroxyl radicals, hydrides, etc. remaining in the processing chamber, an adsorption type It is preferable to use an air pump. Typical examples of adsorption type vacuum pumps are cryopumps, The pump is an on-pump and a titanium sublimation pump. A pump with a cold trap can be used.

[0113] The purity of the sputtering gas used in forming the gate insulating layer 252 is set to 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration By making the content of the silicon dioxide contained in the gate insulating layer 252 1 ppm or less, preferably 0.1 ppm or less, It is possible to reduce the amount of hydrogen, water, hydroxyl groups, hydrides, etc. contained in the catalyst.

[0114] Next, as shown in FIG. 11B, an oxide semiconductor layer 253A is formed over the gate insulating layer 202. The oxide semiconductor layer 253A is formed by using a printing method, an ink-jet method, or the like. Alternatively, a method such as sputtering, CVD, coating, or patterning can be used on the gate insulating layer 252. The oxide semiconductor layer is formed by laser deposition or other methods, and then shaped by photolithography. The oxide semiconductor layer is etched using the formed resist as a mask to form island-shaped oxide semiconductor layers. A layer 253A can be formed.

[0115] The carrier density of the oxide semiconductor layer is determined by the hydrogen concentration of the source gas and the target under the film formation conditions. The oxide semiconductor depends on the concentration of oxygen, the material and composition of the film, and the heat treatment conditions. or increasing the oxygen concentration in the oxide semiconductor layer to reduce oxygen vacancies. By this, the oxide semiconductor layer becomes i-type or substantially i-type. In order to perform a process to make the oxide semiconductor layer i-type or substantially i-type later, the oxide semiconductor layer 2 53A may be either i-type or n-type.

[0116] Note that in the case where the oxide semiconductor layer is formed by a sputtering method, the oxide semiconductor layer is oxidized by heating the substrate. Impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the compound semiconductor layer can be reduced. Furthermore, the first heat treatment can promote crystal growth.

[0117] In addition, when the oxide semiconductor layer is formed by a sputtering method, the metal in the metal oxide target The relative density of the metal oxide is 80% or more, preferably 95% or more, and more preferably 99.9%. By setting the above, the impurity concentration in the oxide semiconductor layer can be reduced, and the electrical characteristics and Therefore, a highly reliable transistor can be obtained.

[0118] In addition, by performing preheating treatment before forming the oxide semiconductor layer, Hydrogen, water, hydroxyl groups, and hydrides remaining on the inner wall, target surface, and target material Therefore, impurities such as hydrogen, water, a hydroxyl group, and hydride contained in the oxide semiconductor layer can be removed. It is possible to reduce the amount of

[0119] In addition, similarly to the gate insulating layer 252, the oxide semiconductor layer may be formed before, during, or after the formation of the oxide semiconductor layer. After the formation, hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the sputtering equipment are removed. It is preferable to use an adsorption type vacuum pump to remove hydrogen, water, and hydroxide. Since the hydrogen, water, hydroxyl groups, hydrogen, and the like contained in the oxide semiconductor layer are exhausted, The concentration of chlorides and other substances can be reduced.

[0120] Next, first heat treatment is performed to remove hydrogen, water, a hydroxyl group, and water contained in the oxide semiconductor layer 253A. Remove impurities such as chlorides, i.e., carry out at least one of dehydration and dehydrogenation. Note that oxygen vacancies are also formed in the oxide semiconductor layer 253A by the first heat treatment. The first heat treatment removes impurities such as hydrogen, water, hydroxyl groups, and hydrides. The oxide semiconductor layer is shown as an oxide semiconductor layer 253B in FIG.

[0121] The temperature of the first heat treatment is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. The heat treatment device used for the first heat treatment is not particularly limited. The object to be treated is heated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or a GRTA (Gas Rapid Thermal thermal annealing) equipment, LRTA (Lamp Rapid Thermal An Use an RTA (Rapid Thermal Anneal) device such as a LRTA devices can be used with halogen lamps, metal halide lamps, and xenon lamps. Lamps such as clamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps The GRTA device heats the object to be treated by radiating light (electromagnetic waves) emitted from the It is a device that performs heat treatment using high-temperature gas.

[0122] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that hydrogen, water, hydroxyl groups, hydrides, etc. are not contained. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the treatment equipment must be 6N or less. (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0123] In the first heat treatment, the inside of the furnace is in a nitrogen atmosphere during the temperature rise, and the inside of the furnace is in a nitrogen atmosphere during the cooling. The atmosphere may be switched to an oxygen atmosphere inside, and dehydration or dehydrogenation may be performed in a nitrogen atmosphere. After this, the atmosphere is changed to an oxygen atmosphere to replenish oxygen inside the oxide semiconductor layer. The hydrogen concentration can be reduced, and oxygen can be supplied to the oxygen vacancies in the oxide semiconductor layer in which oxygen vacancies are formed. It is possible to supply an element, and form an i-type or substantially i-type oxide semiconductor layer. It can be achieved.

[0124] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer The layer 253A may be crystallized to become a crystallized oxide semiconductor layer. In some cases, the oxide semiconductor layer has a crystallinity of 90% or more, or 80% or more.

[0125] Furthermore, depending on the first heating conditions or the material of the oxide semiconductor layer, an amorphous oxide semiconductor A crystalline structure is formed in the surface layer of the layer, with crystals whose c-axes are nearly parallel to the direction perpendicular to the surface. In some cases, the layer may be an oxide semiconductor layer.

[0126] Note that the first heat treatment is performed after the first terminal and the second terminal are formed over the oxide semiconductor layer. You may go.

[0127] Here, the substrate is introduced into an electric furnace and heated at 450 Heat treatment is carried out at ℃ for 1 hour.

[0128] Next, as shown in FIG. 11(C), a first terminal that functions as a source electrode and a drain electrode is formed. A first terminal 254A and a second terminal 254B are formed.

[0129] The first terminal 254A and the second terminal 254B are the same as the first terminal 204A shown in the second embodiment. and second terminal 204B can be formed in the same manner.

[0130] Next, as shown in FIG. 11(D), the gate insulating layer 252, the oxide semiconductor layer 253B, and the first An insulating layer 255 is formed on the first terminal 254A and the second terminal 254B. It can be formed by a sputtering method, a CVD method, a printing method, a coating method, etc. When a silicon oxide layer is formed as the edge layer 255 by a sputtering method, the silicon oxide The oxide semiconductor layer 253A is then heated to supply oxygen to oxygen vacancies generated by the first heat treatment. It is possible to supply oxygen as a donor, reduce oxygen vacancies, and satisfy the stoichiometric ratio. As a result, an i-type or substantially i-type oxide semiconductor can be obtained. A body layer 253 can be formed.

[0131] Next, a second heat treatment (preferably 200 The second heat treatment is performed at a temperature of 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. This heat treatment may be performed after forming a protective insulating layer or a planarizing insulating layer on the insulating layer 255. As a result, the oxide semiconductor layer generated by the first heat treatment is transferred from the oxide insulating layer of the insulating layer 255 to the oxide semiconductor layer. It is possible to supply oxygen to oxygen vacancies that exist, and to reduce the oxygen vacancies that contribute as donors. As a result, it is possible to obtain a structure that satisfies the stoichiometric ratio. The i-type oxide semiconductor layer 253 can be formed in this way.

[0132] In this embodiment mode, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.

[0133] Furthermore, heat treatment was carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. The heat treatment can increase the reliability of the field-effect transistor.

[0134] By the above steps, the i-type or substantially i-type oxide semiconductor layer is formed in the channel region. The field-effect transistor 102 has an extremely small off-state current and is an enhancement type. can be produced.

[0135] (Embodiment 5) FIG. 12 shows a semiconductor device using the power element shown in any one of the first to third embodiments as a protection element. The protection element is a protective element that protects the power supply terminal from overvoltage. It functions by passing current through the power element to prevent overcurrent from flowing into the circuit being protected. The power path includes all circuits with low withstand voltage that are destroyed by the application of an overvoltage. As an example of the element, the four-terminal power MOSFET shown in the first and second embodiments is This will be explained using:

[0136] FIG. 12 shows a power MOSFET 501, a control circuit 502, a circuit to be protected 503, and an input terminal The control circuit 502 is a semiconductor device having an input terminal 504 and an output terminal 505. 04 or the output terminal 505, and detects the overvoltage applied to the power MOS It controls the operation of the FET 501 .

[0137] FIG. 13 shows the details of the control circuit 502. The control circuit 502 is an overvoltage detection circuit. 511, inverter 512, positive power supply 513, switch transistors 514, 515, 5 16, a capacitance element 517, a negative voltage generating circuit 518, an oscillation circuit 519, a frequency dividing circuit 520, a delay The positive power supply 513 is the same as that shown in the first embodiment. The switch transistors 514, 515, and 516 correspond to the high voltage source 108. These correspond to the field effect transistors 102, 103, and 104 shown in the first embodiment. The capacitor 517 corresponds to the capacitor 105 shown in the first embodiment. 518 corresponds to the low voltage generating source 109 shown in the first embodiment. 520, the delay circuit 521, and the AND circuit 522 are the same as those in the first embodiment. This corresponds to the control circuit 107. Note that the control circuit 502 is not limited to this configuration.

[0138] Next, the operation of the control circuit 502 and the power MOSFET 501 shown in FIG. 13 will be described. The overvoltage detection circuit 511 detects whether an overvoltage that greatly exceeds the normal power supply voltage is detected at the input terminal 50. In this embodiment, when an overvoltage is input, It has the function of outputting a pulse.

[0139] The output terminal of the overvoltage detection circuit 511 is connected to the gate terminal of the switch transistor 514 and the The output terminal of the inverter 512 is connected to the input terminal of the switch transistor 513. This connects to the gate terminal of the resistor 515. When an overvoltage is input, the switch The transistor 514 is turned on, and the gate terminal of the power MOSFET 501 is connected to the positive power supply 51 3, and the power MOSFET 501 is turned on. A current flows through the output terminal 505, and an overcurrent is prevented from flowing through the protected circuit 503 shown in FIG. Stop.

[0140] When no overvoltage is applied, the output of the overvoltage detection circuit 511 is low, and the switch The switch transistor 514 is turned off and the switch transistor 515 is turned on. The circuit 518 is configured by a charge pump circuit shown in FIG. 17 or the like, and generates a negative voltage.

[0141] The protection circuit is not a circuit that operates frequently, so it is a waste of power to constantly pass a large current through it. Therefore, it is not suitable from the viewpoint of power. Therefore, the negative voltage generating circuit 518 is switched on intermittently. The power consumption is reduced by charging the capacitor element 517 through the switch transistor 516. It is possible.

[0142] The oscillation signal obtained by the oscillation circuit 519 is divided by the frequency divider circuit 520, and the divided signal is , is supplied to the gate terminal of the switch transistor 516. That is, the output of the frequency divider circuit 520 One of the terminals is connected to a first input terminal of the AND circuit 522. The other output terminal is connected to a second input terminal of an AND circuit 522 via a delay circuit 521. In this way, the pulse width is the delay time of the delay circuit 521, and the period is A pulse similar to the output of 20 can be obtained. By using this pulse, The gate terminal of the switch transistor 516 can be controlled.

[0143] The oscillator circuit 519 can be a general oscillator circuit, such as a ring oscillator. The frequency divider circuit 520 may be a flip-flop. The delay circuit 521 may be a circuit using an inverter, a circuit using a CR delay circuit, etc. However, there is no particular limitation to the method for forming the pulse. It can also be done as follows.

[0144] In this way, a negative voltage is held in the capacitance element 517, and when no overvoltage is applied, A negative voltage is applied to the power MOSFET 501 via the switch transistor 515. While a negative voltage is applied to the gate terminal of the power MOSFET 501, FET 501 is turned off and does not conduct current.

[0145] Figure 14 shows a semiconductor device in which a power MOSFET is connected in series with a circuit to be protected. Unlike 2, when an overvoltage is applied to the input terminal, the power MOSFET 601 turns on. This prevents overvoltage from being applied to the circuit 603 to be protected.

[0146] The semiconductor device shown in FIG. 14 includes a power MOSFET 601, a control circuit 602, and a circuit to be protected. 603, an input terminal 604, and an output terminal 605. The control circuit 602 is 604 or the output terminal 605, and detects the overvoltage applied to the power MO It controls the SFET 601.

[0147] 15 shows the details of the control circuit 602. The control circuit 602 includes an overvoltage detection circuit 611, an inverter a positive power supply 613; switch transistors 614, 615, and 616; a capacitance element 6 17, negative voltage generating circuit 618, oscillation circuit 619, frequency dividing circuit 620, delay circuit 621, AN The positive power supply 613 is configured by the high voltage generating source 1 shown in the first embodiment. 08. Switch transistors 614, 615, and 616 correspond to the embodiment The capacitor element 617 corresponds to the field effect transistors 103, 102, and 104 shown in FIG. The negative voltage generating circuit 618 corresponds to the capacitor 105 shown in the first embodiment. This corresponds to the low voltage generation source 109 shown in the first embodiment. The AND circuit 621 and the AND circuit 622 correspond to the refresh control circuit 107 shown in the first embodiment. However, the control circuit 602 is not limited to this configuration.

[0148] Next, the operation of the control circuit 602 and the power MOSFET 601 shown in FIG. The overvoltage detection circuit 611 detects whether an overvoltage that greatly exceeds the normal power supply voltage is detected at the input terminal 60. In this embodiment, when an overvoltage is input, It has the function of outputting a pulse.

[0149] The output terminal of the overvoltage detection circuit 611 is inverted with the gate terminal of the switch transistor 615. The output terminal of the inverter 612 is connected to a switch transistor 614. This allows the switch to operate when an overvoltage is applied to the input terminal 604. The switch transistor 615 is turned on, and the gate terminal of the power MOSFET 601 is negatively charged. This connects the input terminal 604 and the protected circuit 603 is disconnected, preventing overcurrent from flowing through the protected circuit 603. 618 is composed of a charge pump circuit shown in FIG. 17 and generates a negative voltage.

[0150] When no overvoltage is applied, the output of the overvoltage detection circuit 611 is low, and the switch The switch transistor 615 is turned off, the switch transistor 614 is turned on, and the power MOS The gate terminal of the FET 601 is connected to a capacitance element 617. The capacitance element 617 has a capacitance as described below. As a result, a positive voltage is maintained from the positive power supply, and the power MOSFET 601 is turned on.

[0151] The protection circuit is not a circuit that operates frequently, so it is a waste of power to constantly pass a large current through it. Therefore, it is not suitable from the viewpoint of power. Therefore, the positive power supply 613 is switched on intermittently. By charging the capacitor 617 via the transistor 616, power consumption can be reduced. can.

[0152] The oscillation signal obtained by the oscillation circuit 619 is divided by the frequency divider circuit 620, and the divided signal is The output terminal of the frequency divider circuit 620 is connected to the gate terminal of the switch transistor 616. One of the terminals is connected to a first input terminal of an AND circuit 622. The other output terminal is connected to the second input terminal of the AND circuit 622 via the delay circuit 621. In this way, the pulse width is the delay time of the delay circuit 621, and the period is the frequency of the frequency divider circuit 620. By using this pulse, the switch The gate terminal of transistor 616 can be controlled.

[0153] The oscillator circuit 619 can be a general oscillator circuit such as a ring oscillator. The frequency divider circuit 620 may be a flip-flop. The delay circuit 621 may be a circuit using an inverter, a circuit using a CR delay circuit, etc. However, there is no particular limitation to the method for forming the pulse. So that's fine.

[0154] In this way, a positive voltage is held across the capacitor 617, and when no overvoltage is applied, , a positive voltage is applied to the power MOSFET 601 via the switch transistor 614. While a positive voltage is applied to the gate terminal of the power MOSFET 601, The FET 601 is turned on, and the input terminal 604 is connected to the circuit 603 to be protected shown in FIG. can be.

[0155] 16 shows an example of the configuration of the overvoltage detection circuits 511 and 611. 1 to 705 are diode-connected, and a diode chain is formed by a transistor 707 and a resistor 70 6, inverter 708. When the number of stages of the diode chain is n, If the threshold voltage of the transistor is Vth, then the normal operating voltage is <nVthとなるようにn When an overvoltage is applied, the transistors 701 to 705 are turned on, and the diodes When transistor 705 is turned on, it allows current to flow through the power supply chain. 707 also turns on, and a high signal is output from the output of inverter 708.

[0156] In this embodiment, a semiconductor device using an oxide semiconductor layer with a wide band gap for a channel region is described. A semiconductor device using a power MOSFET with a MOSFET resistor as a protection element to protect against overvoltage This can prevent the destruction of the

[0157] (Embodiment 6) In this embodiment, applications of the power devices described in the above embodiments will be described. The semiconductor device, which is the power device described in the above embodiment, is used in, for example, a computer, etc. In addition to the protection circuits for the batteries of electronic devices such as displays that can display images, Battery protection circuits installed in vehicles (bicycles, etc.) powered by electric power from a device or fixed power source It can be used as.

[0158] Referring to FIG. 18, a semiconductor device that is a power device and functions as a protection circuit is provided. An example of application will be described.

[0159] FIG. 18(A) shows an example of an application of a semiconductor device that functions as a protection circuit, such as an electromagnetic cooker. The induction cooker 1000 is configured to generate heat by passing a current through a coil portion 1001. The electromagnetic induction generated by the induction cooker is used to heat the cooker. 1001, a battery 1002 for supplying current to the coil section 1001, and a protection circuit. A functioning semiconductor device 1003 and a solar cell 100 for charging a battery 1002 18(A), a thick film is used as a means for charging the battery 1002. Although a solar battery 1004 is shown, it may be charged by other means. The semiconductor device 1003 can reduce the application of overvoltage to the battery 1002, and functions as a protection circuit. However, it is possible to reduce power consumption when the device is not in operation.

[0160] FIG. 18B shows an example of an application of a semiconductor device that functions as a protection circuit, which is an electric bicycle. The electric bicycle 1010 is driven by passing a current through a motor unit 1011. The electric bicycle 1010 is powered by the electric current flowing through the motor unit 1011. A battery 1012 for supplying current and a semiconductor device 101 functioning as a protection circuit 18(B), the battery 1012 is specifically provided as a means for charging the battery 1012. Although not shown in the figure, a separate generator or the like may be provided for charging. The semiconductor device 1013 can reduce the application of an overvoltage to the battery 1012 during charging. This allows for low power consumption when the protection circuit is not in operation. B) Pedals are shown in the illustration, but they are not necessary.

[0161] FIG. 18C shows an example of an application of a semiconductor device that functions as a protection circuit. The electric vehicle 1020 is driven by passing a current through a motor unit 1021. The electric vehicle 1020 obtains power by supplying electricity to the motor unit 1021. a battery 1022 for supplying current, and a semiconductor device 102 that functions as a protection circuit. 18(C), the battery 1022 is specifically provided as a means for charging the battery 1022. Although not shown in the figure, a separate generator or the like may be provided for charging. The semiconductor device 1023 can reduce the application of an overvoltage to the battery 1022 during charging. This makes it possible to reduce power consumption when the protection circuit is not in operation.

[0162] In this embodiment, the contents described in each drawing may be the same as those described in another embodiment. However, they can be freely combined or replaced as appropriate.

Claims

1. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

2. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; the second conductive layer overlaps with the fourth conductive layer in a plan view; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

3. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; the third conductive layer does not overlap with the fourth conductive layer in a plan view; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

4. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; the second conductive layer overlaps with the fourth conductive layer in a plan view; the third conductive layer does not overlap with the fourth conductive layer in a plan view; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

5. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; the second conductive layer overlaps with the fourth conductive layer in a plan view; an insulating surface is in contact with an entire lower surface of a region of the oxide semiconductor layer that overlaps with the second conductive layer in a plan view; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

6. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; the third conductive layer does not overlap with the fourth conductive layer in a plan view; an insulating surface is in contact with an entire lower surface of a region of the oxide semiconductor layer that overlaps with the second conductive layer in a plan view; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

7. an oxide semiconductor layer including a channel formation region of a transistor and first to fourth conductive layers; the first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer; the second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer; the third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer; the fourth conductive layer functions as a gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening; the second conductive layer overlaps with the fourth conductive layer in a plan view; the third conductive layer does not overlap with the fourth conductive layer in a plan view; an insulating surface is in contact with an entire lower surface of a region of the oxide semiconductor layer that overlaps with the second conductive layer in a plan view; a region of the second conductive layer that is in contact with the oxide semiconductor layer includes a region that overlaps with the opening of the fourth conductive layer in a plan view; Semiconductor device.

8. In any one of claims 1 to 7, The oxide semiconductor layer contains In, Ga, and Zn.

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