Power amplifier circuit

Abstract

To achieve both improvement of efficiency and suppression of damage.SOLUTION: A power amplifier circuit includes a first amplifier that includes a field effect transistor as an amplifier element, amplifies a first high-frequency signal, and outputs a second high-frequency signal, a second amplifier that includes a bipolar transistor as an amplifier element, amplifies a second high-frequency signal, and outputs a third high-frequency signal, a control unit that outputs a control signal that controls a first power source voltage supplied to the first amplifier, and a regulator that outputs the first power source voltage, which is the voltage according to the control signal, to the first amplifier. A second power source voltage supplied to the second amplifier is an envelope tracking voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power amplifier circuit. [Background technology]

[0002] Patent Document 1 listed below describes a high frequency power amplifier circuit that uses a silicon MOSFET power amplifier element in the front stage and a GaAsFET power amplifier element in the rear stage.

[0003] There is a power amplifier circuit in which a plurality of amplifiers each formed on a semiconductor substrate made of a different material are combined.

[0004] An amplifier including a field effect transistor (FET) formed on a silicon (e.g., SOI (Silicon On Insulator)) substrate may be referred to as a FET amplifier. Examples of silicon substrates include an SOI-CMOS structure, a Bulk-CMOS structure, and an SOS-CMOS structure, but the present disclosure is not limited thereto.

[0005] Furthermore, an amplifier including a bipolar transistor formed on a gallium arsenide (GaAs) substrate may be called a bipolar amplifier. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 5-152978 Summary of the Invention [Problem to be solved by the invention]

[0007] While FETs have excellent high-frequency characteristics, they have the characteristic of low inter-terminal breakdown voltage (drain-source breakdown voltage, gate-source breakdown voltage).

[0008] For example, the drain-source breakdown voltage of an FET is often lower than the collector-emitter breakdown voltage of a bipolar transistor, and the gate-source breakdown voltage of an FET is often lower than the base-emitter breakdown voltage.

[0009] For this reason, FET amplifiers generally use a fixed power supply voltage or APT (Average Power Tracking), which makes it easy to control the voltage across the FET to be equal to or lower than the breakdown voltage across the terminals.

[0010] One technique for suppressing amplifier loss and improving power efficiency is envelope tracking, which varies the power supply voltage of an amplifier in accordance with the envelope of a high-frequency signal.

[0011] Even in a power amplifier circuit that combines multiple amplifiers each formed on a semiconductor substrate made of different materials, it is desirable to apply envelope tracking technology to both FET amplifiers and bipolar amplifiers from the viewpoint of power efficiency. However, applying envelope tracking technology to FET amplifiers presents some difficulties, as follows:

[0012] When amplifiers are used in cellular communication devices (e.g., smartphones, tablets, etc.), the power supply voltage varies over a wide range. Furthermore, with envelope tracking technology, the bandwidth over which the power supply voltage varies can be 100 MHz (megahertz) or more. Therefore, if the bias voltage (gate voltage) of an FET cannot be changed to track the power supply voltage over a bandwidth of 100 MHz or more, the voltage across its terminals may exceed its breakdown voltage, potentially resulting in damage.

[0013] The present disclosure has been made in view of the above, and aims to achieve both improved efficiency and damage suppression in a power amplifier circuit. [Means for solving the problem]

[0014] A power amplifier circuit according to one aspect of the present disclosure includes a first amplifier including a field-effect transistor as an amplifying element and amplifying a first high-frequency signal to output a second high-frequency signal, a second amplifier including a bipolar transistor as an amplifying element and amplifying the second high-frequency signal to output a third high-frequency signal, a control unit that outputs a control signal to control a first power supply voltage supplied to the first amplifier, and a regulator that outputs a first power supply voltage that is a voltage corresponding to the control signal to the first amplifier. The second power supply voltage supplied to the second amplifier is an envelope tracking voltage. [Effects of the Invention]

[0015] According to the present disclosure, it is possible to achieve both improved efficiency and damage suppression in a power amplifier circuit. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a power amplifier circuit according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of a table stored in the storage unit. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of a variable resistor. [Figure 4] FIG. 4 is a diagram showing the results of a circuit simulation of the power amplifier circuit of the comparative example. [Figure 5] FIG. 5 is a diagram showing the results of a circuit simulation of the power amplifier circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing the results of a circuit simulation of the power amplifier circuit according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing the results of a circuit simulation of the power amplifier circuit according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing the results of a circuit simulation of the power amplifier circuit according to the first embodiment. [Figure 9] FIG. 9 is a diagram illustrating a configuration of a power amplifier circuit according to the second embodiment. [Figure 10]FIG. 10 is a diagram illustrating an example of the detection characteristics of the power detector. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a power amplifier circuit according to the third embodiment. [Figure 12] FIG. 12 is a diagram illustrating a configuration of a power amplifier circuit according to the fourth embodiment. [Figure 13] FIG. 13 is a diagram illustrating a configuration of a power amplifier circuit according to the fifth embodiment. [Figure 14] FIG. 14 is a diagram illustrating a configuration of a power amplifier circuit according to the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present invention is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0018] First Embodiment (composition) FIG. 1 is a diagram illustrating a configuration of a power amplifier circuit according to a first embodiment.

[0019] The power amplifier circuit 1 amplifies a high-frequency signal RFin and outputs a high-frequency signal RFout. The power amplifier circuit 1 is exemplified as being mounted in a cellular communication device (e.g., a smartphone, a tablet, etc.), but the present disclosure is not limited thereto.

[0020] Based on signal S1 output from the control unit of the cellular communication device, processing unit 101 refers to table 103 stored in storage unit 102 and outputs signal S2 to power amplifier circuit 1. Based on signal S2, power amplifier circuit 1 controls a first power supply voltage Vcc1 (described below) of a first amplifier PA1 (described below).

[0021] The control unit of the cellular communication device outputs a signal S1 based on the power of the cellular communication device (e.g., the power mode, output power Pout, etc. of the cellular communication device). In other words, the signal S1 is a signal that represents power. Examples of the power mode of the cellular communication device include a high power mode (HPM) and a low power mode (LPM), but the present disclosure is not limited thereto.

[0022] The high power mode is exemplified as an amplification operation of the cellular communication device at a relatively high first output power, and the low power mode is exemplified as an amplification operation of the cellular communication device at a relatively low second output power, but the present disclosure is not limited thereto.

[0023] Examples of the storage unit 102 include a read only memory (ROM), a random access memory (RAM), and a flash memory (registered trademark), but the present disclosure is not limited to these.

[0024] FIG. 2 is a diagram illustrating an example of a table stored in the storage unit.

[0025] Table 103 associates information about signal S1 with information about signal S2. The information about signal S1 may include, for example, information about the power mode (e.g., HPM, LPM) of the cellular communication device and information about the output power Pout [dBm], but the present disclosure is not limited thereto. The information about signal S2 may include, for example, information about the first power supply voltage Vcc1, but the present disclosure is not limited thereto.

[0026] For example, in high power mode, P 11 >P 12 >···>P 1m In the case of V 11 ≧V 12 ≧ ≧ V 1mThat is, in the high power mode, the first power supply voltage Vcc1 increases as the output power Pout increases, and the first power supply voltage Vcc1 decreases as the output power Pout decreases, but the present disclosure is not limited to this.

[0027] Also, for example, in low power mode, P 21 >P 22 >···>P 2n In the case of V 21 ≧V 22 ≧ ≧ V 2n That is, in the low power mode, the first power supply voltage Vcc1 increases as the output power Pout increases, and the first power supply voltage Vcc1 decreases as the output power Pout decreases, but the present disclosure is not limited to this.

[0028] The processing unit 101 refers to the table 103 based on the signal S1, determines the signal S2, and outputs it to the power amplifier circuit 1.

[0029] 1, the power amplifier circuit 1 includes a first semiconductor substrate 2 and a second semiconductor substrate 3. The first semiconductor substrate 2 is a silicon (e.g., SOI (Silicon On Insulator)) substrate. The second semiconductor substrate 3 is a gallium arsenide (GaAs) substrate.

[0030] A control unit 11, a regulator 12, and a first amplifier PA1 are formed on the first semiconductor substrate 2. The first amplifier PA1 includes a field effect transistor (FET). The first amplifier PA1 may be configured by stacking a plurality of FETs (with their drain-source paths connected in series).

[0031] A second amplifier PA2 is formed on the second semiconductor substrate 3. The second amplifier PA2 includes a bipolar transistor.

[0032] The input terminal of the second amplifier PA2 is electrically connected to the output terminal of the first amplifier PA1.

[0033] Each transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor is the minimum configuration that constitutes a transistor.

[0034] Based on a signal S2 output from the processing unit 101, the control unit 11 outputs a signal S3 to a switch 41 (described later) in a variable resistor 23 in the regulator 12, thereby controlling the resistance value of the variable resistor 23. In this way, the control unit 11 controls the first power supply voltage Vcc1. Although an example is shown in which the control unit 11 communicates with the processing unit 101 using MIPI (Mobile Industry Processor Interface), the present disclosure is not limited to this.

[0035] Regulator 12 outputs a first power supply voltage Vcc1, which is a voltage based on a signal S3 input from control unit 11, to first amplifier PA1. Regulator 12 can vary the first power supply voltage Vcc1 based on signal S3. For example, based on signal S3, regulator 12 can output a constant first power supply voltage Vcc1 of 2 V, a constant first power supply voltage Vcc1 of 3 V, a constant first power supply voltage Vcc1 of 4 V, or a constant first power supply voltage Vcc1 of 5 V.

[0036] The first power supply voltage Vcc1 may be a constant voltage that provides a constant output in response to a signal.

[0037] The regulator 12 includes an operational amplifier 21, a resistor 22, a variable resistor 23, and a boost circuit 24.

[0038] The operational amplifier 21 operates using a power supply voltage Vbat. A reference voltage Vref is input to a non-inverting input terminal (+ terminal) of the operational amplifier 21. An inverting input terminal (- terminal) of the operational amplifier 21 is electrically connected to a node N1.

[0039] One end of the resistor 22 is electrically connected to the output terminal of the operational amplifier 21. The other end of the resistor 22 is electrically connected to the node N1.

[0040] In other words, the operational amplifier 21 is subjected to negative feedback.

[0041] One end of the variable resistor 23 is electrically connected to the node N1. The other end of the variable resistor 23 is electrically connected to a reference potential. The reference potential is exemplified by the ground potential, but the present disclosure is not limited thereto.

[0042] FIG. 3 is a diagram illustrating an example of the configuration of a variable resistor.

[0043] The variable resistor 23 includes circuits 31, 32, ..., 3n, which are connected in parallel.

[0044] Each of the circuits 31, 32, . . . , 3n includes a switch 41 and a resistor 42 connected in series.

[0045] The control unit 11 turns on and off the switches 41 in the circuits 31, 32, ..., 3n, changing the number of resistors 42 connected in parallel, and thus varying the resistance value of the variable resistor 23. The fewer the number of resistors 42 connected in parallel, the larger the resistance value of the variable resistor 23, and the more the number of resistors 42 connected in parallel, the smaller the resistance value.

[0046] 1 again, the voltage at node N1 is the voltage obtained by dividing the first power supply voltage Vcc1 between resistor 22 and variable resistor 23. The voltage at node N1 decreases as the resistance value of variable resistor 23 decreases, and increases as the resistance value of variable resistor 23 increases.

[0047] The operational amplifier 21 outputs a first power supply voltage Vcc1 that corresponds to the resistance value of the variable resistor 23. More specifically, when the resistance value of the variable resistor 23 decreases (the voltage at node N1 decreases), the operational amplifier 21 increases the first power supply voltage Vcc1. On the other hand, when the resistance value of the variable resistor 23 increases (the voltage at node N1 increases), the operational amplifier 21 decreases the first power supply voltage Vcc1.

[0048] The control unit 11 controls the resistance value of the variable resistor 23 so that the resistance value decreases as the power increases, and the regulator 12 increases the first power supply voltage Vcc1 as the power increases.

[0049] The control unit 11 controls the resistance value of the variable resistor 23 so that the smaller the power is, the larger the resistance value, and the regulator 12 controls the first power supply voltage Vcc1 so that the smaller the power is, the lower the resistance value.

[0050] The boost circuit 24 is electrically connected to the output terminal of the operational amplifier 21. The boost circuit 24 does not operate if the first power supply voltage Vcc1 output by the operational amplifier 21 is sufficient. The boost circuit 24 boosts the first power supply voltage Vcc1 when a voltage higher than the first power supply voltage Vcc1 output by the operational amplifier 21 is required. The boost circuit 24 can be omitted if the first power supply voltage Vcc1 output by the operational amplifier 21 is sufficient.

[0051] The first amplifier PA1 operates using a first power supply voltage Vcc1. The first amplifier PA1 amplifies the high frequency signal RFin and outputs the high frequency signal RF1 to the second amplifier PA2.

[0052] The second amplifier PA2 operates using a second power supply voltage Vcc2. The second power supply voltage Vcc2 is an envelope tracking voltage that changes according to, for example, the envelopes of the radio frequency signals RFin and RFout using an envelope tracking technique. The second amplifier PA2 amplifies the radio frequency signal RF1 and outputs the radio frequency signal RFout.

[0053] (Circuit simulation results for comparison example) Fig. 4 is a diagram showing the results of a circuit simulation of a power amplifier circuit of a comparative example. Fig. 4 is a diagram showing the results of a circuit simulation of the power amplifier circuit 1 when the envelope tracking technique is applied to both the first power supply voltage Vcc1 and the second power supply voltage Vcc2. In Fig. 4, the horizontal axis represents the output power Pout [dBm], and the vertical axis represents the efficiency [%].

[0054] In FIG. 4, line 201 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 1 V. Line 202 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 2 V. Line 203 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 3 V. Line 204 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 4 V. Line 205 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 5 V.

[0055] (Circuit simulation results for the first embodiment) 5 to 8 are diagrams showing the results of circuit simulation of the power amplifier circuit of the first embodiment. In Fig. 5 to Fig. 8, the horizontal axis represents output power Pout [dBm], and the vertical axis represents efficiency [%].

[0056] FIG. 5 is a diagram showing the results of a circuit simulation of the power amplifier circuit 1 when the first power supply voltage Vcc1 is 2V.

[0057] 5, line 211 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 1 V. Line 212 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 2 V. Line 213 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 3 V. Line 214 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 4 V. Line 215 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 5 V.

[0058] FIG. 6 is a diagram showing the results of a circuit simulation of the power amplifier circuit 1 when the first power supply voltage Vcc1 is 3V.

[0059] 6, line 221 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 1V. Line 222 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 2V. Line 223 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 3V. Line 224 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 4V. Line 225 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 5V.

[0060] FIG. 7 is a diagram showing the results of a circuit simulation of the power amplifier circuit 1 when the first power supply voltage Vcc1 is 4V.

[0061] 7, line 231 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 1 V. Line 232 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 2 V. Line 233 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 3 V. Line 234 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 4 V. Line 235 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 5 V.

[0062] FIG. 8 is a diagram showing the results of a circuit simulation of the power amplifier circuit 1 when the first power supply voltage Vcc1 is 5V.

[0063] In FIG. 8, line 241 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 1 V. Line 242 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 2 V. Line 243 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 3 V. Line 244 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 4 V. Line 245 shows the relationship between the output power Pout and efficiency of the power amplifier circuit 1 when the second power supply voltage Vcc2 is 5 V.

[0064] (effect) For example, let us look at the maximum point 211a of the line 211 (where the second power supply voltage Vcc2 is 1V) in Figure 5 (where the first power supply voltage Vcc1 is 2V) and the maximum point 221a of the line 221 (where the second power supply voltage Vcc2 is 1V) in Figure 6 (where the first power supply voltage Vcc1 is 3V).

[0065] The output power Pout at the maximum point 211a is approximately 21.5 dBm, and the efficiency at the maximum point 211a is approximately 38%. The output power Pout at the maximum point 221a is approximately 21.5 dBm, and the efficiency at the maximum point 221a is approximately 33%.

[0066] Thus, when the second power supply voltage Vcc2 is low (in this example, the second power supply voltage Vcc2 is 1V), i.e., when the power is low, it is more efficient to have the first power supply voltage Vcc1 low (in this example, the first power supply voltage Vcc1 is 1V).

[0067] Also, for example, let us focus on the maximum point 212a of the line 212 (the second power supply voltage Vcc2 is 2V) in Figure 5 (the first power supply voltage Vcc1 is 2V) and the maximum point 222a of the line 222 (the second power supply voltage Vcc2 is 2V) in Figure 6 (the first power supply voltage Vcc1 is 3V).

[0068] The output power Pout at the maximum point 212a is approximately 28 dBm, and the efficiency at the maximum point 212a is approximately 51%. The output power Pout at the maximum point 222a is approximately 28 dBm, and the efficiency at the maximum point 222a is approximately 48%.

[0069] Thus, when the second power supply voltage Vcc2 is low (in this example, the second power supply voltage Vcc2 is 2V), i.e., when the power is low, it is more efficient to have the first power supply voltage Vcc1 low (in this example, the first power supply voltage Vcc1 is 2V).

[0070] Therefore, as described above, processing unit 101 outputs signal S2 to control unit 11 based on signal S1 representing power. Control unit 11 controls variable resistor 23 based on signal S2. Regulator 12 outputs first power supply voltage Vcc1 to first amplifier PA1 according to the resistance value of variable resistor 23. Regulator 12 increases first power supply voltage Vcc1 as the power increases, and decreases first power supply voltage Vcc1 as the power decreases.

[0071] This allows the power amplifier circuit 1 to improve its efficiency.

[0072] Furthermore, the first power supply voltage Vcc1 does not employ envelope tracking technology. Therefore, even if the bias voltage (gate voltage) of the FET of the first amplifier PA1 cannot be changed quickly, the terminal voltage is prevented from exceeding the terminal breakdown voltage. This allows the power amplifier circuit 1 to prevent damage to the first amplifier PA1.

[0073] In this way, the power amplifier circuit 1 can achieve both improved efficiency and reduced damage to the first amplifier PA1.

[0074] <Second embodiment> (composition) FIG. 9 is a diagram illustrating a configuration of a power amplifier circuit according to the second embodiment.

[0075] Compared with the power amplifier circuit 1 (see FIG. 1), the power amplifier circuit 1A further includes a power detector 4. In the second embodiment, the processing unit 101 and the storage unit 102 (see FIG. 1) are not necessary.

[0076] The power detector 4 detects the output power Pout of the second amplifier PA2, and outputs a voltage Vdet corresponding to the output power Pout to the control unit 11. The control unit 11 controls the variable resistor 23 based on the voltage Vdet.

[0077] Fig. 10 is a diagram showing an example of the detection characteristics of a power detector, in which the horizontal axis represents output power Pout [dBm] and the vertical axis represents voltage Vdet [V].

[0078] The larger the output power Pout, the higher the voltage Vdet the power detector 4 sets. In the example of Fig. 10, the voltage Vdet is directly proportional to the output power Pout, but the present disclosure is not limited to this.

[0079] The control unit 11 controls the resistance value of the variable resistor 23 to be smaller as the output power Pout increases, that is, as the voltage Vdet increases, and the regulator 12 increases the first power supply voltage Vcc1 as the output power Pout increases.

[0080] The control unit 11 controls the resistance value of the variable resistor 23 to be larger as the output power Pout is smaller, that is, as the voltage Vdet is lower, and the regulator 12 controls the first power supply voltage Vcc1 to be lower as the output power Pout is smaller.

[0081] 10, in a region 252 where the voltage Vdet is below point 251a, the regulator 12 outputs a constant first power supply voltage Vcc1 of 2 V to the first amplifier PA1. In a region 253 where the voltage Vdet is equal to or greater than point 251a and less than point 251b, the regulator 12 outputs a constant first power supply voltage Vcc1 of 3 V to the first amplifier PA1. In a region 254 where the voltage Vdet is equal to or greater than point 251b and less than point 251c, the regulator 12 outputs a constant first power supply voltage Vcc1 of 4 V to the first amplifier PA1. In a region 255 where the voltage Vdet is equal to or greater than point 251c, the regulator 12 outputs a constant first power supply voltage Vcc1 of 5 V to the first amplifier PA1.

[0082] (effect) The power detector 4 detects the output power Pout and outputs a voltage Vdet corresponding to the output power Pout to the control unit 11. The control unit 11 controls the variable resistor 23 based on the voltage Vdet. The regulator 12 outputs a first power supply voltage Vcc1 to the first amplifier PA1 according to the resistance value of the variable resistor 23. The regulator 12 increases the first power supply voltage Vcc1 as the output power Pout increases, and decreases the first power supply voltage Vcc1 as the output power Pout decreases.

[0083] As a result, the power amplifier circuit 1A can improve the efficiency, similar to the power amplifier circuit 1.

[0084] Furthermore, the first power supply voltage Vcc1 does not employ envelope tracking technology. Therefore, even if the bias voltage (gate voltage) of the FET of the first amplifier PA1 cannot be changed quickly, the terminal voltage is prevented from exceeding the terminal breakdown voltage. This allows the power amplifier circuit 1A to prevent damage to the first amplifier PA1.

[0085] In this way, the power amplifier circuit 1A can achieve both improved efficiency and reduced damage to the first amplifier PA1.

[0086] <Third embodiment> (composition) FIG. 11 is a diagram illustrating a configuration of a power amplifier circuit according to the third embodiment.

[0087] Compared to the power amplifier circuit 1 (see FIG. 1), the power amplifier circuit 1B further includes an impedance adjustment circuit 5. One end of the impedance adjustment circuit 5 is electrically connected to the output terminal of the first amplifier PA1. The other end of the impedance adjustment circuit 5 is electrically connected to the input terminal of the second amplifier PA2.

[0088] The impedance adjustment circuit 5 may also serve as an inter-stage matching circuit between the first amplifier PA1 and the second amplifier PA2.

[0089] The impedance value of the impedance adjustment circuit 5 changes depending on the first power supply voltage Vcc1. For example, the impedance value of the impedance adjustment circuit 5 decreases as the first power supply voltage Vcc1 increases, and increases as the first power supply voltage Vcc1 decreases.

[0090] (effect) The first power supply voltage Vcc1 at which the efficiency of the power amplifier circuit 1B is at its peak varies depending on the load impedance of the first amplifier PA1. In other words, when the first power supply voltage Vcc1 varies, the load impedance of the first amplifier PA1 at which the efficiency is at its peak also varies.

[0091] Therefore, the impedance value of the impedance adjustment circuit 5 changes depending on the first power supply voltage Vcc1. For example, the impedance value of the impedance adjustment circuit 5 decreases as the first power supply voltage Vcc1 increases, and increases as the first power supply voltage Vcc1 decreases.

[0092] As a result, the power amplifier circuit 1B can further improve the efficiency compared to the power amplifier circuit 1.

[0093] <Fourth embodiment> (composition) FIG. 12 is a diagram illustrating a configuration of a power amplifier circuit according to the fourth embodiment.

[0094] Compared to the power amplifier circuit 1B (see FIG. 11), the power amplifier circuit 1C has an impedance adjustment circuit 5 electrically connected to the output terminal of the second amplifier PA2.

[0095] (effect) The first power supply voltage Vcc1 at which the efficiency of the power amplifier circuit 1C is at its peak varies depending on the load impedance of the second amplifier PA2. In other words, when the first power supply voltage Vcc1 varies, the load impedance of the second amplifier PA2 at which the efficiency is at its peak also varies.

[0096] Therefore, the impedance value of the impedance adjustment circuit 5 changes depending on the first power supply voltage Vcc1. For example, the impedance value of the impedance adjustment circuit 5 decreases as the first power supply voltage Vcc1 increases, and increases as the first power supply voltage Vcc1 decreases.

[0097] This allows the power amplifier circuit 1C to further improve its efficiency, similar to the power amplifier circuit 1B.

[0098] <Fifth embodiment> (composition) FIG. 13 is a diagram illustrating a configuration of a power amplifier circuit according to the fifth embodiment.

[0099] Compared to the power amplifier circuit 1A (see FIG. 9), the power amplifier circuit 1D further includes an impedance adjustment circuit 5. One end of the impedance adjustment circuit 5 is electrically connected to the output terminal of the first amplifier PA1. The other end of the impedance adjustment circuit 5 is electrically connected to the input terminal of the second amplifier PA2.

[0100] Although not shown, the impedance adjustment circuit 5 may be electrically connected to the control unit 11.

[0101] (effect) The first power supply voltage Vcc1 at which the efficiency of the power amplifier circuit 1B is at its peak varies depending on the load impedance of the first amplifier PA1. In other words, when the first power supply voltage Vcc1 varies, the load impedance of the first amplifier PA1 at which the efficiency is at its peak also varies.

[0102] Therefore, the impedance value of the impedance adjustment circuit 5 changes depending on the first power supply voltage Vcc1. For example, the impedance value of the impedance adjustment circuit 5 decreases as the first power supply voltage Vcc1 increases, and increases as the first power supply voltage Vcc1 decreases.

[0103] This allows the power amplifier circuit 1B to have a further improved efficiency compared to the power amplifier circuit 1A.

[0104] Sixth Embodiment (composition) FIG. 14 is a diagram illustrating a configuration of a power amplifier circuit according to the sixth embodiment.

[0105] Compared to the power amplifier circuit 1D (see FIG. 13), the power amplifier circuit 1E has an impedance adjustment circuit 5 electrically connected to the output terminal of the second amplifier PA2.

[0106] Although not shown, the impedance adjustment circuit 5 may be electrically connected to the control unit 11.

[0107] (effect) The first power supply voltage Vcc1 at which the efficiency of the power amplifier circuit 1E is at its peak varies depending on the load impedance of the second amplifier PA2. In other words, when the first power supply voltage Vcc1 varies, the load impedance of the second amplifier PA2 at which the efficiency is at its peak also varies.

[0108] The impedance value of the impedance adjustment circuit 5 changes depending on the first power supply voltage Vcc1. For example, the impedance value of the impedance adjustment circuit 5 decreases as the first power supply voltage Vcc1 increases, and increases as the first power supply voltage Vcc1 decreases.

[0109] This allows the power amplifier circuit 1E to further improve its efficiency, similar to the power amplifier circuit 1D.

[0110] (Addendum) Although the impedance adjustment circuit 5 is electrically connected between the second amplifier PA2 and the power detector 4, the present disclosure is not limited to this. The impedance adjustment circuit 5 may also be electrically connected to a stage subsequent to the power detector 4.

[0111] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configurations.

[0112] (1) a first amplifier including a field effect transistor as an amplifying element, amplifying the first high frequency signal and outputting a second high frequency signal; a second amplifier including a bipolar transistor as an amplifying element, amplifying the second high frequency signal and outputting a third high frequency signal; a control unit that outputs a control signal that controls a first power supply voltage supplied to the first amplifier; a regulator that outputs the first power supply voltage, which is a voltage according to the control signal, to the first amplifier; Including, the second power supply voltage supplied to the second amplifier is an envelope tracking voltage; Power amplifier circuit.

[0113] (2) The power amplifier circuit according to (1) above, The control unit controls the first power supply voltage according to power. Power amplifier circuit.

[0114] (3) The power amplifier circuit according to (1) above, a power detector for detecting the output power of the second amplifier; Further comprising: the control unit controls the first power supply voltage in accordance with the output power. Power amplifier circuit.

[0115] (4) The power amplifier circuit according to any one of (1) to (3) above, The regulator an operational amplifier having a reference voltage input to a non-inverting input terminal and outputting the first power supply voltage from an output terminal; a resistor having one end electrically connected to the output terminal of the operational amplifier and the other end electrically connected to the inverting input terminal of the operational amplifier; a variable resistor having one end electrically connected to the inverting input terminal of the operational amplifier and the other end electrically connected to a reference potential, the resistance value of which varies in response to the control signal; Including, Power amplifier circuit.

[0116] (5) The power amplifier circuit according to any one of (1) to (4) above, an impedance adjustment circuit that adjusts the load impedance of the first amplifier or the second amplifier in accordance with the first power supply voltage; Further comprising: Power amplifier circuit.

[0117] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit and scope of the present invention, and equivalents thereof are also included in the present invention. [Explanation of symbols]

[0118] 1, 1A, 1B, 1C, 1D, 1E Power amplifier circuit 2. First semiconductor substrate 3 Second semiconductor substrate 4 Power Detector 5 Impedance adjustment circuit 11 Control section 12 Regulator 21 Operational Amplifiers 22 Resistance 23 Variable Resistor 24 Boost circuit 101 Processing section 102 Storage section 103 Table PA1 First amplifier PA2 Second amplifier

Claims

1. a first amplifier including a field effect transistor as an amplifying element, amplifying the first high frequency signal and outputting a second high frequency signal; a second amplifier including a bipolar transistor as an amplifying element, amplifying the second high frequency signal and outputting a third high frequency signal; a control unit that outputs a control signal that controls a first power supply voltage supplied to the first amplifier; a regulator that outputs the first power supply voltage, which is a voltage according to the control signal, to the first amplifier; Including, the second power supply voltage supplied to the second amplifier is an envelope tracking voltage; Power amplifier circuit.

2. 2. The power amplifier circuit according to claim 1, the control unit controls the first power supply voltage in accordance with power. Power amplifier circuit.

3. 2. The power amplifier circuit according to claim 1, a power detector for detecting the output power of the second amplifier; Further comprising: the control unit controls the first power supply voltage in accordance with the output power. Power amplifier circuit.

4. 2. The power amplifier circuit according to claim 1, The regulator an operational amplifier having a reference voltage input to a non-inverting input terminal and outputting the first power supply voltage from an output terminal; a resistor having one end electrically connected to the output terminal of the operational amplifier and the other end electrically connected to the inverting input terminal of the operational amplifier; a variable resistor having one end electrically connected to the inverting input terminal of the operational amplifier and the other end electrically connected to a reference potential, the resistance value of which varies in response to the control signal; Including, Power amplifier circuit.

5. 2. The power amplifier circuit according to claim 1, an impedance adjustment circuit that adjusts the load impedance of the first amplifier or the second amplifier in accordance with the first power supply voltage; Further comprising: Power amplifier circuit.

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