Semiconductor device, method for manufacturing semiconductor device, and substrate

Abstract

To provide a semiconductor device which can achieve both high temperature reliability of a solder junction, and adhesion between a lead frame and a sealing resin.SOLUTION: A semiconductor device includes a lead frame, a first solder layer, a semiconductor element, and a sealing resin layer. The first solder layer is provided on the lead frame. The semiconductor element is provided on the first solder layer. The sealing resin layer is provided on the semiconductor element and the lead frame. The lead frame has a first base part, a first barrier metal layer, and a first adhesive layer. The first barrier metal layer is provided on the first base part. The first barrier metal layer has a first solder region and a first sealing region. The first barrier metal layer contains metal having diffusion speed to a solder lower than that of copper. The first adhesive layer is provided on the first sealing region. The first adhesive layer contains copper. The first solder layer is provided on the first solder region . The sealing resin layer is provided on the semiconductor element and the first adhesive layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, and a substrate. [Background technology]

[0002] Semiconductor devices are known in which a semiconductor element is bonded to a lead frame via a solder layer and the semiconductor element is encapsulated in an encapsulating resin. To ensure high-temperature operation, such semiconductor devices must satisfy both high-temperature reliability of the solder joints and good adhesion between the lead frame and the encapsulating resin. For example, in-vehicle semiconductor devices, both high-temperature reliability of the solder joints and good adhesion between the lead frame and the encapsulating resin must be satisfied at temperatures as high as 175°C. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-92064 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device, a method for manufacturing a semiconductor device, and a substrate that can achieve both high-temperature reliability of the solder joints and adhesion between the lead frame and the sealing resin. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a lead frame, a first solder layer, a semiconductor element, and an encapsulating resin layer. The first solder layer is provided on the lead frame. The semiconductor element is provided on the first solder layer. The encapsulating resin layer is provided on the semiconductor element and on the lead frame. The lead frame has a first base, a first barrier metal layer, and a first adhesion layer. The first barrier metal layer is provided on the first base. The first barrier metal layer has a first solder region and a first encapsulating region. The first barrier metal layer contains a metal that diffuses into the solder at a lower rate than copper. The first adhesion layer is provided on the first encapsulating region. The first adhesion layer contains copper. The first solder layer is provided on the first solder region. The encapsulating resin layer is provided on the semiconductor element and on the first adhesion layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 3] FIG. 10 is a plan view illustrating a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 5] FIG. 10 is a plan view illustrating a semiconductor device according to a third embodiment. [Figure 6] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a plan view illustrating a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 10 is a plan view illustrating a semiconductor device according to a fifth embodiment. [Figure 10] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment. [Figure 11] FIG. 2 is a plan view illustrating a substrate according to an embodiment. [Figure 12] FIG. 2 is a cross-sectional view illustrating a substrate according to an embodiment. [Figure 13] 13(a) to 13(c) are cross-sectional views illustrating a part of the substrate according to the embodiment. [Figure 14] 14(a) to 14(d) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. [Figure 15] 10 is a graph showing an example of a reflow profile in the method for manufacturing a semiconductor device according to the embodiment. [Figure 16] 1A to 1C are plan views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 17] 1 is a table showing the results of Examples and Comparative Examples. [Figure 18] 18(a) and 18(b) are explanatory diagrams showing a method for measuring the adhesion strength of the example and the comparative example. [Figure 19] 1 is a table showing the results of Examples and Comparative Examples. [Figure 20] 1 is a table showing the results of Examples and Comparative Examples. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] <Semiconductor device> (First embodiment) FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. As shown in FIGS. 1 and 2, the semiconductor device 100 according to the first embodiment includes a lead frame 10, a first solder layer 20, a semiconductor element 30, and a sealing resin layer 40.

[0009] In the following description, the direction from the lead frame 10 toward the semiconductor element 30 is referred to as "upper", and the direction from the semiconductor element 30 toward the lead frame 10 is referred to as "lower".

[0010] The lead frame 10 is located below the semiconductor device 100. A first solder layer 20 is provided on the lead frame 10. A semiconductor element 30 is provided on the first solder layer 20. A sealing resin layer 40 is provided on the semiconductor element 30 and the lead frame 10.

[0011] The lead frame 10 has a first base 11, a first barrier metal layer 12, and a first adhesion layer 13. The first base 11 is located at the bottom of the lead frame 10. The first barrier metal layer 12 is provided on the first base 11. The first barrier metal layer 12 is provided on at least the surface of the first base 11 on which the semiconductor element 30 is mounted. The first adhesion layer 13 is provided on the first barrier metal layer 12. The first adhesion layer 13 is provided on at least the first barrier metal layer 12 provided on the surface of the first base 11 on which the semiconductor element 30 is mounted.

[0012] The first base portion 11 is, for example, in the form of a flat plate. The first base portion 11 includes a metal. The first base portion 11 includes, for example, copper (Cu).

[0013] The first barrier metal layer 12 is, for example, flat and plate-like (film-like). The first barrier metal layer 12 covers a portion of the first base 11, preferably the entire surface that contacts the plate-like first base 11. The first barrier metal layer 12 covers, for example, the entire surface of the first base 11 in plan view. The first barrier metal layer 12 contains a metal that has a lower diffusion rate into the solder than copper. The diffusion rate is the movement speed when the solder is in a liquid or solid phase. The first barrier metal layer 12 contains, for example, one or more elements selected from the group consisting of nickel (Ni), chromium (Cr), and titanium (Ti). The first barrier metal layer 12 preferably contains, for example, nickel. The first barrier metal layer 12 functions, for example, as a barrier metal layer that prevents the first solder layer 20 from contacting the first base 11.

[0014] The first barrier metal layer 12 has a first solder region 12a and a first sealing region 12b. The first solder region 12a overlaps with the first solder layer 20 and the semiconductor element 30 in the vertical direction. The first sealing region 12b does not overlap with the first solder layer 20 and the semiconductor element 30 in the vertical direction. The first sealing region 12b is, for example, the region of the first barrier metal layer 12 excluding the first solder region 12a. For example, the first sealing region 12b surrounds at least a portion, and more preferably the entirety, of the first solder region 12a in a plan view.

[0015] The thickness T1 of the first barrier metal layer 12 is, for example, not less than 0.05 μm and not more than 5 μm. The thickness of the first solder region 12a is, for example, the same as the thickness of the first sealing region 12b, or in some cases, thinner than the thickness of the first sealing region 12b. The thickness T1 of the first barrier metal layer 12 is, for example, the same as the thickness of the first solder region 12a and the thickness of the first sealing region 12b. Alternatively, the thickness T1 of the first barrier metal layer 12 may be, for example, equal to the thickness of the first sealing region 12b and thicker than the thickness of the first solder region 12a.

[0016] The first adhesion layer 13 is provided on the first sealing region 12b. For example, in a plan view, the first adhesion layer 13 covers the entire surface of the first sealing region 12b. The first adhesion layer 13 is located above the first barrier metal layer 12 in the vertical direction and covers a portion of the first barrier metal layer 12 that does not overlap with the first solder layer 20 and the semiconductor element 30, more preferably the entire surface. The first adhesion layer 13 covers a portion of the first barrier metal layer 12 that does not overlap with the semiconductor element 30, more preferably the entire surface. The first adhesion layer 13 is located on a portion of the first solder layer 20, more specifically, on the side of the first solder layer 20 facing the first barrier metal layer 12. For example, in a plan view, the first adhesion layer 13 surrounds a portion of the first solder layer 20, more preferably the entire periphery. The first adhesion layer 13 is, for example, in a plate-like (film-like) shape with through holes that penetrate in the vertical direction. The first adhesion layer 13 is plate-shaped (film-shaped) with a through-hole penetrating in the direction from the first base portion 11 toward the semiconductor element 30. The first solder layer 20 is located inside the through-hole. The first adhesion layer 13 contains, for example, a metal material that diffuses into the first solder layer 20 at a higher rate than the first barrier metal layer 12. The first adhesion layer 13 contains, for example, copper.

[0017] The thickness T2 of the first adhesion layer 13 is, for example, 0.05 μm or more and 2 μm or less. The thickness T2 of the first adhesion layer 13 is preferably 1.5 μm or less, and more preferably 1.0 μm or less. The thickness T2 of the first adhesion layer 13 is, for example, thinner than the thickness of the first solder layer 20. The thickness T2 of the first adhesion layer 13 is, for example, thinner than the thickness T1 of the first barrier metal layer 12.

[0018] The first adhesion layer 13 has an upper surface 13x and a lower surface 13y. The upper surface 13x is in contact with the sealing resin layer 40. The lower surface 13y is in contact with the first barrier metal layer 12. The upper surface 13x is preferably roughened. The roughening will be described later.

[0019] The first solder layer 20 is provided on the first solder region 12a of the first barrier metal layer 12. The first solder layer 20 is provided in the form of a material such as solder paste, solder sheet, or solder wire, and is formed by soldering through a heat treatment. The first solder layer 20 contains solder. The first solder layer 20 may be formed in advance on the back surface of the semiconductor element 30 and then mounted and bonded to a heated lead frame 10. The first solder layer 20 on the back surface of the semiconductor element 30 is formed, for example, on the semiconductor element 30 in a wafer state before being singulated. The first solder layer 20 contains, for example, lead-free solder. The first solder layer 20 contains, for example, one or more elements selected from the group consisting of tin, silver, copper, antimony, nickel, and bismuth. The first solder layer 20 may also contain, for example, lead-containing solder. Even when the first solder layer 20 contains lead-containing solder, the same effects as when the first solder layer 20 contains lead-free solder can be obtained.

[0020] The semiconductor element 30 is provided on the first solder layer 20. The first solder layer 20 is provided between the first barrier metal layer 12 and the semiconductor element 30. The semiconductor element 30 is provided on the first solder region 12a of the first barrier metal layer 12 via the first solder layer 20. The semiconductor element 30 is, for example, a power semiconductor element that controls and converts power. The semiconductor element 30 includes, for example, at least one of a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0021] The encapsulating resin layer 40 is provided on the semiconductor element 30 and on the first adhesive layer 13. The encapsulating resin layer 40 is provided at least on the surface of the lead frame 10 on which the semiconductor element 30 is mounted. The encapsulating resin layer 40 covers at least a portion of, or the entire surface of, the semiconductor element 30 and the lead frame 10. That is, the encapsulating resin layer 40 is provided on a portion of the surface of the lead frame 10 to which the semiconductor element 30 is solder-bonded, via the first adhesive layer 13. More specifically, the encapsulating resin layer 40 is provided on a portion of the periphery of the solder joint of the lead frame 10, via the first adhesive layer 13. More preferably, the encapsulating resin layer 40 is provided on the surface of the lead frame 10 to which the semiconductor element 30 is solder-bonded, via the first adhesive layer 13. Portions of the encapsulating resin layer 40 are located on the sides of the semiconductor element 30 and the first solder layer 20. The encapsulating resin layer 40 is in contact with the upper surface 13x of the first adhesive layer 13. The sealing resin layer 40 includes, for example, a thermosetting resin, and for example, one or more materials selected from the group consisting of an epoxy resin and a silicone gel.

[0022] The average void fraction of the first solder layer 20 is preferably less than 2.5%, and more preferably 1.3% or less.

[0023] Although not shown in Fig. 2, a connecting member is provided on the semiconductor element 30 to connect the surface electrodes of the semiconductor element 30 to the lead frame 10. The connecting member may be, for example, a bonding wire or a connector. The connector may be, for example, a copper plate.

[0024] A portion of the first solder layer 20 does not have to overlap with the semiconductor element 30 in the vertical direction. In other words, in a plan view, a portion of the first solder layer 20 may protrude from the semiconductor element 30. For example, the first solder layer 20 may bleed and protrude from the semiconductor element 30.

[0025] The lead frame 10 may further have another layer in addition to the first barrier metal layer 12 and the first adhesive layer 13. The other layer may be provided between the first base and the first barrier metal layer 12, or between the first barrier metal layer 12 and the first adhesive layer 13. The other layer may be one layer or two or more layers.

[0026] The effects of the semiconductor device according to the embodiment will be described below.

[0027] Semiconductor devices are known in which a semiconductor element is bonded to a lead frame via a solder layer and the semiconductor element is encapsulated in an encapsulating resin. Such semiconductor devices are required to achieve both high-temperature reliability of the solder joint and good adhesion between the lead frame and the encapsulating resin.

[0028] In particular, when the solder layer contains lead-free solder, problems with high-temperature reliability, such as the generation of voids between the solder layer and the lead frame or peeling of the solder layer from the lead frame, may occur when the solder layer is left at high temperatures for a long period of time. One possible method for improving the high-temperature reliability of the solder joint is to provide a metal layer containing a metal such as nickel on the lead frame and then bond the semiconductor element to the metal layer via the solder layer. However, providing such a metal layer may result in poor adhesion between the lead frame and the encapsulating resin. In particular, semiconductor devices whose solder layer contains lead-free solder are required to achieve both high-temperature reliability of the solder joint and good adhesion between the lead frame and the encapsulating resin.

[0029] In the semiconductor device 100 according to the embodiment, a first barrier metal layer 12 is provided on a first base portion 11, and a first adhesive layer 13 is provided on the first barrier metal layer 12. A first solder layer 20 is provided in contact with the first barrier metal layer 12, and a sealing resin layer 40 is provided in contact with the first adhesive layer 13 on the lead frame 10. By providing the first solder layer 20 in contact with the first barrier metal layer 12, the high-temperature reliability of the solder joint can be improved. Furthermore, by providing the first barrier metal layer 12 between the first base portion 11 and the first solder layer 20, diffusion of metal from the first base portion 11 to the first solder layer 20 can be suppressed. Furthermore, for example, by forming the first adhesive layer 13 not only on the first solder region 12a of the first barrier metal layer 12 that overlaps with the first solder layer 20 but also on the first sealing region 12b that does not overlap with the first solder layer 20, the first adhesive layer 13 can be left on the first sealing region 12b after the formation of the first solder layer 20. Then, by providing the sealing resin layer 40 so that it is in contact with the first adhesive layer 13, the adhesion between the lead frame 10 and the sealing resin layer 40 can be improved. Therefore, it is possible to achieve both high-temperature reliability of the solder joint and adhesion between the lead frame 10 and the sealing resin layer 40.

[0030] Furthermore, by setting the thickness T1 of the first barrier metal layer 12 to 0.05 μm or more, it is possible to more reliably prevent the first solder layer 20 from coming into contact with the first base portion 11, and to more reliably allow the first barrier metal layer 12 to function as a barrier metal layer. By setting the thickness T1 of the first barrier metal layer 12 to 5 μm or less, the stress during the formation of the first barrier metal layer 12 does not become too large, thereby preventing a decrease in adhesion between the first barrier metal layer 12 and the first base portion 11 and warping of the semiconductor device 100. Furthermore, the first barrier metal layer 12 can be formed more easily.

[0031] By including one or more elements selected from the group consisting of nickel, chromium, and titanium in the first barrier metal layer 12, the diffusion rate of the first barrier metal layer 12 into the first solder layer 20 can be more reliably made lower than the diffusion rate of the first adhesion layer 13 into the first solder layer 20. This makes it possible to prevent the first barrier metal layer 12 from dissolving into the first solder layer 20 and disappearing during the solder bonding process.

[0032] By setting the thickness T2 of the first adhesion layer 13 to 0.05 μm or more, it is possible to more reliably prevent the sealing resin layer 40 from contacting the first barrier metal layer 12, and more reliably improve the adhesion between the lead frame 10 and the sealing resin layer 40. By setting the thickness T2 of the first adhesion layer 13 to 2 μm or less, even when the first adhesion layer 13 dissolves in the first solder layer 20 during the solder bonding process, it is possible to suppress the effects of deterioration in characteristics such as the wettability of the molten solder, and maintain solder bondability. In addition, the first adhesion layer 13 can be formed more easily.

[0033] Roughening the upper surface 13x of the first adhesion layer 13 can improve the adhesion between the upper surface 13x of the first adhesion layer 13 and the sealing resin layer 40. This can further improve the adhesion between the lead frame 10 and the sealing resin layer 40.

[0034] (Second embodiment) FIG. 3 is a plan view illustrating a semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view illustrating a semiconductor device according to the second embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. As shown in FIGS. 3 and 4, the semiconductor device 100A according to the second embodiment is the same as the semiconductor device 100 according to the first embodiment, except that the shape of the first solder layer 20 is different.

[0035] In the semiconductor device 100A, a portion of the first solder layer 20 protrudes from the semiconductor element 30 in a plan view. In this way, the first solder layer 20 may protrude from at least one side of the semiconductor element 30 in a plan view. In the examples of FIGS. 3 and 4, the first solder layer 20 protrudes from all four sides of the semiconductor element 30 in a plan view. In the examples of FIGS. 3 and 4, the area of the first solder layer 20 is larger than the area of the semiconductor element 30 in a plan view.

[0036] For example, when manufacturing a semiconductor device, the first solder layer 20 is provided over a wider area (for example, the entire surface) of the underside of the semiconductor element 30 in order to more reliably bond the semiconductor element 30 to the lead frame 10. In such a case, a part of the first solder layer 20 may protrude from the semiconductor element 30, as shown in FIGS.

[0037] In the semiconductor device 100A, by providing the first solder layer 20 so that it is in contact with the first barrier metal layer 12, the high-temperature reliability of the solder joint can be improved. Furthermore, by providing the first barrier metal layer 12 between the first base portion 11 and the first solder layer 20, it is possible to suppress the diffusion of metal from the first base portion 11 to the solder layer 20. Furthermore, by providing the sealing resin layer 40 so that it is in contact with the first adhesion layer 13, it is possible to improve the adhesion between the lead frame 10 and the sealing resin layer 40. Therefore, it is possible to achieve both high-temperature reliability of the solder joint and adhesion between the lead frame 10 and the sealing resin layer 40.

[0038] (Third embodiment) FIG. 5 is a plan view illustrating a semiconductor device according to the third embodiment. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to the third embodiment. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. As shown in FIGS. 5 and 6, the semiconductor device 100B according to the third embodiment is the same as the semiconductor device 100 according to the first embodiment, except that the shape of the first solder layer 20 is different.

[0039] In the semiconductor device 100B, the first solder layer 20 is hourglass-shaped in cross section. In the semiconductor device 100B, the side surfaces of the first solder layer 20 are constricted. In the examples of FIGS. 5 and 6, the side surfaces of the first solder layer 20 are curved so as to convex inward. In the semiconductor device 100B, in plan view, the area of the first solder layer 20 at the upper end and the area of the solder layer 20 at the lower end are larger than the area of the first solder layer 20 at a position between the upper end and the lower end.

[0040] For example, when manufacturing a semiconductor device, if a first solder layer 20 is formed on a joining surface and then joined, the volume of the first solder layer 20 may decrease as the first solder layer 20 solidifies, causing the shape of the first solder layer 20 to become hourglass-shaped.

[0041] In the semiconductor device 100B, the first solder layer 20 is provided in contact with the first barrier metal layer 12, thereby improving the high-temperature reliability of the solder joint. Furthermore, providing the first barrier metal layer 12 between the first base portion 11 and the first solder layer 20 suppresses metal diffusion from the first base portion 11 to the first solder layer 20. Furthermore, providing the sealing resin layer 40 in contact with the first adhesion layer 13 improves the adhesion between the lead frame 10 and the sealing resin layer 40. Therefore, both the high-temperature reliability of the solder joint and the adhesion between the lead frame 10 and the sealing resin layer 40 can be achieved. Furthermore, in the semiconductor device 100B, the first solder layer 20 is hourglass-shaped, which allows the sealing resin layer 40 to easily penetrate into the inside of the first solder layer 20. Therefore, mechanical peeling of the sealing resin layer 40 is unlikely to occur.

[0042] (Fourth embodiment) FIG. 7 is a plan view illustrating a semiconductor device according to the fourth embodiment. FIG. 8 is a cross-sectional view illustrating a semiconductor device according to the fourth embodiment. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. As shown in FIGS. 7 and 8, the semiconductor device 100C according to the fourth embodiment is the same as the semiconductor device 100 according to the first embodiment, except that the lead frame 10 further includes an intermediate metal layer 18.

[0043] In the semiconductor device 100C, the lead frame 10 further includes an intermediate metal layer 18. The intermediate metal layer 18 includes, for example, a first intermediate region 18a and a second intermediate region 18b. The first intermediate region 18a is located between the first barrier metal layer 12 and the first solder layer 20. More specifically, the first intermediate region 18a is located between the first solder region 12a of the first barrier metal layer 12 and the first solder layer 20. The second intermediate region 18b is located between the first barrier metal layer 12 and the first adhesive layer 13. More specifically, the second intermediate region 18b is located between the first sealing region 12b of the first barrier metal layer 12 and the first adhesive layer 13.

[0044] The intermediate metal layer 18 is, for example, in the form of a flat plate (film). The intermediate metal layer 18 includes, for example, one or more selected from the group consisting of silver (Ag), titanium (Ti), and palladium (Pd).

[0045] The thickness T9a of the first intermediate region 18a is, for example, 1.0 μm or less. The thickness T9b of the second intermediate region 18b is, for example, 0.1 μm or more and 1.0 μm or less. The thickness T9a of the first intermediate region 18a is, for example, the same as the thickness T9b of the second intermediate region 18b. The thickness T9a of the first intermediate region 18a may be, for example, thinner than the thickness T9b of the second intermediate region 18b. The thickness T9a of the first intermediate region 18a and the thickness T9b of the second intermediate region 18b are, for example, approximately the same as the thickness T2 of the first adhesive layer 13 or thinner than the thickness T2 of the first adhesive layer 13.

[0046] The first intermediate region 18a may be provided over the entire surface between the first barrier metal layer 12 and the first solder layer 20, or may be provided only in a portion of the surface between the first barrier metal layer 12 and the first solder layer 20. The second intermediate region 18b may be provided over the entire surface between the first barrier metal layer 12 and the first adhesion layer 13, or may be provided only in a portion of the surface between the first barrier metal layer 12 and the first adhesion layer 13. For example, some or all of the intermediate metal layer 18 provided on the substrate (substrate 200 described below) before the semiconductor element 30 is bonded may disappear due to heating during bonding.

[0047] In the semiconductor device 100C, the first solder layer 20 is provided in contact with the first barrier metal layer 12, thereby improving the high-temperature reliability of the solder joint. Furthermore, providing the first barrier metal layer 12 between the first base portion 11 and the first solder layer 20 suppresses metal diffusion from the first base portion 11 to the first solder layer 20. Furthermore, providing the encapsulating resin layer 40 in contact with the first adhesion layer 13 improves the adhesion between the lead frame 10 and the encapsulating resin layer 40. Therefore, both the high-temperature reliability of the solder joint and the adhesion between the lead frame 10 and the encapsulating resin layer 40 can be achieved. Furthermore, in the semiconductor device 100C, providing the intermediate metal layer 18 on the first barrier metal layer 12 suppresses oxidation of the first barrier metal layer 12, thereby enabling the first barrier metal layer 12 to function more easily as a barrier metal layer. Furthermore, providing the intermediate metal layer 18 on the first barrier metal layer 12 improves the wettability of the solder.

[0048] (Fifth embodiment) FIG. 9 is a plan view illustrating a semiconductor device according to the fifth embodiment. FIG. 10 is a cross-sectional view illustrating a semiconductor device according to the fifth embodiment. FIG. 10 is a cross-sectional view taken along the line XX shown in FIG. As shown in FIGS. 9 and 10, the semiconductor device 100D according to the fifth embodiment is the same as the semiconductor device 100 according to the first embodiment, except that a connector 60 having a metal layer is provided.

[0049] The second solder layer 50 is provided on the semiconductor element 30. The connector 60 is provided on the second solder layer 50. In other words, the connector 60 is provided on the semiconductor element 30 with the second solder layer 50 interposed therebetween.

[0050] The connector 60 has a second base 61, a second barrier metal layer 62, and a second adhesion layer 63. The second base 61 is located at the top of the connector 60. The second barrier metal layer 62 is provided below the second base 61. The second barrier metal layer 62 is provided on at least the surface of the second base 61 that faces the semiconductor element 30. The second adhesion layer 63 is provided below the second barrier metal layer 62. The second adhesion layer 63 is provided at least below the second barrier metal layer 62 that is provided on the surface of the second base 61 that faces the semiconductor element 30.

[0051] The second base portion 61 is, for example, in the form of a flat plate. The second base portion 61 includes a metal. The second base portion 61 includes, for example, copper (Cu).

[0052] The second barrier metal layer 62 is, for example, in the form of a flat plate (film). The second barrier metal layer 62 covers a portion of the second base 61, preferably the entire surface that contacts the plate-shaped second base 61. The second barrier metal layer 62 contains a metal that has a lower diffusion rate into solder than copper. The second barrier metal layer 62 contains, for example, one or more elements selected from the group consisting of nickel (Ni), chromium (Cr), and titanium (Ti). The second barrier metal layer 62 preferably contains, for example, nickel. The second barrier metal layer 62 functions, for example, as a barrier metal layer that prevents the second solder layer 50 from contacting the second base 61.

[0053] The second barrier metal layer 62 has a second solder region 62a and a second sealing region 62b. The second solder region 62a overlaps with the second solder layer 50 and the semiconductor element 30 in the vertical direction. The second sealing region 62b does not overlap with the second solder layer 50 and the semiconductor element 30 in the vertical direction. The second sealing region 62b is, for example, the region of the second barrier metal layer 62 excluding the second solder region 62a. The second sealing region 62b surrounds at least a portion, and more preferably the entirety, of the second solder region 62a in a plan view, for example.

[0054] The thickness T3 of the second barrier metal layer 62 is, for example, not less than 0.05 μm and not more than 5 μm. The thickness of the second solder region 62a is, for example, the same as the thickness of the second sealing region 62b, or in some cases, thinner than the thickness of the second sealing region 62b. The thickness T3 of the second barrier metal layer 62 is, for example, the same as the thickness of the second solder region 62a and the thickness of the second sealing region 62b. Alternatively, the thickness T3 of the second barrier metal layer 62 may be, for example, equal to the thickness of the second sealing region 62b and thicker than the thickness of the second solder region 62a.

[0055] The second adhesion layer 63 is located below the second barrier metal layer 62 in the vertical direction and covers a portion, more preferably the entire surface, of the second barrier metal layer 62 that does not overlap with the second solder layer 50 and the semiconductor element 30. The second adhesion layer 63 covers a portion, more preferably the entire surface, of the second barrier metal layer 62 that does not overlap with the semiconductor element 30. The second adhesion layer 63 is located on a portion of the second solder layer 50, more specifically, on a lateral side of the second solder layer 50 on the second barrier metal layer 62 side. For example, in a plan view, the second adhesion layer 63 surrounds a portion, more preferably the entire periphery, of the second solder layer 50. The second adhesion layer 63 is, for example, plate-shaped (film-shaped) with a through-hole penetrating in the vertical direction. The second adhesion layer 63 is plate-shaped (film-shaped) with a through-hole penetrating in the direction from the second base 61 toward the semiconductor element 30. The second solder layer 50 is located inside the through-hole. The second adhesion layer 63 includes, for example, a metal material that diffuses into the second solder layer 50 at a higher rate than the second barrier metal layer 62. The second adhesion layer 63 includes, for example, copper.

[0056] The thickness T4 of the second adhesion layer 63 is, for example, not less than 0.05 μm and not more than 2 μm. The thickness T4 of the second adhesion layer 63 is preferably not more than 1.5 μm, and more preferably not more than 1.0 μm. The thickness T4 of the second adhesion layer 63 is, for example, thinner than the thickness of the first solder layer 20. The thickness T4 of the second adhesion layer 63 is, for example, thinner than the thickness T3 of the second barrier metal layer 62.

[0057] The second adhesion layer 63 has an upper surface 63x and a lower surface 63y. The lower surface 63y is in contact with the sealing resin layer 40. The upper surface 63x is in contact with the second barrier metal layer 62. The lower surface 63y is preferably roughened. The roughening will be described later.

[0058] 9 and 10 , the second barrier metal layer 62 and the second adhesion layer 63 are provided only under the second base portion 61. The second barrier metal layer 62 and the second adhesion layer 63 may also be provided on the second base portion 61. That is, the second barrier metal layer 62 and the second adhesion layer 63 may be provided on both sides of the second base portion 61. On the second base portion 61, the second adhesion layer 63 is provided on the second barrier metal layer 62. By providing the second barrier metal layer 62 and the second adhesion layer 63 on both sides of the second base portion 61, it is possible to improve adhesion with the sealing resin layer 40, facilitate manufacturing, and reduce costs, compared to, for example, a case in which the second barrier metal layer 62 is provided on both sides and the second adhesion layer 63 is provided on one side.

[0059] The second solder layer 50 is provided below the second solder region 62a of the second barrier metal layer 62. The second solder layer 50 is provided between the second barrier metal layer 62 and the semiconductor element 30. The semiconductor element 30 is provided below the second solder region 12a of the second barrier metal layer 62 via the second solder layer 50. The second solder layer 50 is supplied in the form of a material such as a solder paste, a solder sheet, or a solder wire, and is formed by soldering through a heat treatment. The second solder layer 50 includes solder. The second solder layer 50 includes, for example, lead-free solder. The second solder layer 50 includes, for example, one or more elements selected from the group consisting of tin, silver, copper, antimony, nickel, and bismuth. The second solder layer 50 may also include, for example, lead-containing solder. Even when the second solder layer 50 contains lead-containing solder, the same effects as when the second solder layer 50 contains lead-free solder can be obtained.

[0060] The semiconductor device 100D further includes a third solder layer 70 and a connection frame 80. The third solder layer 70 is provided between the connection frame 80 and the connector 60.

[0061] In the semiconductor device 100D, the connector 60 is provided on the third solder layer 70. That is, the connector 60 is provided on the connection frame 80 with the third solder layer 70 interposed therebetween.

[0062] The connector 60 further has a third barrier metal layer 64 and a third adhesion layer 65. The third barrier metal layer 64 is provided below the second base 61. The third barrier metal layer 64 is provided on at least the surface of the second base 61 facing the third solder layer 70. The third adhesion layer 65 is provided below the third barrier metal layer 64. The third adhesion layer 65 is provided at least below the third barrier metal layer 64 provided on the surface of the second base 61 facing the third solder layer 70.

[0063] The third barrier metal layer 64 is, for example, in the form of a flat plate (film). The third barrier metal layer 64 covers a portion of the second base 61, preferably the entire surface that contacts the plate-shaped second base 61. The third barrier metal layer 64 contains a metal that has a lower diffusion rate into solder than copper. The third barrier metal layer 64 contains, for example, one or more elements selected from the group consisting of nickel (Ni), chromium (Cr), and titanium (Ti). The third barrier metal layer 64 preferably contains, for example, nickel. The third barrier metal layer 64 functions, for example, as a barrier metal layer that prevents the third solder layer 70 from contacting the second base 61.

[0064] The third barrier metal layer 64 has a third solder region 64a and a third sealing region 64b. The third solder region 64a overlaps with the third solder layer 70 in the vertical direction. The third sealing region 64b does not overlap with the third solder layer 70 in the vertical direction. The third sealing region 64b is, for example, the region of the third barrier metal layer 64 excluding the third solder region 64a. The third sealing region 64b surrounds at least a portion, and more preferably the entirety, of the third solder region 64a in a plan view, for example.

[0065] The thickness T5 of the third barrier metal layer 64 is, for example, not less than 0.05 μm and not more than 5 μm. The thickness of the third solder region 64a is, for example, the same as the thickness of the third sealing region 64b, or in some cases thinner than the thickness of the third sealing region 64b. The thickness T5 of the third barrier metal layer 64 is, for example, the same as the thickness of the third solder region 64a and the thickness of the third sealing region 64b. Alternatively, the thickness T5 of the third barrier metal layer 64 may be, for example, equal to the thickness of the third sealing region 64b and thicker than the thickness of the third solder region 64a.

[0066] The third adhesion layer 65 is located below the third barrier metal layer 64 in the vertical direction and covers a portion of the third barrier metal layer 64 that does not overlap with the third solder layer 70, more preferably the entire surface. The third adhesion layer 65 covers a portion of the third barrier metal layer 64 that does not overlap with the third solder layer 70, more preferably the entire surface. The third adhesion layer 65 is located on a portion of the third solder layer 70, more specifically, on the lateral side of the third solder layer 70 on the third barrier metal layer 64 side. For example, in a plan view, the third adhesion layer 65 surrounds a portion of, more preferably the entire, periphery of the third solder layer 70. The third adhesion layer 65 is, for example, plate-shaped (film-shaped) with a through-hole penetrating in the vertical direction. The third adhesion layer 65 is plate-shaped (film-shaped) with a through-hole penetrating in the direction from the second base portion 61 toward the third solder layer 70. The third solder layer 70 is located inside the through-hole. The third adhesion layer 65 includes, for example, a metal material that diffuses into the third solder layer 70 at a higher rate than the third barrier metal layer 64. The third adhesion layer 65 includes, for example, copper.

[0067] The thickness T6 of the third adhesion layer 65 is, for example, not less than 0.05 μm and not more than 2 μm. The thickness T6 of the third adhesion layer 65 is preferably not more than 1.5 μm, and more preferably not more than 1.0 μm. The thickness T6 of the third adhesion layer 65 is, for example, thinner than the thickness of the third solder layer 70. The thickness T6 of the third adhesion layer 65 is, for example, thinner than the thickness T5 of the third barrier metal layer 64.

[0068] The third adhesion layer 65 has an upper surface 65x and a lower surface 65y. The lower surface 65y is in contact with the sealing resin layer 40. The upper surface 65x is in contact with the third barrier metal layer 64. The lower surface 65y is preferably roughened. The roughening will be described later.

[0069] 9 and 10 , the third barrier metal layer 64 and the third adhesion layer 65 are provided only under the second base portion 61. The third barrier metal layer 64 and the third adhesion layer 65 may also be provided on the second base portion 61. That is, the third barrier metal layer 64 and the second adhesion layer 65 may be provided on both surfaces of the second base portion 61. On the second base portion 61, the third adhesion layer 65 is provided on the third barrier metal layer 64. By providing the third barrier metal layer 64 and the third adhesion layer 65 on both surfaces of the second base portion 61, it is possible to improve adhesion with the sealing resin layer 40, facilitate manufacturing, and reduce costs, compared to, for example, a case in which the third barrier metal layer 64 is provided on both surfaces and the third adhesion layer 65 is provided on one surface.

[0070] The third solder layer 70 is provided below the third solder region 64a of the third barrier metal layer 64. The third solder layer 70 is supplied in the form of a material such as a solder paste, a solder sheet, or a solder wire, and is formed by soldering through a heat treatment. The third solder layer 70 includes solder. The third solder layer 70 includes, for example, lead-free solder. The third solder layer 70 includes, for example, one or more elements selected from the group consisting of tin, silver, copper, antimony, nickel, and bismuth. The third solder layer 70 may also include, for example, lead-containing solder. Even when the third solder layer 70 includes lead-containing solder, the same effects as when the third solder layer 70 includes lead-free solder can be obtained.

[0071] 9 and 10, the third barrier metal layer 64 is provided continuously with the second barrier metal layer 62. The third barrier metal layer 64 does not have to be provided continuously with the second barrier metal layer 62. In the example of FIG. 10, the third adhesion layer 65 is provided continuously with the second adhesion layer 63. The third adhesion layer 65 does not have to be provided continuously with the second adhesion layer 63.

[0072] The connection frame 80 further has a third base 81, a fourth barrier metal layer 82, and a fourth adhesion layer 83. The fourth barrier metal layer 82 is provided on the third base 81. The fourth barrier metal layer 82 is provided on at least the surface of the third base 81 that faces the third solder layer 70. The fourth adhesion layer 83 is provided on the fourth barrier metal layer 82. The fourth adhesion layer 83 is provided on at least the fourth barrier metal layer 82 that is provided on the surface of the third base 81 that faces the third solder layer 70.

[0073] The fourth barrier metal layer 82 is, for example, in the form of a flat plate (film). The fourth barrier metal layer 82 covers a portion of the third base portion 81, preferably the entire surface that contacts the plate-shaped third base portion 81. The fourth barrier metal layer 82 contains a metal that has a lower diffusion rate into solder than copper. The fourth barrier metal layer 82 contains, for example, one or more elements selected from the group consisting of nickel (Ni), chromium (Cr), and titanium (Ti). The fourth barrier metal layer 82 preferably contains, for example, nickel. The fourth barrier metal layer 82 functions, for example, as a barrier metal layer that prevents the third solder layer 70 from contacting the third base portion 81.

[0074] The fourth barrier metal layer 82 has a fourth solder region 82a and a fourth sealing region 82b. The fourth solder region 82a overlaps with the third solder layer 70 in the vertical direction. The fourth sealing region 82b does not overlap with the third solder layer 70 in the vertical direction. The fourth sealing region 82b is, for example, the region of the fourth barrier metal layer 82 excluding the fourth solder region 82a. For example, the fourth sealing region 82b surrounds at least a portion, and more preferably the entirety, of the fourth solder region 82a in a plan view.

[0075] The thickness T7 of the fourth barrier metal layer 82 is, for example, not less than 0.05 μm and not more than 5 μm. The thickness of the fourth solder region 82a is, for example, the same as the thickness of the fourth sealing region 82b, or in some cases thinner than the thickness of the fourth sealing region 82b. The thickness T7 of the fourth barrier metal layer 82 is, for example, the same as the thickness of the fourth solder region 82a and the thickness of the fourth sealing region 82b. Alternatively, the thickness T7 of the fourth barrier metal layer 82 may be, for example, equal to the thickness of the fourth sealing region 82b and thicker than the thickness of the fourth solder region 82a.

[0076] The fourth adhesion layer 83 is located above the fourth barrier metal layer 82 in the vertical direction and covers a portion of the fourth barrier metal layer 82 that does not overlap with the third solder layer 70, more preferably the entire surface. The fourth adhesion layer 83 covers a portion of the fourth barrier metal layer 82 that does not overlap with the third solder layer 70, more preferably the entire surface. The fourth adhesion layer 83 is located on a portion of the third solder layer 70, more specifically, on the lateral side of the third solder layer 70 on the fourth barrier metal layer 82 side. For example, in a plan view, the fourth adhesion layer 83 surrounds a portion of, more preferably the entire, periphery of the third solder layer 70. The fourth adhesion layer 83 is, for example, plate-shaped (film-shaped) with a through hole penetrating in the vertical direction. The fourth adhesion layer 83 is plate-shaped (film-shaped) with a through hole penetrating in the direction from the third base 81 toward the third solder layer 70. The third solder layer 70 is located inside the through hole. The fourth adhesion layer 83 includes, for example, a metal material that diffuses into the third solder layer 70 at a higher rate than the fourth barrier metal layer 82. The fourth adhesion layer 83 includes, for example, copper.

[0077] The thickness T8 of the fourth adhesion layer 83 is, for example, not less than 0.05 μm and not more than 2 μm. The thickness T8 of the fourth adhesion layer 83 is preferably not more than 1.5 μm, and more preferably not more than 1.0 μm. The thickness T8 of the fourth adhesion layer 83 is, for example, thinner than the thickness of the third solder layer 70. The thickness T8 of the fourth adhesion layer 83 is, for example, thinner than the thickness T7 of the fourth barrier metal layer 82.

[0078] The fourth adhesion layer 83 has an upper surface 83x and a lower surface 83y. The upper surface 83x is in contact with the sealing resin layer 40. The lower surface 83y is in contact with the fourth barrier metal layer 82. The upper surface 83x is preferably roughened. The roughening will be described later.

[0079] 9 and 10 illustrate the case where the connection frame 80 is connected to the connector 60 via the third solder layer 70, but the third solder layer 70 and the connection frame 80 may be omitted. In this case, the connector 60 does not need to have the third barrier metal layer 64 and the third adhesion layer 65.

[0080] The first to fifth embodiments may be combined as appropriate.

[0081] <Substrate> FIG. 11 is a plan view illustrating a substrate according to an embodiment. FIG. 12 is a cross-sectional view illustrating a substrate according to an embodiment. FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG. 11 and 12, a substrate 200 according to the embodiment includes a first base portion 11, a first barrier metal layer 12, and a first adhesion layer 13. The substrate 200 is used in manufacturing the semiconductor device 100 described above.

[0082] The first base portion 11 and the first barrier metal layer 12 are similar to the lead frame 10 and the first barrier metal layer 12 of the above-described semiconductor device 100, and therefore a description thereof will be omitted. The first barrier metal layer 12 is provided on at least one surface of the first base portion 11. The first barrier metal layer 12 is provided at least on the surface of the first base portion 11 on which the semiconductor element 30 is mounted.

[0083] In the substrate 200, the first adhesion layer 13 is provided on the first barrier metal layer 12. The first adhesion layer 13 is provided at least on the first barrier metal layer 12 provided on the surface of the first base 11 on which the semiconductor element 30 is mounted. The first adhesion layer 13 covers at least a portion of the first barrier metal layer 12. The first adhesion layer 13 preferably covers the entire surface of the first barrier metal layer 12. In the substrate 200, the first adhesion layer 13 is provided not only on the first sealing region 12b of the first barrier metal layer 12 but also on the first solder region 12a. In the substrate 200, the first adhesion layer 13 is provided on the entire surface of the first barrier metal layer 12. Otherwise, the first adhesion layer 13 of the substrate 200 is similar to the first adhesion layer 13 of the semiconductor device 100 described above, and therefore a description thereof will be omitted.

[0084] 13(a) to 13(c) are cross-sectional views illustrating a part of the substrate according to the embodiment. 13(a) to 13(c) are enlarged views of the region R1 shown in FIG. As shown in FIGS. 13(a) to 13(c), the upper surface 13x of the first adhesion layer 13 is, for example, roughened.

[0085] 13(a) shows the upper surface 13x of the first adhesion layer 13 roughened by roughening plating. As shown in FIG. 13(a), the upper surface 13x of the first adhesion layer 13 roughened by roughening plating has large irregularities with a depth of, for example, 1 μm or more and 2 μm or less. The average surface roughness of the upper surface 13x of the first adhesion layer 13 roughened by roughening plating is, for example, 1.8 μm.

[0086] 13(b) shows the upper surface 13x of the first adhesion layer 13 roughened by the etching process. As shown in FIG. 13(b), the upper surface 13x of the first adhesion layer 13 roughened by the etching process has small irregularities with a depth of, for example, less than 1 μm. The average surface roughness of the upper surface 13x of the first adhesion layer 13 roughened by the etching process is, for example, 0.6 μm.

[0087] 13(c) shows the upper surface 13x of the first adhesion layer 13 roughened by the blackening treatment. As shown in FIG. 13(c), the upper surface 13x of the first adhesion layer 13 roughened by the blackening treatment has needle-like irregularities. The average surface roughness of the upper surface 13x of the first adhesion layer 13 roughened by the blackening treatment is, for example, 1.5 μm.

[0088] <Method of manufacturing a semiconductor device> 14(a) to 14(d) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the embodiment. FIG. 15 is a graph showing an example of a reflow profile in the method for manufacturing a semiconductor device according to the embodiment. As shown in FIGS. 14(a) to 14(d), the method for manufacturing a semiconductor device according to the embodiment includes a first step, a second step, a third step, and a fourth step.

[0089] In the first step, a substrate 200 is prepared, which includes a first base portion 11, a first barrier metal layer 12, and a first adhesion layer 13. The substrate 200 is similar to the substrate 200 described above, and therefore a detailed description will be omitted. The first barrier metal layer 12 includes a first solder region 12a and a first sealing region 12b. The first adhesion layer 13 includes a first adhesion region 13a and a second adhesion region 13b. The first adhesion region 13a is located on the first solder region 12a. The second adhesion region 13b is located on the first sealing region 12b. The first barrier metal layer 12 and the first adhesion layer 13 are formed by, for example, plating, physical vapor deposition, or chemical vapor deposition. The first barrier metal layer 12 and the first adhesion layer 13 are preferably formed by plating. The first barrier metal layer 12 covers a portion of or the entire surface of the first base portion 11. The first adhesion layer 13 is provided on the surface of the first barrier metal layer 12 opposite to the first base portion 11. The first adhesion layer 13 covers a part of or the entire surface of the first barrier metal layer 12.

[0090] When the upper surface 13x of the first adhesion layer 13 is roughened, a treatment for roughening the upper surface 13x of the first adhesion layer 13 is performed in the first step. The roughening treatment may be performed on only a portion of the upper surface 13x of the first adhesion layer 13, or on the entire upper surface 13x of the first adhesion layer 13. The roughening treatment is performed on at least the upper surface of the second adhesion region 13b. The roughening treatment may be performed on the upper surfaces of the first adhesion region 13a and the second adhesion region 13b.

[0091] The upper surface 13x of the first adhesion layer 13 is roughened by, for example, roughening plating, etching, or blackening. Roughening plating is, for example, forming a plating layer having a granular asperity on the surface in a plating process for forming the first adhesion layer 13. Etching and blackening are, for example, formed after the first adhesion layer 13 is formed, by chemical treatment with an acidic chemical solution to partially dissolve the upper surface 13x of the first adhesion layer 13, thereby forming the asperity.

[0092] In the second step, the semiconductor element 30 is provided on the first adhesion region 13a of the first adhesion layer 13 of the substrate 200, with the first solder layer 20 interposed therebetween. The first solder layer 20 is provided on the surface of the first adhesion layer 13 opposite the first base portion 11. More specifically, the second step is performed by applying a cream-like solder paste, which is the material for the first solder layer 20, onto the first adhesion region 13a of the first adhesion layer 13, and then placing the semiconductor element 30 thereon. Instead of applying the cream-like solder paste onto the first adhesion layer 13, a solder sheet or solder wire may be placed on the first adhesion region 13a of the first adhesion layer 13.

[0093] In the third step, the first solder layer 20 is reflowed, causing the portion of the first adhesion layer 13 that contacts the first solder layer 20 (first adhesion region 13a) to diffuse into the first solder layer 20, bringing the first solder layer 20 into contact with the first barrier metal layer 12 (first solder region 12a). As a result, the first adhesion region 13a of the first adhesion layer 13 is removed, leaving the second adhesion region 13b. The first barrier metal layer 12 contains a metal that diffuses into the solder at a slower rate than copper. Therefore, when the first solder layer 20 is reflowed, the first adhesion layer 13, which contains copper, dissolves in the first solder layer 20, while the first barrier metal layer 12 remains without dissolving in the first solder layer 20.

[0094] The reflow of the first solder layer 20 is performed by changing the temperature and pressure as shown in Figure 15. The vertical axis of Figure 15 represents temperature and pressure, and the horizontal axis of Figure 15 represents time. In Figure 15, the temperature is represented by a solid line and the pressure by a dashed line. The reflow is performed, for example, under the following conditions: 150-350℃ Heating rate: 1.8℃ / sec Holding time over 350℃: 98 seconds Peak temperature: 374℃ The above reflow conditions are an example when using a tin-antimony solder (manufactured by Senju Metal Industry Co., Ltd., product name: H3637) with a solidus temperature of 320°C or higher and a liquidus temperature of 350°C or higher as the solder material, and do not limit the reflow conditions.

[0095] Furthermore, while the solder is melting during reflow, the pressure inside the heating furnace is reduced to perform a decompression treatment, thereby discharging voids inside the first solder layer 20 to the outside of the first solder layer 20, thereby reducing the average void fraction of the first solder layer 20. The pressure inside the heating furnace during the decompression treatment is, for example, 1000 Pa or less, preferably 10 Pa or less, and more preferably 1 Pa or less. Furthermore, by setting the thickness of the first solder layer 20 to, for example, 20 μm or more, preferably 40 μm or more, voids become more likely to move during the decompression treatment, thereby reducing the average void fraction of the first solder layer 20. Furthermore, by setting the thickness of the first adhesive layer 13 to, for example, 2 μm or less, preferably 1 μm or less, and more preferably 0.5 μm or less, it is possible to prevent a decrease in the fluidity of the solder when Cu (first adhesive layer 13) dissolves in the molten solder (first solder layer 20), and to prevent voids from becoming more difficult to displace, thereby reducing the average void fraction of the first solder layer 20. For example, by these means, the average void ratio of the first solder layer 20 can be reduced to less than 2.5%.

[0096] In the fourth step, the sealing resin layer 40 is provided on the semiconductor element 30 and on the first adhesion layer 13 (second adhesion region 13b). The sealing resin layer 40 is formed using, for example, an epoxy resin, which is a thermosetting resin, under the following conditions. Molding temperature: 185℃ Cure time: 60 seconds Holding pressure: 12MPa After-cure: 175℃, 4 hours

[0097] The semiconductor device 100 according to the embodiment can be manufactured by the above-described first to fourth steps. According to the manufacturing method of the semiconductor device according to the embodiment, it is possible to manufacture a semiconductor device that can achieve both high-temperature reliability of the solder joints and adhesion between the lead frame 10 and the sealing resin layer 40. In the manufacturing method of the semiconductor device described above, description of wire bonding and lead (connector) bonding is omitted.

[0098] In the method for manufacturing a semiconductor device according to the embodiment, one semiconductor device 100 may be manufactured from one substrate 200, or multiple semiconductor devices 100 may be manufactured from one substrate 200. Manufacturing multiple semiconductor devices 100 from one substrate 200 can reduce manufacturing costs, for example. Hereinafter, a case where multiple semiconductor devices 100 are manufactured from one substrate 200 will be described.

[0099] FIG. 16 is a plan view illustrating a method for manufacturing a semiconductor device according to the embodiment. 16, when manufacturing a plurality of semiconductor devices 100 from one substrate 200, in the first step, the substrate 200 is prepared on which a plurality of semiconductor elements 30 can be mounted. For example, the example of FIG. 16 shows the substrate 200 on which 20 semiconductor elements 30 can be mounted.

[0100] 16, the first base 11 has a first portion 11a and a second portion 11b. The first portion 11a is a portion on which the semiconductor element 30 is placed. The second portion 11b is a portion on which the semiconductor element 30 is not placed. A first barrier metal layer 12 and a first adhesion layer 13 are provided on the first portion 11a. The first barrier metal layer 12 and the first adhesion layer 13 are not provided on the second portion 11b.

[0101] 16, the first base portion 11 has, for example, a plurality of first portions 11a that are spaced apart from one another and second portions 11b that are located between the plurality of first portions 11a. For example, by performing plating, physical vapor deposition, chemical vapor deposition, or the like while the second portions 11b are masked, the first barrier metal layer 12 and the first adhesion layer 13 can be formed on the first portions 11a without forming the first barrier metal layer 12 and the first adhesion layer 13 on the second portions 11b.

[0102] In this way, by not forming the first barrier metal layer 12 and the first adhesion layer 13 on the second portion 11b on which the semiconductor element 30 is not placed, manufacturing costs can be reduced compared to forming the first barrier metal layer 12 and the first adhesion layer 13 on both the first portion 11a and the second portion 11b (the entire surface of the first base portion 11).

[0103] In the first step, after forming the first barrier metal layer 12 and the first adhesion layer 13 on the first portion 11a, a predetermined portion of the first portion 11a may be punched out and removed to form a mounting portion on which the semiconductor element 30 is to be mounted and a wiring portion formed around the mounting portion.

[0104] When manufacturing a plurality of semiconductor devices 100 from one substrate 200, for example, the first step is followed by the above-described second, third, and fourth steps, and then the fifth step is performed to separate the semiconductor devices 100. The fifth step may be performed, for example, between the first and second steps, between the second and third steps, or between the third and fourth steps.

[0105] <Examples and Comparative Examples> Examples and comparative examples will be described below.

[0106] (Examples 1-1 to 1-3, Comparative Examples 1-1 to 1-2) FIG. 17 is a table showing the results of the examples and comparative examples. In Examples 1-1 to 1-3, the average void fraction after reflow and the high-temperature reliability of the solder joints were evaluated for semiconductor device samples manufactured using a substrate having a copper first base portion, a nickel first barrier metal layer, and a copper first adhesive layer on the first barrier metal layer. In Comparative Example 1-1, the average void fraction after reflow and the high-temperature reliability of the solder joints were evaluated for semiconductor device samples manufactured using a substrate having neither a first barrier metal layer nor a first adhesive layer on the copper first base portion. In Comparative Example 1-2, the average void fraction after reflow and the high-temperature reliability of the solder joints were evaluated for semiconductor device samples manufactured using a substrate having a nickel first barrier metal layer on the copper first base portion, and having neither a first adhesive layer on the first barrier metal layer. The thicknesses of the layers are as shown in FIG. 17. In Examples 1-1 to 1-3 and Comparative Examples 1-1 and 1-2, high-temperature lead-free solder "H3637" manufactured by Senju Metal Industry Co., Ltd. was used as the solder material. The results are shown in FIG. 17. The average void ratio was calculated as the average value of the void ratios in the solder layers of six samples. Regarding the high-temperature reliability of the solder joints, samples with no large voids or peeling in the solder joints were given a "Good" rating, and samples with large voids or peeling were given an "Poor" rating.

[0107] The void fraction of the solder layer was obtained using the following procedure. First, a transmission X-ray image of the solder layer was taken using a Mars Tohken Solutions X-ray inspection system TUX-3210N. The conditions for taking the transmission X-ray image were a tube voltage of 80 kV, a tube current of 100 μA, a focal spot size of 3, and a Z-axis coordinate of 50 mm. Next, the area of voids was measured from the captured X-ray image, and the ratio of the void area to the area of the entire joint surface was defined as the void fraction, and the void fraction was calculated. To calculate the void fraction, Mars Tohken Solutions' BAG bump analysis software was used. After importing the captured X-ray image into the image software, the highlight and shadow conditions were set in the "Image Acquisition Settings" and the image contrast was adjusted. After setting the inspection range from the X-ray image, the void inspection method was set to "Void inspection within specified area" in "Inspection settings," smoothing processing was performed (filter size set to 10), and the threshold value was determined in the "Void detection" setting so that the void shape and size matched between the binarized image and the captured X-ray image. Additionally, the void fraction can also be calculated using general-purpose image processing software.

[0108] As shown in Figure 17, in Comparative Example 1-1, which did not have a first barrier metal layer or a first adhesive layer, the average void fraction after reflow was high, and large voids were generated immediately after reflow. Furthermore, after being left at 175°C for 500 hours, solder peeling occurred. In contrast, in Examples 1-1 to 1-3 and Comparative Example 1-2, which had a first barrier metal layer, the average void fraction after reflow was lower than in Comparative Example 1-1, and no large voids or peeling occurred after being left at 175°C for 500 hours or 2000 hours after reflow. This suggests that the high-temperature reliability of solder joints can be improved by providing a first barrier metal layer.

[0109] (Examples 2-1 to 2-6, Comparative Examples 2-1 to 2-2) 18(a) and 18(b) are explanatory diagrams showing a method for measuring the adhesion strength of the example and the comparative example. FIG. 19 is a table showing the results of the examples and comparative examples. In Examples 2-1 to 2-6, adhesion between the substrate and the encapsulating resin was evaluated for semiconductor device samples manufactured using a substrate having a first nickel barrier metal layer on a first copper base portion and a first copper adhesive layer on the first barrier metal layer. In Examples 2-1 to 2-3, the upper surface of the first adhesive layer was not roughened. In Examples 2-4 to 2-6, the upper surface of the first adhesive layer was roughened using the method shown in FIG. 19. In Comparative Example 2-1, adhesion between the substrate and the encapsulating resin was evaluated for semiconductor device samples manufactured using a substrate having no first barrier metal layer or first adhesive layer on a first copper base portion. In Comparative Example 2-2, adhesion between the substrate and the encapsulating resin was evaluated for semiconductor device samples manufactured using a substrate having a first nickel barrier metal layer on a first copper base portion and no first adhesive layer on the first barrier metal layer. The thickness of each layer is as shown in FIG. 19. In Examples 2-1 to 2-6 and Comparative Examples 2-1 to 2-2, the sealing resin used was an epoxy resin "EME-G501B" manufactured by Sumitomo Bakelite Co., Ltd. The results are shown in Figure 19. The average adhesion strength was calculated as the average value of six samples.

[0110] The adhesion between the substrate and the sealing resin was evaluated as follows. First, as shown in Figure 18(a), a sample S was prepared in which sealing resin was formed so that the diameter was 2.0 mm, the height was 2.0 mm, and the angle was 85 degrees. Next, as shown in Figure 18(b), the sample S was fixed to a measuring device and measurements were performed. The sample S was fixed in a position where the distance D was 300 μm or more and there were no resin burrs. The measurement conditions were as follows: Load cell: 5kg Tool: Nordson DAGE SHR-187-5000 Shear speed: 100 μm / s Shear height (H): 1500 μm Tool movement: 500 μm Maximum distance: 2000μm

[0111] As shown in FIG. 19, Comparative Example 2-2, in which the first adhesive layer was not provided, had a low average adhesion strength. In contrast, Examples 2-1 to 2-6, in which the first adhesive layer was provided, had a higher average adhesion strength than Comparative Example 2-2. This suggests that providing a first adhesive layer on the first barrier metal layer can improve the adhesion between the lead frame and the sealing resin. Furthermore, Examples 2-4 to 2-6, in which the upper surface of the first adhesive layer was roughened, had a higher average adhesion strength than Examples 2-1 to 2-3, in which the upper surface of the first adhesive layer was not roughened. This suggests that roughening the upper surface of the first adhesive layer can further improve the adhesion between the lead frame and the sealing resin.

[0112] (Examples 3-1 to 3-6, Comparative Examples 3-1 to 3-2) FIG. 20 is a table showing the results of the examples and comparative examples. In Examples 3-1 to 3-6 and Comparative Examples 3-1 to 3-2, the adhesion between the substrate and the sealing resin was evaluated in the same manner as in Examples 2-1 to 2-6 and Comparative Examples 2-1 to 2-2, except that the epoxy resin "EME-G700LTD" manufactured by Sumitomo Bakelite Co., Ltd. was used as the sealing resin. The thickness of each layer is as shown in FIG. 20. The results are shown in FIG. 20. The average adhesion strength was calculated as the average value of six samples.

[0113] As shown in FIG. 20, Comparative Example 3-2, in which the first adhesive layer was not provided, had a low average adhesion strength. In contrast, Examples 3-1 to 3-6, in which the first adhesive layer was provided, had a higher average adhesion strength than Comparative Example 3-2. This suggests that providing a first adhesive layer on the first barrier metal layer can improve the adhesion between the lead frame and the sealing resin. Furthermore, Examples 3-4 to 3-6, in which the upper surface of the first adhesive layer was roughened, had a higher average adhesion strength than Examples 3-1 to 3-3, in which the upper surface of the first adhesive layer was not roughened. This suggests that roughening the upper surface of the first adhesive layer can further improve the adhesion between the lead frame and the sealing resin.

[0114] From the above, it is suggested that by providing a first barrier metal layer on the first base and providing a first adhesion layer on the first barrier metal layer, it is possible to achieve both high-temperature reliability of the solder joint and adhesion between the lead frame and the sealing resin.

[0115] Embodiments may include the following features.

[0116] (Configuration 1) A lead frame; a first solder layer provided on the lead frame; a semiconductor element provided on the first solder layer; an encapsulating resin layer provided on the semiconductor element and on the lead frame; Equipped with The lead frame is a first base; a first barrier metal layer provided on the first base portion, having a first solder region and a first sealing region, the first barrier metal layer including a metal having a diffusion rate into solder lower than that of copper; an adhesion layer including copper and provided on the first sealing region; and the first solder layer is disposed on the first solder region; The semiconductor device, wherein the sealing resin layer is provided on the semiconductor element and on the first adhesion layer.

[0117] (Configuration 2) 2. The semiconductor device according to configuration 1, wherein the first barrier metal layer has a thickness of 0.05 μm or more and 5 μm or less.

[0118] (Configuration 3) 3. The semiconductor device according to claim 1, wherein the first barrier metal layer includes at least one selected from the group consisting of nickel, chromium, and titanium.

[0119] (Configuration 4) 4. The semiconductor device according to any one of configurations 1 to 3, wherein the first adhesive layer has a thickness of 0.05 μm or more and 2 μm or less.

[0120] (Configuration 5) 5. The semiconductor device according to any one of configurations 1 to 4, wherein the upper surface of the first adhesive layer is roughened.

[0121] (Configuration 6) 6. The semiconductor device according to any one of configurations 1 to 5, wherein the first solder layer contains one or more selected from the group consisting of tin, silver, copper, antimony, nickel, bismuth, and lead.

[0122] (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the first solder layer has an average void ratio of less than 2.5%.

[0123] (Configuration 8) a second solder layer provided on the semiconductor element; a connector provided on the second solder layer; Furthermore, The connector comprises: a second base; a second barrier metal layer provided under the second base portion, having a second solder region and a second sealing region, the second barrier metal layer including a metal having a diffusion rate into the solder lower than that of copper; a second adhesion layer provided under the second sealing region and containing copper; and the second solder layer is disposed below the second solder region; 8. The semiconductor device according to any one of configurations 1 to 7, wherein the sealing resin layer is provided below the second adhesive layer.

[0124] (Configuration 9) A connecting frame; a third solder layer provided between the connection frame and the connector; Furthermore, The connector comprises: a third barrier metal layer provided under the second base portion, having a third solder region and a third sealing region, the third barrier metal layer including a metal having a diffusion rate into the solder lower than that of copper; a third adhesion layer provided under the third sealing region and containing copper; and the third solder layer is disposed below the third solder region; 9. The semiconductor device according to claim 8, wherein the sealing resin layer is provided below the third adhesive layer.

[0125] (Configuration 10) A connecting frame; a third solder layer provided between the lead frame and the connector; Furthermore, The connection frame is The third base; a fourth barrier metal layer provided on the third base portion, having a fourth solder region and a fourth sealing region, the fourth barrier metal layer including a metal having a diffusion rate into solder lower than that of copper; a fourth adhesion layer provided on the fourth sealing region and containing copper; and the third solder layer is disposed on the fourth solder region; 10. The semiconductor device according to claim 8, wherein the sealing resin layer is provided on the fourth adhesive layer.

[0126] (Configuration 11) a first step of preparing a substrate having a first base portion, a first barrier metal layer provided on the first base portion and containing a metal having a diffusion rate into solder lower than that of copper, and a first adhesion layer provided on the entire surface of the first barrier metal layer and containing copper; a second step of providing a semiconductor element on the first adhesive layer via a first solder layer; a third step of reflowing the first solder layer to diffuse a portion of the first adhesion layer that contacts the first solder layer into the first solder layer, thereby bringing the first solder layer into contact with the first barrier metal layer; a fourth step of providing an encapsulating resin layer on the semiconductor element and on the first adhesive layer; A method for manufacturing a semiconductor device comprising:

[0127] (Configuration 12) 12. The method for manufacturing a semiconductor device according to claim 11, wherein the first barrier metal layer has a thickness of 0.05 μm or more and 5 μm or less.

[0128] (Configuration 13) 13. The method for manufacturing a semiconductor device according to claim 11, wherein the first barrier metal layer includes at least one selected from the group consisting of nickel, chromium, and titanium.

[0129] (Configuration 14) 14. The method for manufacturing a semiconductor device according to any one of configurations 11 to 13, wherein the first adhesive layer has a thickness of 0.05 μm or more and 2 μm or less.

[0130] (Configuration 15) 15. The method for manufacturing a semiconductor device according to any one of configurations 11 to 14, wherein in the first step, the top surface of the first adhesive layer is roughened.

[0131] (Configuration 16) 16. The method for manufacturing a semiconductor device according to any one of configurations 11 to 15, wherein the first solder layer contains one or more selected from the group consisting of tin, silver, copper, antimony, nickel, bismuth, and lead.

[0132] (Configuration 17) a first base; a first barrier metal layer provided on the first base portion and including a metal having a diffusion rate into solder lower than that of copper; a first adhesion layer including copper and provided on the entire surface of the first barrier metal layer; A substrate comprising:

[0133] (Configuration 18) 18. The substrate of claim 17, wherein the first barrier metal layer has a thickness of 0.05 μm to 5 μm.

[0134] (Configuration 19) 19. The substrate of claim 17 or 18, wherein the first barrier metal layer comprises one or more selected from the group consisting of nickel, chromium, and titanium.

[0135] (Configuration 20) 20. The substrate according to any one of configurations 17 to 19, wherein the thickness of the first adhesive layer is 0.05 μm or more and 2 μm or less.

[0136] (Configuration 21) 21. The substrate of claim 20, wherein the first adhesive layer has a thickness of 1.5 μm or less.

[0137] (Configuration 22) 22. The substrate according to any one of configurations 17 to 21, wherein the upper surface of the first adhesive layer is roughened.

[0138] As described above, according to the embodiments, a semiconductor device, a method for manufacturing a semiconductor device, and a substrate are provided that can achieve both high-temperature reliability of the solder joints and adhesion between the lead frame and the sealing resin.

[0139] While the present invention has been described above by way of example, it is not intended to limit the scope of the present invention. This novel embodiment may be embodied in various other forms, and various omissions, substitutions, modifications, etc. may be made without departing from the spirit of the invention. This embodiment and its modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents. [Explanation of symbols]

[0140] 10: Lead frame 11:First base 11a: 1st part 11b:Second part 12: First barrier metal layer 12a: First solder area 12b: First sealing area 13: First adhesive layer 13a: First contact area 13b: Second contact area 13x:Top surface 13y: Bottom surface 18: Intermediate metal layer 18a: 1st intermediate area 18b: 2nd intermediate area 20: First solder layer 30: Semiconductor element 40: Sealing resin layer 50: Second solder layer 60: Connector 61:Second base 62: Second barrier metal layer 62a: Second solder area 62b: Second sealing area 63: Second adhesive layer 63x:Top surface 63y: Bottom surface 64: Third barrier metal layer 64a: Third solder area 64b: Third sealing area 65: Third adhesive layer 65x:Top 65y: Bottom surface 70: 3rd solder layer 80: Connection frame 81:Third base 82: Fourth barrier metal layer 82a: 4th solder area 82b: 4th sealing area 83: 4th adhesive layer 83x:Top surface 83y: Bottom surface 100, 100A, 100B, 100C, 100D: semiconductor device 200: Substrate

Claims

1. A lead frame; a first solder layer provided on the lead frame; a semiconductor element provided on the first solder layer; an encapsulating resin layer provided on the semiconductor element and on the lead frame; Equipped with The lead frame is A first base portion; a first barrier metal layer provided on the first base portion, the first barrier metal layer having a first solder region and a first sealing region, the first barrier metal layer including a metal having a diffusion rate into the solder lower than that of copper; a first adhesion layer provided on the first sealing region and containing copper; and the first solder layer is disposed on the first solder region; The semiconductor device, wherein the sealing resin layer is provided on the semiconductor element and on the first adhesion layer.

2. The semiconductor device according to claim 1 , wherein the first adhesion layer has a thickness of 0.05 μm or more and 2 μm or less.

3. The semiconductor device according to claim 1 , wherein an upper surface of the first adhesion layer is roughened.

4. The semiconductor device according to claim 1 , wherein the first solder layer has an average void fraction of less than 2.5%.

5. a second solder layer disposed on the semiconductor element; a connector disposed on the second solder layer; Furthermore, The connector comprises: A second base; a second barrier metal layer provided under the second base portion, having a second solder region and a second sealing region, the second barrier metal layer including a metal having a diffusion rate into the solder lower than that of copper; a second adhesion layer provided under the second sealing region and containing copper; and the second solder layer is disposed below the second solder region; The semiconductor device according to claim 1 , wherein the sealing resin layer is provided below the second adhesive layer.

6. a first step of preparing a substrate having a first base portion, a first barrier metal layer provided on the first base portion and containing a metal having a diffusion rate into solder lower than that of copper, and a first adhesion layer provided on the entire surface of the first barrier metal layer and containing copper; a second step of providing a semiconductor element on the first adhesive layer via a first solder layer; a third step of reflowing the first solder layer to diffuse a portion of the first adhesion layer that contacts the first solder layer into the first solder layer, thereby bringing the first solder layer into contact with the first barrier metal layer; a fourth step of providing an encapsulating resin layer on the semiconductor element and on the first adhesive layer; A method for manufacturing a semiconductor device comprising:

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein said first barrier metal layer includes at least one selected from the group consisting of nickel, chromium, and titanium.

8. The method for manufacturing a semiconductor device according to claim 6 , wherein the first adhesion layer has a thickness of 0.05 μm or more and 2 μm or less.

9. The method for manufacturing a semiconductor device according to claim 6 , wherein the upper surface of the first adhesive layer is roughened in the first step.

10. A first base portion; a first barrier metal layer provided on the first base portion and including a metal having a diffusion rate into solder lower than that of copper; a first adhesion layer including copper and provided on the entire surface of the first barrier metal layer; A substrate comprising:

11. The substrate according to claim 10 , wherein the first adhesion layer has a thickness of 0.05 μm or more and 2 μm or less.

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