Semiconductor device

Abstract

To make a breakdown voltage high by eliminating the need of structure design for surge tolerance of an HVIC.SOLUTION: An upper arm control circuit (HVIC) 1H performs drive control of an upper arm switching element sw1 which actuates a load L0 based on an upper arm drive signal which is transmitted from a control unit and inputted to a terminal INHU. An overvoltage detection circuit 1oc detects an overvoltage state of the upper arm control circuit 1H and outputs an overvoltage detection signal d1. A lower arm control circuit (LVIC) 1L performs drive control of a lower arm switching element sw2 which is connected in series to the upper arm switching element sw1 based on a lower arm drive signal, which is transmitted from the control unit and inputted to a terminal INLU, or the overvoltage detection signal d1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] An inverter device for driving a motor is equipped with an upper arm switching element that controls the current flowing through the coil inside the motor, and a drive circuit (HVIC: High Voltage IC) that controls the on / off of the upper arm switching element.

[0003] Related technologies include, for example, a technology that protects a high-side switching drive circuit from negative surges generated by the self-inductance of wiring by providing a resistor between an input buffer and a power supply to suppress the flow of surge current into the low-side switching drive circuit (Patent Document 1).Also proposed is a technology that prevents chain damage of the inverter circuit by suppressing the application of overvoltage using an overvoltage protection Zener diode inserted between the high-voltage side control power supply terminal and the low-voltage side control power supply terminal (Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-72942 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-148511 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device with high breakdown voltage that does not require structural design for surge resistance of HVIC. [Means for solving the problem]

[0006] To solve the above problem, a semiconductor device is provided that includes an upper-arm control circuit that controls the drive of an upper-arm switching element based on an upper-arm drive signal transmitted from a control unit, an overvoltage detection circuit that detects an overvoltage state of the upper-arm control circuit and outputs an overvoltage detection signal, and a lower-arm control circuit that controls the drive of a lower-arm switching element connected in series to the upper-arm switching element based on a lower-arm drive signal or the overvoltage detection signal transmitted from the control unit. [Effects of the Invention]

[0007] According to one aspect, it is possible to achieve high voltage resistance without the need for structural design for surge resistance of HVIC. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of an inverter device. [Figure 3] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor driving device. [Figure 4] FIG. 2 is a diagram illustrating an example of an internal configuration of a semiconductor control device. [Figure 5] FIG. 2 is a diagram illustrating an example of a connection state between a semiconductor control device and a coil. [Figure 6] FIG. 2 is a diagram illustrating an example of the configuration of an upper arm control circuit. [Figure 7] FIG. 2 is a diagram illustrating an example of the configuration of a control circuit. [Figure 8] FIG. 2 is a diagram illustrating an example of the configuration of a drive circuit. [Figure 9] FIG. 2 is a diagram illustrating an example of the configuration of a lower arm control circuit. [Figure 10] FIG. 2 is a diagram illustrating an example of the configuration of an inverter circuit. [Figure 11] FIG. 2 is a diagram illustrating an example of the configuration of an inverter circuit. [Figure 12] FIG. 2 is a diagram illustrating an example of the configuration of a NAND circuit. [Figure 13]FIG. 2 is a diagram illustrating an example of the configuration of a NOR circuit. [Figure 14] FIG. 2 illustrates an example of the configuration of a comparator. [Figure 15] FIG. 2 is a diagram illustrating an example of the configuration of a reference voltage circuit. [Figure 16] 5 is a diagram illustrating an example of the relationship between a drive signal of a switching element and a current flowing through a coil. FIG. [Figure 17] FIG. 10 is a diagram illustrating an example of timing during a switching operation. [Figure 18] FIG. 10 is a diagram illustrating an example of timing during a switching operation. [Figure 19] FIG. 2 is a diagram showing an example of a cross-sectional structure of a main part of an upper arm control circuit. [Figure 20] FIG. 1 is a diagram illustrating an example of a mounting structure of a semiconductor control device. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same configuration may be designated by the same reference numerals to avoid redundant description. In this specification, unless otherwise specified, "connection" means "electrical connection." Furthermore, regarding voltages or signals, a low potential level of the logic is referred to as a Lo level, and a high potential level of the logic is referred to as a Hi level. Furthermore, the ground potential is a reference potential of the entire system including the semiconductor device, and is 0V (GND).

[0010] 1 is a diagram illustrating an example of a semiconductor device. The semiconductor device 10 includes an upper arm control circuit (HVIC) 1H, a lower arm control circuit (LVIC: Low Voltage IC) 1L, an upper arm switching element sw1, a lower arm switching element sw2, diodes D1 and D2, and an overvoltage detection circuit 1oc. The semiconductor device 10 further includes power supplies V1 and V2, a resistor R0, a diode D0, and a capacitor C0, and is connected to a load L0. The semiconductor device 10 is applied to, for example, an IPM (Intelligent Power Module) that is widely used in automotive electrical systems.

[0011] The upper arm control circuit 1H has terminals VB, VS, VCC, INHU, COMH, and VS1, and the lower arm control circuit 1L has terminals VCC, COM, and INLU.

[0012] The upper arm control circuit 1H controls the drive of the upper arm switching element sw1 that operates the load L0 based on the upper arm drive signal sH input to the terminal INHU. The overvoltage detection circuit 1oc determines whether the upper arm control circuit 1H is in an overvoltage state, and outputs an overvoltage detection signal d1 if it detects an overvoltage state.

[0013] The lower arm control circuit 1L controls the drive of the lower arm switching element sw2 connected in series to the upper arm switching element sw1 based on the lower arm drive signal sL input to the terminal INLU or the overvoltage detection signal d1.

[0014] The upper arm drive signal sH and the lower arm drive signal sL are transmitted from a control unit 12 (for example, a microcomputer). The overvoltage detection circuit 1oc may be configured to be included in a lower arm control circuit 1L, as shown in FIG. 9, which will be described later.

[0015] The positive terminal of the power supply V1 is connected to one end of the resistor R0, the terminal VCC on the upper arm side, and the terminal VCC on the lower arm side. The negative terminal of the power supply V1 is connected to the terminal COM and the reference potential (hereinafter sometimes referred to as GND).

[0016] The other end of the resistor R0 is connected to the anode of a diode D0, the cathode of which is connected to one end of a capacitor C0 and to the terminal VB, and the other end of the capacitor C0 is connected to the terminal VS.

[0017] Resistor R0, diode D0, and capacitor C0 constitute a bootstrap circuit that supplies voltage for driving the gate of upper-arm switching element sw1. Therefore, upper-arm control circuit 1H controls the drive of upper-arm switching element sw1 using a drive power supply voltage between a high-potential side drive power supply voltage (voltage at terminal VB) that is a floating potential and a low-potential side drive power supply voltage (voltage at terminal VS).

[0018] On the other hand, a diode D1 (first diode) is connected in antiparallel to the upper arm switching element sw1, and a diode D2 (second diode) is connected in antiparallel to the lower arm switching element sw2.

[0019] The high potential terminal (first high potential terminal) of the upper arm switching element sw1 is connected to the cathode of the diode D1 and a high potential side power supply terminal (terminal P) connected to the positive terminal of the power supply V2.

[0020] The low potential terminal (first low potential terminal) of the upper arm switching element sw1 is connected to a low potential side drive power supply terminal (terminal VS1) to which a low potential side drive power supply voltage (voltage at terminal VS) is applied, an output terminal (terminal U) connected to load L0, the anode of diode D1, the high potential terminal (second high potential terminal) of the lower arm switching element sw2, and the cathode of diode D2.

[0021] The low potential terminal (second low potential terminal) of the lower arm switching element sw2 is connected to the anode of the diode D2, the negative terminal of the power supply V2, and a low potential side power supply terminal (terminal NU) connected to GND. The terminal COMH is connected to the negative terminal of the power supply V1 and GND via the overvoltage detection circuit 1oc and terminal COM.

[0022] When the overvoltage detection signal d1 is output from the overvoltage detection circuit 1oc, the lower arm switching element sw2 turns on, the terminal VS1 becomes conductive to the terminal NU, and the drive power supply voltage applied to the upper arm control circuit 1H drops.

[0023] Here, when the upper arm switching element sw1 is off and the lower arm switching element sw2 is on, the potential (collector potential) of the high potential terminal of the lower arm switching element sw2 becomes approximately equal to the device reference potential (GND).

[0024] Next, when the lower arm switching element sw2 is turned off, the collector potential of the lower arm switching element sw2 increases rapidly, and when it exceeds the power supply potential of the device, the current flowing through the lower arm switching element sw2 starts to flow through the upper arm diode D1.

[0025] In the transient state when current begins to flow through diode D1, the high dynamic resistance of diode D1 causes the collector potential of lower-arm switching element sw2 to exceed the power supply potential of the device. At this time, the collector-emitter voltage of lower-arm switching element sw2 and the voltage between terminal VB and terminal COMH of upper-arm control circuit 1H reach their maximums. In this case, if the withstand voltage of upper-arm control circuit 1H is lower than the withstand voltage of the switching element, there is a possibility that upper-arm control circuit 1H will be destroyed.

[0026] For this reason, it is conceivable to give the upper arm control circuit 1H a high-voltage withstand structure so that the upper arm control circuit 1H will not be destroyed even in an overvoltage state in which a voltage higher than the withstand voltage of the switching element is applied. However, giving the element structure of the upper arm control circuit 1H a high withstand voltage is technically difficult, and also increases manufacturing costs due to factors such as an increase in the area of the semiconductor substrate.

[0027] On the other hand, when the voltage between terminal VB and terminal COMH of the upper arm control circuit 1H exceeds a predetermined withstand voltage, a current (leakage current IL1) flows from terminal VB (floating potential) to terminal COMH (ground potential), and the leakage current IL1 flowing out from terminal COMH increases.

[0028] Therefore, in the semiconductor device 10 of the present invention, in addition to controlling the drive of the lower arm switching element sw2 based on the lower arm drive signal sL input to the terminal INLU, when the overvoltage detection circuit 1oc detects an overvoltage state of the upper arm control circuit 1H based on the leakage current IL1, the lower arm switching element sw2 is turned on based on the overvoltage detection signal d1 output when an overvoltage state occurs.

[0029] With this control, when the lower-arm switching element sw2 is turned on when the upper-arm control circuit 1H is in an overvoltage state, the increase in the VB voltage at terminal VB is suppressed (the increase in the voltage applied to terminal U is also suppressed), so the leakage current IL1 between terminal VB and terminal COMH also decreases and becomes constant, the overvoltage state of the upper-arm control circuit 1H is resolved, and overvoltage protection can be achieved. This makes it possible to achieve a high withstand voltage without the need for structural design for surge resistance in the upper-arm control circuit 1H.

[0030] <Outline of inverter devices using semiconductor devices> The present invention will be described in detail below. Fig. 2 is a diagram showing an example of the configuration of an inverter device. The inverter device 1 includes a power supply 11, a control unit 12, a motor 13, a power supply 14, and a semiconductor driver 21a having the functions of the semiconductor device 10.

[0031] The power supply 11 supplies a power supply voltage Vcc, and is, for example, an automobile battery with Vcc=15V. The control unit 12 is, for example, an automobile electronic control unit (ECU). The motor 13 corresponds to the load L0, and is, for example, a three-phase AC motor. The power supply 14 supplies a power supply voltage Vdd, and is, for example, an automobile battery with Vdd=400V. The semiconductor drive device 21a drives the motor 13 based on the upper arm / lower arm drive signals output from the control unit 12.

[0032] <Configuration Example of Semiconductor Driver 21a> 2 is a diagram showing an example of the configuration of a semiconductor driving device. A semiconductor driving device 21a shown in FIG. 2 includes a semiconductor control device 21, resistors 22, 23, 24, diodes 25, 26, 27, and capacitors 28, 29, 30.

[0033] The semiconductor control device 21 also has a terminal VCC, which is a power supply terminal, a terminal P, and a terminal COM, which is a common ground terminal. The terminal VCC is connected to the positive terminal of the power supply 11 in Figure 2, and the terminal P is connected to the positive terminal of the power supply 14 in Figure 2. The terminal COM is connected to GND.

[0034] Furthermore, the semiconductor control device 21 has a terminal INHU (high-side U-phase input terminal), a terminal INHV (high-side V-phase input terminal), a terminal INHW (high-side W-phase input terminal), a terminal INLU (low-side U-phase input terminal), a terminal INLV (low-side V-phase input terminal), and a terminal INLW (low-side W-phase input terminal).

[0035] Terminals INHU, INHV, and INHW receive the high-side upper arm drive signals Sinhu, Sinhv, and Sinhw, respectively, output from the control unit 12. Terminals INLU, INLV, and INLW receive the low-side lower arm drive signals Sinlu, Sinlv, and Sinlw, respectively, output from the control unit 12.

[0036] Furthermore, the semiconductor control device 21 has a terminal U (U-phase output terminal), a terminal V (V-phase output terminal), a terminal W (W-phase output terminal), a terminal NU (inverted U-phase output terminal), a terminal NV (inverted V-phase output terminal), and a terminal NW (inverted W-phase output terminal) for operating the motor 13. The terminals U, V, and W are connected to the motor 13, and the terminals NU, NV, and NW are connected to GND.

[0037] Furthermore, the semiconductor control device 21 has a terminal VccHU (high-side U-phase power supply terminal), a terminal VccHV (high-side V-phase power supply terminal), a terminal VccHW (high-side W-phase power supply terminal), and a terminal VccL (low-side power supply terminal).

[0038] The semiconductor control device 21 also has a terminal VBU (high-side U-phase drive power supply terminal), a terminal VBV (high-side V-phase drive power supply terminal), a terminal VBW (high-side W-phase drive power supply terminal), a terminal VSU (high-side U-phase low potential terminal), a terminal VSV (high-side V-phase low potential terminal), and a terminal VSW (high-side W-phase low potential terminal).

[0039] In the connection relationship between the resistors 22, 23, 24, the diodes 25, 26, 27, and the capacitors 28, 29, 30, one end of the resistor 22 is connected to the terminal VCC, the terminal VccHU, the terminal VccHV, one end of the resistor 23, the terminal VccHW, one end of the resistor 24, and the terminal VccL.

[0040] The other end of the resistor 22 is connected to the anode of a diode D25, the cathode of the diode D25 is connected to the terminal VBU and one end of a capacitor 28, and the other end of the capacitor 28 is connected to the terminal VSU.

[0041] The other end of the resistor 23 is connected to the anode of a diode D26, the cathode of the diode D26 is connected to the terminal VBV and one end of a capacitor 29, and the other end of the capacitor 29 is connected to the terminal VSV.

[0042] The other end of the resistor 24 is connected to the anode of a diode D27, the cathode of the diode D27 is connected to the terminal VBW and one end of a capacitor 30, and the other end of the capacitor 30 is connected to the terminal VSW.

[0043] The resistor 22, diode 25, and capacitor 28 constitute a bootstrap circuit on the U-phase side, the resistor 23, diode 26, and capacitor 29 constitute a bootstrap circuit on the V-phase side, and the resistor 24, diode 27, and capacitor 30 constitute a bootstrap circuit on the W-phase side. When the potentials of terminals VSU, VSV, and VSW are at the Lo level, capacitors 28, 29, and 30 are charged to a voltage equivalent to the power supply voltage Vcc.

[0044] <Example of internal configuration of semiconductor control device 21> 4 is a diagram showing an example of the internal configuration of a semiconductor control device 21. The semiconductor control device 21 includes upper arm control circuits 31, 32, and 33, a lower arm control circuit 34, switching elements 41, 42, 43, 44, 45, and 46, and FWDs (Free Wheeling Diodes) 51, 52, 53, 54, 55, and 56.

[0045] The switching elements 41, 42, 43, 44, 45, and 46 are, for example, insulated gate bipolar transistors (IGBTs), or may be power metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0046] The upper arm control circuit 31 controls the current flowing through the switching element 41, the upper arm control circuit 32 controls the current flowing through the switching element 42, and the upper arm control circuit 33 controls the current flowing through the switching element 43. The lower arm control circuit 34 controls the current flowing through the switching elements 44, 45, and 46.

[0047] Here, the gate of the switching element 41 is connected to the output end of the upper arm control circuit 31. The high potential terminal of the switching element 41 is connected to the high potential terminal of the switching element 42, the high potential terminal of the switching element 43, the cathode of FWD51, the cathode of FWD52, the cathode of FWD53, and the terminal P.

[0048] The low potential terminal of the switching element 41 is connected to the terminal VSU, the anode of the FWD 51, the terminal U, the high potential terminal of the switching element 44, and the cathode of the FWD . The gate of the switching element 42 is connected to the output terminal of the upper arm control circuit 32. The low potential terminal of the switching element 42 is connected to the terminal VSV, the anode of the FWD52, the terminal V, the high potential terminal of the switching element 45, and the cathode of the FWD55.

[0049] The gate of the switching element 43 is connected to the output terminal of the upper arm control circuit 33. The low potential terminal of the switching element 43 is connected to the terminal VSW, the anode of the FWD53, the terminal W, the high potential terminal of the switching element 46, and the cathode of the FWD56.

[0050] The gate of the switching element 44 is connected to the first output terminal of the lower arm control circuit 34, and the low potential terminal of the switching element 44 is connected to the anode of the FWD 54 and the terminal NU. The gate of the switching element 45 is connected to the second output terminal of the lower arm control circuit 34, and the low potential terminal of the switching element 45 is connected to the anode of the FWD 55 and the terminal NV.

[0051] The gate of the switching element 46 is connected to the third output terminal of the lower-arm control circuit 34, and the low-potential terminal of the switching element 46 is connected to the anode of the FWD 56 and the terminal NW. Each of the upper-arm control circuits 31, 32, and 33 has a terminal COMH, and the lower-arm control circuit 34 has a terminal COMH(L), with the terminals COMH and COMH(L) being connected to each other. The terminal COMH is also connected to GND via the terminal COMH(L), a resistor in the lower-arm control circuit 34, and the terminal COM (described later in FIG. 9).

[0052] <Connection between semiconductor control device and coil> 5 is a diagram showing an example of a connection state between the semiconductor control device and the coils. The motor 13 is a three-phase AC motor, and is provided with a U-phase coil 301, a V-phase coil 302, and a W-phase coil 303.

[0053] One end of U-phase coil 301 is connected to terminal U, one end of V-phase coil 302 is connected to terminal V, and one end of W-phase coil 303 is connected to terminal W. The other end of U-phase coil 301 is connected to the other end of V-phase coil 302 and the other end of W-phase coil 303. Current IU flows through U-phase coil 301 via terminal U, current IV flows through V-phase coil 302 via terminal V, and current IW flows through W-phase coil 303 via terminal W.

[0054] <Configuration example of upper arm control circuit 31> Figure 6 is a diagram showing an example of the configuration of the upper arm control circuit. Upper arm control circuits 31, 32, and 33 may have the same configuration, so only upper arm control circuit 31 will be described. Upper arm control circuit 31 has a control circuit 61, a drive circuit 66, resistors 62 and 63, and switching elements 64 and 65, and is configured on a single chip. Note that NMOS transistors are used for switching elements 64 and 65.

[0055] The terminal VCCHU is connected to a power supply terminal of the control circuit 61. The terminal INHU is connected to an input terminal of the control circuit 61. A first output terminal of the control circuit 61 is connected to a gate of the switching element 64, and a second output terminal of the control circuit 61 is connected to a gate of the switching element 65.

[0056] Terminal VBU is connected to one end of resistor 62, one end of resistor 63, and a power supply end of drive circuit 66. The other end of resistor 62 is connected to the drain of switching element 64 and a first input end of drive circuit 66, and the other end of resistor 63 is connected to the drain of switching element 65 and a second input end of drive circuit 66.

[0057] The terminal COMH is connected to the reference potential end of the control circuit 61, the source of the switching element 64, and the source of the switching element 65. The output end of the drive circuit 66 is connected to the terminal OUT, and the reference potential end of the drive circuit 66 is connected to the terminal VSU.

[0058] Here, resistor 62 and switching element 64, and resistor 63 and switching element 65 function as level shift circuits, respectively. When the gate voltages of switching elements 64 and 65 are at Hi level, the drain voltages of switching elements 64 and 65 are at the same potential as terminal COMH. When the gate voltages of switching elements 64 and 65 are at Lo level, the drain voltages of switching elements 64 and 65 are at the same potential as terminal VBU.

[0059] <Configuration example of control circuit 61> 7 is a diagram showing an example of the configuration of the control circuit 61. The control circuit 61 includes terminals VCCHU, COMH, INHU, S, R, inverter circuits 71, 72, 75, and 78, resistors 73 and 76, and capacitors 74 and 77.

[0060] The terminal VCCHU is connected to the power supply terminals of the inverter circuits 71 and 72. The terminal INHU, to which the upper arm drive signal Sinhu is input from the control unit 12, is connected to the input terminal of the inverter circuit 71. The output terminal of the inverter circuit 71 is connected to the input terminal of the inverter circuit 72, one terminal of the resistor 76, and the power supply terminal of the inverter circuit 78. The output terminal of the inverter circuit 72 is connected to one terminal of the resistor 73 and the power supply terminal of the inverter circuit 75.

[0061] The other end of resistor 73 is connected to one end of capacitor 74 and the input end of inverter circuit 75. The other end of resistor 76 is connected to one end of capacitor 77 and the input end of inverter circuit 78. The other end of capacitor 74 is connected to the reference potential end of inverter circuit 72, the reference potential end of inverter circuit 75, the reference potential end of inverter circuit 78, the other end of capacitor 77, the reference potential end of inverter circuit 71, and terminal COMH. The output end of inverter circuit 75 is connected to terminal S, and the output end of inverter circuit 78 is connected to terminal R.

[0062] Here, the resistor 73 and the capacitor 74, and the resistor 76 and the capacitor 77 respectively constitute delay circuits, and when the output voltage levels of the inverter circuits 71 and 72 change, the input voltage levels of the inverter circuits 75 and 78 change with a delay.

[0063] The control circuit 61 outputs a pulse signal when the upper arm drive signal Sinhu output from the control unit 12 is input to the terminal INHU. For example, when the voltage of the signal Sinhu increases from less than 2.5 V to 2.5 V or more, a Hi-level voltage pulse is output from the terminal S. The voltage pulse becomes Lo-level after a certain time (for example, 0.1 μs) has elapsed.

[0064] When the voltage of signal Sinhu drops from 2.5V or higher to less than 2.5V, a Hi-level voltage pulse is output from terminal R. When the voltage level of signal Sinhu does not change, the voltage levels of terminals S and R are Lo.

[0065] <Configuration example of the drive circuit 66> 8 is a diagram showing an example of the configuration of the drive circuit 66. The drive circuit 66 includes a terminal VBU, a terminal VSU, a terminal S, a terminal R, a terminal OUT, and NAND circuits (negative AND circuits) 81 and .

[0066] The terminal VBU is connected to the power supply terminal of the NAND circuit 81 and the power supply terminal of the NAND circuit 82. The terminal VSU is connected to the reference potential terminal of the NAND circuit 81 and the reference potential terminal of the NAND circuit 82.

[0067] The terminal S is connected to a first input terminal of the NAND circuit 81, and the terminal R is connected to a first input terminal of the NAND circuit 82. The output terminal of the NAND circuit 81 is connected to the terminal OUT and a second input terminal of the NAND circuit 82. The output terminal of the NAND circuit 82 is connected to the second input terminal of the NAND circuit 81.

[0068] Here, the drive circuit 66 functions as an RS latch circuit. The voltage levels of the terminals S and R are Hi level in a steady state, and when the signal Sinhu input to the terminal INHU of the control circuit 61 shown in Fig. 7 changes from Lo level to Hi level, a Lo level pulse signal is input to the terminal S of the drive circuit 66, and the voltage level of the terminal OUT becomes Hi level.

[0069] 7 changes from Hi level to Lo level, a Lo level pulse signal is input to terminal R of drive circuit 66, and the voltage level of terminal OUT becomes Lo level. When the voltage of terminal OUT is Hi level, switching element 41 to which terminal OUT is connected turns on, and when it is Lo level, it turns off.

[0070] <Configuration example of lower arm control circuit 34> 9 is a diagram showing an example of the configuration of the lower-arm control circuit 34. The lower-arm control circuit 34 includes terminals VCCL, COM, COMH(L), INLU, INLV, INLW, OUTLU, OUTLV, and OUTLW, NOR circuits (negative-OR circuits) 91, 92, and 93, inverter circuits 94, 95, and 96, a comparator 97, a reference voltage circuit 98, and a resistor 99. The circuit including the comparator 97, the reference voltage circuit 98, and the resistor 99 constitutes the overvoltage detection circuit 10c shown in FIG.

[0071] The terminal VCCL is connected to the power supply terminals of the comparator 97, the reference voltage circuit 98, the NOR circuits 91, 92, 93, and the inverter circuits 94, 95, 96. The terminal COMH(L) is connected to the non-inverting input terminal (+) of the comparator 97 and one end of the resistor 99. The terminal COM is connected to the other end of the resistor 99, the reference potential terminal of the comparator 97, the reference potential terminal of the reference voltage circuit 98, the reference potential terminals of the inverter circuits 94, 95, 96, and the reference potential terminals of the NOR circuits 91, 92, 93.

[0072] The output terminal of the reference voltage circuit 98 is connected to the inverting input terminal (-) of the comparator 97. The output terminal of the comparator 97 is connected to a first input terminal of the NOR circuit 91, a first input terminal of the NOR circuit 92, and a first input terminal of the NOR circuit 93.

[0073] A terminal INLU to which the lower arm drive signal Sinlu is input is connected to a second input terminal of the NOR circuit 91, and a terminal INLV to which the lower arm drive signal Sinlv is input is connected to a second input terminal of the NOR circuit 92. A terminal INLW to which the lower arm drive signal Sinlw is input is connected to a second input terminal of the NOR circuit 93.

[0074] The output terminal of the NOR circuit 91 is connected to the input terminal of an inverter circuit 94, and the output terminal of the inverter circuit 94 is connected to the terminal OUTLU. The output terminal of the NOR circuit 92 is connected to the input terminal of an inverter circuit 95, and the output terminal of the inverter circuit 95 is connected to the terminal OUTLV. The output terminal of the NOR circuit 93 is connected to the input terminal of an inverter circuit 96, and the output terminal of the inverter circuit 96 is connected to the terminal OUTLW.

[0075] The terminal OUTLU is connected to the gate of the switching element 44, the terminal OUTLV is connected to the gate of the switching element 45, and the terminal OUTLW is connected to the gate of the switching element 46.

[0076] The lower arm control circuit 34 turns on / off the switching element 44 in response to a lower arm drive signal Sinlu output from the control unit 12 being input to a terminal INLU. Similarly, the lower arm control circuit 34 turns on / off the switching element 45 in response to a lower arm drive signal Sinlv output from the control unit 12 being input to a terminal INLV, and turns on / off the switching element 46 in response to a lower arm drive signal Sinlw output from the control unit 12 being input to a terminal INLW. Furthermore, when the voltage at the terminal COMH(L) becomes larger than the output voltage of the reference voltage circuit 88, the switching elements 44, 45, 46 are turned on.

[0077] Here, the resistor 99 is an element that converts the leakage current IL1 flowing from the terminal COMH of the upper arm control circuits 31, 32, 33 into a voltage signal when the leakage current IL1 is input via the terminal COMH(L), and detects the magnitude of the leakage current IL1. The reference voltage circuit 98 outputs a reference voltage.

[0078] The comparator 97 compares the voltage signal with a reference voltage to determine whether the upper arm control circuits 31, 32, and 33 are in an overvoltage state. In this case, the comparator 97 detects an overvoltage state when the voltage signal is equal to or higher than the reference voltage, and outputs a Hi-level overvoltage detection signal (corresponding to the overvoltage detection signal d1 in FIG. 1) which is input to the first input terminals of the NOR circuits 91, 92, and 93. When an overvoltage state is not present, the comparator 97 outputs a Lo-level signal.

[0079] For example, if the normal circuit current is 1 mA, the resistance value of resistor 99 is set to 100 Ω, and the abnormal current is set to 10 mA. Therefore, if a current of 10 mA or more flows through resistor 99, comparator 97 will output a Hi-level signal.

[0080] <Switching elements 41, 42, 43, 44, 45, 46> The switching elements 41, 42, 43, 44, 45, and 46 switch the voltage applied from the power supply 14 to the motor 13. The switching elements 41, 42, 43, 44, 45, and 46 are, for example, high-voltage switching elements.

[0081] The switching elements 41, 42, 43, 44, 45, and 46 of this embodiment are, for example, vertical N-type insulated gate bipolar transistors (IGBTs) with an emitter electrode formed on the front surface of a substrate and a collector electrode formed on the back surface. The switching elements 41, 42, 43, 44, 45, and 46 have, for example, an on-resistance of 10 mΩ and a breakdown voltage of several hundred volts.

[0082] The switching elements 41, 42, 43, 44, 45, and 46 are not limited to IGBTs, but may be MOS transistors or bipolar transistors. <Configuration example of inverter circuit 71> 10 is a diagram showing an example of the configuration of an inverter circuit 71. The inverter circuit 71 includes a terminal IN, a terminal OUT, a terminal VH (high potential side terminal), a terminal VL (low potential side terminal), and MOS transistors 101 and 102.

[0083] The MOS transistors 101 and 102 are NMOS transistors. The MOS transistor 101 is a depletion-type NMOS transistor in which a current flows between the drain and source when the gate-source voltage is 0 V. The inverter circuit 71 inverts the voltage level of the terminal IN and outputs it to the terminal OUT.

[0084] The terminal VH is connected to the drain of the NMOS transistor 101. The gate of the NMOS transistor 101 is connected to the source of the NMOS transistor 101, the terminal OUT, and the drain of the NMOS transistor 102. The terminal IN is connected to the gate of the NMOS transistor 102. The terminal VL is connected to the source of the NMOS transistor 102.

[0085] <Configuration examples of inverter circuits 72, 75, 78, 94, 95, 96> FIG. 11 is a diagram showing an example of the configuration of an inverter circuit. Inverter circuits 72, 75, 78, 94, 95, 96 include a terminal IN, a terminal OUT, a terminal VH (high potential side terminal), a terminal VL (low potential side terminal), and MOS transistors 111, 112. MOS transistor 111 is a PMOS transistor, and MOS transistor 112 is an NMOS transistor. Inverter circuits 72, 75, 78, 94, 95, 96 invert the voltage level of terminal IN and output it to terminal OUT.

[0086] Terminal IN is connected to the gates of PMOS transistor 111 and NMOS transistor 112. Terminal VH is connected to the source of PMOS transistor 111. The drain of PMOS transistor 111 is connected to terminal OUT and the drain of NMOS transistor 112. Terminal VL is connected to the source of NMOS transistor 112.

[0087] <Configuration examples of NAND circuits 81, 82> FIG. 12 is a diagram showing an example of the configuration of a NAND circuit. NAND circuits 81, 82 include a terminal IN1, a terminal IN2, a terminal OUT, a terminal VH (high potential side terminal), a terminal VL (low potential side terminal), and MOS transistors 121, 122, 123, 124. MOS transistors 121, 122 are PMOS transistors. MOS transistors 123, 124 are NMOS transistors.

[0088] Terminal IN1 is connected to the gates of PMOS transistor 121 and NMOS transistor 123. Terminal IN2 is connected to the gates of PMOS transistor 122 and NMOS transistor 124.

[0089] Terminal VH is connected to the sources of PMOS transistor 121 and PMOS transistor 122. Terminal OUT is connected to the drains of PMOS transistor 121, PMOS transistor 122, and NMOS transistor 123.

[0090] Terminal VL is connected to the back gates of NMOS transistor 123, NMOS transistor 124, and the source of NMOS transistor 124. The source of NMOS transistor 123 is connected to the drain of NMOS transistor 124.

[0091] Here, when the voltage levels of terminal IN1 and terminal IN2 are both at the Hi level, the voltage level of terminal OUT becomes the Lo level, and in other cases, the voltage level of terminal OUT becomes the Hi level.

[0092] <Configuration examples of NOR circuits 91, 92, 93> FIG. 13 is a diagram showing an example of the configuration of a NOR circuit. NOR circuits 91, 92, 93 include terminal IN1, terminal IN2, terminal OUT, terminal VH (high potential side terminal), terminal VL (low potential side terminal), and MOS transistors 131, 132, 133. MOS transistors 131, 132, 133 are NMOS transistors, and MOS transistor 131 is a depletion type NMOS transistor.

[0093] Terminal IN1 is connected to the gate of NMOS transistor 132, and terminal IN2 is connected to the gate of NMOS transistor 133. Terminal VH is connected to the drain of NMOS transistor 131. Terminal OUT is connected to the source of NMOS transistor 131, the gate of NMOS transistor 131, the drain of NMOS transistor 132, and the drain of NMOS transistor 133. Terminal VL is connected to the sources of NMOS transistor 132 and NMOS transistor 133.

[0094] Here, when the voltage levels of the terminals IN1 and IN2 are both Lo level, the voltage level of the terminal OUT becomes Hi level, and in other cases the voltage level of the terminal OUT becomes Lo level.

[0095] <Configuration example of comparator 97> 14 is a diagram showing an example of the configuration of a comparator 97. The comparator 97 includes a terminal INP (non-inverting input terminal (+)), a terminal INN (inverting input terminal (-)), a terminal OUT, a terminal VH (high potential side terminal), a terminal VL (low potential side terminal), and MOS transistors 141, 142, 143, 144, 145, 146, 147, 148, and 149.

[0096] The MOS transistors 141, 142, 143, 144, and 145 are PMOS transistors. The MOS transistors 146, 147, 148, and 149 are NMOS transistors, and the MOS transistor 146 is a depletion-type NMOS transistor.

[0097] The terminal INP is connected to the gate of the PMOS transistor 145, and the terminal INN is connected to the gate of the PMOS transistor 144. The terminal VH is connected to the source of the PMOS transistor 141, the source of the PMOS transistor 142, the back gate of the PMOS transistor 142, the back gate of the PMOS transistor 144, the back gate of the PMOS transistor 145, and the source of the PMOS transistor 143.

[0098] The terminal VL is connected to the source of the NMOS transistor 146 , the source of the NMOS transistor 147 , the source of the NMOS transistor 148 and the source of the NMOS transistor 149 .

[0099] The drain of the PMOS transistor 141 is connected to the drain of the NMOS transistor 146 and the gate of the NMOS transistor 146. The gate of the PMOS transistor 141 is connected to the gate of the PMOS transistor 142 and the gate of the PMOS transistor 143.

[0100] The drain of PMOS transistor 142 is connected to the source of PMOS transistor 144 and the source of PMOS transistor 145. The drain of PMOS transistor 144 is connected to the drain of NMOS transistor 147, the gate of NMOS transistor 147, and the gate of NMOS transistor 148.

[0101] The drain of the PMOS transistor 145 is connected to the drain of the NMOS transistor 148 and the gate of the NMOS transistor 149. The terminal OUT is connected to the drain of the PMOS transistor 143 and the drain of the NMOS transistor 149.

[0102] Here, the voltage levels of the terminals INP and INM are compared, and if the voltage level of the terminal INP is higher, the voltage level of the terminal OUT becomes Hi level, otherwise the voltage level of the terminal OUT becomes Lo level.

[0103] <Configuration example of reference voltage circuit 98> 15 is a diagram showing an example of the configuration of a reference voltage circuit. The reference voltage circuit 98 includes a terminal OUT, a terminal VH (high potential terminal), a terminal VL (low potential terminal), MOS transistors 151 and 152, and resistors 153 and 154. The MOS transistors 151 and 152 are NMOS transistors, and the MOS transistor 151 is a depletion-type NMOS transistor.

[0104] The terminal VH is connected to the drain of the NMOS transistor 151. The gate of the NMOS transistor 151 is connected to the source of the NMOS transistor 151, the gate of the NMOS transistor 152, the drain of the NMOS transistor 152, and one end of the resistor 153. The terminal VL is connected to the source of the NMOS transistor 152 and one end of the resistor 154. The terminal OUT is connected to the other end of the resistor 153 and the other end of the resistor 154.

[0105] Here, the pinch-off voltage when the source current of the MOS transistor 151 flows to the MOS transistor 152 is divided by resistors 153 and 154 and the divided voltage is output to the terminal OUT. <Relationship between the driving signal of the switching element and the current flowing through the coil> Fig. 16 is a diagram showing an example of the relationship between the drive signals of the switching elements and the currents flowing through the coils. The diagram shows the period corresponding to time t0 to time t4 in Figs. 17 and 18, which will be described later. Three-phase AC currents, which are 120° out of phase with each other, flow through U-phase coil 301, V-phase coil 302, and W-phase coil 303 of motor 13, causing motor 13 to rotate.

[0106] In this case, in section T1, the upper arm drive signal Sinhu is input to the terminal INHU to drive the switching element 41 to perform switching, and in section T2, the lower arm drive signal Sinlu is input to the terminal INLU to drive the switching element 44 to perform switching.

[0107] In addition, in section T3, the upper arm drive signal Sinhv is input to the terminal INHV to switch the switching element 42, and in sections T4 and T5, the lower arm drive signal Sinlv is input to the terminal INLV to switch the switching element 45.

[0108] Furthermore, in section T6, the upper arm drive signal Sinhw is input to the terminal INHW to drive the switching element 43, and in section T7, the lower arm drive signal Sinlw is input to the terminal INLW to drive the switching element 46.

[0109] <Switching operation timing> 17 and 18 are diagrams showing an example of the timing during switching operation. FIG. 17 shows an example of a schematic diagram of the time changes in voltages and signals within semiconductor control device 21 when the U phase of semiconductor control device 21 is performing switching operation and the maximum value of the VB voltage of the U phase (VBU in the diagram) is lower than the withstand voltage between terminals VBU and COMH. Note that the "switching operation" of the U phase of semiconductor control device 21 refers to the turning on and off of switching element 44. Furthermore, if the current flowing through terminal NU is IU, the direction of flow from terminal NU to GND is positive. Furthermore, t0 to t4 is the section shown in FIG. 18.

[0110] At time t0, the signals input from the control unit 12 to the terminals INLU and INHU are at Lo level, and the switching elements 41 and 44 are in the off state. In addition, the current IU flowing through the U-phase coil 301 has a negative current value and flows from the terminal U to the terminal P via the FWD 51. Therefore, the potential VU of the terminal U is approximately equal to the potential Vp of the power supply 14.

[0111] At time t1, the control unit 12 raises the lower arm drive signal Sinlu input to the terminal INLU from Lo level to Hi level in order to turn on the switching element 44. When the switching element 44 turns on, the potential VU of the terminal U becomes equal to the potential of the grounded terminal NU, and the potential of VB (VBU) becomes approximately equal to the voltage Vcc of the power supply 11 via the resistor 22 and the diode 25.

[0112] At time t2, the control unit 12 lowers the lower arm drive signal Sinlu input to the terminal INLU from Hi level to Lo level to turn off the switching element 44. Therefore, the lower arm IGBT gate voltage (gate voltage of the switching element 44) in the figure is Hi level between time t1 and time t2.

[0113] When the switching element 44 is turned off, the potential VU of the terminal U becomes equal to the voltage Vp of the power supply 14, and the potential of VB (VBU) becomes equal to Vcc+Vp. Therefore, the maximum value of the U-phase VB voltage (VBU) is smaller than the withstand voltage between the terminal VBU and the terminal COMH (does not exceed the overvoltage level).

[0114] In this state, no current equivalent to the leakage current that flows when the upper arm control circuit is in an overvoltage state is input from terminal COMH to terminal COMH(L) of the lower arm control circuit 34. For this reason, the voltage of terminal COMH(L) does not exceed the voltage of the reference voltage circuit 98 (for example, 1 V), and the overvoltage detection level remains at 0 V.

[0115] On the other hand, Figure 18 shows an example of an outline of the time changes in voltages and signals within the semiconductor control device 21 when the U phase of the semiconductor control device 21 is switching and the maximum value of the VB voltage (VBU) of the U phase is greater than the withstand voltage between terminal VBU and terminal COMH.

[0116] The period from time t0 to time t1 is the same as in Figure 17. At time t2, when the lower arm drive signal Sinlu falls to the Lo level, the current IU decreases and the voltage VBU (the voltage at terminal VBU) increases. When the current IU is 0 and the voltage VBU approaches Vp, the current flowing through the U-phase coil 301 connected to terminal U starts to flow to terminal P via FWD51. Immediately after the current starts to flow through FWD51, the dynamic resistance of FWD51 is large, and therefore the voltages VU and VBU become larger than the voltage Vp.

[0117] At time t3, when the voltage VBU exceeds the withstand voltage between terminal VBU and terminal COMH of the upper arm control circuit 31 (exceeds the overvoltage level), a current (leakage current IL1) is input from terminal COMH to terminal COMH(L) of the lower arm control circuit 34.

[0118] The lower arm control circuit 34 converts the current input to the terminal COMH(L) into a voltage using a resistor 99, and when the voltage of the terminal COMH(L) becomes greater than the voltage of the reference voltage circuit 98 (for example, 1 V (when the overvoltage detection level exceeds a predetermined level)), the terminals OUTLU, OUTLV, and OUTLW output a Hi-level signal.

[0119] The high-level signals output from the terminals OUTLU, OUTLV, and OUTLW correspond to the high-level signals output from the lower-arm IGBT gate voltages from time t3 to time t4 in the figure. These high-level signals have the level of the threshold voltages of the switching elements 44, 45, and 46.

[0120] When the signal at terminal OUTLU becomes Hi level, switching element 44 turns on and voltage VBU is clamped to be equal to the withstand voltage between terminal VBU and terminal COMH. This limits the leakage current flowing between terminal VBU and terminal COMH, eliminates the overvoltage state of upper-arm control circuit 31, and prevents destruction of upper-arm control circuit 31.

[0121] Then, at time t4, when the dynamic resistance of the FWD 51 decreases, the voltage VBU decreases from the overvoltage level, and the voltage VU becomes approximately equal to the voltage Vp. In this way, in the semiconductor control device 21, when a voltage greater than the withstand voltage is applied between the terminal VB (terminal VBU of the upper arm control circuit 31 of the U phase in the examples of Figures 17 and 18) and the terminal COMH of the upper arm control circuits 31, 32, 33, the lower arm switching elements 44, 45, 46 are turned on to limit the VB voltage, thereby protecting the upper arm control circuits 31, 32, 33 from excessive voltage.

[0122] <Structure of upper arm control circuit 31> FIG. 19 is a diagram showing an example of a cross-sectional structure of a main part of an upper arm control circuit. (Structure of low-voltage p-MOS MOS transistor 111) An n-well 202 is formed on the surface of a P-type substrate 201, and a gate oxide film 211 and a gate electrode 212 are laminated on the n-well 202. Using the gate oxide film 211 and the gate electrode 212 as a mask, ion implantation is performed to form a P + Layer 203 is formed to serve as the drain and source electrodes.

[0123] (Structure of low-voltage n-MOS transistors 102 and 112) A gate oxide film 211 and a gate electrode 212 are laminated on a P-type substrate 201. Using the gate oxide film 211 and the gate electrode 212 as a mask, n-type electrodes are formed by ion implantation. + Layer 204 is formed to serve as the drain and source electrodes.

[0124] (Structure of high-voltage n-MOS transistors 64 and 65) A high-voltage n-well 205 is formed on the surface of a P-type substrate 201, and a gate oxide film 211, an insulating oxide film 213, and a gate electrode 212 are laminated on the high-voltage n-well 205. The gate oxide film 211, the insulating oxide film 213, and the gate electrode 212 are used as masks to form an n-type n-well 205 by ion implantation. + A layer 204 is formed to serve as the drain and source electrodes. The drain electrode of the MOS transistor 64 is connected to the terminal S, and the drain electrode of the MOS transistor 65 is connected to the terminal R.

[0125] (Structure of low-voltage p-MOS transistors 121 and 122) A high-voltage n-well 206 is formed on the surface of a P-type substrate 201, and a gate oxide film 211 and a gate electrode 212 are laminated on the high-voltage n-well 206. Using the gate oxide film 211 and the gate electrode 212 as a mask, P + Layer 203 is formed to serve as the drain and source electrodes.

[0126] (Structure of low-voltage n-MOS transistors 123 and 124) A high-voltage n-well 206 is formed on the surface of a P-type substrate 201, and a p-well 207 is formed on the surface of the high-voltage n-well 206. A gate oxide film 211 and a gate electrode 212 are stacked on the p-well 207, and an n-well 207 is formed by ion implantation using the gate oxide film 211 and the gate electrode 212 as a mask. + Layer 204 is formed to serve as the drain and source electrodes.

[0127] (Structure of resistors 62 and 63) An insulating oxide film 213 is laminated on a P-type substrate 201, and a resistive polysilicon film 214 is laminated on the insulating oxide film 213 to form a polysilicon resistor. One end of the resistor is connected to terminal VB via an AlSi (aluminum silicon alloy) layer, and is also connected to terminals S and R.

[0128] Here, when a voltage exceeding the withstand voltage of high-voltage n-well 206 formed in P-type substrate 201 is applied to the upper-arm control circuit, leakage current IL1 flows from terminal VB (corresponding to terminal VBU in the case of U-phase upper-arm control circuit 31) joined to high-voltage n-well 206 toward terminal COMH joined to P-type substrate 201. Terminal VB (first terminal) is a terminal to which a floating high-potential drive power supply voltage (VB voltage) is applied, and terminal COMH (second terminal) is a terminal connected to the ground potential.

[0129] <Mounting structure of semiconductor control device 21> 20 is a diagram showing an example of a mounting structure of the control device. The upper arm control circuit 31 is connected to the terminals VBU, VSU, VCCHU, and INHU via a wire group wp1 that includes four wires each. The upper arm control circuit 32 is connected to the terminals VBV, VSV, VCCHV, and INHV via a wire group wp2 that includes four wires each.

[0130] The upper arm control circuit 33 is connected to the terminals VBW, VSW, VCCHW, and INHW via a wire group wp3 that includes four wires each, and the lower arm control circuit 34 is connected to the terminals COM, VCCL, INLU, INLV, and INLW via a wire group wp4 that includes five wires each.

[0131] The upper arm control circuit 31 is connected to the emitter of the IGBT 41 via a VS wire wvsu and to the gate of the IGBT 41 via a gate wire wg1. The upper arm control circuit 32 is connected to the emitter of the IGBT 42 via a VS wire wvsv and to the gate of the IGBT 42 via a gate wire wg2. The upper arm control circuit 33 is connected to the emitter of the IGBT 43 via a VS wire wvsw and to the gate of the IGBT 43 via a gate wire wg3.

[0132] The lower arm control circuit 34 is connected to the gate of the IGBT 44 via a gate wire wg4, to the gate of the IGBT 45 via a gate wire wg5, and to the gate of the IGBT 46 via a gate wire wg6.

[0133] The emitter of IGBT41 is connected to the anode of FWD51 via a wire w5, the emitter of IGBT42 is connected to the anode of FWD52 via a wire w6, and the emitter of IGBT43 is connected to the anode of FWD53 via a wire w7.

[0134] The emitter of the IGBT 44 is connected to the anode of the FWD 54 via a wire w8, the emitter of the IGBT 45 is connected to the anode of the FWD 55 via a wire w9, and the emitter of the IGBT 46 is connected to the anode of the FWD 56 via a wire w10.

[0135] The anode of FWD51 is connected to terminal U via wire w11, the anode of FWD52 is connected to terminal V via wire w12, and the anode of FWD53 is connected to terminal W via wire w13.

[0136] The anode of FWD54 is connected to the terminal NU via a wire w14, the anode of FWD55 is connected to the terminal NV via a wire w15, and the anode of FWD56 is connected to the terminal NW via a wire w16.

[0137] The cathodes of FWDs 51, 52, and 53 are joined to terminal P through patterns on the back surface of the chip. The cathode of FWD 54 is joined to terminal U through frame (lead frame) f1, the cathode of FWD 55 is joined to terminal V through frame f2, and the cathode of FWD 56 is joined to terminal W through frame f3.

[0138] Here, the terminals COMH of the upper arm control circuits 31, 32, and 33 are connected to a frame f0 divided for the lower arm control circuit 34. In Fig. 20, they are connected by wires w1, w2, and w3 (COMH wires) (alternatively, the back surfaces of the chips of the upper arm control circuits 31, 32, and 33 may be bonded with a conductive material). The frame f0 is then connected to the terminal COMH(L) of the lower arm control circuit 34 by a wire w4 (COMH wire).

[0139] As described above, in the semiconductor device of the present invention, the upper-arm control circuit controls the drive of the upper-arm switching element using a drive power supply voltage between a floating high-potential drive power supply voltage and a low-potential drive power supply voltage, the overvoltage detection circuit detects an overvoltage state of the upper-arm control circuit based on leakage current flowing from the floating potential of the upper-arm control circuit to ground, and the lower-arm control circuit is configured to turn on the lower-arm switching element to reduce the drive power supply voltage of the upper-arm control circuit when it receives an overvoltage detection signal.

[0140] In this way, when the HVIC is in an overvoltage state, leakage current flowing from the floating potential of the HVIC to the ground potential is detected, and when the leakage current exceeds a reference value, the switching element of the lower arm is turned on, thereby reducing the voltage applied to the upper arm control circuit.

[0141] This makes it possible to protect the HVIC from destruction even when a positive surge voltage larger than the withstand voltage is applied to terminals U, V, and W. It also eliminates the need for a structural design that makes the withstand voltage of the upper arm control circuit higher than the withstand voltage of the switching element (e.g., IGBT).

[0142] Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Furthermore, various modifications and improvements can be made to the above embodiments. Furthermore, the technical scope of the present invention may include forms in which modifications or improvements have been made and their equivalents without departing from the spirit of the present invention. [Explanation of symbols]

[0143] 10 Semiconductor device V1, V2 power supply 1H Upper arm control circuit (HVIC) 1L Lower arm control circuit (LVIC) sw1 upper arm switching element sw2 Lower arm switching element L0 load R0 resistance D0 diode D1, D2 diodes C0 capacitor 1oc overvoltage detection circuit d1 Overvoltage detection signal IL1 Leakage current sH Upper arm drive signal sL Lower arm drive signal 1. Inverter device 11, 14 Power supply 12 Control Unit 13 Motor 21a Semiconductor driver 21 Semiconductor control device 22, 23, 24 Resistor 25, 26, 27 Diodes 28, 29, 30 Capacitors Sinhu, Sinhv, Sinhw Upper arm drive signal on the high side Sinlu, Sinlv, Sinlw Low-side lower arm drive signals 31, 32, 33 Upper arm control circuit 34 Lower arm control circuit 41, 42, 43, 44, 45, 46 Switching elements 51, 52, 53, 54, 55, 56 FWD 301 U-phase coil 302 V-phase coil 303 W-phase coil IU Current flowing through the U-phase coil IV Current flowing through V-phase coil IW Current flowing through the W-phase coil 61 Control circuit 62, 63 Resistor 64, 65 N-channel MOS transistor 66 Drive circuit 71, 72, 75, 78 Inverter circuit 73, 76 Resistance 74, 77 Capacitors 81, 82 NAND circuit 91, 92, 93 NOR circuit 94, 95, 96 Inverter circuit 97 Comparator 98 Reference Voltage Circuit 99 Resistance 101 Depletion-type MOS transistor 102 N-channel MOS transistor 111 P-channel MOS transistor 112 N-channel MOS transistor 121, 122 P-channel MOS transistor 123, 124 N-channel MOS transistor 131 Depletion-type MOS transistor 132, 133 N-channel MOS transistor 141, 142, 143, 144, 145 P-channel MOS transistor 146 Depletion-type MOS transistor 147, 148, 149 N-channel MOS transistor 151 Depletion-type MOS transistor 152 N-channel MOS transistor 153, 154 Resistance 201 P type board 202 n-well 203 P + layer 204n + layer 205, 206 High voltage n-well 207 p-well 211 Gate oxide 212 gate electrode 213 Insulating oxide film 214 Resistive polysilicon film wp1, wp2, wp3, wp4 wire group wvsu, wvsv, wvsw VS wire wg1, wg2, wg3, wg4, wg5, wg6 gate wires w1, w2, w3, w4 COMH wire w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16 wires f0, f1, f2, f3 frames

Claims

1. an upper arm control circuit that controls the drive of the upper arm switching element based on an upper arm drive signal transmitted from the control unit; an overvoltage detection circuit that detects an overvoltage state of the upper arm control circuit and outputs an overvoltage detection signal; a lower arm control circuit that controls the driving of a lower arm switching element connected in series to the upper arm switching element based on a lower arm driving signal or the overvoltage detection signal transmitted from the control unit; A semiconductor device having:

2. 2. The semiconductor device according to claim 1, wherein said overvoltage detection circuit detects said overvoltage state of said upper arm control circuit based on a leakage current flowing from a floating potential of said upper arm control circuit to a ground potential.

3. 3. The semiconductor device according to claim 2, wherein said lower arm control circuit turns on said lower arm switching element when said overvoltage detection signal is received.

4. 3. The semiconductor device according to claim 2, wherein the overvoltage detection circuit comprises: a resistor that converts the leakage current into a voltage signal; a reference voltage circuit that outputs a reference voltage; and a comparator that compares the voltage signal with the reference voltage and, if the voltage signal is equal to or greater than the reference voltage, detects the overvoltage state of the upper arm control circuit and outputs the overvoltage detection signal.

5. the upper arm control circuit controls the drive of the upper arm switching element using a drive power supply voltage between a high potential side drive power supply voltage and a low potential side drive power supply voltage of the floating potential; a first diode is connected in anti-parallel to the upper arm switching element, and a second diode is connected in anti-parallel to the lower arm switching element; a first high potential terminal of the upper arm switching element is connected to a high potential side power supply terminal that is connected to the cathode of the first diode and the positive terminal of a power supply; a first low potential terminal of the upper arm switching element is connected to a low potential side drive power supply terminal to which the low potential side drive power supply voltage is applied, an output terminal connected to a load, an anode of the first diode, a second high potential terminal of the lower arm switching element, and a cathode of the second diode; a second low potential terminal of the lower arm switching element is connected to the anode of the second diode, the negative terminal of the power supply, and a low potential side power supply terminal connected to the ground potential; When the lower arm control circuit turns on the lower arm switching element based on the overvoltage detection signal, the low potential side drive power supply terminal is connected to the low potential side power supply terminal, and the drive power supply voltage drops.

4. The semiconductor device according to claim 3.

6. the lower arm control circuit includes a two-input, one-output NOR circuit and an inverter circuit; 6. The semiconductor device according to claim 5, wherein the overvoltage detection signal is input to a first input terminal of the NOR circuit, the lower arm drive signal is input to a second input terminal of the NOR circuit, the output terminal of the NOR circuit is connected to an input terminal of the inverter circuit, and the output terminal of the inverter circuit is connected to a gate of the lower arm switching element.

7. 6. The semiconductor device according to claim 5, wherein the leakage current is a current that flows from a first terminal connected to the n-well and to which the high-potential side drive power supply voltage of the floating potential is applied to a second terminal connected to the P-type substrate and connected to the ground potential when the drive power supply voltage applied to the upper arm control circuit exceeds a breakdown voltage of an n-well formed in a P-type substrate.

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