Semiconductor device

Abstract

To enable cascode connection by using a high-pressure element with a low gate breakdown voltage, improve the breakdown voltage, and prevent malfunction due to a walk-out current.SOLUTION: A semiconductor device 100 includes: a cascode connection part 110 including a first semiconductor element 101, a second semiconductor element 102, a first resistor 111, a first Zener diode 112, and a first high-voltage diode 115; and an erroneous ON prevention circuit 120. The cascode connection part 110 is configured such that a drain of the first semiconductor element 101 and a source of the second semiconductor element 102 are cascode-connected, the first resistor 111 and the first Zener diode 112 are connected between the gate and the source of the second semiconductor element 102, and the first high-voltage diode 115 is connected between the gate of the first semiconductor element 101 and the gate of the second semiconductor element 102. The erroneous ON prevention circuit 120 prevents malfunction due to a walk-out current in the cascode connection part 110.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A typical motor that is driven by switching the current flowing through a coil uses a drive circuit (semiconductor device) that includes a semiconductor switching element (such as an insulated-gate bipolar transistor (IGBT)). Another example of a semiconductor device is a power conversion device in which a group of inverter devices for one phase is formed by connecting a plurality of single-phase inverter devices in series, and these are then combined into, for example, three phases to form a three-phase inverter system.

[0003] Such inverter systems use a gate drive circuit (gate driver) that inputs logic pulses to drive the gates of the next stage. The semiconductor devices used in these gate drivers require some of their transistors to be high-voltage transistors.

[0004] Patent Document 1 describes a level shift circuit that includes a means for transmitting a drive signal to a control terminal of a semiconductor element.

[0005] Figure 10 is a diagram showing the circuit configuration of a MOS (Metal-Oxide-Semiconductor) gate driver IC (semiconductor device) that includes high-voltage transistors. Figure 10 shows the U-phase as a representative of the three-phase control signals U, V, and W, and also shows the upper arm driver circuit. In the following figures, circled transistors indicate high-voltage transistors, while uncircled ones indicate low-voltage transistors. The MOS gate driver IC shown in FIG. 10 includes a reference power supply terminal 1, a low-voltage power supply terminal 2, a U-phase control input terminal (hereinafter referred to as the input terminal) 3 for inputting a U-phase control input signal IN, a U-phase upper arm drive circuit power supply terminal (BU) 7, a U-phase upper arm gate drive output terminal (PGU) 8, and a reference terminal (U) 9 for the U-phase upper arm output.

[0006] The reference power supply terminal 1 is a terminal of reference potential, which is GND potential in this case. The low-voltage power supply terminal 2 is a terminal of a low-voltage power supply of about 15 V. The U-phase control input terminal 3 receives an input signal IN from a low-voltage control unit (microcomputer) not shown. The U-phase upper arm drive circuit power supply terminal (BU) 7, the U-phase upper arm gate drive output terminal (PGU) 8, and the U-phase upper arm output reference terminal (U) 9 are high-voltage terminals.

[0007] 10 includes a pre-driver circuit (low-voltage circuit) 4, a high-voltage NMOS 5, a level shift circuit 10, and an upper arm driver circuit 30. The high-voltage NMOS 5 forms a high-voltage element section 20 (enclosed by a dashed line in FIG. 10). The low-voltage circuit 4 drives the high-voltage NMOS 5. The level shift circuit 10 includes a protection circuit made up of a Zener diode (VZ) 11 and a resistor 12, a buffer 13, and a diode 14. The high potential side of level shift circuit 10 is connected to U-phase upper arm drive circuit power supply terminal (BU) 7. The output of level shift circuit 10 is connected to upper arm drive circuit 30, and is connected via upper arm drive circuit 30 to U-phase upper arm gate drive output terminal (PGU) 8. The output of level shift circuit 10 is also connected to U-phase upper arm output reference terminal (U) 9 via backflow prevention diode 14, without passing through upper arm drive circuit 30.

[0008] 10, the high-voltage side includes U-phase upper arm driver circuit power supply terminal (BU) 7, U-phase upper arm gate drive output terminal (PGU) 8, U-phase upper arm output reference terminal (U) 9, upper arm driver circuit 30, and level shift circuit 10. For this reason, a high-voltage NMOS 5 is used in high-voltage element section 20 to improve breakdown voltage. In particular, in a pre-driver IC using dielectric isolation technology, when ESD (Electrostatic Discharge) occurs, destruction occurs in the high-voltage NMOS 5 where the ESD is concentrated. For example, as shown in box a in Figure 10, the ESD voltage concentrates in one place in the high-voltage element section 20, causing destruction of the high-voltage NMOS 5. Here, the ESD tolerance of the high-voltage NMOS 5 is determined by its withstand voltage.

[0009] FIG. 11 is a diagram showing a circuit configuration of a gate driver IC (semiconductor device) in the case where the high-voltage elements having low gate withstand voltages shown in FIG. 10 are cascode-connected (vertical stacked). The MOS gate driver IC shown in Fig. 11 includes a high-voltage element section 21 in which high-voltage NMOS5 and high-voltage NMOS6, which are high-voltage elements with low gate breakdown voltage, are cascode-connected. The cascode connection in which the high-voltage NMOS5 is source-grounded has the advantage of high low-frequency gain and large output resistance. In addition, the high-voltage NMOS5 and high-voltage NMOS6 can be capacitively divided.

[0010] When high-voltage elements (high-voltage NMOS5 and high-voltage NMOS6) with low gate withstand voltage are cascode-connected to improve withstand voltage, there is a concern that the gate may be destroyed due to the low gate withstand voltage. For example, in the MOS gate driver IC shown in Figure 11, when the voltage at the U-phase upper arm drive circuit power supply terminal (BU) 7 rises from 0V to 600V, the potential between the cascode-connected high-voltage NMOS5 and high-voltage NMOS6 rises from 0V to approximately 300V, even with capacitive voltage division (symbol b in Figure 11). The gates of the high-voltage elements (high-voltage NMOS5 and high-voltage NMOS6, especially the high-voltage NMOS6 on the high-potential side) with low gate withstand voltage will be destroyed due to their withstand voltage of 20V (symbol c in Figure 11). [Prior art documents] [Patent documents]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 3-021114 Summary of the Invention [Problem to be solved by the invention]

[0012] As mentioned above, it is known that ESD voltage concentrates on the high-voltage elements in the gate driver IC shown in Figure 10, and for this reason the ESD tolerance of the high-voltage elements is fixed. However, in pre-driver ICs using dielectric isolation technology, unless effective measures such as using high-voltage transistors are taken, breakdown occurs in the high-voltage NMOS where ESD concentrates. Furthermore, in the gate driver IC of FIG. 11, when a high-voltage element with a low gate withstand voltage is cascode-connected, the gate will be destroyed when a high voltage is applied, just as in the case of FIG. Furthermore, the unstable characteristics caused by the walkout phenomenon may cause a walkout current to flow, causing the cascode-connected high-voltage NMOS to malfunction (see below).

[0013] The present invention has been made in view of the above circumstances, and aims to provide a semiconductor device that enables cascode connection using high-voltage elements with low gate breakdown voltage, thereby improving breakdown voltage and preventing malfunction due to walk-out current. [Means for solving the problem]

[0014] In order to solve the above problem, the semiconductor device of the present invention comprises a cascode connection portion including a first semiconductor element, a second semiconductor element, a first resistor, a first Zener diode, and a first high-voltage diode, and an erroneous ON prevention circuit, wherein the cascode connection portion is configured such that the drain of the first semiconductor element and the source of the second semiconductor element are cascode-connected, the first resistor and the first Zener diode are connected between the gate and source of the second semiconductor element, and the first high-voltage diode is connected between the gate of the first semiconductor element and the gate of the second semiconductor element, and the erroneous ON prevention circuit is a circuit that prevents malfunction due to walk-out current in the cascode connection portion. [Effects of the Invention]

[0015] According to the present invention, a cascode connection is possible using a high-voltage element with a low gate breakdown voltage, thereby improving the breakdown voltage and preventing malfunction due to walk-out current. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a diagram showing a circuit configuration of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a diagram showing a detailed circuit configuration of a mistaken ON prevention circuit of a semiconductor device according to an embodiment of the present invention; FIG. [Figure 3] 1 is a circuit diagram of an inverter device including a gate driver having a semiconductor device according to an embodiment of the present invention. [Figure 4] 10 is a diagram showing, as a comparative example, the circuit configuration of a semiconductor device that does not include the erroneous ON prevention circuit of the semiconductor device according to the embodiment of the present invention. FIG. [Figure 5] 10A and 10B are diagrams illustrating the operation state during a transition immediately after a signal of H is input to the input IN of the semiconductor device according to the embodiment of the present invention. [Figure 6] 6 is a diagram illustrating the operation state after FIG. 5. FIG. [Figure 7] 10A and 10B are diagrams illustrating the operation state during a transition immediately after an L signal is input to the input IN of the semiconductor device according to the embodiment of the present invention. [Figure 8] 3A and 3B are diagrams illustrating an operating state of the erroneous ON prevention circuit of the semiconductor device according to the embodiment of the present invention. [Figure 9] 8 is a diagram illustrating a state after the operation of the erroneous ON prevention circuit in FIG. 7. FIG. [Figure 10] FIG. 1 is a diagram showing the circuit configuration of a conventional MOS gate driver IC including a high-voltage transistor. [Figure 11] 11 is a diagram showing a circuit configuration of a gate driver IC in the case where the high-voltage elements in FIG. 10 having low gate withstand voltages are cascode-connected. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Embodiment) Fig. 1 is a diagram showing the circuit configuration of a semiconductor device according to an embodiment of the present invention. Components that are the same as those in Fig. 11 are given the same reference numerals. The semiconductor device of this embodiment is an example applied to a three-phase IGBT / MOS gate driver IC. The upper arm driver circuit of the U phase is taken as an example. The semiconductor device 100 includes a pre-driver circuit 4, a cascode connection unit 110 (enclosed by a dashed line in FIG. 1), a false-ON prevention circuit 120, a level shift circuit 10, and an upper arm drive circuit 30.

[0018] <Cascode connection part 110> The cascode connection unit 110 includes a first semiconductor element 101 (HVNM1), a second semiconductor element 102 (HVNM2), a first resistor 111 (R1), a first Zener diode 112 (VZ1), and a first high-voltage diode 115. The cascode connection section 110 connects the drain of the first semiconductor element 101 (HVNM1) to the source of the second semiconductor element 102 (HVNM2), connects a first resistor 111 (R1) and a first Zener diode 112 (VZ1) between the gate and source of the second semiconductor element 102 (HVNM2), and connects a first high-voltage diode 115 (HVDd1) between the gate of the first semiconductor element 101 (HVNM1) and the gate of the second semiconductor element 102 (HVNM2).

[0019] The drain of the first semiconductor element 101 (HVNM1) and the source of the second semiconductor element 102 (HVNM2) are at the HVNM1-2 intermediate potential 117. A first resistor 111 (R1) and a first Zener diode 112 (VZ1) connect this HVNM1-2 intermediate potential 117 and the gate of the second semiconductor element 102 (HVNM2).

[0020] The cascode connection unit 110 increases the breakdown resistance by cascode-connecting the areas where ESD voltage concentrates, and even when the first semiconductor element 101 (HVNM1) and the second semiconductor element 102 (HVNM2), which are high-voltage elements with low gate breakdown voltages, are cascode-connected, by adding the first high-voltage diode 115, the first resistor 111 (R1), and the first Zener diode (VZ1) 112 between the gates with low breakdown voltages, it is possible to prevent breakdown of the gates when high voltage is applied.

[0021] A pre-driver circuit (low-voltage circuit) 4 drives a first semiconductor element 101 (HVNM1) and a second semiconductor element 102 (HVNM2) that are cascode-connected.

[0022] The level shift circuit 10 includes a protection circuit consisting of a Zener diode (VZ) 11 and a resistor (R2) 12, a buffer (Buffer1) 13, and a diode 14. The level shift circuit 10 operates by passing a current through a first semiconductor element 101 (HVNM1) and a second semiconductor element 102 (HVNM2). The high potential side of level shift circuit 10 is connected to U-phase upper arm drive circuit power supply terminal (BU) 7. The output of level shift circuit 10 is connected to upper arm drive circuit 30, and is connected via upper arm drive circuit 30 to U-phase upper arm gate drive output terminal (PGU) 8. The output of level shift circuit 10 is also connected to U9 via backflow prevention diode 14, without passing through upper arm drive circuit 30.

[0023] <Error ON prevention circuit 120> The false-ON prevention circuit 120 is provided in parallel with the cascode connection section 110, and prevents the upper arm driver circuit 30 from false-ON operation when a walk-out current occurs in the cascode connection section 110.

[0024] FIG. 2 is a diagram showing a detailed circuit configuration of the erroneous ON prevention circuit 120 of the semiconductor device 100 of FIG. As shown in FIG. 2, the false-ON prevention circuit 120 includes a third semiconductor element 103 (HVNM3), a fourth semiconductor element 104 (HVNM4), a second resistor 113 (R3), a second Zener diode (VZ2) 114, a second high-voltage diode 116 (HVDd2), an inverter (NOT1) 15 that inverts the output of the pre-driver circuit (low-withstand voltage circuit) 4, a fifth semiconductor element 121 (MP1), a second Zener diode (VZ2) 122, a resistor 123 (R4), and the fifth semiconductor element 121 (MP1).

[0025] The false-ON prevention circuit 120 connects the drain of the third semiconductor element 103 (HVNM3) and the source of the fourth semiconductor element 104 (HVNM4), connects a second resistor 113 (R3) and a second Zener diode (VZ2) 114 between the gate and source of the fourth semiconductor element 104 (HVNM4), and connects a second high-voltage diode 116 (HVDd2) between the gate of the third semiconductor element 103 (HVNM3) and the gate of the fourth semiconductor element 104 (HVNM4).

[0026] An inverter (NOT1) 15 inverts the output of the pre-driver circuit 4 and drives a third semiconductor element 103 (HVNM3) and a fourth semiconductor element 104 (HVNM4) that are cascode-connected.

[0027] The source of the fifth semiconductor element 121 (MP1) is connected to the U-phase upper arm drive circuit power supply terminal (BU) 7, and the drain of the fifth semiconductor element 121 (MP1) is connected to the upper arm drive circuit 30 via a buffer (Buffer1) 13. The second Zener diode 122 (VZ2) and resistor 123 (R4) have their high potential sides connected to the U-phase upper arm drive circuit power supply terminal (BU) 7 and their low potential sides connected to the drain of the fourth semiconductor element 104 (HVNM4) and the gate of the fifth semiconductor element 121 (MP1).

[0028] When a current flows through the third semiconductor element 103 (HVNM3) and the fourth semiconductor element 104 (HVNM4), the gate potential of the fifth semiconductor element 121 (MP1) drops and the fifth semiconductor element 121 (MP1) turns ON. That is, when the third semiconductor element 103 (HVNM3) and the fourth semiconductor element 104 (HVNM4) are ON, the fifth semiconductor element 121 (MP1) turns ON to prevent a signal from being transmitted from the cascode connection unit 110 to the output stage (here, the buffer (Buffer1) 13).

[0029] The circuit section of the cascode connection section 110, which includes the first semiconductor element 101 (HVNM1), the second semiconductor element 102 (HVNM2), the first resistor 111 (R1), the first Zener diode (VZ1) 112, and the first high-voltage diode 115, and the circuit section of the false-ON prevention circuit 120, which includes the third semiconductor element 103 (HVNM3), the fourth semiconductor element 104 (HVNM4), the second resistor 113 (R3), the second Zener diode (VZ2) 114, and the second high-voltage diode 116 (HVDd2), are configured in a mirror configuration, and the characteristics are aligned at the transistor level. This aligns the operation timing of the false-ON prevention circuit 120 with the operation timing of the cascode connection section 110, thereby ensuring stable switching operation.

[0030] FIG. 3 is a circuit diagram of an inverter device 200 including a gate driver 220 having the semiconductor device 100 of FIGS. The inverter device 200 includes a control unit 210, a gate driver 220 having the semiconductor device 100, an inverter circuit 230 that drives the motor M, and the motor M itself. The inverter device 200 is connected to a DC power supply Vs and is connected to the motor M by three phases, namely, U-phase wiring, V-phase wiring, and W-phase wiring. The inverter device 200 applies a drive voltage to the motor M to control the rotation of the motor M. The motor M is a three-phase brushless DC motor and includes coils Lu, Lv, and Lw for each phase and a rotor (not shown). One end of these coils Lu, Lv, and Lw is Y-connected. The other ends of the coils Lu, Lv, and Lw are connected to the U-phase output, V-phase output, and W-phase output of the inverter circuit 230, respectively. The inverter circuit 230 supplies drive currents to the U-phase, V-phase, and W-phase coils Lu, Lv, and Lw of the motor M to rotate the rotor.

[0031] The inverter circuit 230 has a U-phase switching leg in which switching elements Q1 and Q2 are connected in series, a V-phase switching leg in which switching elements Q3 and Q4 are connected in series, and a W-phase switching leg in which switching elements Q5 and Q6 are connected in series. The inverter circuit 230 is connected to a DC power supply Vs and is further connected to a resistor Rs.

[0032] The U-phase, V-phase, and W-phase switching legs each include upper-arm switching elements Q1, Q3, and Q5, and lower-arm switching elements Q2, Q4, and Q6. The emitter terminals of the switching elements Q1, Q3, and Q5 are connected to the positive pole of the DC power supply Vs. The emitter terminals of the switching elements Q1, Q3, and Q5 are connected to the collector terminals of the switching elements Q2, Q4, and Q6, respectively, and AC signals of the U-phase, V-phase, and W-phase are output from the connection points. The collector terminals of the switching elements Q2, Q4, and Q6 are connected to ground (the negative pole of the DC power supply Vs) via resistors Rs. The gate terminals of the switching elements Q1 to Q6 are connected to the gate driver 220.

[0033] The inverter circuit 230 receives power from the DC power supply Vs, and when a drive signal is input from the gate driver 220, it passes three-phase AC current through the U-phase wiring, V-phase wiring, and W-phase wiring of the motor M. Gate driver 220 (part of the motor drive unit) constitutes the motor drive unit in combination with inverter circuit 230 connected thereto, and is connected to control unit 210. Gate driver 220 includes semiconductor device 100 shown in Fig. 4, and U-phase upper arm gate drive output terminal (PGU) 8 of upper arm drive circuit 30 of semiconductor device 100 is connected to switching elements Q1, Q3, and Q5 on the upper arm side (the same applies to the lower arm, not shown).

[0034] The control unit 210 includes, for example, a rotational position calculation unit, a rotational speed calculation unit, a current supply timing adjustment unit, a current supply signal generation unit (all not shown), etc., and is included in a microprocessor. Note that each unit may be realized by software, and its function may be virtually represented.

[0035] The operation of the semiconductor device 100 configured as described above will now be described. First, the reason why the semiconductor device 100 includes the erroneous ON prevention circuit 120 in addition to the cascode connection section 110 will be described. 4 is a diagram showing, as a comparative example, the circuit configuration of a semiconductor device 90 that does not include the erroneous ON prevention circuit 120 (FIGS. 1 and 2). The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. The semiconductor device 90 of the comparative example shown in FIG. 4 has a configuration in which the erroneous ON prevention circuit 120 is removed from the semiconductor device 100 shown in FIG. 4 , even when the first semiconductor element 101 (HVNM1) is turned off and the HVNM1-2 intermediate potential 117 rises, the semiconductor device 90 of the comparative example can lower the gate voltage of the second semiconductor element 102 (HVNM2) to the same potential as the HVNM1-2 intermediate potential 117 and turn off the second semiconductor element 102 (HVNM2). This prevents gate breakdown, enables cascode connection, and improves the breakdown voltage while using high-voltage elements (the first semiconductor element 101 (HVNM1) and the second semiconductor element 102 (HVNM2)) with low gate breakdown voltages. However, there are concerns about malfunctions such as those described below.

[0036] In the semiconductor device 90 of the comparative example shown in FIG. 4, even if the highest voltage (600 V) of the device limit is applied to BU7, only the voltage for the cascode connection (300 V in the case of two stages) can be applied to the cascode-connected high-voltage NMOS, and a voltage up to the walkout occurrence voltage (about 500 V) cannot be applied, which may result in malfunction due to walkout current.

[0037] The walkout phenomenon will be briefly described. In order to suppress the decrease in breakdown voltage at the periphery of the element portion (cell) of a semiconductor device, there is a fabrication method in which the channel region is formed wider than the end of the gate trench to the periphery outside. This fabrication method is prone to the walk-out and walk-in phenomena. Here, the walk-out phenomenon refers to a phenomenon in which, for example, the drain-source breakdown voltage (BVDSS) characteristics are unstable in the first measurement, but normal characteristics are observed from the second measurement onwards (repeated remeasurements). The walk-out current is a current that causes a cascode-connected high-voltage NMOS to malfunction due to the unstable characteristics caused by the walk-out phenomenon.

[0038] Malfunctions due to walk-out current will now be described in detail. As shown by the symbol aa in FIG. 4, (1) when IN=L, a voltage of 600 V is applied to BU7. (2) At this time, only about 0 to 300 V is applied between the first semiconductor element 101 (HVNM1) and the second semiconductor element 102 (HVNM2) due to capacitive voltage division. (3) When IN=H→L is input, the first semiconductor element 101 (HVNM1), which is the lower high-voltage NMOS, turns OFF, and at this point a voltage of 600V is applied to the first semiconductor element 101 (HVNM1), which is the lower high-voltage NMOS, for the first time (symbol bb in Figure 4), and at this time a walk-out current flows (symbol cc in Figure 4). (4) The walk-out current and the voltage drop across R2 (symbol dd in FIG. 4) cause the buffer (Buffer1) 13 to react, and the upper arm driver circuit 30 is erroneously turned on. (5) The upper arm drive circuit 30 is erroneously turned on, causing the PGU8 to be erroneously turned on (symbol ee in FIG. 4).

[0039] The semiconductor device 100 (FIGS. 1 and 2) of this embodiment adds a false-ON prevention circuit 120 that prevents malfunction due to a walk-out current to the semiconductor device 90 shown in FIG. 4. This makes it possible to prevent malfunction when a walk-out current occurs.

[0040] Next, the operation of the semiconductor device 100 will be described. 5 to 9 are diagrams illustrating the operation of the semiconductor device 100 of FIG. 2. FIG. 5 shows the operating state during a transition immediately after an H signal is input to input IN3, and FIG. 6 shows the operating state after FIG. 5. FIG. 7 shows the operating state during a transition immediately after an L signal is input to input IN3, and FIG. 8 shows the operating state of the false-ON prevention circuit 120. FIG. 9 shows the operating state after FIG. 7, and the state after the false-ON prevention circuit 120 has operated. The thick lines in the diagrams indicate elements and paths that are in an active state.

[0041] <When the first semiconductor element 101 (HVNM1) is ON> As shown in FIG. 5, when an H signal is input to input IN3 of semiconductor device 100, the high-voltage element of first semiconductor element 101 (HVNM1) turns ON, and HVNM1-2 intermediate potential 117, which is the intermediate potential between HVNM1 and HVNM2, becomes the GND potential.

[0042] When the HVNM1-2 intermediate potential becomes the GND potential, the potential difference between the gate and source of the second semiconductor element 102 (HVNM2) increases, and the high-voltage element of HVNM2 turns ON, as shown in Fig. 6. When HVNM2 turns ON, the level shift circuit 10 becomes conductive, and a current flows through resistor R2 of the level shift circuit 10, causing the level shift circuit 10 to perform a level shift operation on the potential of reference terminal (U) 9 of the U-phase upper arm output. At this time, the third semiconductor element 103 (HVNM3) and the fourth semiconductor element 104 (HVNM4) of the false ON prevention circuit 120 are off and therefore not affected.

[0043] <When the first semiconductor element 101 (HVNM1) is OFF> 7, when an L signal is input to the input IN3 of the semiconductor device 100, the first semiconductor element 101 (HVNM1) turns OFF, which causes the HVNM1-2 intermediate potential 117 to rise. At this time, the gate of the second semiconductor element 102 (HVNM2) is clamped by the first Zener diode 112 (VZ1) with a Zener voltage relative to the HVNM1-2 intermediate potential 117 to prevent the application of high voltage. If only the first Zener diode 112 (VZ1) was present, charge would remain on the gate of the second semiconductor element 102 (HVNM2), so a first resistor 111 (R1) is inserted between the gate and source of the second semiconductor element 102 (HVNM2) to allow the current from the first high-voltage diode 115 to escape to the HVNM1-2 intermediate potential 117 side via the first resistor 111 (R1).

[0044] However, at this time, 600 V is applied to the first semiconductor element 101 (HVNM1), causing a walk-out current to flow.

[0045] <Activation of the false ON prevention circuit 120> At this time, the third semiconductor element 103 (HVNM3) and the fourth semiconductor element 104 (HVNM4) of the false ON prevention circuit 120 are turned ON, and the fifth semiconductor element 121 (MP1) is turned ON, thereby preventing the signal from being transmitted to the buffer (Buffer1) 13.

[0046] More specifically, the erroneous ON prevention circuit 120 operates as follows. 8, when an L signal is input to input IN3 of semiconductor device 100, inverter (NOT1) 15 inverts the output of pre-driver circuit 4 and applies it to the gates of cascode-connected third semiconductor element 103 (HVNM3) and fourth semiconductor element 104 (HVNM4). Third semiconductor element 103 (HVNM3) and fourth semiconductor element 104 (HVNM4) are turned ON. This lowers the drain potential of fourth semiconductor element 104 (HVNM4), lowering the gate potential of fifth semiconductor element 121 (MP1), turning ON fifth semiconductor element 121 (MP1).

[0047] When the fifth semiconductor element 121 (MP1) is turned on, the BU7 on the high potential side is connected to the upper arm drive circuit 30. This cuts off the output of the cascode connection unit 110, and the signal is not transmitted from the cascode connection unit 110 to the buffer (Buffer1) 13.

[0048] 9, the gate voltage of the second semiconductor element 102 (HVNM2) is lowered to the same potential as the HVNM1-2 intermediate potential 117 through the first resistor R1, thereby turning off the high-voltage element of HVNM2. By turning off HVNM2, no current flows through the resistor 12 (R2) of the level shift circuit 10, and a level shift operation to the GND potential is performed.

[0049] [effect] As described above, the semiconductor device 100 (see FIG. 1) of this embodiment includes the cascode connection unit 110 including the first semiconductor element 101 (HVNM1), the second semiconductor element 102 (HVNM2), the first resistor 111 (R1), the first Zener diode (VZ1) 112, and the first high-voltage diode 115 (HVDd1), and the false-ON prevention circuit 120. The cascode connection unit 110 is connected between the drain of the first semiconductor element 101 (HVNM1) and the second semiconductor element 102 (HVNM2). The sources of the first and second semiconductor elements 101 (HVNM1) and 102 (HVNM2) are cascode-connected, a first resistor 111 (R1) and a first Zener diode (VZ1) 112 are connected between the gate and source of the second semiconductor element 102 (HVNM2), and a first high-voltage diode 115 (HVDd1) is connected between the gate of the first semiconductor element 101 (HVNM1) and the gate of the second semiconductor element 102 (HVNM2). The false-ON prevention circuit 120 is a circuit that prevents malfunction due to walk-out current in the cascode connection section 110.

[0050] <Effects of providing the cascode connection unit 110> With this configuration, even if the first semiconductor element 101 (HVNM1) is turned off and the HVNM1-2 intermediate potential 117 rises, the gate voltage of the second semiconductor element 102 (HVNM2) can be lowered to the same potential as the HVNM1-2 intermediate potential 117, thereby turning off the second semiconductor element 102 (HVNM2). This allows for the use of high-voltage elements (HVNM1 and HVNM2) with low gate breakdown voltages, preventing gate breakdown and enabling cascode connection, thereby improving breakdown voltage. That is, as indicated by the arrows flowing into the cascode connection portion 110 (enclosed by a dashed line in FIG. 1 ) in FIG. 1 , high-voltage elements with low gate breakdown voltages can be used as high-voltage elements where ESD voltages concentrate. Because high-voltage elements with low gate breakdown voltages can be used, conventional general-purpose high-voltage elements can be used as they are, resulting in cost reduction and ease of implementation through the use of general-purpose components. Furthermore, the area occupied by high-voltage transistors on a semiconductor substrate is larger than that occupied by low-voltage transistors, which poses an obstacle when incorporating them into a pre-driver IC. However, even in this respect, the use of conventional general-purpose high-voltage elements can simplify the design and reduce costs.

[0051] <Effects of having the false ON prevention circuit 120> In a semiconductor device 90 (see FIG. 5) that includes only the cascode connection portion 110, a malfunction may occur when a walkout current flows. However, the semiconductor device 100 (see FIG. 4) includes the false-ON prevention circuit 120, which can prevent a malfunction when a walkout current occurs. By preventing malfunctions due to walk-out current in the cascode connection portion 110, the reliability of the semiconductor device 100 can be improved.

[0052] In the case of a two-stage high-voltage drive circuit, if a device that applies a voltage equal to or higher than the walkout generation voltage is introduced, malfunctions due to the generation of a walkout current can be prevented even in semiconductor device 90 that only includes cascode connection unit 110. However, this requires the introduction of a new device that applies a voltage equal to or higher than the walkout generation voltage, which leads to increased costs. The erroneous ON prevention circuit 120 of the semiconductor device 100 of this embodiment has a simple circuit configuration and does not require any new device.

[0053] In the semiconductor device 100 of this embodiment (see FIG. 2), the erroneous ON prevention circuit 120 includes a third semiconductor element 103 (HVNM3), a fourth semiconductor element 104 (HVNM4), a second resistor 113 (R3), a second Zener diode (VZ2) 114, a second high-voltage diode 116 (HVDd2), and a fifth semiconductor element 121 (MP1). The drain of the third semiconductor element 103 (HVNM3) and the source of the fourth semiconductor element are cascode-connected, and the fourth semiconductor element 104 A second resistor and a second Zener diode are connected between the gate and source of the third semiconductor element 103 (HVNM3) and the fourth semiconductor element 104 (HVNM4), a second high-voltage diode is connected between the gate of the third semiconductor element 103 (HVNM3) and the gate of the fourth semiconductor element 104 (HVNM4), and the fifth semiconductor element 121 (MP1) is turned ON when the third semiconductor element 103 (HVNM3) and the fourth semiconductor element 104 (HVNM4) are ON, preventing a signal from being transmitted from the cascode connection unit 110 to the output stage.

[0054] This allows a simple circuit configuration to prevent malfunctions when a walk-out current occurs. The false-ON prevention circuit 120 (see FIG. 2) has a high affinity with the circuit of the cascode connection unit 110, and can be manufactured using the same process (same mask process, etc.) as the circuit of the cascode connection unit 110. This ease of manufacturing also contributes to cost reductions.

[0055] In addition to being able to be fabricated using the same process, the cascode connection unit 110 and the false-ON prevention circuit 120 have similar circuit configurations at the transistor level, which makes the operation behavior of both stable and allows for the realization of a semiconductor device with high operational stability.

[0056] In the semiconductor device 100 of this embodiment (see Figures 1 and 2), when the cascode connection section 110 turns off the first semiconductor element 101 (HVNM1) and the HVNM1-2 intermediate potential 117 rises, the first Zener diode (VZ1) 112 clamps the gate voltage of the second semiconductor element 102 (HVNM2) to the Zener voltage.

[0057] By doing this, when an L signal is input to input IN3, HVNM1 is turned OFF, and the HVNM1-2 intermediate potential 117 rises, the semiconductor device 100 can prevent high voltage from being applied to the gate of the second semiconductor element 102 (HVNM2).

[0058] In the semiconductor device 100 of this embodiment (see Figures 1 and 2), the cascode connection section 110 releases current from the first high-voltage diode 115 to the HVNM1-2 intermediate potential 117 side via the first resistor 111 (R1), lowering the gate voltage of the second semiconductor element 102 (HVNM2) to the same potential as the HVNM1-2 intermediate potential 117, which is the intermediate potential between HVNM1 and HVNM2, and turning off the second semiconductor element 102 (HVNM2).

[0059] In this way, the semiconductor device 100 can perform a level shift operation to the GND potential without flowing current through the resistor R2 of the level shift circuit 10 by turning off the high-voltage element of the second semiconductor element 102 (HVNM2).

[0060] In the semiconductor device 100 of this embodiment (see Figures 1 and 2), the output of the level shift circuit 10 that drives the second semiconductor element 102 (HVNM2), the upper arm drive circuit 30, PGU8, and the drive circuit (upper arm drive circuit 30) of the upper arm or lower arm switching elements (Q1 to Q6) that drive the motor M are connected.

[0061] In this way, the semiconductor device 100 can be used in, for example, a gate driver 220 configured with a pre-driver IC, and can be applied to a motor drive control device or a power conversion device having an inverter system.

[0062] The present invention is not limited to the above-described embodiment, and includes other modifications and applications within the scope of the claims. For example, although MOSFETs are used as switching elements, other types of elements can also be used. Depending on the device, the main terminals and sense terminals may be called "collector" and "emitter" instead of the above-mentioned "drain" and "source."

[0063] Furthermore, the signal lines shown are those considered necessary for the explanation, and do not necessarily represent all control lines or information lines in the product. In reality, it can be assumed that almost all components are interconnected. [Explanation of symbols]

[0064] 1 Reference power supply terminal 2 Low voltage power terminal 3 Input terminal for inputting input signal IN (U-phase control input terminal) 4 Pre-driver circuit (low voltage circuit) 7 U-phase upper arm drive circuit power supply terminal (BU) 8 U-phase upper arm gate drive output terminal (PGU) 9 Reference terminal for U-phase upper arm output (U) 10 Level shift circuit 11 Third Zener diode (VZ3) 12 Second resistor (R2) 13 Buffer (Buffer1) (output stage) 14 Reverse current prevention diode 15 Inverter (NOT1) 30 Upper arm drive circuit (drive circuit for upper arm or lower arm switching element) 100 Semiconductor device (pre-driver circuit) 101 HVNM1 (first semiconductor element) 102 HVNM2 (second semiconductor element) 103 Third Semiconductor Element (HVNM3) 104 Fourth Semiconductor Element (HVNM4) 110 Cascode connection 111 First resistor (R1) 112 First Zener diode (VZ1) 113 Third Resistor (R3) 114 Second Zener Diode (VZ2) 115 First high voltage diode (HVDd1) 116 Second high voltage diode (HVDd2) 117 HVNM1-2 intermediate potential (intermediate potential between the first semiconductor element and the second semiconductor element) 120 Erroneous ON prevention circuit 121 Fifth Semiconductor Element (MP1) 122 Fourth Zener Diode (VZ4) 123 Fourth Resistor (R4) 200 Inverter device 210 Control Unit 220 Gate Driver 230 Inverter Circuit Medium motor

Claims

1. a cascode connection portion including a first semiconductor element, a second semiconductor element, a first resistor, a first Zener diode, and a first high-voltage diode; a false ON prevention circuit; The cascode connection portion is the drain of the first semiconductor element and the source of the second semiconductor element are cascode-connected; the first resistor and the first Zener diode are connected between the gate and source of the second semiconductor element; the first high-voltage diode is connected between a gate of the first semiconductor element and a gate of the second semiconductor element; The false ON prevention circuit is a circuit for preventing malfunction due to walk-out current in the cascode connection portion; A semiconductor device characterized by:

2. The false ON prevention circuit is a third semiconductor element, a fourth semiconductor element, a second resistor, a second Zener diode, a second high-voltage diode, and a fifth semiconductor element; the drain of the third semiconductor element and the source of the fourth semiconductor element are cascode-connected; the second resistor and the second Zener diode are connected between the gate and source of the fourth semiconductor element; the second high-voltage diode is connected between the gate of the third semiconductor element and the gate of the fourth semiconductor element; When the third semiconductor element and the fourth semiconductor element are ON, the fifth semiconductor element is turned ON to prevent a signal from being transmitted from the cascode connection portion to the output stage.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. When the cascode connection portion turns off the first semiconductor element and an intermediate potential between the first semiconductor element and the second semiconductor element rises, the first Zener diode clamps the gate voltage of the second semiconductor element to a Zener voltage.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

4. The cascode connection portion releases the current from the first high-voltage diode to the intermediate potential side via the first resistor, and reduces the gate voltage of the second semiconductor element to the same potential as the intermediate potential, thereby turning off the second semiconductor element.

4. The semiconductor device according to claim 3.

5. a level shift circuit that drives the second semiconductor element; The output of the level shift circuit is connected to a drive circuit of a switching element of an upper arm or a lower arm that drives a motor.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

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