Differential amplifier and semiconductor device

Abstract

To provide a differential amplifier capable of a high-speed operation.SOLUTION: A differential amplifier 1 comprises: an input differential pair 12 that generates an output voltage Vout1 corresponding to a difference between a first input voltage Vinp and a second input voltage Vinn, and is connected to a non-inverting input terminal INP to which the first input voltage Vinp is input and an inverting input terminal INN to which the second input voltage Vinn is input; an active load circuit 20 including a cascode current mirror circuit 22 connected as an active load to the input differential pair 12; and an output stage 30 that generates the output voltage according to a signal at an output node of the cascode current mirror circuit 22. In the active load circuit 20, a capacitor is provided between a gate of a transistor constituting a first stage of the cascode current mirror circuit 22 and a reference voltage node.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a differential amplifier and a semiconductor device. [Background technology]

[0002] A differential amplifier (op-amp) is used to amplify the difference between two input voltages. For example, Patent Document 1 discloses an op-amp that includes an input differential pair, a tail current source that supplies a tail current to the input differential pair, and a cascode current mirror circuit connected to the input differential pair as an active load. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-96970

[0004] [overview] However, the inventors have come to recognize the following problem. Generally, a phase compensation capacitor is provided at the output stage of a differential amplifier. If the capacitance of this capacitor is large, high-frequency components are attenuated, making it difficult to achieve high-speed operation of the differential amplifier.

[0005] The present disclosure has been made in light of the above circumstances, and one of its exemplary purposes is to provide a differential amplifier capable of high-speed operation.

[0006] One aspect of the present disclosure relates to a differential amplifier. The differential amplifier generates an output voltage corresponding to the difference between a first input voltage and a second input voltage. The differential amplifier includes an input differential pair connected to a non-inverting input terminal to which the first input voltage is input and an inverting input terminal to which a second input voltage is input; an active load circuit including a cascode current mirror circuit configured by stacking two transistors and connected as an active load to the input differential pair; and an output stage that generates an output voltage corresponding to a signal at an output node of the cascode current mirror circuit. The active load circuit includes a capacitor provided between the gate of the transistor constituting the first stage of the cascode current mirror circuit and a reference voltage node.

[0007] Another aspect of the present disclosure relates to a semiconductor device including the differential amplifier described above.

[0008] Any combination of the above components and conversion of the expressions of the present disclosure into methods, devices, systems, etc. are also valid aspects of the present disclosure. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a differential amplifier according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a circuit diagram of a differential amplifier according to a comparative technique. [Figure 3] FIG. 3 is a diagram showing frequency characteristics of the differential amplifiers according to the first and second comparative examples. [Figure 4] FIG. 4 is a diagram showing frequency characteristics of the differential amplifiers according to the first comparative example and the first embodiment. [Figure 5] FIG. 5 is a diagram illustrating frequency characteristics of the differential amplifiers according to the first and second embodiments.

[0010] [Detailed explanation] (overview) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] A differential amplifier according to one embodiment generates an output voltage corresponding to the difference between a first input voltage and a second input voltage. The differential amplifier includes an input differential pair connected to a non-inverting input terminal to which the first input voltage is input and an inverting input terminal to which a second input voltage is input, an active load circuit including a cascode current mirror circuit configured by stacking two transistors and connected as an active load to the input differential pair, and an output stage that generates an output voltage corresponding to a signal at an output node of the cascode current mirror circuit. In the active load circuit, a capacitor is provided between the gate of the transistor constituting the first stage of the cascode current mirror circuit and a reference voltage node.

[0012] This configuration allows the phase of the signal to be adjusted using a capacitor connected between the gate of the transistor that constitutes the first stage of the cascode current mirror circuit and the reference voltage node, thereby reducing the capacitance of the phase compensation capacitor and realizing a differential amplifier capable of high-speed operation.

[0013] In one embodiment, the active load circuit further includes a resistor connected in series to the capacitor between the gate of the transistor constituting the first stage of the cascode current mirror circuit and the resistor.

[0014] In one embodiment, the input differential pair may include a first transistor connected to the non-inverting input terminal and a second transistor connected to the inverting input terminal. The cascode current mirror circuit may include a third transistor and a fourth transistor constituting a first stage and a fifth transistor and a sixth transistor constituting a second stage. The drain of the sixth transistor may be connected to the output node of the cascode current mirror circuit. The drain of the first transistor may be connected to the drain of the fourth transistor and the source of the sixth transistor. The drain of the second transistor may be connected to the drain of the third transistor and the source of the fifth transistor.

[0015] In one embodiment, the output stage may include a high-side transistor, a low-side transistor, a first phase compensation capacitor provided between the drain and source of the high-side transistor, and a second phase compensation capacitor provided between the drain and source of the low-side transistor.

[0016] A semiconductor device according to one embodiment includes the above differential amplifier.

[0017] This configuration allows the phase of the signal to be adjusted using a capacitor connected between the gate of the transistor that constitutes the first stage of the cascode current mirror circuit and the reference voltage node, thereby reducing the capacitance of the phase compensation capacitor and realizing a differential amplifier capable of high-speed operation.

[0018] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0019] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0020] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0021] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0022] FIG. 1 is a circuit diagram of a differential amplifier 1 according to an embodiment of the present disclosure. The differential amplifier 1 according to this embodiment can be mounted on various semiconductor devices. The differential amplifier 1 is configured to generate an output voltage Vout1 corresponding to the difference between two input voltages (a first input voltage Vin1 and a second input voltage Vin2). As shown in FIG. 1, the differential amplifier 1 according to this embodiment includes an input stage 10, an active load circuit 20, an output stage 30, a non-inverting input terminal INP, an inverting input terminal INN, and an output terminal OUT. The non-inverting input terminal INP receives the first input voltage Vin1, and the inverting input terminal INN receives the second input voltage Vin2. The output terminal OUT outputs the output voltage Vout1.

[0023] The input stage 10 includes an input differential pair 12 and a transistor MP3.

[0024] The input differential pair 12 includes transistors MP1 and MP2, each of which is configured as a P-channel MOS (Metal Oxide Semiconductor) transistor. The gate of transistor MP1 is connected to a non-inverting input terminal INP, and the drain of transistor MP1 is connected to a current mirror circuit 22 (described later) of the active load circuit 20. The gate of transistor MP2 is connected to an inverting input terminal INN, and the drain of transistor MP2 is connected to the current mirror circuit 22.

[0025] The transistor MP3 constitutes a tail current source that supplies a tail current Itail to the source of the input differential pair 12. The source of the transistor MP3 is supplied with a power supply voltage VDD, and the drain of the transistor MP3 is connected to the sources of the input differential pair 12 (specifically, the sources of the transistors MP1 and MP2). A signal vp1 is input to the gate of the transistor MP3, and the transistor MP3 is appropriately biased.

[0026] The active load circuit 20 includes a current mirror circuit 22, a phase adjustment circuit 24, and transistors MP4 to MP8 and MN5.

[0027] The current mirror circuit 22 is a cascade current mirror circuit configured by stacking transistors MN1 to MN4 in two stages and connected as an active load to the input differential pair 12. The transistors MN1 to MN4 according to this embodiment are each configured as an N-channel MOS transistor. The transistor MN1 (third transistor) and the transistor MN2 (fourth transistor) configure the first stage of the current mirror circuit 22, and the transistor MN3 (fifth transistor) and the transistor MN4 (sixth transistor) configure the second stage of the current mirror circuit 22.

[0028] The source of transistor MN1 is connected to a reference voltage node 26 to which a negative power supply voltage VSS (reference voltage) is supplied, and the gate of transistor MN1 is connected in common with the gate of transistor MN2 and to the drain of transistor MN3. The drain of transistor MN1 is connected in common with the source of transistor MN3 and to the drain of transistor MP2 of input differential pair 12. The source of transistor MN2 is connected to the reference voltage node 26, and the drain of transistor MN2 is connected in common with the source of transistor MN4 and to the drain of transistor MP1 of input differential pair 12. The drain of transistor MN4 is connected to an output node 220 of current mirror circuit 22. A signal vn1 is input to the gates of transistors MN3 and MN4, respectively, and transistors MN3 and MN4 are appropriately biased.

[0029] The phase adjustment circuit 24 is configured to adjust the phase of a signal passing between the gates of transistors MN1 and MN2, and more specifically, to delay the phase of a signal passing between the gates of transistors MN1 and MN2. The phase adjustment circuit 24 is provided between the gates of transistors MN1 and MN2 and a reference voltage node 26. The phase adjustment circuit 24 according to this embodiment includes a capacitor C1 and a resistor R1 connected in series. One end of the capacitor C1 opposite the resistor R1 is connected to the gates of transistors MN1 and MN2. The other end of the resistor R1 opposite the capacitor C1 is connected to the reference voltage node 26. Note that the capacitor C1 and the resistor R1 may be provided in reverse.

[0030] The transistors MP4 to MP8 are each formed as a P-channel MOS transistor, and the transistor MN5 is formed as an N-channel MOS transistor. The power supply voltage VDD is supplied to the sources of the transistors MP4 and MP5. The drain of the transistor MP4 is connected to the source of the transistor MP6. The drain of the transistor MP5 is connected to the source of the transistor MP7. The drain of the transistor MP6 is connected to the drain of the transistor MN3 of the current mirror circuit 22. The drain of the transistor MP7 is connected in common with the source of the transistor MP8 and to the drain of the transistor MN5. The drain of the transistor MP8 is connected in common with the source of the transistor MN5 and to the output node 220 of the current mirror circuit 22.

[0031] A signal vp2 is input to the bases of transistors MP4 and MP5, and transistors MP4 and MP5 are appropriately biased. A signal vp3 is input to the bases of transistors MP6 and MP7, and transistors MP6 and MP7 are appropriately biased. A signal vp4 is input to the base of transistor MP8, and transistor MP8 is appropriately biased. A signal vn2 is input to the base of transistor MN5, and transistor MN5 is appropriately biased.

[0032] The output stage 30 generates an output voltage Vout1 that corresponds to the output from the active load circuit 20. In this embodiment, the output stage 30 generates the output voltage Vout1 that corresponds to the signal (voltage) of the output node 220 of the current mirror circuit 22. The output stage 30 has a high-side transistor MH, a low-side transistor ML, and a phase compensation circuit 32.

[0033] The high-side transistor MH is composed of a P-channel MOS transistor, and the low-side transistor ML is composed of an N-channel MOS transistor. The source of the high-side transistor MH is supplied with a power supply voltage VDD, and the gate of the high-side transistor MH is connected to the drain of transistor MN5. The drain of the high-side transistor MH is connected to the output terminal OUT in common with the drain of the low-side transistor ML. The source of the low-side transistor ML is connected to a reference voltage node 26, and the gate of the low-side transistor ML is connected to the drain of transistor MP8.

[0034] The phase compensation circuit 32 is configured to compensate for the phase of the output voltage Vout1, specifically, to restore a phase delay. Phase compensation by the phase compensation circuit 32 ensures the stability of the output voltage Vout1. The phase compensation circuit 32 of this embodiment includes phase compensation capacitors C2 and C3 and resistors R2 and R3. The capacitor C2 (first phase compensation capacitor) and the resistor R2 are connected in series, and the capacitor C3 (second phase compensation capacitor) and the resistor R3 are connected in series. One end of the capacitor C2 opposite the resistor R2 is connected to the base of the high-side transistor MH, and one end of the resistor R2 opposite the capacitor C2 is connected to the drain of the high-side transistor MH. One end of the capacitor C3 opposite the resistor R3 is connected to the gate of the low-side transistor ML, and one end of the resistor R3 opposite the capacitor C3 is connected to the drain of the low-side transistor ML.

[0035] In the differential amplifier 1 according to this embodiment, when the input voltages Vinp and Vinn are input to the input differential pair 12, the transistors MP1 and MP2 generate drain currents Id1 and Id2 corresponding to the input voltages Vinp and Vinn, respectively (Itail=Id1+Id2).

[0036] A differential signal corresponding to the drain currents Id1 and Id2 is transmitted to the output node 220 via the first transmission path P1 and the second transmission path P2. The first transmission path P1, along which one signal of the differential signal is transmitted, is a path from the drain of the transistor MP1 to the output node 220, specifically a path that passes through the transistor MN4. The second transmission path P2, along which the other signal of the differential signal is transmitted, is a path from the drain of the transistor MP2 to the output node 220, specifically a path that passes through the transistors MN1, MN2, and MN4.

[0037] The first transmission path P1 can transmit signals at a higher speed than the second transmission path P2 because the signal does not pass through the transistors MN1 and MN2. In this embodiment, a phase adjustment circuit 24 is connected between the transistors MN1 and MN2 of the second transmission path P2. Therefore, the phase of the signal transmitted through the second transmission path P2 is adjusted (phase delayed) by the phase adjustment circuit 24 and transmitted to the output node 220. As a result, the burden of phase compensation by the phase compensation circuit 32 in the output stage 30 is reduced, and the capacitances of the capacitors C2 and C3 of the phase compensation circuit 32 can be reduced. By reducing the capacitances of the capacitors C2 and C3, attenuation of high-frequency components is suppressed, and the differential amplifier 1 can operate at a higher speed.

[0038] The differential amplifier 1 according to this embodiment has been described above. The differential amplifier 1 according to this embodiment includes an input differential pair 12, an active load circuit 20, and an output stage 30. The input differential pair 12 is connected to a non-inverting input terminal INP to which a first input voltage Vinp is input and an inverting input terminal INN to which a second input voltage Vinn is input. The active load circuit 20 includes a current mirror circuit 22 configured by stacking two transistor stages and receiving a differential signal from the input differential pair 12. The output stage 30 generates an output voltage Vout1 according to a signal at an output node 220 of the current mirror circuit 22. Here, in the active load circuit 20, a capacitor C1 is provided between a reference voltage node 26 and the gates of transistors MN1 and MN2 that configure the first stage of the current mirror circuit 22.

[0039] According to this configuration, the phase of one of the differential signals of the input differential pair 12 is adjusted by the capacitor C1. This allows the capacitance of the phase compensation capacitors C2 and C3 in the output stage 30 to be reduced, thereby realizing a differential amplifier 1 capable of high-speed operation.

[0040] Furthermore, according to the differential amplifier 1 of this embodiment, the active load circuit 20 is provided with a resistor R1 connected in series to the capacitor C1 between the gates of the transistors MN1 and MN2 that form the first stage of the current mirror circuit 22. This increases the unity gain frequency of the differential amplifier 1, making it possible to further speed up the operation of the differential amplifier 1. Note that even if the resistor R1 is not provided, the operation of the differential amplifier 1 can still be speeded up.

[0041] 2 is a circuit diagram of a differential amplifier 9 according to the comparative technology. The differential amplifier 9 according to the comparative technology includes an input stage 10, an active load circuit 90, and an output stage 30. The differential amplifier 9 according to the comparative technology differs from the differential amplifier 1 according to the above embodiment in that the active load circuit 90 does not include a phase adjustment circuit 24.

[0042] FIG. 3 is a diagram showing the frequency characteristics of the differential amplifiers according to the first and second comparative examples. The upper part of FIG. 3 shows the frequency characteristics of gain (dB), and the lower part of FIG. 3 shows the frequency characteristics of phase (°). The differential amplifiers according to the first and second comparative examples are the differential amplifier 9 according to the above-mentioned comparative technique when the capacitances of the capacitors C2 and C3 are Ca (first comparative example) and Cb (second comparative example). Here, Ca <Cbである。

[0043] As shown in FIG. 3, the unity gain frequencies of Comparative Examples 1 and 2 are f1 and f2, respectively, with f1 > f2. That is, by reducing the capacitance of capacitors C2 and C3, attenuation of high-frequency components is suppressed. However, looking at the phase-frequency characteristics, the phase is P2 (> -180°) at unity gain frequency f2 in Comparative Example 2, whereas the phase is P1 (< -180°) at unity gain frequency f1 in Comparative Example 1. For this reason, Comparative Example 1 has no phase margin. As such, it is difficult for the differential amplifier 9 according to the comparison technique to have a phase margin while suppressing attenuation in the high-frequency band.

[0044] FIG. 4 is a diagram showing the frequency characteristics of the differential amplifiers according to Comparative Example 1 and Example 1. The upper part of FIG. 4 shows the frequency characteristics of gain (dB), and the lower part of FIG. 4 shows the frequency characteristics of phase (°). The differential amplifier according to Example 1 is a circuit in which the resistor R1 is removed from the phase adjustment circuit 24 of the differential amplifier 1 according to the above embodiment, that is, a circuit in which the other end of the capacitor C1 is directly connected to the reference voltage node 26. Furthermore, when the capacitance value of the phase compensation capacitors C2 and C3 according to Example 1 is Cc, Ca=Cc <Cbである。

[0045] 4, the gain-frequency characteristics according to the first embodiment are affected by the capacitor C1 connected to the current mirror circuit 22, but have a unity gain frequency f3 similar to that of the first comparative example. This is because, in the first embodiment, the signal passing through the first transmission path P1 is not slowed down by the effect of the capacitor C1. In this way, the differential amplifier according to the first embodiment can suppress the attenuation of high-frequency components in a manner similar to that of the first comparative example.

[0046] Furthermore, in the phase-frequency characteristics according to Example 1, the pole is shifted to the higher frequency side compared to the phase-frequency characteristics according to Comparative Example 1, and phase reduction at the unity gain frequency is suppressed. A parasitic capacitor (not shown) on transistor MN2 (for example, between the gate and drain) prevents phase compensation capacitors C2 and C3 from shifting the pole to the higher frequency side. In Example 1, capacitor C1 suppresses the effect of the parasitic capacitor on transistor MN2 on the pole, so the pole can be shifted to the higher frequency side compared to Comparative Example 1. As a result, the phase at unity gain frequency f3 is P3 (>-180°), and the differential amplifier according to Example 1 has a phase margin. As such, the differential amplifier according to Example 1 can provide a phase margin while suppressing attenuation of high-frequency components.

[0047] 5 is a diagram showing the frequency characteristics of the differential amplifiers according to Examples 1 and 2. The upper part of FIG. 5 shows the frequency characteristics of gain (dB), and the lower part of FIG. 5 shows the frequency characteristics of phase (°). The differential amplifier according to Example 2 is the differential amplifier 1 according to the above embodiment, that is, a differential amplifier including a phase adjustment circuit 24 including a capacitor C1 and a resistor R1 connected in series. The capacitances of capacitors C1 to C3 are assumed to be the same in Examples 1 and 2.

[0048] The impedance of the capacitor C1 is expressed as 1 / (2πf×C1). As the frequency f increases, the impedance of the capacitor C1 approaches 0. However, by connecting the resistor R1 in series with the capacitor C1, the impedance of the phase adjustment circuit 24 does not become smaller than R1. Therefore, in the second embodiment, even if the frequency f increases, the impedance of the phase adjustment circuit 24 can be maintained at or above R1, thereby suppressing signal attenuation in the second transmission path P2. As a result, as shown in FIG. 5, the gain according to the second embodiment is larger than the gain according to the first embodiment in the high frequency range, and the unity gain frequency f4 according to the second embodiment is higher than the unity gain frequency f3 according to the first embodiment.

[0049] In this way, by providing the resistor R1 in the phase adjustment circuit 24, it is possible to further suppress the attenuation of high frequency components and further speed up the operation of the differential amplifier. Also, the phase P4 (>-180°) at the unity gain frequency f4 according to the second embodiment does not change significantly from the phase P3 at the unity gain frequency f3 according to the first embodiment. Therefore, the differential amplifier according to the second embodiment can provide a phase margin to the differential amplifier while further speeding up the operation of the differential amplifier.

[0050] (supplement) Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. Furthermore, not only the embodiments but also embodiments, examples, and modifications not described herein are included in the scope of the present invention.

[0051] (Addendum) One aspect of the technology disclosed in this specification can be understood as follows.

[0052] (Item 1) A differential amplifier that generates an output voltage according to a difference between a first input voltage and a second input voltage, an input differential pair connected to a non-inverting input terminal to which the first input voltage is input and an inverting input terminal to which the second input voltage is input; an active load circuit including a cascode current mirror circuit configured by stacking two transistors and connected as an active load to the input differential pair; an output stage that generates the output voltage according to a signal at an output node of the cascode current mirror circuit; the active load circuit includes a capacitor provided between a gate of a transistor constituting a first stage of the cascode current mirror circuit and a reference voltage node; Differential amplifier.

[0053] (Item 2) the active load circuit further includes a resistor connected in series to the capacitor between the gate of the transistor constituting the first stage of the cascode current mirror circuit and the capacitor; The differential amplifier described in item 1.

[0054] (Item 3) the input differential pair includes a first transistor connected to the non-inverting input terminal and a second transistor connected to the inverting input terminal; the cascode current mirror circuit includes a third transistor and a fourth transistor that constitute a first stage, and a fifth transistor and a sixth transistor that constitute a second stage; a drain of the sixth transistor is connected to an output node of the cascode current mirror circuit; a drain of the first transistor is connected to a drain of the fourth transistor and a source of the sixth transistor; the drain of the second transistor is connected to the drain of the third transistor and the source of the fifth transistor; A differential amplifier as described in item 1 or 2.

[0055] (Item 4) the output stage includes a high-side transistor, a low-side transistor, a first phase compensation capacitor provided between a drain and a source of the high-side transistor, and a second phase compensation capacitor provided between a drain and a source of the low-side transistor. 4. The differential amplifier according to any one of items 1 to 3.

[0056] (Item 5) A semiconductor device comprising the differential amplifier according to any one of items 1 to 4. [Explanation of symbols]

[0057] 1 differential amplifier, 10 input stage, 12 input differential pair, 20 active load circuit, 22 current mirror circuit, 24 phase adjustment circuit, 30 output stage, 32 phase compensation circuit, 220 output node, INP non-inverting input terminal, INN inverting input terminal, OUT output terminal, MP1 to MP8, MN1 to MN5 transistors, MH high-side transistor, ML low-side transistor, R1 to R3 resistors, C1 to C3 capacitors.

Claims

1. A differential amplifier that generates an output voltage according to a difference between a first input voltage and a second input voltage, an input differential pair connected to a non-inverting input terminal to which the first input voltage is input and an inverting input terminal to which the second input voltage is input; an active load circuit including a cascode current mirror circuit configured by stacking two transistors and connected to the input differential pair as an active load; an output stage that generates the output voltage according to a signal at an output node of the cascode current mirror circuit; the active load circuit includes a capacitor provided between a gate of a transistor constituting a first stage of the cascode current mirror circuit and a reference voltage node; Differential amplifier.

2. the active load circuit further includes a resistor connected in series to the capacitor between the gate of the transistor constituting the first stage of the cascode current mirror circuit and the capacitor; 2. The differential amplifier according to claim 1.

3. the input differential pair includes a first transistor connected to the non-inverting input terminal and a second transistor connected to the inverting input terminal; the cascode current mirror circuit includes a third transistor and a fourth transistor constituting a first stage, and a fifth transistor and a sixth transistor constituting a second stage; a drain of the sixth transistor is connected to an output node of the cascode current mirror circuit; a drain of the first transistor is connected to a drain of the fourth transistor and a source of the sixth transistor; the drain of the second transistor is connected to the drain of the third transistor and the source of the fifth transistor; 2. The differential amplifier according to claim 1.

4. the output stage includes a high-side transistor, a low-side transistor, a first phase compensation capacitor provided between a drain and a source of the high-side transistor, and a second phase compensation capacitor provided between a drain and a source of the low-side transistor.

2. The differential amplifier according to claim 1.

5. A semiconductor device comprising the differential amplifier according to claim 1 .

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