Inductor topology for phase noise reduction

Abstract

To provide an inductor topology for phase noise reduction.SOLUTION: A voltage-controlled oscillator may include an inductor. The inductor may include a first coil coupled to an electronic component. The inductor may include a first coil coupled to the first circuit component, a second coil coupled to the first circuit component via a junction and being in parallel with the first coil, and a shared circuit path coupled to the second circuit component, the first coil and the second coil, the shared circuit path overlapping the junction. The inductor may be configured to reduce phase noise generated by the electronic component.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiments relate generally to inductors, and more particularly to inductors for voltage controlled oscillators (VCOs). [Background technology]

[0002] In a mobile communication device, a transceiver may transmit and receive radio signals. The transceiver may include a voltage-controlled oscillator (VCO) that changes the frequency of the transmitted or received signal. However, the VCO may generate phase noise (e.g., a frequency-domain representation of random variations in the phase of the transmitted or received signal, corresponding to time-domain deviations from perfect periodicity) that can affect the performance of the transceiver and the quality of the transmitted or received signal. Summary of the Invention

[0003] A summary of certain embodiments disclosed herein is provided below. It should be understood that these aspects are presented merely to provide the reader with an overview of these particular embodiments, and that these aspects are not intended to limit the scope of the disclosure. Indeed, the disclosure may encompass a variety of aspects not set forth below.

[0004] In one embodiment, an inductor may include a first terminal, a second terminal, and a shared branch coupled to the second terminal. The inductor may further include a first coil coupled to the first terminal extending in a counterclockwise direction from the first terminal to the shared branch. The inductor may further include a second coil coupled to the first terminal extending in a clockwise direction from the first terminal to the shared branch, the first coil being symmetrical to the second coil about the shared branch.

[0005] In another embodiment, an electronic device may include one or more antennas. The electronic device may also include a transceiver coupled to the one or more antennas. The transceiver may include a first circuit, a second circuit, and an inductor. The inductor may have a first coil and a second coil coupled to the first circuit, and a shared branch coupled to the first coil and the second coil, bisecting the inductor and coupled to the second circuit, wherein the first coil is in parallel with the second coil.

[0006] In yet another embodiment, a voltage controlled oscillator may include a first circuit component, a second circuit component, and an inductor. The inductor may include a first coil coupled to the first circuit component, a second coil coupled to the first circuit component through a junction and in parallel with the first coil, and a shared circuit path coupled to the second circuit component, the first coil, and the second coil, the shared circuit path overlapping the junction.

[0007] Various refinements of the above-described features may exist in connection with various aspects of the present disclosure. Additional features may also be incorporated into these various aspects as well. These refinements and additional features may exist individually or in any combination. For example, various features discussed below in connection with one or more of the illustrated embodiments may be incorporated, alone or in any combination, into any of the above-described aspects of the present disclosure. The foregoing summary is intended solely to familiarize the reader with certain aspects and context of embodiments of the present disclosure without limiting the claimed subject matter.

[0008] Various aspects of the present disclosure can be better understood by reading the following Detailed Description and by referring to the following drawings, in which like numbers refer to like parts, and in which: [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure. [Figure 2] 2 is a functional diagram of the electronic device of FIG. 1 according to an embodiment of the present disclosure. [Figure 3] 2 is a schematic diagram of a transmitter of the electronic device of FIG. 1 according to an embodiment of the present disclosure. [Figure 4] 2 is a schematic diagram of a receiver of the electronic device of FIG. 1 according to an embodiment of the present disclosure. [Figure 5] FIG. 1 shows an inductor having two coils in series in a figure-eight configuration. [Figure 6] FIG. 10 illustrates an inductor having two coils in parallel in a figure-eight configuration, according to an embodiment of the present disclosure. [Figure 7A] 7 is a three-dimensional view of the inductor of FIG. 6 according to an embodiment of the present disclosure. [Figure 7B] 7 is a three-dimensional view of the inductor of FIG. 6 according to an embodiment of the present disclosure. [Figure 8] 7 is a plot illustrating the inductance of the inductor of FIG. 5 and the inductance of the inductor of FIG. 6 according to an embodiment of the present disclosure. [Figure 9] 7 is a plot illustrating the quality factor of the inductor of FIG. 5 and the quality factor of the inductor of FIG. 6 according to an embodiment of the present disclosure. [Figure 10] 10A-10C illustrate alternative configurations of figure-eight parallel inductors according to embodiments of the present disclosure. [Figure 11A] 11 is a three-dimensional view of the inductor of FIG. 10 according to an embodiment of the present disclosure. [Figure 11B] 11 is a three-dimensional view of the inductor of FIG. 10 according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] One or more specific embodiments are described below. In the interest of providing a concise description of these embodiments, not all features of an actual implementation are described herein. As with any engineering or design project, it should be understood that the development of any such actual implementation will require numerous implementation-specific decisions to be made in order to achieve the developer's specific objectives, including compliance with system- and business-related constraints, which may vary from implementation to implementation. Moreover, it should be understood that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0011] When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” mean that there are one or more elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, it should be understood that references to “one embodiment” or “embodiments” in the present disclosure are not intended to exclude the existence of additional embodiments that incorporate the recited features. Furthermore, particular features, structures, or characteristics may be combined as appropriate in one or more embodiments. Use of the terms “approximately,” “near,” “about,” “approximately,” and / or “substantially” should be understood to mean including proximity to a target (e.g., a design, value, amount), including within any reasonable or predictable tolerance of error (e.g., within 0.1% of a target, within 1% of a target, within 5% of a target, within 10% of a target, within 25% of a target, etc.). Furthermore, it should be understood that any exact values, numbers, measurements, etc. provided herein are intended to include approximations (e.g., within appropriate or predictable tolerances of error) of the exact values, numbers, measurements, etc.

[0012] The present disclosure is directed to reducing phase noise in voltage-controlled oscillators (VCOs), and more particularly, using inductors located within the VCO. In particular, increasing the power consumption and / or quality factor of the inductor can reduce phase noise. The quality factor of an inductor is the ratio of the inductive reactance of the inductor to its resistance at a given frequency and is a measure of the inductor's efficiency. That is, the higher the quality factor of an inductor, the more likely it is to behave like an ideal inductor.

[0013] VCO phase noise reduction can be achieved by designing an inductor to increase its power dissipation. To increase the inductor's power dissipation, the inductor's inductance should be reduced by decreasing the inner diameter of one or more coils within the inductor. However, as the inner diameter decreases, the inductor's quality factor decreases, which can increase phase noise and negate the benefit of reducing inductance. Furthermore, assuming an inductor has a series figure-eight (or 8-shape) topology to provide primary flux cancellation, decreasing the inner diameter of both figure-eight coils can lead to an even lower quality factor. As an example, if the two coils in a series figure-eight inductor have the same inductance, the inductor's total inductance is the sum of the inductances of the two coils.

[0014] Embodiments of the present disclosure provide an inductor topology that achieves reduced inductance and increased quality factor (e.g., compared to a series figure-eight configuration) to reduce phase noise while maintaining magnetic flux cancellation. In the disclosed parallel figure-eight inductor configuration, coils are arranged in parallel to form an inductor with a total inductance approximately equal to half the inductance of each coil (assuming each coil has the same inductance). This contrasts with a series figure-eight configuration, in which two coils are arranged in series to form an inductor whose total inductance is the sum of the inductances of each coil. Because each coil of the proposed inductor can have a larger inductance and inner diameter with the parallel figure-eight inductor configuration (e.g., compared to a series figure-eight configuration), an increased inductor quality factor is achieved. This reduced inductance and increased quality factor can result in reduced phase noise.

[0015] 1 is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. The electronic device 10 may include, among other things, one or more processors 12 (collectively referred to herein as a single processor for convenience and which may be implemented in any suitable manner within a processing circuit), memory 14, non-volatile storage 16, a display 18, input structures 22, input / output (I / O) interfaces 24, a network interface 26, and a power supply 29. The various functional blocks illustrated in FIG. 1 may include hardware elements (including circuitry), software elements (including machine-executable instructions), or a combination of both hardware and software elements (which may be referred to as logic). The processor 12, memory 14, non-volatile storage 16, display 18, input structures 22, input / output (I / O) interfaces 24, network interface 26, and / or power supply 29 may each be communicatively coupled to one another, directly or indirectly (e.g., via another component, a communications bus, or a network), to transmit and / or receive data between one another. It should be noted that FIG. 1 is merely an example of a particular implementation and is intended to illustrate the types of components that may be present in electronic device 10.

[0016] By way of example, electronic device 10 may include any suitable computing device, including a desktop or notebook computer (e.g., in the form of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® mini, or Mac Pro® available from Apple Inc., Cupertino, California), a portable or handheld electronic device such as a wireless electronic device or smartphone (e.g., in the form of an iPhone® model available from Apple Inc., Cupertino, California), a tablet (e.g., in the form of an iPad® model available from Apple Inc., Cupertino, California), or a wearable electronic device (e.g., in the form of an Apple Watch® available from Apple Inc., Cupertino, California). Note that processor 12 and / or other related items in FIG. 1 may be collectively referred to herein as “data processing circuitry.” Such data processing circuitry may be implemented, in whole or in part, as software, as hardware, or both. 1 may be a single housed processing module or may be incorporated, in whole or in part, within any of the other elements in electronic device 10. Processor 12 may be implemented as any combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gate logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing calculations or other manipulations of information. Processor 12 may include one or more application processors, one or more baseband processors, or both, and perform various functions described herein.

[0017] In the electronic device 10 of FIG. 1 , the processor 12 is operatively coupled to the memory 14 and the nonvolatile memory 16 and may execute various algorithms. Such programs or instructions executed by the processor 12 may be stored on any suitable article of manufacture, including one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the nonvolatile storage 16, individually or collectively, for storing instructions or routines. The memory 14 and the nonvolatile storage 16 may include any suitable article of manufacture for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disks, and optical disks. Additionally, programs (e.g., operating systems) encoded on such computer program products may also include instructions that can be executed by the processor 12 to enable the electronic device 10 to provide various functions.

[0018] In certain embodiments, display 18 may allow a user to easily view images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen, which may allow a user to easily interact with the user interface of electronic device 10. It should further be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light emitting diode (LED) displays, organic light emitting diode (OLED) displays, active matrix organic light emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0019] Input structure 22 of electronic device 10 may allow a user to interact with electronic device 10 (e.g., press a button to increase or decrease a volume level). I / O interface 24 may allow electronic device 10 to interface with various other electronic devices, such as network interface 26. In some embodiments, I / O interface 24 may include an I / O port for a wired connection for charging and / or content manipulation using a standard connector and protocol, such as a Lightning connector provided by Apple Inc. (Cupertino, California), Universal Serial Bus (USB), or other similar connector and protocol. The network interface 26 may include one or more interfaces, for example, for a personal area network (PAN) such as ultra-wideband (UWB) or Bluetooth®, for a local area network (LAN) or wireless local area network (WLAN) using one of the IEEE 802.11x protocol family (e.g., WI-FI®), and / or for a wide area network (WAN) such as any standard associated with the 3rd Generation Partnership Project (3GPP®), including, for example, a third generation (3G) cellular network, a Universal Mobile Telecommunications System (UMTS), a fourth generation (4G) cellular network, a Long Term Evolution (LTE®), a Long Term Evolution Licensed Assisted Access (LTE-LAA) cellular network, a fifth generation (5G) cellular network, and / or a New Radio (NR) cellular network, a satellite network, etc. In particular, network interface 26 may include one or more interfaces for using the Release 15 cellular communications standard of the 5G specifications, which includes the millimeter wave (mm wave) frequency range (e.g., 24.25 to 300 gigahertz (GHz)), and / or any other cellular communications standard release (e.g., Release 16, Release 17, or any subsequent release) that defines and / or enables a frequency range used for wireless communications.The network interface 26 of the electronic device 10 may enable communication over the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0020] Network interface 26 may also include one or more interfaces for, for example, broadband fixed wireless access networks (e.g., WIMAX®), mobile broadband wireless networks (Mobile WIMAX®), asynchronous digital subscriber lines (ADSL, VDSL, etc.), digital video broadcasting terrestrial (DVB-T) and its extension DVB handheld (DVB-H®) networks, ultra-wideband (UWB) networks, alternating current (AC) power lines, etc.

[0021] As shown, the network interface 26 may include a transceiver 30. In some embodiments, all or a portion of the transceiver 30 may be located within the processor 12. The transceiver 30 may support transmission and reception of various wireless signals via one or more antennas and thus may include a transmitter and a receiver. The transceiver 30 may further include an inductor, which may be coupled to any suitable circuitry of the transceiver 30 to reduce phase noise of the circuit. The power source 29 of the electronic device 10 may be any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter. In certain embodiments, the electronic device 10 may take the form of a computer, a portable electronic device, a wearable electronic device, or other type of electronic device.

[0022] 2 is a functional diagram of the electronic device of FIG. 1, according to an embodiment of the present disclosure. As shown, processor 12, memory 14, transceiver 30, transmitter 52, receiver 54, and / or antenna 55 (shown as 55A-55N and collectively referred to as antenna 55) may be communicatively coupled to each other directly or indirectly (e.g., via another component, a communications bus, or a network) to transmit and / or receive data between each other.

[0023] The electronic device 10 may include a transmitter 52 and / or a receiver 54 that enable transmission and reception of data, respectively, between the electronic device 10 and an external device, for example, via a network (including, e.g., a base station) or a direct connection. As shown, the transmitter 52 and receiver 54 may be combined into a transceiver 30. The electronic device 10 may also have one or more antennas 55A-55N electrically coupled to the transceiver 30. The antennas 55A-55N may be configured in omnidirectional or directional configurations, such as single-beam, dual-beam, or multi-beam arrays. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas of an antenna group or module 55A-55N may be communicatively coupled to a respective transceiver 30 and may each emit radio frequency signals that may combine constructively and / or destructively to form a beam. The electronic device 10 may include multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas suitable for various communication standards. In some embodiments, the transmitter 52 and receiver 54 may transmit and receive information via wires or other systems or means of telegraph lines.

[0024] As shown, the various components of electronic device 10 may be coupled together by a bus system 56. Bus system 56 may include a data bus and may also include, in addition to a data bus, a power bus, a control signal bus, and a status signal bus, for example. The components of electronic device 10 may be coupled together or may use some other mechanism to receive or provide inputs to each other.

[0025] As described above, the transceiver 30 of the electronic device 10 may include a transmitter and a receiver coupled to at least one antenna to enable the electronic device 10 to transmit and receive wireless signals. FIG. 3 is a block diagram of a transmitter 52 (e.g., a transmission circuit) that may be part of the transceiver 30, according to an embodiment of the present disclosure. As shown, the transmitter 52 may receive outgoing data 60 in the form of a digital signal that is transmitted via one or more antennas 55. A digital-to-analog converter (DAC) 62 of the transmitter 52 may convert the digital signal to an analog signal, which may then be combined with a carrier signal by a modulator 63. A mixer 64 may change the frequency of the carrier signal via a voltage-controlled oscillator 66 (VCO). The VCO 66 is an oscillator whose oscillation frequency is controlled by a voltage. The VCO 66 may include one or more circuit components, such as one or more resistors, capacitors, inductors (including the inductors described herein that reduce phase noise in an input signal received by the VCO 66 to produce an output signal), transistors, diodes, etc. In some embodiments, VCO 66 may include a digitally controlled oscillator (DCO), which may refer to VCO 66 driven by a carrier signal provided by DAC 62.

[0026] A power amplifier (PA) 67 may receive the radio frequency signal from the mixer 64 and amplify the modulated signal to an appropriate level to drive transmission of the signal via one or more antennas 55. A filter 68 (e.g., filter circuitry and / or software) of the transmitter 52 may then remove undesired noise from the amplified signal to generate transmit data 70, which is transmitted via one or more antennas 55. The filter 68 may include any suitable filter or filters to remove undesired noise from the amplified signal, such as a bandpass filter, a bandstop filter, a lowpass filter, a highpass filter, and / or a decimation filter. Additionally, the transmitter 52 may include any suitable additional components not shown, or may not include certain of the components shown, to enable the transmitter 52 to transmit the outgoing data 60 via one or more antennas 55. For example, the transmitter 52 may include additional mixers and / or digital upconverters (e.g., to convert the input signal from a baseband frequency to an intermediate frequency). As another example, transmitter 52 may not include filter 68 if power amplifier 67 outputs an amplified signal in a desired frequency range (so that filtering of the amplified signal may not be necessary).

[0027] FIG. 4 is a schematic diagram of a receiver 54 (e.g., a receiving circuit) that may be part of the transceiver 30, according to an embodiment of the present disclosure. As shown, the receiver 54 may receive received data 80 in the form of an analog signal from one or more antennas 55. A low-noise amplifier (LNA) 81 may amplify the received analog signal to an appropriate level for processing by the receiver 54. A mixer 82 may vary the frequency of the amplified signal via a voltage-controlled oscillator 84 (VCO). The VCO 84 may be the same as or similar to the VCO 66 of the transmitter 52 described above. A filter 85 (e.g., a filter circuit and / or software) may remove undesired noise, such as cross-channel interference, from the signal. The filter 85 may also remove additional signals at frequencies other than the desired signal received by one or more antennas 55. The filter 85 may include any suitable filter or filters that remove undesired noise or signals from the received signal, such as a band-pass filter, a band-stop filter, a low-pass filter, a high-pass filter, and / or a decimation filter. A demodulator 86 may remove the radio frequency envelope and / or extract a demodulated signal from the filtered signal for processing. An analog-to-digital converter (ADC) 88 may receive the demodulated analog signal and convert it to a digital signal of incoming data 90 for further processing by the electronic device 10. Additionally, the receiver 54 may include any suitable additional components not shown, or may not include certain of the components shown, to enable the receiver 54 to receive the incoming data 80 via one or more antennas 55. For example, the receiver 54 may include additional mixers and / or digital downconverters (e.g., to convert the input signal from an intermediate frequency to a baseband frequency).

[0028] Embodiments herein provide an inductor topology that reduces phase noise. In the parallel figure-eight inductor configuration of the present disclosure, two coils of an inductor are arranged in parallel, and the total inductance of the inductor is approximately half the inductance of each coil (when each coil has an equivalent inductance). With the parallel figure-eight inductor configuration, the inductance and inner diameter of each coil can be larger (e.g., compared to a series figure-eight inductor configuration), which can improve the quality factor of the inductor. That is, a series figure-eight inductor configuration may have two coils arranged in series, and therefore the total inductance of the series figure-eight inductor can be the sum of the inductances of each coil. Therefore, the parallel figure-eight inductor configuration can produce lower phase noise due to the reduced inductance and increased quality factor.

[0029] With the above in mind, and for comparison, FIG. 5 illustrates an inductor 100 having two coils in a figure-eight configuration in series. The first series coil 102 may have an inner diameter 104. The inner diameter 104 may be greater than 1 micrometer, such as between 5 micrometers and 80 micrometers, between 30 micrometers and 70 micrometers, between 40 micrometers and 60 micrometers, 45 micrometers, and / or 55 micrometers. The inner diameter 104 of the first series coil 102 may define the inductance L of the first series coil 102. The first series coil 102 may generate a magnetic flux 106 (e.g., in a positive direction along the z-axis, i.e., "out" of the page or paper of FIG. 5) when a current is applied to the first series coil 102 (e.g., in a counterclockwise direction 105). The first series coil 102 may be in series with the second series coil 108, and the second series coil 108 may be coupled to the first series coil 102 via a first junction 109 and a second junction 111. The second series coil 108 may receive current from the first series coil 102 via the first junction 109 and complete the circuit via the second junction 111. Furthermore, the second junction 111 may overlap the first junction 109 (e.g., be located above or on a different x-y plane than the first junction 109 with respect to the z-axis), although in alternative embodiments, the first junction 109 may overlap the second junction 111. The second junction 111 may be coupled to the first series coil 102 via connection 115A. That is, the connection portion 115A may be disposed between the xy plane in which the first series coil 102 is disposed and the xy plane in which the second junction portion 111 is disposed, and / or may include these planes. Similarly, the second junction portion 111 may be coupled to the second series coil 108 via the connection portion 115B. That is, the second connection portion 115B may be disposed between the xy plane in which the second series coil 108 is disposed and the xy plane in which the second junction portion 111 is disposed, and / or may include these planes.

[0030] The second series coil 108 may have an inner diameter approximately the same as the inner diameter 104. Thus, the inner diameter 104 of the second series coil 108 may define the same inductance L as the first series coil 102. The second series coil 108 may generate a magnetic flux 113 that is equal in magnitude but opposite in direction (e.g., in the negative direction along the z-axis, i.e., "into" the page or plane of FIG. 5 ) to the magnetic flux 106 when a current is applied to the second series coil 108 (e.g., in a clockwise direction 107). The magnetic flux 106 of the first series coil 102 may be equal in magnitude and opposite in direction to the magnetic flux 113 of the second series coil 108. This may result in magnetic flux cancellation of the magnetic fluxes 106, 113 generated by the current flowing through each coil. In some embodiments, the direction of the magnetic flux 106, 113 along the z-axis of the first series coil 102 and the second series coil 108 may be switched.

[0031] In some embodiments, the first series coil 102 and the second series coil 108 may be coupled to one or more circuit components (e.g., resistors, capacitors, additional inductors, transistors, diodes, etc.) of the VCO 66 of the transmitter 52, although in additional or alternative embodiments, the first series coil 102 and the second series coil 108 may be coupled to any other suitable components to reduce phase noise. For example, when the inductor 100 is coupled in series, the first circuit component may provide or output current to the inductor 100 via the positive trace 110 (e.g., a positive pin or terminal), and that current may be transmitted to the second circuit component via the negative trace 112 (e.g., a negative pin or terminal). When the inductor 100 is coupled in parallel, the first circuit component and the second component may be a single component. The first series coil 102 may be directly coupled to the positive and negative traces 110 and 112 (e.g., without any intermediate circuitry or components between the first series coil 102 and the electronic components), while the second series coil 108 may not be directly coupled to the positive and negative traces 110 and 112. That is, the input 114 of the first series coil 102 may be coupled to the positive trace 110, and the output 116 may be coupled to the negative trace 112.

[0032] As mentioned above, it is desirable to reduce the phase noise of VCO 66 and / or VCO 84. The phase noise in decibels relative to the carrier per Hertz (Hz) (dBc) may be determined using Equation 1 below, in dBc / Hz.

number

[0033] Equation 1 is based on the Coulomb constant (K), temperature (T), and quality factor (Q t or Q), power consumption value (P DC ), current and voltage efficiencies (α I and α V), the noise factor of the transistor (γ), the center frequency (ω), and the offset frequency (Δω). Since many of these factors are static or dependent on the environment, the quality factor (Q) and P DC can be reasonably modified to reduce the phase noise. Thus, by increasing the quality factor (Q), P DC Decreasing φ can reduce the overall phase noise.

[0034] P DC Increasing the inner diameter 104 of the inductor 100 may reduce the inductance L of the inductor 100. The inductance of the inductor 100 is directly correlated to the inner diameter 104 of the inductor 100; that is, as the inner diameter 104 decreases, the inductance decreases. Due to the series topology of the inductor 100, the total inductance of the inductor 100 is the sum of the inductance of the first series coil 102 and the inductance of the second series coil 108. Therefore, reducing the inner diameter 104 (e.g., of one or both coils) can lower the total inductance of the inductor 100, thereby reducing P DC , which may reduce phase noise. However, as the inner diameter 104 decreases, the quality factor (Q) of the inductor 100 also decreases. This may result in higher overall phase noise.

[0035] With the above in mind, FIG. 6 illustrates an inductor 120 having two coils in parallel in a figure-eight configuration, according to an embodiment of the present disclosure. The first coil 122 may have an inner diameter 124. The inner diameter 124 of the first coil 122 may define the inductance L of the first coil 122. The inner diameter 124 may be greater than 1 micrometer, such as between 5 micrometers and 150 micrometers, between 30 micrometers and 120 micrometers, between 50 micrometers and 100 micrometers, between 60 micrometers and 90 micrometers, and / or between 70 micrometers and 85 micrometers. For example, the inner diameter 124 may be approximately 100 micrometers. When a current is applied by positive trace 110, the current may travel (e.g., in a counterclockwise direction 123) through first coil 122 and return through a circuit path or shared branch 129 (e.g., bisecting inductor 120), generating magnetic flux 125 (e.g., in a positive direction along the z-axis, i.e., "out" of the plane or page of FIG. 6). First coil 122 may be positioned symmetrically opposite second coil 128 with respect to shared branch 129.

[0036] The second coil 128 may have an inner diameter approximately the same as the inner diameter 124. Thus, the inner diameter 124 of the second coil 128 may provide the same inductance L as the first coil 122. When current is imparted by the positive trace 110, the current may also travel through the second coil 128 (e.g., in a clockwise direction 126 and approximately simultaneously or concurrently with the current traveling through the first coil 122) and return through the shared branch 129, generating a magnetic flux 127 having the same magnitude but in the opposite direction (e.g., in the negative direction along the z-axis, i.e., "into" the page or plane of FIG. 6 ) as the magnetic flux 125 when current was imparted to the first coil 122. This may result in magnetic flux cancellation of the magnetic fluxes 125, 127 generated by the current traveling through each coil 122, 128, respectively. In some embodiments, the direction of the current, and therefore the direction of the magnetic flux 125, 127 along the z-axis of the first coil 122 and the second coil 128, may be swapped. In alternative embodiments, the second coil 128 may have an inner diameter different from the inner diameter 124. This would cause the second coil 128 to generate a magnetic flux having a different magnitude than the magnetic flux 127 when a current is applied, although additional circuitry or components may be used to create a magnetic flux that compensates for the difference in the magnetic flux generated by each coil 122, 128.

[0037] In some embodiments, the first coil 122 and the second coil 128 may be coupled directly (without any intermediate circuitry or components) to the positive trace 110 and the negative trace 112. When the inductor 120 is coupled in series, the positive trace 110 may be coupled to a first circuit component, and the negative trace 112 may be coupled to a second circuit component. In particular, the first circuit component may provide an input signal having a current to the inductor 120 via the positive trace 110, and the inductor 120 may reduce phase noise of the input signal to generate an output signal at the negative trace 112 to the second circuit component. When the inductor 120 is coupled in parallel, the first circuit component and the second component may be a single component.

[0038] The first coil 122 and the second coil 128 may be coupled to the positive trace 110 at a shared input 130, and the first coil 122 and the second coil 128 may further be coupled to the negative trace 112 at a shared output 132. The shared input 130 for the first coil 122 and the second coil 128 may include a connection 138A that couples to the first coil 122 and the second coil 128. That is, the connection 138A may be located between and / or include an xy plane in which the first coil 122 is located and an xy plane in which the second coil 128 is located. The shared output input 132 may include a connection 138B that couples to the first coil 122 and the second coil 128. That is, connection 138B may be located between and / or include the xy plane in which first coil 122 is located and the xy plane in which second coil 128 is located. That is, input 130 and output 132 are shared between first coil 122 and second coil 128. From shared input 130, current may branch or split to each coil 122, 128. The current may recombine at shared output 132 via shared branch 129 and be coupled to negative trace 112. Second coil 128 may receive current from input 130 via junction 134 located below junction 136 connecting shared branch 129 to negative trace 112 (e.g., on an xy plane with a larger z value than junction 136), although in some embodiments, second coil 128 may be located above junction 136 (e.g., on an xy plane with a larger z value than junction 136). Junction 134 may be coupled to second coil 128 via connection 138C. That is, connection 138C may be located between and / or include the xy plane in which second coil 128 is located and the xy plane in which junction 134 is located. First coil 122 may be described as being “parallel” to second coil 128 because current enters coils 122, 128 from positive trace 110, travels through coils 122, 128, and exits coils 122, 128 from shared branch 129 and negative trace 112 at approximately the same time (e.g., approximately the same time).

[0039] As shown, at least a portion of each of the first coil 122 and the second coil 128 may include an octagonal shape. For example, the octagonal portion of each of the first coil 122 and the second coil 128 may have six 135° angles between seven sides, with one of the seven sides (the portion of the shared branch 129) forming a first line and another of the seven sides (the one closest to the shared input 130) forming a second line that intersects the first line (e.g., at a 90° angle). In practice, each coil 122, 128 may have a total of seven sides.

[0040] To further illustrate the topology of the inductor 120 in which two coils are in parallel, FIGS. 7A and 7B show the inductor 120 of FIG. 6 in three dimensions, according to an embodiment of the present disclosure. FIG. 7A is a top view of the inductor 120. As shown, the connection 131 of the first coil 122 to the input 130 is routed on a first xy plane located above (e.g., having a larger z-value than) the junction 134 of the second coil 128 to the input 130. Notably, the connection 131 of the first coil 122 to the input 130 may be at the same level or xy plane as the junction 136 that couples the shared branch 129 to the negative trace 112. In additional or alternative embodiments, the junction 134 of the second coil 128 to the input 130 may be located below (e.g., on an xy plane with a smaller z-value than) the connection 131 and junction 136 of the first coil 122 to the input 130. Additionally, the shared branch 129 may combine current from each coil 122, 128 into the output 132 at a junction 144 at the same level or along the x-y plane as the junction 136 connecting the shared branch 129 to the negative trace 112, and above (e.g., at a more positive value along the z-axis than junction 134) the junction 134 from the second coil 128 to the input 130. Thus, the first coil 122 and the second coil 128 may be configured such that the connection 131 of the first coil 122 to the input 130 and the junction 136 connecting the shared branch 129 to the negative trace 112 overlap. Furthermore, as shown, the shared branch 129 overlaps the junction 136.

[0041] Additionally, the metal of inductor 120 may have a thickness greater than 0.1 micrometer, such as between 0.1 micrometers and 10 micrometers, between 0.5 micrometers and 5 micrometers, between 1 micrometer and 4 micrometers, between 2.5 micrometers and 3.8 micrometers, and / or between 3 micrometers and 3.7 micrometers, suitable for carrying current and reducing the height of inductor 120 to better fit within electronic device 10. Additionally, the metal of connection 131 of input 130 of second coil 128 may have a thickness greater than 0.01 micrometer, such as between 0.01 micrometers and 2.5 micrometers, between 0.1 micrometers and 1.5 micrometers, between 0.25 micrometers and 1 micrometer, and / or between 0.5 micrometers and 0.8 micrometers, suitable for carrying current and reducing the height of inductor 120 to better fit within electronic device 10. Additionally, the metal of the connection of input portion 130 of second coil 128 located at junctions 134 and 136 may have a thickness greater than 0.01 micrometer, such as 0.01 micrometer to 2.5 micrometers, 0.1 micrometer to 1.5 micrometers, 0.25 micrometer to 1 micrometer, and / or 0.7 micrometer to 0.9 micrometers, suitable for conducting current and allowing junctions 134 and 136 to overlap one another without excessively increasing the height of inductor 120. In some embodiments, the metal of inductor 120 may be replaced with any suitable conductive material.

[0042] 5, the first series coil 102 and the second series coil 108 of the inductor 100 are in series with each other. As such, the total inductance L of the inductor 100 may be the sum of the inductances of both coils. In contrast, in the topology of the inductor 120 of FIG. 6, the inputs and outputs of the first coil 122 and the second coil 128, respectively, may be directly (e.g., without any intervening components or circuitry) coupled to the positive and negative traces 110 and 112 such that the first coil 122 and the second coil 128 are in parallel with each other, such that the inductance of the inductor 120 may be determined using Equation 2 below:

number

[0043] Equation 2 may define the total inductance of inductor 120, the inductance L1 of first coil 122, and the inductance L2 of second coil 128. When the inductances (L1) of first coil 122 and (L2) of second coil 128 are equivalent, the layer inductance L of inductor 120 is TOTAL may be approximately half the inductance of one of the coils.

[0044] The parallel figure-eight configuration of inductor 120 may avoid drawbacks of other inductor configurations that do not use two coils in parallel. For example, if the inputs of two coils are coupled together through a first resistor and the outputs of the two coils are coupled together through a second resistor, the two coils may be too far from each other to achieve sufficient flux cancellation of the magnetic flux generated by the currents traveling through each coil. However, both coils may be coupled to a single high-speed capacitor bank, where the input and output of each coil are connected together.

[0045] In another configuration, two coils may be located close to each other, but with the input and output of each coil facing in opposite directions. Therefore, the two coils may not be coupled together. The proximity of the two coils provides adequate flux cancellation of the magnetic flux generated by the currents flowing through each coil. However, each coil may receive power from its respective high-speed capacitor bank asynchronously. For proper inductor guidance and performance, the high-speed capacitor banks may need to be synchronized with each other. In comparison, the parallel figure-eight configuration of inductor 120, by its topology, avoids the drawbacks inherent in these configurations.

[0046] With the above in mind, FIG. 8 is a plot 150 illustrating inductances 152 and 154 of inductor 100 of FIG. 5 and inductances 156 and 158 of inductor 120 of FIG. 6 in accordance with an embodiment of the present disclosure. As shown in plot 150, the x-axis represents frequency (GHz) and the y-axis represents inductance in henries (H). Inductance 152 corresponds to the total inductance of inductor 100 at 125° C. (Celsius), inductance 154 corresponds to the total inductance of inductor 100 at 55° C., inductance 156 corresponds to the total inductance of inductor 120 at 125° C., and inductance 158 corresponds to the total inductance of inductor 120 at 125° C. As shown, inductances 152, 154, 156, and 158 generally increase as the corresponding frequency increases. Notably, at a particular frequency 151, the inductances of inductor 100 and inductor 120 may be comparable. In one example, when that particular frequency 151 is approximately equal to about 25.00 GHz, inductances 152 and 154 may be 106.9128 picohenries (pH) and 106.3418 pH, respectively, and inductances 156 and 158 may be 102.9843 pH and 102.5915 pH, respectively.

[0047] 9 is a plot 160 illustrating quality factors 162 and 164 of inductor 100 of FIG. 5 and quality factors 166 and 168 of inductor 120 of FIG. 6 in accordance with an embodiment of the present disclosure. As shown in plot 160, the x-axis represents frequency (GHz) and the y-axis represents quality factor (Q). Plot 160 also shows quality factor 162 of inductor 100 at 125° C., quality factor 164 of inductor 100 at 55° C., quality factor 166 of inductor 120 at 125° C., and quality factor 168 of inductor 120 at 55° C., each illustrating temperature variations and the sensitivity affecting the quality factor.

[0048] At a certain frequency 161, the quality factors 166 and 168 of inductor 120 are greater than the quality factors 162 and 164 of inductor 100. In one example, when the certain frequency 161 is approximately equal to 25.00 GHz, the quality factors 166 and 168 of inductor 120 are 27.2649 and 23.9551, respectively, and the quality factors 162 and 164 of inductor 100 are 20.0021 and 17.5877, respectively. Referring back to FIG. 7 , both inductor 100 and inductor 120 have similar inductances at 25.00 GHz. Thus, the parallel coil configuration of inductor 120 may achieve a higher overall quality factor while achieving similar inductances compared to the series coil configuration of inductor 100, resulting in a greater phase noise reduction (e.g., as evident from Equation 1 above).

[0049] In some embodiments, alternative parallel coil configurations may be implemented within the transceiver 30. For example, FIG. 10 illustrates an alternative configuration of a parallel inductor 170, according to an embodiment of the present disclosure. The first coil 172 of the inductor 170 may have an inner diameter 174. The inner diameter 174 of the first coil 172 may define the inductance L of the first coil 172. When current is applied from the positive trace 110 to the first coil 172 (e.g., in a counterclockwise direction 173), the first coil 172 may generate magnetic flux 175 (e.g., in a positive direction along the z-axis, i.e., "out" of the plane or page of FIG. 10). The current may then return to the negative trace 112 through the shared branch 179. The first coil 172 may be symmetrically positioned opposite the second coil 178 relative to the shared branch 179.

[0050] The second coil 178 may have an inner diameter approximately the same as the inner diameter 174. Thus, the inner diameter 174 of the second coil 178 may define the same inductance L as the first coil 172. When current is applied to the second coil 178 from the positive trace 110 (e.g., in a clockwise direction 176), the second coil 178 may generate a magnetic flux 177 (e.g., in a negative direction along the z-axis, i.e., "into" the page or plane of FIG. 10 ). The current may then return through the shared branch 179. The magnetic flux 175 of the first coil 172 may be equal in magnitude and opposite in direction to the magnetic flux 177 of the second coil 178. This may result in magnetic flux cancellation of the magnetic fluxes 175, 177 generated by each coil. In some embodiments, the directions of the magnetic fluxes 175, 177 along the z-axis of the first coil 172 and the second coil 178, respectively, may be swapped. In alternative embodiments, second coil 178 may have an inner diameter different from inner diameter 174. This may cause second coil 178 to generate a magnetic flux different from magnetic flux 175, although additional circuitry or components may compensate for the difference in magnetic flux generated by each coil.

[0051] In some embodiments, the first coil 172 and the second coil 178 may be coupled directly (without any intermediate circuitry or components) to the positive trace 110 and the negative trace 112. When the inductor 170 is coupled in series, the positive trace 110 may be coupled to a first circuit component, and the negative trace 112 may be coupled to a second circuit component. In particular, the first circuit component may provide an input signal having a current to the inductor 170 via the positive trace 110, and the inductor 170 may reduce phase noise of the input signal to generate an output signal at the negative trace 112 to the second circuit component. When the inductor 170 is coupled in parallel, the first circuit component and the second component may be a single component.

[0052] 10, the first input branch 180A of the first coil 172 and the second input branch 180B of the second coil 178 are each separately coupled to the positive trace 110. That is, each coil 172, 178 has a direct and independent connection to the positive trace 110 (e.g., without any intervening or intermediate circuitry or components). This is in contrast to the configuration of the inductor 120 in FIG. 6, which uses a shared input 130 to couple the first coil 122 and the second coil 128 to the positive trace 110. The input branches 180A, 180B of each coil 172, 178 may be coextensive with, aligned with, or parallel to the shared branch 179.

[0053] In some embodiments, the positive trace 110 may be disposed below the input branches 180A and 180B (e.g., below or above an xy plane having a smaller z value than the input branches 180A and 180B). The positive trace 110 may be coupled to the input branches 180A and 180B via connections 186A and 186B, respectively. That is, the connection 186A may be disposed between and / or include the xy plane in which the input branch 180A is disposed and the xy plane in which the positive trace 110 is disposed. Similarly, the connection 186B may be disposed between and / or include the xy plane in which the input branch 180B is disposed and the xy plane in which the positive trace 110 is disposed.

[0054] As a result of each coil 172, 178 having a direct, independent connection (e.g., input branch 180A, 180B) to positive trace 110, an input signal in the form of an alternating current (AC) voltage wave received from positive trace 110 may be split into two AC voltage waves, each traveling down a respective input branch 180A, 180B. Splitting the input signal in this manner may result in the two split AC voltage waves traversing input branches 180A, 180B being out of phase with each other due to, for example, practical imperfections (e.g., manufacturing imperfections causing input branches 180A, 180B not to have exactly the same dimensions, material composition, environmental conditions, etc.). This may create signal modulation issues, signal-to-noise ratio maximization issues, or other signal processing challenges in circuitry coupled to the output of inductor 170. To reduce or eliminate this phase shift, each of the input branches 180A, 180B of each coil 172, 178 may be coupled together by a coupler 184 to ensure that the signals (e.g., AC voltage waveforms) on each input branch 180A, 180B are in phase with each other. As shown, the coupler 184 may be orthogonal or intersecting with the shared branch 179. That is, the transverse axis of the coupler 184 may be orthogonal or intersecting with the transverse axis of the shared branch 179. The coupler 184 may be located below the connection 181 of the first coil 172 to the input 180 (e.g., below or above an xy plane having a smaller z value than the connection 181). The coupler 184 may be connected to the first coil 172 via connection 186C. That is, connection 186C may be located between the xy plane in which the coupler 184 is located and the xy plane in which the first coil 172 is located. Similarly, coupler 184 may be located below connection 185 of second coil 178 to input 180 (e.g., below or above the xy plane with a smaller z value than connection 185). Coupler 184 may be connected to second coil 178 via connection 186D. That is, connection 186D may be located between the xy plane in which coupler 184 is located and the xy plane in which second coil 178 is located.

[0055] Additionally, the first coil 172 and the second coil 178 may be coupled to the negative trace 112 at a shared output 182. That is, the output 182 is shared between the first coil 172 and the second coil 178. In some embodiments, the negative trace 112 may be located below the shared output 182 (e.g., below or above an xy plane having a smaller z value than the shared output 182). The negative trace 112 may be coupled to the shared output 182 via a connection 186E. That is, the connection 186E may be located between and / or include the xy plane in which the shared output 182 is located and the xy plane in which the negative trace 112 is located.

[0056] From the inputs 180 of the first coil 172 and the second coil 178, current may travel through the first coil 172 and the second coil 178. As previously described in some embodiments, current may travel from only one input 180 of either the first coil 172 or the second coil 178 through the coupler 184 to the opposite coil. In either case, the current may rejoin at the shared output 182 via the shared branch 179 and travel to the negative trace 112. The first coil 172 may be described as being “parallel” to the second coil 178 because the current enters the coils 172, 178 from the positive trace 110, travels through the coils 172, 178, and exits the coils 172, 178 at approximately the same time (e.g., approximately simultaneously) via the shared branch 179 and the negative trace 112 through the shared output 182.

[0057] As shown, at least a portion of each of first coil 172 and second coil 178 may include an octagonal shape. For example, the octagonal portion of each of first coil 172 and second coil 178 may have six 135° angles between seven sides, with one of the seven sides (the portion of shared branch 179) forming a first line and another of the seven sides (the one closest to input branches 180A, 180B) forming a second line that intersects the first line (e.g., at a 90° angle). In practice, each coil 172, 178 may have a total of seven sides.

[0058] To further illustrate the configuration of the inductor 170 in which the two coils are in parallel, FIGS. 11A and 11B show a three-dimensional view of the inductor 170 of FIG. 10 in accordance with an embodiment of the present disclosure. FIG. 11A shows a top view of the inductor 170, and FIG. 11B shows a bottom view of the inductor 170. The connection 181 of the first coil 172 to the input 180 overlaps the coupler 184 (e.g., above or on the xy plane with a larger z value than the coupler 184). In particular, the connection 181 of the first coil 122 to the input 130 may be at the same level or on the xy plane as the connection 185 of the second coil 178 to the input 180 and the shared branch 179 where the first coil 172 and second coil 178 converge. The coupler 184 may couple the inputs 180 of each coil 172, 178 and provide current from the positive trace 110 to the input 180. Thus, the first coil 172 and the second coil 178 may be configured such that the connection 181 to the input 180 of the first coil 172, the connection 185 to the input 180 of the second coil 178, and the shared branch 179 each overlap the coupler 184.

[0059] Additionally, the metal of inductor 170 may have a thickness greater than 0.1 micrometer, such as between 0.1 micrometer and 10 micrometers, between 0.5 micrometer and 5 micrometers, between 1 micrometer and 4 micrometers, between 2.5 micrometer and 3.8 micrometers, and / or between 3 micrometer and 3.7 micrometers, suitable for carrying current and reducing the height of inductor 170 to better fit within electronic device 10. The metal of coupler 184 may have a thickness greater than 0.01 micrometer, such as between 0.01 micrometer and 2.5 micrometers, between 0.1 micrometer and 1.5 micrometers, between 0.25 micrometer and 1 micrometer, and / or between 0.5 micrometer and 0.8 micrometers. The metal of inductor 170 may include or be replaced by any suitable conductive material.

[0060] It should be understood that the specific embodiments described above are shown by way of example, and that these embodiments may be susceptible to various modifications and alternative forms. It is further understood that the claims are not limited to the particular forms disclosed, but rather cover all modifications, equivalents, and alternatives falling within the spirit and intent of this disclosure.

[0061] The technology presented and claimed herein is applied with reference to tangible objects and specific examples of practical nature that clearly advance the art, and therefore is not abstract, insubstantial, or merely theoretical. Furthermore, where any of the claims appended at the end of this specification contain one or more elements recited as "means for [performing] _____ [function]" or "step for [performing] _____ [function]," it is intended that such elements be construed in accordance with 35 U.S.C. 112(f). However, with respect to any of the claims containing elements recited in any other manner, it is not intended that such elements be construed in accordance with 35 U.S.C. 112(f).

[0062] It is understood that use of personally identifiable information should comply with generally recognized privacy policies and practices that meet or exceed industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and handled in a manner that minimizes the risk of unintended or unauthorized access or use, and the nature of authorized uses should be clearly indicated to users.

Claims

1. a first terminal; a second terminal; and a shared branch coupled to the second terminal; a first coil coupled to the first terminal and extending in a counterclockwise direction from the first terminal to the shared branch; a second coil coupled to the first terminal extending in a clockwise direction from the first terminal to the shared branch, the first coil being symmetrical to the second coil about the shared branch; An inductor comprising:

2. The inductor of claim 1 , wherein the first terminal overlaps the second terminal.

3. The inductor of claim 1 , wherein the first terminal is split into the first coil and the second coil.

4. The inductor of claim 1 , wherein the shared branch joins the first coil and the second coil.

5. The inductor of claim 1 , wherein the first coil and the second coil have the same diameter.

6. 2. The inductor of claim 1, wherein the first coil is coupled to the first terminal via a first input branch and the second coil is coupled to the first terminal via a second input branch.

7. The inductor of claim 6 , wherein the first input branch and the second input branch are coextensive with the shared branch.

8. The inductor of claim 6 , further comprising a coupler connecting the first input branch to the second input branch, the transverse axis of the coupler intersecting the transverse axis of the shared branch.

9. The inductor of claim 8 , wherein the shared branch overlaps the coupler.

10. one or more antennas; a transceiver coupled to the one or more antennas, the transceiver including a first circuit, a second circuit, and an inductor, the inductor having a first coil and a second coil coupled to the first circuit, and a shared branch coupled to the first coil and the second coil, bisecting the inductor, and coupled to the second circuit, the first coil being in parallel with the second coil; Electronic devices.

11. The electronic device of claim 10 , wherein the inductor is configured to reduce phase noise generated by the first circuit.

12. 11. The electronic device of claim 10, wherein when a current is applied to the inductor, the first coil generates a first magnetic field and the second coil generates a second magnetic field, the first magnetic field being approximately equal in magnitude to and opposite in direction to the second magnetic field.

13. The electronic device of claim 10 , wherein the first coil and the second coil are each at least partially octagonal in shape.

14. The electronic device of claim 10 , wherein the first coil and the second coil each comprise seven sides.

15. 15. The electronic device of claim 14, wherein each of the seven sides forms an angle of 135 degrees with another of the seven sides.

16. The electronic device of claim 14 , wherein one of the seven sides comprises the shared branch.

17. a first circuit component; a second circuit component; and an inductor; and a voltage controlled oscillator comprising: a first coil coupled to the first circuit component; a second coil coupled to the first circuit component via a junction and in parallel with the first coil; and a shared circuit path coupled to the second circuit component, the first coil, and the second coil, the shared circuit path overlapping the junction.

18. 18. The voltage controlled oscillator of claim 17, wherein the inductor is configured to receive a first signal from the one of the first circuit components and to generate a second signal having less phase noise than the first signal.

19. 20. The voltage controlled oscillator of claim 18, wherein the inductor is configured to output the second signal to the second circuit component.

20. 18. The voltage controlled oscillator of claim 17, wherein the first coil is coupled to the first circuit component via a first input, the first input overlapping the junction coupling the second coil to the first circuit component.

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