Semiconductor device

Abstract

To provide a semiconductor device with excellent electric characteristics, a semiconductor device with high reliability, and a semiconductor device consuming less power.SOLUTION: A semiconductor device includes a gate electrode, a first insulating layer on the gate electrode, a metal oxide layer on the first insulating layer, a pair of electrodes on the metal oxide layer, and a second insulating layer on the pair of electrodes. The first insulating layer includes a first region and a second region. The first region is in contact with the metal oxide layer and includes a region containing more oxygen than the second region. The second region includes a region containing more nitrogen than the first region. The metal oxide layer has at least an oxygen concentration gradient in a film thickness direction, and the oxygen concentration is high on the first region side and the second insulating layer side.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a display device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. The vessel may include a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, and the like. , a storage device, a driving method thereof, or a manufacturing method thereof can be cited as an example. can. [Background technology]

[0004] Oxide semiconductors have been attracting attention as semiconductor materials that can be used in transistors. In Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, The oxide semiconductor layer serving as a channel contains indium and gallium, and the ratio of indium By making μ larger than the gallium fraction, the field effect mobility (simply called μFE) A semiconductor device is disclosed in which the resistance (sometimes referred to as "resistance") is improved.

[0005] An oxide semiconductor that can be used for the semiconductor layer can be formed by a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. In addition, it is possible to improve and use some of the production equipment for amorphous silicon transistors. In addition, transistors using oxide semiconductors have high Because it has high field-effect mobility, it can realize a high-performance display device with an integrated driving circuit. . [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 Summary of the Invention [Problem to be solved by the invention]

[0007] As display devices become more highly precise and semiconductor devices become more highly integrated, there is a demand for miniaturization of transistors. One of the ways to miniaturize transistors is to shorten the channel length. However, in a transistor with a short channel length, the capacitance of the channel region is The carrier density and defect levels significantly affect the electrical characteristics and reliability.

[0008] In view of the above, an object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. It is an object of the present invention to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of the present invention is to provide a method for manufacturing a semiconductor device with high yield. Another object of the present invention is to provide a method for manufacturing a novel semiconductor device. .

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a gate electrode, a first insulating layer on the gate electrode, and a gate insulating layer on the first insulating layer. A metal oxide layer, a pair of electrodes on the metal oxide layer, and a second insulating layer on the pair of electrodes. The metal oxide layer is made of indium and the element M (M is gallium, aluminum, silicon, , boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium tantalum, tungsten, or magnesium), and zinc, The edge layer has a first region and a second region, the first region contacting the metal oxide layer, and The second region has a higher oxygen content than the first region, and the second region has a higher nitrogen content than the first region. The metal oxide layer has a region where the content of oxygen is high, and the metal oxide layer has a region where the concentration of oxygen is high in the thickness direction. The semiconductor device has a concentration gradient, and the concentration gradient is higher on the first region side and the second insulating layer side. be.

[0011] In the semiconductor device described above, the first region has a thickness of 1 nm to 10 nm in the film thickness direction. It is preferable to have a lower region.

[0012] In the above-mentioned semiconductor device, when the atomic ratio of In is 1, the atomic ratio of M is It is preferable that the ratio is 0.5 or more and 1.5 or less, and the atomic ratio of Zn is 0.1 or more and 2 or less. It's nice.

[0013] In the above-mentioned semiconductor device, when the atomic ratio of In is 4, the atomic ratio of M is It is preferable that the ratio is 1.5 or more and 2.5 or less, and the ratio of the number of Zn atoms is 2 or more and 4 or less. .

[0014] In the above-mentioned semiconductor device, when the atomic ratio of In is 5, the atomic ratio of M is It is preferable that the ratio is 0.5 or more and 1.5 or less, and the ratio of the number of Zn atoms is 5 or more and 7 or less. .

[0015] In the semiconductor device, the metal oxide layer comprises a first metal oxide layer and a second metal oxide layer. a second metal oxide layer on the metal layer, the first metal oxide layer being thicker than the second metal oxide layer; It is preferable that the layer has a region with lower crystallinity than the layer.

[0016] In the semiconductor device, the metal oxide layer comprises a first metal oxide layer and a second metal oxide layer. a second metal oxide layer on the metal oxide layer, and a third metal oxide layer in contact with the underside of the first metal oxide layer. and the first metal oxide layer is either the second metal oxide layer or the third metal oxide layer. It is preferable to have a region that is less crystalline than either one or both of them.

[0017] In the above-mentioned semiconductor device, a third insulating layer is further provided on the second insulating layer, and the third insulating layer The edge layer preferably comprises silicon and nitrogen.

[0018] In the above-mentioned semiconductor device, a third insulating layer is further provided on the second insulating layer, and the third insulating layer The edge layer is a mixture of an element X (X being one or more of aluminum, indium, gallium, or zinc) and an acid. It is preferable that the compound contains the element.

[0019] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode and forming a first insulating layer on the gate electrode. a step of adding oxygen to the vicinity of the surface of the first insulating layer; and a step of forming a film on the first insulating layer. forming a metal oxide layer; forming a pair of electrodes on the metal oxide layer; and forming a second insulating layer on the electrode, wherein in the step of forming the metal oxide layer, The metal oxide layer is formed in a vacuum in two separate steps, a first step and a second step. The first step is performed before the second step, and the second step has a larger total amount of deposition gas than the first step. This is a method for manufacturing a semiconductor device having a high oxygen flow rate in the body.

[0020] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of forming a gate electrode and forming a first insulating layer on the gate electrode. a step of adding oxygen to the vicinity of the surface of the first insulating layer; and a step of forming a film on the first insulating layer. forming a metal oxide layer; forming a pair of electrodes on the metal oxide layer; and forming a second insulating layer on the electrode, wherein in the step of forming the metal oxide layer, The metal oxide layer is formed in vacuum in three steps, one after the other. The first step is performed before the second step, and the second step has a larger total amount of deposition gas than the first step. The oxygen flow rate of the body is high, and the third step is performed before the first step, and the first step This is a method for manufacturing a semiconductor device in which the flow rate ratio of oxygen in the entire deposition gas is higher than that in the case of the conventional method. [Effects of the Invention]

[0021] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. A semiconductor device with high performance can be provided. Alternatively, a semiconductor device with low power consumption can be provided. A novel semiconductor device can be provided, or a highly productive method for manufacturing a semiconductor device can be provided. Alternatively, a method for manufacturing a semiconductor device with high yield can be provided. A method for making a body device can be provided.

[0022] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0023] [Figure 1] 1 shows an example of the configuration of a semiconductor device. [Figure 2] 1 is a conceptual diagram showing the path of oxygen diffusing into a semiconductor layer. [Figure 3] FIG. 4 is a cross-sectional view showing an example of a gap portion. [Figure 4] 1 shows an example of the configuration of a semiconductor device. [Figure 5] 1 shows an example of the configuration of a semiconductor device. [Figure 6] 1 shows an example of the configuration of a semiconductor device. [Figure 7] 1 shows an example of the configuration of a semiconductor device. [Figure 8] 1 shows an example of the configuration of a semiconductor device. [Figure 9] 1 shows an example of the configuration of a semiconductor device. [Figure 10] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 12] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 15] 1 shows an example of the configuration of a display device. [Figure 16] 1 shows an example of the configuration of a display device. [Figure 17] 1 shows an example of the configuration of a display device. [Figure 18] 1 shows an example of the configuration of a display device. [Figure 19] 1 shows an example of the configuration of a display device. [Figure 20] 1 shows an example of the configuration of a display device. [Figure 21] 1A and 1B are a block diagram and a circuit diagram of a display device. [Figure 22] FIG. [Figure 23] An example of the configuration of electronic devices. [Figure 24] 1 shows an example of the configuration of a television device. [Figure 25] 1 is an XPS spectrum according to Example 1. [Figure 26] 1 is a cross-sectional TEM image according to Example 1. [Figure 27] 1 is a cross-sectional TEM image according to Example 1. [Figure 28] FIG. 10 is a diagram for explaining measurement coordinates of a sample according to Example 2. [Figure 29] 1 is an XRD spectrum according to Example 2. [Figure 30] 1 is an XRD spectrum according to Example 2. [Figure 31] 1 is an XRD spectrum according to Example 2. [Figure 32] 1 is an XRD spectrum according to Example 2. [Figure 33] 10 shows the Id-Vg characteristics of a transistor according to Example 3. [Figure 34] 10 shows the Id-Vg characteristics of a transistor according to Example 3. [Figure 35] 10 shows the Id-Vg characteristics of a transistor according to Example 3. [Figure 36] 10 shows the Id-Vg characteristics of a transistor according to Example 3. [Figure 37] 10 shows the results of a GBT test on the transistor according to Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0024] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0025] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations and are not limited to the shapes or values shown in the drawings.

[0026] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. It should be noted that this is added to avoid confusion and is not intended to limit the number.

[0027] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0028] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal It has a channel region, and current flows between the source and drain through the channel region. In this specification and the like, the channel region is a region through which a current mainly flows. This refers to the area where the fluid flows.

[0029] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0030] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0031] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0032] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0033] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source When gs is lower than the threshold voltage Vth, the gate and This refers to the state in which the voltage Vgs between the n-channel and n-channel transistors is higher than the threshold voltage Vth. The off-state current of a transistor is the voltage between the gate and source, Vgs, that is, the threshold voltage, Vt It may refer to the drain current when it is lower than h.

[0034] The off-state current of a transistor may depend on Vgs. The off-state current is I or less if there is a Vgs value at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows in the off state at a given Vgs. , an off-state at Vgs within a predetermined range or a sufficiently reduced off-current is obtained. It may refer to the off-state current at Vgs.

[0035] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The on-current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -1 3 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vg The drain current at s = -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: , or 1×10 when Vgs is in the range of -0.5V to -0.8V -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 A or less Vgs exists. Therefore, the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0036] In this specification and the like, the off-state current of a transistor having a channel width W is calculated based on the It is sometimes expressed as the current value that flows per watt. In the latter case, the unit of the off-state current is current / length. It may be expressed in units with an element (e.g., A / μm).

[0037] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the values are measured at room temperature, 60°C, 85°C, 95°C, or 125°C. It may also represent the current that is generated when the reliability of a semiconductor device that includes the transistor is guaranteed. or the temperature at which a semiconductor device containing the transistor is used (e.g. For example, the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less at room temperature, 60°C, 85°C, 95°C, 125°C, The temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or The temperature at which the semiconductor device containing the transistor is used (for example, any one of 5°C to 35°C) (temperature), there exists a value of Vgs at which the off-state current of the transistor is less than I. It may point to.

[0038] The off-state current of a transistor can depend on the voltage Vds between the drain and source In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or In some cases, the value represents the off-state current at 20 V. Alternatively, the value represents the off-state current of the semiconductor containing the transistor. Vds that guarantees the reliability of semiconductor devices, or semiconductor devices that include the transistor The off-state current of a transistor at Vds is sometimes used in The current is I or less when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, transistors included Vds that guarantees the reliability of the semiconductor device in which the transistor is used, or the semiconductor Vds used in semiconductor devices, etc., where the off-state current of the transistor is I or less It may refer to the existence of a gs value.

[0039] In the above description of the off-state current, the drain may be read as the source. Current may also refer to the current through the source when the transistor is in the off state.

[0040] In this specification and the like, the term "leak current" may be used to mean the same thing as "off-state current." In this specification, the off-state current is, for example, the current when a transistor is in an off state. , may refer to the current flowing between the source and drain.

[0041] In this specification, the threshold voltage of a transistor is the voltage at which a channel is formed in the transistor. This refers to the gate voltage (Vg) when a gate electrode is formed. Specifically, it refers to the threshold voltage of a transistor. The voltage is plotted by plotting the gate voltage (Vg) on the horizontal axis and the square root of the drain current (Id) on the vertical axis. In the simulated curve (Vg-√Id characteristics), the tangent line with the maximum slope is extrapolated to form a straight line. , the gate voltage (Vg Alternatively, the threshold voltage of a transistor can be expressed as the channel length L and the The channel width is W, and the value of Id[A]×L[μm] / W[μm] is 1×10 -9 [A] and It may also refer to the gate voltage (Vg) applied to the device.

[0042] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the dielectric constant is low enough, it may have the properties of an "insulator." The boundary between "insulator" and "insulator" is vague and it may not be possible to strictly distinguish them. The terms "semiconductor" and "insulator" described in the above may be interchangeable in some cases.

[0043] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the electrical conductivity is high enough, it may have the properties of a "conductor." The boundary between "conductor" and "electroconductor" is vague and it may not be possible to strictly distinguish them. The terms "semiconductor" and "conductor" described in the above may be interchangeable in some cases.

[0044] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplifying and rectifying properties. and a switching action, the metal oxide is A semiconductor (metal oxide semiconductor), abbreviated as OS. In addition, when describing OS FET, it is possible to use a metal oxide or an oxide semiconductor. In other words, it is a transistor having a conductor.

[0045] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0046] In the present specification and the like, CAAC (c-axis aligned crystal) l), and when written as CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Represents an example.

[0047] In this specification and the like, CAC-OS or CAC-metal oxide means , a part of the material has a conductive function and a part of the material has an insulating function, and the whole of the material has a It functions as a semiconductor. When de is used in the active layer of a transistor, the conductive function is to transfer electrons (or The insulating function is the function that prevents the flow of electrons, which are carriers. By making the conductive function and insulating function work in a complementary manner, The function to switch the device on / off is set to CAC-OS or CAC-metal. It can be added to CAC-OS or CAC-metal oxide. By separating the functions of each, it is possible to maximize the functions of both. can.

[0048] In this specification and the like, CAC-OS or CAC-metal oxide means The conductive region has the above-mentioned conductive function and the insulating region. The conductive region has the insulating function described above. The regions may be separated at the nanoparticle level. The conductive areas may be unevenly distributed in the material. They may be observed connected in a dot-like pattern.

[0049] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0050] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used for the channel region of a transistor. When the transistor is turned on, the current driving force is high, that is, the on-state current is large, and Therefore, a high field effect mobility can be obtained.

[0051] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0052] An example of the crystal structure of a metal oxide will be described below. Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The following will be explained as an example of a metal oxide film formed by the ring method. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is called sIGZO, and the substrate temperature is room temperature (RT) using the above target. Metal oxides formed by sputtering are called tIGZO. For example, sIGZ O is either nc (nano crystal) or CAAC or both crystals In addition, tIGZO has a crystal structure of nc. RT) includes the temperature when the substrate is not intentionally heated. , multiple IGZO nanocrystals are c-axis oriented and connected without orientation in the ab plane. It is a crystal structure.

[0053] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image or the like on a display surface. Therefore, a display panel is one aspect of an output device.

[0054] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuit) or TCP (Tape Carrier Packet ge) or a connector such as COG (Chip On Ground) is attached to the board. The IC mounted on the display panel module is called a display module. It may also be called a display panel or simply a display panel.

[0055] In this specification, a touch sensor is a sensor that is touched by a detected object such as a finger or a stylus. It has the function of detecting when something is pressed or approached. Therefore, the touch sensor is one aspect of the input device. For example, a touch sensor may have one or more sensor elements.

[0056] In addition, in this specification and the like, a substrate having a touch sensor is referred to as a touch sensor panel or a single In this specification, the base of the touch sensor panel is A board with a connector, such as an FPC or TCP, attached, or a substrate A device with an IC mounted on it using the COG method or other methods is called a touch sensor panel module. It may be called a sensor module, a sensor module, or simply a touch sensor.

[0057] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images and the like on a display surface. The display function (output) and the function of detecting when a finger or stylus touches or presses the display surface. It also has a function as a touch sensor that detects approaching. A touch panel is one type of input / output device.

[0058] The touch panel is, for example, a display panel (or display device) with a touch sensor, It can also be called a display panel (or display device) with a display function.

[0059] The touch panel may also have a configuration including a display panel and a touch sensor panel. Alternatively, the display panel may have a touch sensor function inside or on its surface. It is also possible.

[0060] In addition, in this specification, a substrate of a touch panel is provided with a connector such as an FPC or TCP. Those with connectors attached, or those with ICs mounted on the board using the COG method, etc. When referred to as a touch panel module, display module, or simply a touch panel, There is.

[0061] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. Here, a transistor which is one embodiment of a semiconductor device will be described.

[0062] A transistor of one embodiment of the present invention includes a first conductive layer having a function as a gate electrode, The first insulating layer having a function as a gate insulating layer, the semiconductor layer, and the source electrode a second conductive layer and a third conductive layer having a function as a gate electrode or a drain electrode, and a protective layer The insulating layer has a second insulating layer and a third insulating layer having the above functions.

[0063] The semiconductor layer is preferably a metal oxide film. are gallium, aluminum, silicon, boron, yttrium, tin, copper, and vanadium. , beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum Tungsten, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable that the element M contains one or more of aluminum, gallium, yttrium, and zinc. Thorium or tin is preferred.

[0064] By using a metal oxide film with a low impurity concentration and a low defect level density as the semiconductor layer, This is preferable because it allows the fabrication of a transistor with excellent electrical characteristics. A low impurity concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. A semiconductor layer that is highly intrinsic or substantially highly intrinsic has fewer carrier sources. Therefore, the carrier density can be reduced. A transistor having a negative threshold voltage (also called a normally-on transistor) has electrical characteristics. ) is suppressed. In addition, a semiconductor layer that is highly pure intrinsic or substantially highly pure intrinsic is In the case of high purity pure silicon, the defect level density is low, so the trap level density may also be low. Semiconductor layers that are pure or substantially intrinsic have significantly lower off-state currents.

[0065] The carrier density and defect levels in the channel region of a transistor affect the electrical characteristics of the transistor. In particular, in transistors with short channel lengths, the channel region The carrier density and defect level of the semiconductor significantly affect the electrical characteristics and reliability. By reducing the carrier density and defect levels in the channel region, transistors with short channel lengths can be fabricated. The capacitor also has good electrical characteristics and reliability.

[0066] Oxygen is released from the metal oxide film of the semiconductor layer, causing oxygen vacancies (hereinafter referred to as Vo). If there are many oxygen vacancies in the semiconductor layer, The density of defect states may increase, adversely affecting the electrical characteristics and reliability of transistors. Therefore, in the transistor manufacturing process, it is necessary to introduce a sufficient amount of oxygen into the semiconductor layer. By introducing oxygen vacancies, we can create highly reliable transistors with good electrical properties. In addition to the reduction of oxygen vacancies, the oxygen vacancies can be eliminated in the manufacturing process of the transistor. It is also important to suppress the occurrence of

[0067] When oxygen vacancies and hydrogen exist in the semiconductor layer, hydrogen enters the oxygen vacancies (hereinafter referred to as V The VoH can be a carrier source and This may adversely affect the electrical characteristics and reliability of the transistor. By reducing hydrogen and VoH, the carrier density can be reduced, resulting in good electrical properties and high reliability. This allows for the production of highly reliable transistors. It is important to prevent the diffusion of hydrogen-containing impurities into the semiconductor layer. Examples of impurities include hydrogen and water.

[0068] One method for reducing oxygen vacancies in a semiconductor layer is to form a layer that can release oxygen by heating. By placing the layer in the vicinity of the semiconductor layer and subjecting it to heat treatment, oxygen is supplied from the layer to the semiconductor layer. The following method can be used.

[0069] The second insulating layer, which functions as a protective layer, is in contact with the upper surface of the semiconductor layer. The second insulating layer preferably contains oxygen. It is more preferable that the insulating film contains a large amount of oxygen. For example, the insulating film contains silicon and oxygen. It is preferable to use a film or an insulating film containing silicon, oxygen, and nitrogen.

[0070] In this specification, oxygen contained in excess of the stoichiometric composition is referred to as excess oxygen (exO). Alternatively, the excess oxygen may be, for example, a film or layer containing oxygen that is formed by heating. Excess oxygen can migrate, for example, inside a film or layer. The movement of oxygen occurs between atoms in the film or layer, or while replacing oxygen that makes up the film or layer. In this specification, excess oxygen (exO) It is sometimes simply referred to as oxygen.

[0071] By providing a second insulating film on the semiconductor layer and then performing heat treatment, the semiconductor layer is formed from the second insulating film. Oxygen diffuses into the semiconductor layer, and is supplied into the semiconductor layer. When oxygen approaches an oxygen vacancy in the semiconductor layer, it is captured by the oxygen vacancy and the oxygen vacancy is filled. Furthermore, when oxygen approaches the hydrogen contained in the semiconductor layer, the oxygen and hydrogen react to form water (H2O ) and desorbs from the semiconductor layer as water molecules. When the temperature approaches , oxygen compensates for the oxygen vacancy of VoH. The water reacts with the oxygen in the second insulating layer to form water, which is then desorbed from the semiconductor layer. The oxygen contained in the insulating layer can reduce oxygen vacancies, hydrogen, and VoH in the semiconductor layer. Cut.

[0072] The third insulating layer, which functions as a protective layer, is in contact with the upper surface of the second insulating layer. The insulating layer is preferably made of a material having a higher nitrogen concentration than the second insulating layer. It is preferable that the insulating film has silicon and nitrogen as its main components. The insulating film has the characteristic that water, hydrogen, oxygen, etc. are difficult to diffuse. By providing a third insulating layer on the insulating layer, oxygen is prevented from diffusing from the semiconductor layer and the second insulating layer to the outside. Therefore, the increase in oxygen vacancies in the semiconductor layer can be suppressed. can.

[0073] The third insulating layer may be, for example, an element X (X is aluminum, indium, gallium, or In particular, oxides containing metals and oxygen as the main components can be used. For example, the third insulating layer may be made of aluminum oxide or In-Ga-Zn oxide can be used.

[0074] Furthermore, voids may occur in the second insulating layer. Impurities such as water and hydrogen diffuse from the outside into the semiconductor layer through the hole, increasing the amount of hydrogen in the semiconductor layer. By providing a third insulating layer on the second insulating layer and covering the gap, This prevents impurities from diffusing into the semiconductor layer from the outside, and increases hydrogen in the semiconductor layer. can be suppressed.

[0075] By providing a third insulating layer on the second insulating layer, oxygen vacancies, hydrogen and Vo in the semiconductor layer can be eliminated. Therefore, it is possible to produce a transistor with good electrical characteristics and high reliability. You can create a data.

[0076] A more specific example of one embodiment of the present invention will be described below with reference to the drawings. A transistor will be described as an example of a semiconductor device.

[0077] <Configuration example 1> 1A is a top view of a transistor 100A, which is a semiconductor device of one embodiment of the present invention, and FIG. 1B is a cross-sectional view of the transistor 100A. The diagram is shown in Fig. 1(B) and Fig. 1(C). Fig. 1(B) shows the structure of the dashed line X1- 1(C) corresponds to a cross-sectional view of the cutaway view at X2, and FIG. 1(C) is a cross-sectional view of the cutaway view of the cutaway view taken along the dashed line Y1- It corresponds to the cross-sectional view of the cutaway view at Y2. In order to avoid this, some of the components of the transistor 100A (such as the gate insulating layer) are omitted in the illustration. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is In addition, in the top view of the transistor, In the drawings, as in FIG. 1(A), some of the components may be omitted.

[0078] The transistor 100A includes a conductive layer 104 on a substrate 102 and a semiconductor layer 104 between the substrate 102 and the conductive layer 104. 4, an insulating layer 106 on the insulating layer 106, a metal oxide layer 108 on the metal oxide layer 108, The conductive layer 112a and the conductive layer 112b are in contact with the upper surface and are provided on the metal oxide layer 108 with a gap therebetween. The conductive layer 112a, the conductive layer 112b, and the metal oxide layer 108 are formed on the conductive layer 112a, the conductive layer 112b, and the metal oxide layer 108. It has an insulating layer 114 and an insulating layer 116 on the insulating layer 114 .

[0079] A part of the conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode. The insulating layer 112b functions as the other of the source electrode and the drain electrode. Each edge layer 116 functions as a protective layer.

[0080] The transistor 100A is a so-called channel-etched, single-gate transistor. It is a star.

[0081] As shown in FIGS. 1A, 1B, and 1C, the metal oxide layer 108 is a first A metal oxide layer 108a and a second metal oxide layer 108b on the first metal oxide layer 108a. It is preferable that the laminated structure be:

[0082] The first metal oxide layer 108a and the second metal oxide layer 108b are each a metal oxide The first metal oxide layer 108a and the second metal oxide layer 108b preferably contain The above-mentioned materials can be used for the respective electrodes.

[0083] The first metal oxide layer 108a and the second metal oxide layer 108b each contain In atoms. When the atomic ratio of M is larger than the atomic ratio of M, the field effect mobility of the transistor can be increased. As an example, the first metal oxide layer 108a and the second metal oxide layer The atomic ratio of In, M, and Zn in 108b is In:M:Zn=4:2:3, respectively. or a ratio of In:M:Zn=5:1:7 or a ratio of In:M:Zn=5:1:7 or a ratio of In:M:Zn=7 ... is preferable. Here, "near" means that when In is 4, M is 1.5 or more and 2.5 or less, and Zn is 2. If In is 5, M is 0.5 to 1.5 and Zn is 5 or less. The first metal oxide layer 108a and the second metal oxide layer 108b are formed in approximately the same thickness. By using the same composition, it can be formed using the same sputtering target, which reduces manufacturing costs. can be suppressed.

[0084] The first metal oxide layer 108a and the second metal oxide layer 108b are made of In, M, and The ratio of the number of In and Zn atoms is set to In:M:Zn=1:1:1 or close to that. Here, the neighborhood means that when In is 1, M is 0.5 or more and 1.5 or less, And Zn is 0.1 or more and 2 or less. By making the ratio of the number of In and M atoms approximately the same, In this case, oxygen deficiency occurs in the first metal oxide layer 108a and the second metal oxide layer 108b. Since the occurrence of oxygen deficiency can be suppressed, the electrical properties are good and the reliability is high. This allows for the creation of highly reliable transistors.

[0085] The first metal oxide layer 108a and the second metal oxide layer 108b have different compositions. Although a film formed using a target having the same composition may be used, it is particularly preferable to use a film formed using a target having the same composition. It is preferable to use a laminated film that is continuously formed without being exposed to the atmosphere. This allows the first metal oxide layer 108a and the second metal oxide layer 108b to be formed in a single deposition apparatus. Impurities remaining in the metal oxide layer 108b can be prevented. Since impurities can be a carrier source, suppressing the increase in impurities leads to good electrical properties and reliability. This makes it possible to fabricate highly efficient transistors.

[0086] The second metal oxide layer 108b has a region with higher crystallinity than the first metal oxide layer 108a. It is preferable that the second metal oxide layer 108b has a region with high crystallinity. As a result, the film has better etching resistance than the first metal oxide layer 108a. Therefore, when the conductive layer 112a and the conductive layer 112b are formed, the second metal oxide layer 1 Therefore, the thickness of the 08b can be prevented from being lost by etching. A) Realization of a transistor with a channel-etched structure as shown in Fig. 1(B) and Fig. 1(C). Furthermore, a second metal oxide layer 108 located on the back channel side of the transistor can be formed. By using a film with high crystallinity for b, the diffusion to the first metal oxide layer 108a on the conductive layer 104 side is prevented. By reducing the amount of impurities that can be dispersed, transistors with good electrical properties and high reliability can be manufactured. can.

[0087] In addition, the first metal oxide layer 108a has a lower crystallinity than the second metal oxide layer 108b. By using a film including a region where oxygen is not easily diffused into the first metal oxide layer 108a, This can reduce the rate of oxygen vacancies in the first metal oxide layer 108a. The first metal oxide layer 108a is located on the side closer to the conductive layer 104, and is mainly formed as a channel. Therefore, the first metal oxide layer 108a is a film with few oxygen vacancies. By using the above, a transistor with good electrical characteristics and high reliability can be manufactured.

[0088] The first metal oxide layer 108a and the second metal oxide layer 108b are formed under different film forming conditions, for example. For example, the first metal oxide layer 108a and the second metal oxide layer 108b can be formed separately. The flow rate of oxygen gas in the deposition gas can be made different between the metal oxide layer 108b and the metal oxide layer 108c.

[0089] At this time, the film formation conditions for the first metal oxide layer 108a are as follows: The ratio of the gas flow rate (also called the oxygen flow rate ratio or oxygen partial pressure) is set to 0% or more and 30% or less, preferably The oxygen flow rate ratio is set to 5% or more and 15% or less. By setting the oxygen flow rate ratio as described above, the first metal oxide layer 10 The crystallinity of 8a can be reduced.

[0090] On the other hand, the film formation conditions for the second metal oxide layer 108b are as follows: oxygen flow rate ratio is set to 30% or more; 100% or less, preferably 50% or more and 100% or less, and more preferably 70% or more and 100% or less. % or less. By setting the oxygen flow rate ratio as described above, the crystallinity of the second metal oxide layer 108b can be improved. It can be made higher.

[0091] When the oxygen flow rate ratio is high, a region having a spinel-type crystal structure is generated in the metal oxide layer. When there is a region having a spinel type crystal structure, the region and / or The density of oxygen vacancies may be high at the interface between the region and other regions. The oxygen flow rate ratio at which a region having a Pinel type crystal structure does not occur is, for example, 30% or less. A maximum of 50% or less may be used.

[0092] The substrate temperature during the formation of the first metal oxide layer 108a and the second metal oxide layer 108b is The temperature is preferably from room temperature (25°C) to 200°C, more preferably from room temperature to 130°C. By keeping the substrate temperature within the above range, when using a large-area glass substrate, the bending of the substrate can be reduced. Alternatively, distortion can be suppressed. Here, the first metal oxide layer 108a and the second metal oxide layer 1 If the substrate temperature is the same for both 08b and 08c, productivity can be improved. When the substrate temperatures of the first metal oxide layer 108a and the second metal oxide layer 108b are different, In this case, if the substrate temperature is increased during the formation of the second metal oxide layer 108b, the second metal oxide layer 108b may be formed. The crystallinity of the layer 108b can be further improved.

[0093] For example, the first metal oxide layer 108a may be formed of Cloud-Aligned Electrodes (CAC-OS). Composite oxide semiconductor) film is used, and a second metal CAAC-OS (c-axis-aligned crystallization) is applied to the oxide layer 108b. It is preferable to use a thin film of a semiconductor oxide.

[0094] The crystallinity of the first metal oxide layer 108a and the second metal oxide layer 108b may be, for example, For example, X-ray diffraction (XRD), transmission electron microscope (T EM: Transmission Electron Microscope, electron beam It can be analyzed by electron diffraction, etc.

[0095] The thickness of the first metal oxide layer 108a is 1 nm or more and 50 nm or less, preferably 5 The thickness of the second metal oxide layer 108b may be set to 30 nm or more. The thickness is preferably greater than 10 nm and less than 100 nm, more preferably greater than 20 nm and less than 50 nm. stomach.

[0096] The boundary (interface) between the first metal oxide layer 108a and the second metal oxide layer 108b is clearly visible. Therefore, in the drawings illustrating one embodiment of the present invention, these boundaries may not be clearly visible. The boundary is shown by a dashed line.

[0097] In the metal oxide layer 108, oxygen vacancies in the metal oxide layer 108 act on hydrogen to form When a VoH is formed, the carrier density may increase. Therefore, the metal oxide layer It is preferable that the metal oxide layer 108 has few oxygen deficiencies. In particular, it is preferable that the metal oxide layer 108 contains few impurities containing hydrogen. The low oxygen vacancy and impurities prevent VoH from being formed in the metal oxide layer 108. Therefore, the carrier density is low, and the electrical properties are good and the transistor is highly reliable. You get a transistor.

[0098] The metal oxide layer 108 may have a single layer structure. By applying a structure similar to that of the layer 108a, the on-current of the transistor can be increased. In addition, by applying the same structure as the metal oxide layer 108b to the metal oxide layer 108, The reliability of the transistor can be improved.

[0099] The insulating layer 114 can be an insulating film containing oxygen that is formed in an atmosphere containing oxygen. An insulating film formed in an atmosphere containing oxygen is prone to release a large amount of oxygen when heated. The insulating layer 114 may be made of a material having a lower nitrogen concentration than the insulating layer 116. For example, an insulating film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen is preferably used. It is preferable to use an insulating film containing silicon. In particular, a silicon oxide film or a silicon oxynitride film is preferable. It is more preferable to use a Kon membrane.

[0100] In this specification and the like, silicon oxynitride refers to a material containing silicon, oxygen, and nitrogen. Silicon nitride oxide refers to a film that contains more oxygen than nitrogen as a composition. It refers to a film that contains oxygen and nitrogen and has a higher nitrogen content than oxygen in its composition. The composition was determined by Rutherford Backscattering (RBS) It can be measured using techniques such as ring spectrometry.

[0101] When a silicon oxide film, a silicon oxynitride film, or the like is used as the insulating layer 114, Plasma Enhanced Chemical Vapor Deposition (PECVD) It is preferable to form the film using a PECVD (Polyethylene Polyethylene Vapor Deposition) system. is preferred because it has high step coverage on the surface to be formed and can form a dense insulating film with few defects. It's nice.

[0102] The insulating layer 114 has a laminated structure of an insulating layer 114a and an insulating layer 114b on the insulating layer 114a. The insulating layer 114a and the insulating layer 114b may each have an excess oxygen region. It is preferable that the insulating layer 114a and the insulating layer 114b have an excess oxygen region, so that the metal oxide Oxygen can be supplied to the metal oxide layer 108. Oxygen vacancies that may be formed in the metal oxide layer 108 can be filled with oxygen. Since the resistance can be compensated for by the addition of the SiO 2 , a transistor with good electrical characteristics and high reliability can be provided.

[0103] The insulating layer 114a in contact with the back channel side of the metal oxide layer 108 is thicker than the insulating layer 114b. Therefore, an oxide film with a low nitrogen content can be used as the insulating layer 114a. By using an oxide film with a low nitrogen content, the insulating layer 1 in contact with the metal oxide layer 108 can be In 14a, nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably The ratio is preferably 1 or more and 2 or less. Typically, NO2 or NO) can be formed in a structure that is difficult to form. The insulating layer 114a can be formed using a PECVD device. The formation of insulating layer 114a is performed under film formation conditions in which the power and chamber pressure are lower than those for the formation of insulating layer 114b. It can be used.

[0104] The insulating layer 114a is an insulating film that allows oxygen to pass through. 14a is used to prevent damage to the metal oxide layer 108 when forming the insulating layer 114b to be formed later. It also functions as a relaxation membrane.

[0105] The insulating layer 114b provided on the insulating layer 114a contains more excess oxygen than the insulating layer 114a. The insulating layer 114b may be formed using an oxide film having (exO). The insulating layer 114b can be formed by a PECVD apparatus. The deposition conditions can be higher in power and chamber pressure than those for the formation of insulating films. The substrate temperature during the formation of the edge layer 114b is preferably 180° C. or higher and 280° C. or lower. In the film formed at the aforementioned substrate temperature, the bonding strength between silicon and oxygen is weak, so the film is difficult to be formed in the subsequent process. The heat treatment causes some of the oxygen in the film to be desorbed. As a result, the oxygen content is less than that required for the stoichiometric composition. It is possible to form an insulating film that contains more oxygen than the above and from which part of the oxygen is released by heating. preferable.

[0106] When the insulating layer 114a and the insulating layer 114b are made of the same material, In some cases, the interface of the insulating layer 114b cannot be clearly confirmed. The interface between the insulating layer 114a and the insulating layer 114b is indicated by a broken line. Although the two-layer structure of the insulating layer 114a and the insulating layer 114b has been described, one embodiment of the present invention is This is not limiting, and for example, a single layer structure of either the insulating layer 114a or the insulating layer 114b may be used. Alternatively, it may have a laminated structure of three or more layers.

[0107] The path of oxygen diffusing from the insulating layer 114 into the metal oxide layer 108 is shown in FIGS. 2(A) and 2(B) show the metal oxide layer 108. 2(A) is a conceptual diagram showing the path of diffusing oxygen, and FIG. 2(B) is a conceptual diagram in the channel length direction. FIG. 2(B) is a conceptual diagram in the channel width direction.

[0108] The oxygen contained in the insulating layer 114a and the insulating layer 114b is introduced from above, that is, from the second metal The metal oxide layer 108b is then diffused into the first metal oxide layer 108a (FIG. 2(A) and Route 1) shown in Figure 2(B).

[0109] Alternatively, the oxygen contained in the insulating layer 114a and the insulating layer 114b may be converted into oxygen contained in the first metal oxide layer 114b. The first metal oxide layer 108a and the second metal oxide layer 108b are diffused into the metal oxide layer 108 from their respective sides. (Route 2 shown in Figure 2(B)).

[0110] For example, in the case of Route 1 shown in FIGS. 2(A) and 2(B), the second metal oxide layer If the crystallinity of 108b is high, it may hinder the diffusion of oxygen. In the case of Route 2 shown, the first metal oxide layer 108a and the second metal oxide layer 108 b) from each side to the first metal oxide layer 108a and the second metal oxide layer 108b This allows oxygen to diffuse.

[0111] In the case of Route 2 shown in FIG. 2B, the first metal oxide layer 108a is If there is a region with lower crystallinity than the oxide layer 108b, this region will become a diffusion path for oxygen. Therefore, the second metal oxide layer 108b, which has higher crystallinity than the first metal oxide layer 108a, is also oxidized. Although not shown in FIGS. 2(A) and 2(B), If the insulating layer 106 and the region 106a contain oxygen, the insulating layer 106 and the region 106a also contain oxygen. Oxygen can diffuse into the metal oxide layer 108 .

[0112] As described above, the metal oxide layer 108 has a laminated structure of films with different crystal structures. By using the low region as a diffusion path for oxygen, a transistor with good electrical characteristics and high reliability can be produced. can provide.

[0113] By providing the insulating layer 114 on the metal oxide layer 108, 08 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration is higher on the insulating layer 114 side. As a method for elemental analysis, for example, energy dispersive X-ray spectroscopy (EDX) Energy Dispersive X-ray spectroscopy (ESD) and secondary imaging Secondary Ion Mass Spectrometry (SIMS) etry), X-ray Photoelectron Spectroscopy (XPS:X-ray Photoelectron S spectroscopic, Auger Electron Spectroscopy (AES) n Spectroscopy), etc.

[0114] The first metal oxide layer 108a and the second metal oxide layer 108b are formed from the insulating layer 114a and the insulating layer 114b. Oxygen diffusing into the oxide layer 108b will be described with reference to FIG. As shown, the first metal oxide layer 108a and the second metal oxide layer 108b contain oxygen deficiencies. Oxygen vacancies (Vo), hydrogen vacancies (H), and oxygen vacancies and hydrogen combined (VoH) can exist. The oxygen contained in the edge layer 114a and the insulating layer 114b is transferred to the first metal oxide layer 108a and the second metal oxide layer 108b. When the oxygen approaches the oxygen vacancies in the metal oxide layer 108b, the oxygen is captured by the oxygen vacancies. When oxygen approaches hydrogen, the oxygen and hydrogen react to form water (H2O). and is released as water molecules from the first metal oxide layer 108a and the second metal oxide layer 108b. When oxygen approaches VoH, oxygen compensates for the oxygen vacancy. The hydrogen reacts with other oxygen to form water, and the first metal oxide layer 108a and the second metal oxide layer 108b are The metal oxide layer 108b is desorbed as water. The oxygen contained in the layer 114b causes the first metal oxide layer 108a and the second metal oxide layer 108b to It is possible to reduce oxygen vacancies, hydrogen and VoH in O8b, and therefore improve the electrical properties. Therefore, a highly reliable transistor can be manufactured.

[0115] Here, the first metal oxide layer 108 is formed without providing the insulating layer 114 having excess oxygen. Consider the case where hydrogen is desorbed from the first metal oxide layer 108a and the second metal oxide layer 108b. The hydrogen contained in the first metal oxide layer 108a and the second metal oxide layer 108b is transferred to the first metal oxide layer 108 In some cases, the oxygen atoms bond with oxygen atoms contained in the metal oxide layer 108a and the second metal oxide layer 108b and are released as water molecules. In this case, the first metal oxide layer 108a and the second metal oxide layer 108b have Oxygen is released, which causes oxygen deficiency, which is undesirable.

[0116] On the other hand, in a state where the insulating layer 114 having excess oxygen is provided as shown in this embodiment, Consider the case where hydrogen is desorbed from the first metal oxide layer 108a and the second metal oxide layer 108b. The hydrogen contained in the first metal oxide layer 108a and the second metal oxide layer 108b acts as an insulating The hydrogen reacts with the oxygen supplied from the insulating layer 114 and is desorbed as water molecules. By reacting with the supplied oxygen, the first metal oxide layer 108a and the second metal oxide layer This is preferable because it can prevent new oxygen vacancies from being generated in 108b.

[0117] The first metal oxide layer 108a and the second metal oxide layer 108b are formed from the insulating layer 114a and the insulating layer 114b. By supplying oxygen to the oxide layer 108b, the first metal oxide layer 108a and the second metal oxide layer 108b are The oxygen vacancies, hydrogen, and VoH of the oxide layer 108b can be reduced. The formation of oxygen vacancies and VoH in the second metal oxide layer 108a and the second metal oxide layer 108b is suppressed. By suppressing the generation of oxygen vacancies and VoH, electrical properties are good and reliability is high. This allows for the creation of smaller transistors.

[0118] After the insulating layer 114a is formed, the surface of the insulating layer 114a is heated in a vacuum without being exposed to the atmosphere. It is preferable to form the insulating layer 114b continuously. This can prevent impurities derived from atmospheric components from adhering to the surface of 14a.

[0119] The insulating layer 116 formed on the insulating layer 114b is made of an insulating film that is difficult for oxygen to diffuse and penetrate. Furthermore, the insulating layer 116 has low impurity emission and is resistant to impurity diffusion and permeation. In particular, the insulating layer 116 is preferably formed of an insulating film that does not easily absorb impurities containing hydrogen. It is preferable that the insulating layer 116 is less likely to emit impurities and is less likely to diffuse or penetrate. As a result, the carrier density of the metal oxide layer 108 is low, and the electrical properties are good and the reliability is high. A transistor is obtained.

[0120] The insulating layer 116 can be an insulating film containing silicon and nitrogen. It is preferable to use an insulating film containing silicon and nitrogen as its main components. For example, silicon nitride Silicon nitride, silicon oxide, or the like can be used in a single layer or a laminated layer.

[0121] Alternatively, the insulating layer 116 may contain an element X (X is aluminum, indium, gallium, or In particular, oxides containing metals and oxygen as the main components can be used. For example, the insulating layer 116 may be made of aluminum oxide or The insulating layer 11 can be formed using an oxygen-containing gas. It is more preferable to form the insulating layer 6 by using a gas containing oxygen. This is advantageous because oxygen can be supplied to the insulating layer 114b. As described above, the element reduces oxygen vacancies, hydrogen, and VoH in the metal oxide layer 108. Therefore, a highly reliable transistor with good electrical characteristics can be provided.

[0122] The insulating layer 114a and the insulating layer 114b are insulating films that release oxygen, and the insulating layer 116 is By laminating an insulating film that is difficult for oxygen to diffuse and penetrate, the metal Oxygen can be efficiently supplied to the oxide layer 108. As a result, oxygen deficiency in the metal oxide layer 108 and repairing defects at the interface between the metal oxide layer 108 and the insulating layer 114, thereby reducing the defect level. This makes it possible to manufacture a highly reliable transistor with favorable electrical characteristics.

[0123] The insulating layer 114a and the insulating layer 114b are As shown in FIG. 3A, a void 180 may occur in the conductive layer 112a and the conductive layer 112b. The insulating layer 114a and the insulating layer 114b are formed by the conductive layer 112b. When the voids 180 exist in the insulating layer 114a and the insulating layer 114b, Impurities may diffuse into the metal oxide layer 108 from the outside or from a layer formed later. As shown in Fig. 1B, an insulating layer 116 is provided on the insulating layer 114a and the insulating layer 114b. This can prevent impurities from diffusing into the metal oxide layer 108. This prevents oxygen from escaping and diffusing outward. As a result, the increase in oxygen vacancies, hydrogen, and VoH in the metal oxide layer 108 can be suppressed, and the electrical It is possible to manufacture transistors with good characteristics and high reliability.

[0124] After the insulating layer 114b is formed, the surface of the insulating layer 114b is heated in a vacuum without being exposed to the atmosphere. It is preferable to form the insulating layer 116 continuously. In addition, the insulating layer 114a, 114b can be prevented from being contaminated by impurities derived from atmospheric components. When the insulating layer 114b and the insulating layer 116 are formed successively in a vacuum, the insulating layer 114a and the insulating layer 116 are This is more preferable because it can prevent impurities derived from atmospheric components from adhering to the surface of the edge layer 114b.

[0125] The insulating layer 106 may be made of an insulating film that is resistant to the diffusion of impurities such as hydrogen and oxygen. For example, an insulating film with high barrier properties such as a nitride insulating film can be used. It is preferable to use an insulating film containing silicon and nitrogen as its main components.

[0126] The insulating layer 106 has a region 106a located near its upper surface. In (C), the interface of the region 106a is indicated by a broken line. The region 106a has a higher oxygen concentration than the other regions. The region 106a preferably does not contain oxygen as a main component. It is preferable that the hydrogen concentration in the metal oxide layer 108 is lower than that in the other regions. It is provided adjacent to the area 106a.

[0127] The region 106a may have a thickness of 1 nm or more and 10 nm or less.

[0128] By configuring the region 106a containing a large amount of oxygen and the metal oxide layer 108 to be in contact with each other, Therefore, the formation of defect levels at the interface between the regions 106 can be suppressed. The stacked structure of the metal oxide layer 108 and the metal oxide layer 109 improves the electrical characteristics of the transistor 100A. It can be a good thing.

[0129] By providing the metal oxide layer 108 on the region 106a, the metal oxide layer 1 08 has an oxygen concentration gradient in the film thickness direction, and the oxygen concentration is higher on the region 106a side. As described above, the metal oxide layer 108 has a high oxygen concentration on the insulating layer 114 side. In other words, the metal oxide layer 108 may have an oxygen concentration gradient in the film thickness direction. The oxygen concentration may be higher on the region 106a side than on the insulating layer 114 side. The analytical techniques include energy dispersive X-ray spectroscopy (EDX) and secondary ion mass spectroscopy (SIMS). SIMS, X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), etc. be.

[0130] Transistor 100A further includes region 106a, metal oxide layer 108, and insulating layer 114. The laminated structure is sandwiched between insulating layers 106 and 116. The insulating layer 116 is a layer through which water, hydrogen, oxygen, etc. do not easily diffuse, so that the metal oxide is not easily exposed to the outside. The diffusion of water and hydrogen into the metal oxide layer 108 is prevented, and oxygen is prevented from escaping from the metal oxide layer 108 to the outside. As a result, the electrical characteristics of the transistor 100A can be improved. This not only improves the performance but also increases reliability.

[0131] The presence of the region 106a is due to, for example, the interface between the insulating layer 106 and the metal oxide layer 108. This can be confirmed by performing elemental analysis of the region containing the insulating layer 106. A large amount of oxygen can be detected in the region close to the metal oxide layer 108. A region with a high oxygen concentration may be observed near the interface of the metal oxide layer 108. A region of layer 106 close to metal oxide layer 108 has been observed in which the hydrogen concentration is lower than in other parts. Examples of elemental analysis methods include energy dispersive X-ray spectroscopy (EDX) and Secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy The presence of the region 106a can be confirmed by a transmission electron microscope ( TEM (Transmission Electron Microscopy) images, etc. In some cases, it can be observed as an area with a different contrast from other parts.

[0132] The above is the description of configuration example 1.

[0133] Below, a configuration example of a transistor with a part of its configuration different from that of the above-described Configuration Example 1 will be described. In the following, explanations of parts that overlap with the above-described Configuration Example 1 may be omitted. In the drawings shown below, parts having the same functions as those in the above-described configuration example 1 are indicated by hatching. In some cases, the turns are the same and no symbols are assigned.

[0134] <Configuration example 2> 4A is a top view of a transistor 100B, which is a semiconductor device of one embodiment of the present invention, and FIG. 4B is a cross-sectional view of the transistor 100B. The diagram is shown in Fig. 4(B) and Fig. 4(C). Fig. 4(B) shows the cross section of the dashed line X1- 4(C) corresponds to a cross-sectional view of the cutting view at X2, and FIG. 4(C) is a cross-sectional view of the cutting view taken along the dashed line Y1- This corresponds to the cross-sectional view of the cutaway view at Y2.

[0135] The transistor 100B has a metal oxide layer 108 including a first metal oxide layer 108a, a second metal oxide layer 108b, and a The metal oxide layer 108b and the third metal oxide layer 108c are the same as those illustrated in Configuration Example 1. This is different from the transistor 100A.

[0136] As shown in FIGS. 4(A), 4(B), and 4(C), the metal oxide layer 108 is a third a metal oxide layer 108c and a first metal oxide layer 108a on the third metal oxide layer 108c; and a laminated structure of the second metal oxide layer 108b on the first metal oxide layer 108a. is preferred.

[0137] The first metal oxide layer 108a, the second metal oxide layer 108b and the third metal oxide layer 1 Preferably, each of the third metal oxide layer 108c contains a metal oxide. can be used for the first metal oxide layer 108a and the second metal oxide layer 108b. The material can be applied.

[0138] The first metal oxide layer 108a, the second metal oxide layer 108b and the third metal oxide layer 1 Although the film formed by using targets with different compositions may be used for the 08c, The same composition of target is used for the layered film, which is continuously formed without exposure to the atmosphere. By forming the films successively, the processes can be performed in one film forming apparatus, and the third Between the metal oxide layer 108c and the first metal oxide layer 108a, and between the first metal oxide layer 108c and the first metal oxide layer 108b, This can prevent impurities from remaining between the metal oxide layer 8a and the second metal oxide layer 108b. Impurities in the semiconductor layer can act as carrier sources, so by suppressing the increase in impurities, the electrical properties can be improved. Good, reliable transistors can be fabricated.

[0139] The third metal oxide layer 108c and the second metal oxide layer 108b are It is preferable that the third metal oxide layer 108 has a region with higher crystallinity than the third metal oxide layer 108a. The third metal oxide layer 108c has a highly crystalline region, and thus the layer below the third metal oxide layer 108c (for example, the insulating layer) Impurities diffuse from the edge layer 106, the conductive layer 104, and the substrate 102 into the first metal oxide layer 108a. It can prevent scattering.

[0140] The first metal oxide layer 108a, the second metal oxide layer 108b and the third metal oxide layer 1 08c can be made differently by, for example, changing the film forming conditions. a metal oxide layer 108a, a second metal oxide layer 108b, and a third metal oxide layer 108c; Therefore, the flow rate of oxygen gas in the film forming gas can be varied.

[0141] At this time, the film formation conditions for the first metal oxide layer 108a are as follows: The ratio of the gas flow rate (also called the oxygen flow rate ratio or oxygen partial pressure) is set to 0% or more and 30% or less, preferably The oxygen flow rate ratio is set to 5% or more and 15% or less. By setting the oxygen flow rate ratio as described above, the first metal oxide layer 10 The crystallinity of 8a can be reduced.

[0142] On the other hand, the film formation conditions for the second metal oxide layer 108b and the third metal oxide layer 108c are as follows: The oxygen flow rate ratio is set to be greater than 30% and equal to or less than 100%, preferably greater than 50% and equal to or less than 100%. More preferably, the oxygen flow rate is 70% or more and 100% or less. The crystallinity of the metal oxide layer 108b and the third metal oxide layer 108c can be increased. The second metal oxide layer 108b and the third metal oxide layer 108c have the same oxygen flow rate ratio. Alternatively, a different oxygen flow rate ratio may be used.

[0143] Furthermore, by setting the above-mentioned oxygen flow rate ratio, the third metal oxide layer 108c is formed. Oxygen is added to the insulating layer 106, which is the surface on which the metal oxide layer 108c is to be formed. The oxygen added in O6 can diffuse into the metal oxide layer 108 as excess oxygen. This makes it possible to reduce oxygen vacancies, hydrogen, and VoH in the metal oxide layer.

[0144] The first metal oxide layer 108a, the second metal oxide layer 108b and the third metal oxide layer 1 The substrate temperature during the formation of 08c is preferably from room temperature (25°C) to 200°C. By setting the substrate temperature in the above range, it is possible to form a large-area glass substrate. When a plate is used, bending or distortion of the substrate can be suppressed. The substrate temperature is controlled by the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 108c. If the temperature is the same, productivity can be improved. The substrate temperatures are different for the second metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer 108c. In this case, when the second metal oxide layer 108b and the third metal oxide layer 108c are formed, When the substrate temperature is increased, the second metal oxide layer 108b and the third metal oxide layer 108c The crystallinity can be further increased.

[0145] For example, a CAC-OS film is used for the first metal oxide layer 108a, and a CAC-OS film is used for the second metal oxide layer 108b. It is preferable to use a CAAC-OS film for the metal oxide layer 108b and the third metal oxide layer 108c.

[0146] The thickness of the third metal oxide layer 108c is 1 nm or more and 50 nm or less, preferably 1 The thickness of the first metal oxide layer 108a may be set to 10 nm or more. The thickness may be 1 nm or more and 50 nm or less, preferably 5 nm or more and 20 nm or less. The thickness of the second metal oxide layer 108b is preferably greater than 5 nm and less than 100 nm. may be set to 5 nm or more and 30 nm or less.

[0147] The first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer In some cases, the boundary (interface) of the material layer 108c cannot be clearly confirmed. In the drawings illustrating this, these boundaries are shown by dashed lines.

[0148] <Configuration example 3> 5A is a top view of a transistor 100C, which is a semiconductor device of one embodiment of the present invention, and FIG. 5B is a cross-sectional view of the transistor 100C. The diagram is shown in Fig. 5(B) and Fig. 5(C). Fig. 5(B) shows the cross section of the dashed line X1- 5(C) corresponds to a cross-sectional view of the cutting view at X2, and FIG. 5(C) is a cross-sectional view of the cutting view taken along the dashed line Y1- This corresponds to the cross-sectional view of the cutaway view at Y2.

[0149] The transistor 100C has a stacked structure in which the conductive layer 112a and the conductive layer 112b have a stacked structure. , which is different from the transistor 100A illustrated in the first configuration example.

[0150] The conductive layer 112a is formed by laminating a conductive layer 121a, a conductive layer 122a, and a conductive layer 123a in this order. The conductive layer 112b has a laminated structure including a conductive layer 121b, a conductive layer 122b, and a conductive layer 121b. The conductive layer 123b has a laminated structure in which the conductive layer 123b is laminated in order.

[0151] The conductive layer 121a and the conductive layer 121b are formed on the side surface of the first metal oxide layer 108a and on the metal The conductive layer 121a and the conductive layer 121b are formed to cover the upper and side surfaces of the metal oxide layer 108b. The conductive layer 121b is provided on and in contact with the region 106a of the insulating layer 106. The conductive layers 122a and 122b are provided on the conductive layers 121a and 121b, respectively. The conductive layer 122a and the conductive layer 122b are, in plan view, the conductive layer 121a and the conductive layer 121b. The conductive layer 123a and the conductive layer 123b are located inside the conductive layer 121b. The conductive layer 123a and the conductive layer 123b are provided on the conductive layer 122a and the conductive layer 122b. , are provided to cover the top and side surfaces of the conductive layer 122a and the conductive layer 122b, respectively. Furthermore, a part of the conductive layer 123a and a part of the conductive layer 123b are connected to the conductive layer 121a and the conductive layer 121b, respectively. The conductive layer 121a and the conductive layer 123a are provided in contact with the upper surface of the conductive layer 121b. The conductive layer 121b and the conductive layer 123b are processed so that their ends coincide with each other. The ends are processed so as to coincide in plan view.

[0152] With this structure, the conductive layer 122a is formed by the conductive layers 121a and 123a. The conductive layer 122b can be surrounded by the conductive layer 121b and the conductive layer 123. In other words, the conductive layer 122a and the conductive layer The surface of the conductive layer 122a and the surface of the conductive layer 122b are not exposed. The conductive layer 122b may be made of a material that easily diffuses into the metal oxide layer .

[0153] The conductive layer 122a and the conductive layer 122b are formed by the conductive layer 121a, the conductive layer 121b, and the conductive layer 121b. It is preferable to use a material having a lower resistance than the conductive layer 123a and the conductive layer 123b. The conductive layers 21a, 121b, 123a, and 123b are provided with the conductive layers 122a and A material that is less likely to diffuse into the metal oxide layer 108 than the conductive layer 122b can be used.

[0154] The conductive layer 122a and the conductive layer 122b are formed by at least the conductive layer 121a and the conductive layer 121b. A conductive material different from that of the conductive layer 123a and the conductive layer 123b can be used. The conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b are each provided with different In particular, the conductive layer 121a, the conductive layer 121b, and the conductive layer 121c may be made of a conductive material. If the same conductive material is used for the conductive layer 23a and the conductive layer 123b, the manufacturing equipment can be shared. This is preferable because the contact resistance at these ends can be reduced.

[0155] For example, the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b are It is preferable to use a titanium film or a molybdenum film. It is preferable to use an aluminum film or a copper film for 22b. The conductive layer 112a and the conductive layer 112b have low wiring resistance and good electrical characteristics. It is possible to realize the

[0156] The above is the explanation of configuration example 3.

[0157] <Configuration Example 4> 6A is a top view of a transistor 100D, which is a semiconductor device of one embodiment of the present invention, and FIG. 6B is a cross-sectional view of the transistor 100D. The diagrams are shown in Fig. 6(B) and Fig. 6(C). Fig. 6(B) shows the cross section of the dashed line X1- 6(C) corresponds to a cross-sectional view of the cutting view at X2, and FIG. 6(C) is a cross-sectional view of the cutting view taken along the dashed line Y1- This corresponds to the cross-sectional view of the cutaway view at Y2.

[0158] The transistor 100D includes a conductive layer 120a, a conductive layer 120b, and a conductive layer 112c. In this respect, it differs from the transistor 100C illustrated in the above-described Configuration Example 3.

[0159] The conductive layer 120a is provided on the insulating layer 116 and has a portion overlapping the metal oxide layer 108. At this time, the conductive layer 104 functions as a first gate, and the conductive layer 120a functions as a second gate. A part of the insulating layer 106 functions as a first gate insulating layer, and the insulating layer 1 14 and a portion of the insulating layer 116 function as a second gate insulating layer. 0D is a transistor having a pair of gate electrodes.

[0160] The transistor 100D is a so-called channel-etched, dual-gate transistor. It is a star.

[0161] The conductive layer 120b is electrically connected to the conductive layer 123b of the conductive layer 112b by the connection portion 142b. At the connection portion 142b, the conductive layer 120b is connected to the insulating layer 116 and the insulating layer The conductive layer 112b is electrically connected to the conductive layer 123b through an opening provided in the conductive layer 114. are.

[0162] As shown in FIG. 6C, the conductive layer 120a and the conductive layer 104 are electrically connected by a connection portion 142a. The connecting portion 142a is preferably configured to be electrically connected. In the connection portion 142a, the conductive layer 122c and the conductive layer 123c are provided. The insulating layer 114 and the insulating layer 116 are electrically connected to the conductive layer 123c through openings formed in the insulating layer 114 and the insulating layer 116. The conductive layer 121c is electrically connected to the conductive layer 10 through an opening provided in the insulating layer 106. 4 is electrically connected to

[0163] The metal oxide layer 108 in the transistor 100D is connected to the conductive layer 104 and the conductive layer 120. The conductive layer 104 and the conductive layer 120a are sandwiched between the conductive layer 104 and the conductive layer 120a. The length in the channel width direction is equal to the length in the channel length direction of the metal oxide layer 108 and the length in the channel width direction. Therefore, the metal oxide layer 108 is longer than the insulating layer 106 and the insulating layer 108. 14 and an insulating layer 116 are sandwiched between the conductive layer 104 and the conductive layer 120a. In other words, in the channel width direction of the transistor 100D, the conductive layer 104 The conductive layer 120a surrounds the metal oxide layer 108.

[0164] With this structure, the metal oxide layer 108 of the transistor 100D can be formed as follows: The transistor can be electrically surrounded by the electric fields of the conductive layer 104 and the conductive layer 120a. As in the case of the photodiode 100D, the electric field of the conductive layer 104 and the conductive layer 120a causes the channel region to The device structure of the transistor that electrically surrounds the formed metal oxide layer is called the Surrounding This can be called a ded channel (S-channel) structure.

[0165] The transistor 100D has an S-channel structure, and therefore the conductive layer 104 and the conductive The electric field for inducing a channel is effectively applied to the metal oxide layer 108 by the electric field layer 120a. Therefore, the driving capability of the transistor 100D is improved, and a high ON voltage can be applied. It is also possible to obtain high on-current characteristics. The transistor 100D can be miniaturized. Since the metal oxide layer 108 is surrounded by the layer 104 and the conductive layer 120a, The mechanical strength of the transistor 100D can be increased.

[0166] Furthermore, by adopting the above-described configuration, the region in which carriers flow in the metal oxide layer 108 However, the conductive layer 104 side of the metal oxide layer 108 and the conductive layer 120a side of the metal oxide layer 108 By forming the transistor 100D on both sides, the carrier movement amount is increased. As a result, when a predetermined potential is applied to either the conductive layer 104 or the conductive layer 120a, In this case, the on-state current of the transistor 100D can be increased compared to when the on-state current is increased.

[0167] Note that, as in the transistor 100E shown in FIGS. 7A, 7B, and 7C, The metal oxide layer 108 is then covered with a third metal oxide layer 108c and a second metal oxide layer 108b. a first metal oxide layer 108a and a second metal oxide layer on the first metal oxide layer 108a. 108b may be laminated.

[0168] Also, as in the transistor 100F shown in FIGS. 8(A), 8(B), and 8(C), The conductive layer 112c may not be provided. The conductive layer 104 is formed through openings provided in the insulating layer 106, the insulating layer 114, and the insulating layer 116. 104 is electrically connected to the

[0169] The above is the explanation of configuration example 4.

[0170] <Configuration example 5> 9A is a top view of a transistor 100G, which is a semiconductor device of one embodiment of the present invention, and FIG. 9B is a cross-sectional view of the transistor 100G. The diagrams are shown in Fig. 9(B) and Fig. 9(C). Fig. 9(B) shows the cross section of the dashed line X1- 9(C) corresponds to a cross-sectional view of the cutting view at X2, and FIG. 9(C) is a cross-sectional view of the cutting view taken along the dashed line Y1- This corresponds to the cross-sectional view of the cutaway view at Y2.

[0171] The transistor 100G includes a metal oxide layer 108, a conductive layer 120a, and a conductive layer 120b. The transistor 100F differs from the transistor 100F illustrated in the above-described Configuration Example 4 in that it has an insulating layer 150 between the is doing.

[0172] The insulating layer 150 covers the top and side surfaces of the metal oxide layer 108 and the insulating layer 106. The insulating layer 150 is formed by insulating a metal oxide when the conductive layers 112a and 112b are processed. It functions as a channel protection layer for protecting the oxide layer 108 .

[0173] The transistor 100G is a so-called channel-protected, dual-gate transistor. It is Ta.

[0174] The insulating layer 150 can be made of the same material as the insulating layer 114a described above.

[0175] The conductive layer 112a and the conductive layer 112b are each provided on an insulating layer 150. The electrical layer 112a is electrically connected to the metal oxide layer 108 by the connection portion 152a. In the portion 152a, the conductive layer 112a is connected to the metal via an opening provided in the insulating layer 150. The conductive layer 112b is electrically connected to the oxide layer 108. The conductive layer 112b is electrically connected to the metal oxide layer 108 by the connection portion 152b. At the connection portion 152b, the conductive layer 112b is electrically connected to the insulating layer 108. Electrical connection is made to the metal oxide layer 108 through an opening provided in 150 .

[0176] With this configuration, the etching for processing the conductive layer 112a and the conductive layer 112b can be performed. The etching process is performed while the metal oxide layer 108 is covered with the insulating layer 150. This makes it possible to make the metal oxide layer 108 less susceptible to etching damage. Such a structure allows for a wider range of material choices for the conductive layers 112a and 112b. It is preferable because it spreads.

[0177] In this example, the insulating layer 150 covers not only the top surface but also the side surfaces of the metal oxide layer 108. For example, the insulating layer 150 may be processed into an island shape, and the metal oxide layer 1 It may be configured to be located above the channel formation region 08.

[0178] This concludes the description of configuration example 5.

[0179] <Components of semiconductor device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0180] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, A sapphire substrate or the like may be used as the substrate 102. In addition, silicon or silicon carbide may be used. The materials used are single crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductors such as silicon germanium. It is also possible to apply a solid substrate, an SOI substrate, etc., and a semiconductor element is provided on these substrates. The substrate 102 may be a glass substrate. When used, 6th generation (1500mm x 1850mm), 7th generation (1870mm x 22 00mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 28 By using large area substrates such as 10th generation (2950mm x 3400mm) and 10th generation (2950mm x 3400mm), Therefore, a large display device can be manufactured.

[0181] In addition, a flexible substrate is used as the substrate 102, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor. After completing a part or all of the semiconductor device thereon, the semiconductor device is separated from the substrate 102 and In this case, the transistor is transferred to a substrate with poor heat resistance or a flexible substrate. It can also be transferred to flexible substrates.

[0182] [Conductive Layer] Conductive layer 104, conductive layer 112a, conductive layer 112b, conductive layer 120a, conductive layer 120b These include chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, and a metal element selected from the group consisting of tungsten, manganese, nickel, iron, and cobalt, or Alloys containing metal elements or alloys combining the aforementioned metal elements are used, respectively. It can be formed.

[0183] In addition, the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 120a, and the conductive layer 12 Ob includes oxides containing indium and tin (In-Sn oxide), indium and tungsten oxide, oxides containing indium, tungsten and zinc (In-W oxides); oxides containing indium and titanium (In-W-Zn oxides), and oxides containing indium and titanium (In-Ti oxide), oxides containing indium, titanium and tin (In-Ti-Sn oxide), in oxides containing indium and zinc (In-Zn oxides), oxides containing indium, tin and silicon oxides containing indium, gallium, and zinc (In-Sn-Si oxides); An oxide conductor or an oxide semiconductor such as (In-Ga-Zn oxide) can also be used. do.

[0184] Here, the oxide conductor will be described. In this specification and the like, the oxide conductor is referred to as OC (Oxide Conductor). Examples of oxide conductors include When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, A donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. A metal oxide that has been made conductive can be called an oxide conductor. Metal oxides with conductive properties have a large energy gap, making them transparent to visible light. On the other hand, oxide conductors are metal oxides that have donor levels near the conduction band. Therefore, the influence of absorption by donor levels is small in oxide conductors, and they are It has the same level of transparency as metal oxides that have semiconducting properties.

[0185] The conductive layer 104, the conductive layer 112a, and the conductive layer 112b are made of a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. By using an alloy film, it can be processed using a wet etching process, reducing manufacturing costs. It becomes possible to control it.

[0186] Furthermore, the conductive layers 112a and 112b contain, among the above-mentioned metal elements, copper and titanium in particular. one or more selected from the group consisting of tungsten, tantalum, and molybdenum In addition, the conductive layers 112a and 112b may be made of a copper film or an aluminum film. The use of a silicon film is preferable because it can reduce the resistance of the conductive layers 112a and 112b. be.

[0187] [Insulating layer] The insulating layer 106, which functions as a gate insulating layer, is formed by plasma enhanced chemical vapor deposition (PECVD). Plasma Enhanced Chemical Vapor Depositio n) a silicon nitride oxide film or a silicon nitride film formed by a deposition method, a sputtering method, or the like; An insulating layer containing one or more films such as an aluminum nitride film and an aluminum nitride oxide film can be used. The insulating layer 106 may have a stacked structure of two or more layers.

[0188] The insulating layer 114a and the insulating layer 114b provided on the metal oxide layer 108 are made of PE CVD method, sputtering method, ALD (Atomic Layer Deposition) n) method, etc. film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, acid tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film In particular, an insulating layer formed by the PECVD method can be used. It is preferable to use a silicon oxide film or a silicon oxynitride film.

[0189] The insulating layer 114a has a thickness of 5 nm to 150 nm, preferably 5 nm to 500 nm. An insulating film having a thickness of 0 nm or less can be suitably used.

[0190] The insulating layer 114a preferably has a small amount of defects. Typically, the insulating layer 114a has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 due to the silicon dangling bond is 3 x10 17 spins / cm 3 It is preferable that the number of defects contained in the insulating layer 114a is equal to or less than 1. If the defect density is high, oxygen is bound to the defects, and the oxygen permeability in the insulating layer 114a decreases. It ends up like this.

[0191] In the insulating layer 114a, all of the oxygen that has entered the insulating layer 114a from the outside is absorbed by the insulating layer 114a. Some oxygen does not move out of the insulating layer 114a and remains in the insulating layer 114a. As oxygen enters the insulating layer 114a, oxygen contained in the insulating layer 114a moves out of the insulating layer 114a. This may cause oxygen transfer in the insulating layer 114a. When an insulating film that can transmit oxygen is formed on the insulating layer 114a, Oxygen desorbed from the edge layer 114b is transported to the metal oxide layer 108a and the metal oxide layer 108b via the insulating layer 114a. The metal oxide layer 108b can be transferred to the metal oxide layer 108b.

[0192] The insulating layer 114a is formed using an insulating film with a low density of states caused by nitrogen oxides. The density of levels caused by the nitrogen oxides can be calculated by dividing the density of levels by the valence band of the metal oxide film. The upper edge energy of the conduction band (Ev_os) and the lower edge energy of the conduction band of the metal oxide film (Ec_ os) may be formed between the insulating film and the oxides. Silicon oxynitride film or aluminum oxynitride film that emits less nitrogen oxide is used. You can be there.

[0193] The silicon oxynitride film, which emits a small amount of nitrogen oxides, was analyzed by thermal desorption spectroscopy (TD). In Thermal Desorption Spectroscopy (S), nitrogen This is a membrane that releases more ammonia than elemental oxides, and typically releases ammonia. The amount is 1 x 10 18 / cm 3 5x10 or more 19 / cm 3 The following is the ammonia release rate. The amount of leakage is determined when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by heat treatment.

[0194] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), In this case, NO2 or NO forms a level in the insulating layer 114a. The metal oxide layer 108b is located within the energy gap between the metal oxide layer 108a and the metal oxide layer 108b. When nitrogen oxides diffuse to the interface between the insulating layer 114a and the metal oxide layer 108b, the level However, the insulating layer 114a may trap electrons. The electrons remain near the interface between the insulating layer 114a and the metal oxide layer 108b, so that the transistor This shifts the threshold voltage in the positive direction.

[0195] Nitrogen oxides react with ammonia and oxygen during the heat treatment. The nitrogen oxide contained in a reacts with the ammonia contained in the insulating layer 114b during the heat treatment. As a result, the nitrogen oxides contained in the insulating layer 114a are reduced. Electrons are less likely to be trapped at the interface between the metal oxide layer 14a and the metal oxide layer 108b.

[0196] By using the insulating film as the insulating layer 114a, the threshold voltage of the transistor can be controlled. It is possible to reduce the fluctuation of the electrical characteristics of the transistor. do.

[0197] In addition, the nitrogen concentration of the insulating film measured by SIMS was 6×10 20 atoms / cm 3 The following is the result.

[0198] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the insulating film using the VD method, a dense and hard film can be formed. It is possible.

[0199] The insulating layer 114b is an insulating film containing more oxygen than the oxygen required for the stoichiometric composition. When the insulating film is heated, some of the oxygen is released. The veneer releases oxygen at a rate of 1.0 x 10 19 atoms / cm 3 More than 3.0x, preferably 10 20 atoms / cm 3 The amount of oxygen released is also in the range of TDS The temperature of the heat treatment is in the range of 50°C to 650°C, or 50°C to 550°C. The amount of oxygen released is the total amount in the range of 1000 to 10 ... This is the total amount.

[0200] The insulating layer 114b has a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., up to 400 nm or less can be used.

[0201] Furthermore, it is preferable that the insulating layer 114b has a small amount of defects. Therefore, the spin density of the signal appearing at g=2.001, which is due to the dangling bond of silicon, Degrees are 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating layer 114b is made of a metal, as compared with the insulating layer 114a. Since the oxide layer 108a and the metal oxide layer 108b are separated, the insulating layer 114a A high defect density is acceptable.

[0202] The insulating layer 116, which functions as a protective layer, can be made of the above-mentioned materials. The insulating layer 116 may have a stacked structure of two or more layers. It is preferable to use an insulating film. In addition, the insulating layer 116 emits less impurities and It is preferable to use an insulating film that is difficult for hydrogen to diffuse or penetrate. It is preferable that the material emits less impurities and is less likely to diffuse or penetrate impurities.

[0203] The insulating layer 116 has a thickness of 5 nm to 200 nm, preferably 10 nm to 100 nm. An insulating film having a thickness of 50 nm or less can be suitably used.

[0204] [Semiconductor layer] The first metal oxide layer 108a, the second metal oxide layer 108b and the third metal oxide layer 1 As 08c, the materials shown above can be used.

[0205] The first metal oxide layer 108a, the second metal oxide layer 108b and the third metal oxide layer 1 When 08c is In-M-Zn oxide, the sintering agent used to form the In-M-Zn oxide film is The atomic ratio of the metal elements in the sputtering target preferably satisfies In>M. The atomic ratio of the metal elements in the sputtering target is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Z n=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In :M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, Examples include In:M:Zn=5:2:5.

[0206] In addition, the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer When the material layer 108c is an In-M-Zn oxide, the sputtering target is preferably an In-Zn oxide. It is preferable to use a target containing crystalline In-M-Zn oxide. By using a target containing Zn oxide, a crystalline metal oxide layer 108 is formed. The atomic ratio of the metal oxide layer 108 to be formed is determined by the above-mentioned sputtering method. The atomic ratio of the metal elements contained in the target can vary by ±40%. For example, the composition of the sputtering target used for the metal oxide layer 108 is In:Ga:Zn= In the case of the atomic ratio of 4:2:4.1, the composition of the metal oxide layer 108 to be formed is In:G The atomic ratio may be close to a:Zn=4:2:3.

[0207] In addition, the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer The material layer 108c has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wide energy gap, The current can be reduced.

[0208] In addition, the first metal oxide layer 108a, the second metal oxide layer 108b, and the third metal oxide layer The material layer 108c preferably has a non-single crystal structure. OS(C Axis Aligned Crystalline Oxide Semi conductor), polycrystalline structure, microcrystalline structure, or amorphous structure. In terms of structure, the amorphous structure has the highest defect density, and the CAAC-OS has the lowest defect density. is low.

[0209] <Transistor manufacturing method 1> An example of a method for manufacturing a transistor of one embodiment of the present invention will be described below. The transistor 100C illustrated in the above-described Configuration Example 3 will be described as an example.

[0210] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. method, chemical vapor deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) The CVD method can be a plasma-enhanced chemical vapor deposition (PECVD) method. There are methods such as VD (Plasma Enhanced CVD) and thermal CVD. One of the thermal CVD methods is metal organic chemical vapor deposition (MOCVD). c CVD) method.

[0211] In addition, the formation of thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices requires spin Coating, dipping, spray coating, droplet ejection method (inkjet method, etc.), printing method (screen Printing methods (such as inkjet printing, offset printing, etc.), doctor knife, roll coater, curtain coater Equipment such as a coater or knife coater can be used.

[0212] Furthermore, when processing the thin films that make up the semiconductor device, photolithography and other methods are used. Other methods include nanoimprinting, sandblasting, and lift-off. The thin film may be processed by a method such as a masking method. The island-shaped thin film may be directly formed by the film method.

[0213] There are two typical photolithography methods: A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the photomask after forming a photosensitive thin film. Then, the thin film is processed into a desired shape by performing development.

[0214] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), It uses g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure. Using extreme ultraviolet (EUV) and X-rays, Also, instead of light used for exposure, an electron beam can be used. The use of light, X-rays or electron beams is preferred because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask It is unnecessary.

[0215] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as these can be used.

[0216] 10 to 13 illustrate a method for manufacturing the transistor 100C. In each figure, the left side shows a cross section in the channel length direction, and the right side shows a cross section in the channel width direction. This shows that...

[0217] [Formation of Conductive Layer 104] A conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive layer 104 that functions as a gate electrode is formed by performing processing.

[0218] [Formation of insulating layer 106] An insulating layer 106 is formed to cover the conductive layer 104 and the substrate 102 (FIG. 10(A)). The film 106 can be formed by using, for example, a PECVD method.

[0219] In this embodiment, a silicon nitride film having a thickness of 400 nm is used as the insulating layer 106. The silicon nitride film described above can be made up of a first silicon nitride film and a second silicon nitride film. and a third silicon nitride film. It can be formed as follows.

[0220] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency was generated. If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to 50 nm, good.

[0221] For the second silicon nitride film, silane at a flow rate of 200 sccm and 2000 sccm The PECVD equipment was operated using nitrogen at a flow rate of 2000 sccm and ammonia gas at a flow rate of 2000 sccm as raw material gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply A power of 2000 W may be supplied using a power supply such that the thickness is 300 nm.

[0222] The third silicon nitride film was formed under the same film-forming conditions as the first silicon nitride film, with a thickness of 1000 nm. It is sufficient to form it so that the thickness is 50 nm.

[0223] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during the formation can be 350° C. or less.

[0224] By forming the silicon nitride film into the three-layer laminated structure described above, for example, the conductive layer 104 can be made of copper. When a conductive film including the first silicon nitride film is used, the following effects are achieved. The second silicon nitride film can suppress the diffusion of copper elements from the silicon nitride film 104. and improves the breakdown voltage of the insulating film that functions as a gate insulating film. The third silicon nitride film has a low hydrogen release rate and This makes it possible to suppress the diffusion of hydrogen released from the second silicon nitride film.

[0225] [Formation of region 106a] Next, oxygen 130a is added to the insulating layer 106, and an oxygen-containing region 130a is formed near the surface. It is preferable to form 06a (FIG. 10(B)).

[0226] The oxygen 130a added to the insulating layer 106 may be oxygen radicals, oxygen atoms, or oxygen atom ions. The methods of addition include ion doping, ion doping, and oxygen molecular ions. In addition, a film that suppresses oxygen desorption is formed on the insulating layer 106. After the formation of the film, oxygen 130a may be added to the insulating layer 106 through the film. It is preferable to add 30a and then remove it.

[0227] As the film for suppressing the desorption of the aforementioned oxygen, indium, zinc, gallium, tin, aluminum, Aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten A conductive film or a semiconductor film having one or more of the above groups can be used.

[0228] In addition, when oxygen 130a is added in the plasma treatment, the oxygen is excited by microwaves and By generating a high density oxygen plasma, the amount of oxygen added to the insulating layer 106 can be increased. Furthermore, by performing plasma treatment in an atmosphere containing oxygen, the surface of the insulating layer 106 can be This allows the removal of water and hydrogen adsorbed on the metal oxide to be formed later. The water and hydrogen that may be present in the layer 108 or at the interface between the metal oxide layer 108 and the insulating layer 106 are removed. It can be reduced.

[0229] When silicon nitride or silicon nitride oxide is used as the insulating layer 106, the insulating layer In this case, hydrogen may be contained in 106. In this case, the plasma treatment etc. As a result, the hydrogen concentration in at least the region 106a in contact with the metal oxide layer 108 is reduced. It is possible.

[0230] Before adding oxygen 130a, water and hydrogen are desorbed from the surface and the inside of the insulating layer 106. For example, a heat treatment may be performed at 300° C. or higher in a nitrogen atmosphere to heat the conductive layer 104 The heat treatment is carried out at a temperature lower than the heat-resistant temperature of the substrate, preferably at a temperature of 300°C or higher and 450°C or lower.

[0231] [Formation of Metal Oxide Layer 108] Subsequently, a metal oxide film 128a and a metal oxide film 128b are formed on the insulating layer 106. (Figure 10(C)).

[0232] The metal oxide film 128a and the metal oxide film 128b are formed by depositing metal oxide targets. It is preferable to form the film by the sputtering method used in the present invention.

[0233] In addition, when the metal oxide film 128a and the metal oxide film 128b are formed, in addition to oxygen gas, Inert gas (e.g., helium gas, argon gas, xenon gas, etc.) is mixed with The ratio of oxygen gas to the total deposition gas when depositing a metal oxide film (hereinafter The oxygen flow rate (also referred to as the oxygen flow rate ratio) is 0% or more and 100% or less, preferably 5% or more and 20% or less. The following is the result.

[0234] By lowering the oxygen flow rate and forming a metal oxide film with relatively low crystallinity, it is possible to obtain a highly conductive metal oxide film. On the other hand, by increasing the oxygen flow rate, a metal oxide film with relatively high crystallinity can be obtained. By using a metal oxide film, it is possible to obtain a metal oxide film that is highly resistant to etching and electrically stable. can be done.

[0235] For example, the conditions for forming the metal oxide film 128a and the metal oxide film 128b are as follows: substrate temperature The substrate temperature may be set to a temperature between room temperature and 180°C, preferably a temperature between room temperature and 140°C. When the substrate temperature during the deposition of the metal oxide film is set to, for example, room temperature or higher and lower than 140°C, the productivity is This is preferable.

[0236] More specifically, the oxygen flow rate ratio during the formation of the metal oxide film 128a is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The thickness of the metal oxide film 128a is set to 1 nm or more and 50 nm or less, preferably 5 The thickness may be set to between 100 nm and 30 nm.

[0237] In addition, the oxygen flow rate ratio during the formation of the metal oxide film 128b is preferably set to 50% or more and 100% or less. Preferably, the ratio is 60% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably is 90% or more and 100% or less, typically 100%. The conditions of pressure, temperature, power, etc. during film formation may be different between the metal oxide film 128a and the metal oxide film 128b. By keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened. The thickness of the metal oxide film 128b is preferably greater than 10 nm and less than 100 nm. Preferably, the thickness is set to 20 nm or more and 50 nm or less.

[0238] The metal oxide film 128a and the metal oxide film 128b are films having different compositions. At this time, both the metal oxide film 128a and the metal oxide film 128b may contain In. When Ga—Zn oxide is used, the metal oxide film 128a has a higher SiO 2 content than the metal oxide film 128b. It is preferable to use an oxide target with a high In content.

[0239] Next, a resist mask is formed on the metal oxide film 128b, and the metal oxide films 128a and After processing the metal oxide film 128b by etching, the resist mask is removed. Then, the metal oxide layer 108a and the metal oxide layer 108b are formed (FIG. 11(A)).

[0240] After the metal oxide layer 108a and the metal oxide layer 108b are formed, a heat treatment (hereinafter referred to as the first The first heat treatment may be performed on the metal oxide layer 108a and the metal oxide layer 108b. The hydrogen, water, and the like contained in the metal oxide layer 108b can be reduced. The heat treatment for the purpose of reducing the amount of the metal oxide film 128a and the metal oxide film 128b is performed in an island-like manner. The first heat treatment may be carried out before processing the metal oxide layer. It could be said that it is one.

[0241] The first heat treatment is carried out at a temperature of, for example, 150° C. or higher and lower than the distortion point of the substrate, preferably 200° C. °C or higher and 450 °C or lower, and more preferably 250 °C or higher and 350 °C or lower.

[0242] The first heat treatment can be performed using an electric furnace, an RTA device, or the like. By using this, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. Therefore, the heating time can be shortened. Ultra-dry air (water content less than 20 ppm, preferably less than 1 ppm, preferably less than 10 ppm) This can be done under an atmosphere of air (<100 psi) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. In addition, after heat treatment in a nitrogen or rare gas atmosphere, it is possible to heat in an oxygen or ultra-dry air atmosphere. As a result, hydrogen, water, etc. contained in the metal oxide layer are desorbed, and the metal As a result, the oxygen contained in the metal oxide layer can be supplied to the metal oxide layer. Defects can be reduced.

[0243] [Formation of Conductive Layer 112a and Conductive Layer 112b] Next, a conductive film 121 that will later become the conductive layers 121a and 121b and a conductive film 122 that will later become the conductive layers 121a and 121b are formed. The conductive layer 22a and the conductive film 122 that will become the conductive layer 122b are stacked.

[0244] Subsequently, a resist mask 131 is formed over the conductive film 122 (FIG. 11B). The masks 131 are spaced apart over the areas of the metal oxide layer 108 where channels will be formed. It can be done.

[0245] Thereafter, the conductive film 122 is processed by etching to form the conductive layer 122a and the conductive layer 122b. At this time, as shown in FIG. 11(C), the conductive layer 122a and The end of the conductive layer 122b is processed so as to be positioned inside the end of the resist mask 131. It is preferable to do so.

[0246] The conductive film 122 is preferably etched by an isotropic etching method. A wet etching method can be used for this purpose. The edges of the conductive layer 122b can be etched back.

[0247] After the conductive layers 122a and 122b are formed, the resist mask 131 is removed.

[0248] Subsequently, a conductive film 123 is formed to cover the conductive layer 121a, the conductive layer 122a, and the conductive layer 122b. The conductive film 123 is a conductive film that will later become the conductive layers 123a and 123b. do.

[0249] Subsequently, a resist mask 132 is formed over the conductive film 123 (FIG. 12(A)). At this time, the resist mask 132 is formed using the same photomask as the resist mask 131. This allows for the use of a common photomask, reducing manufacturing costs. It is possible.

[0250] Subsequently, the conductive film 121 and the conductive film 123 are processed by etching to form a conductive layer 121a, The conductive layer 121b, the conductive layer 123a, and the conductive layer 123b are formed. The end of the conductive layer 122a is in contact with the end of the conductive layer 123a, and the conductive layer 122a is not exposed. At this time, the conductive layer 121b and the conductive layer 123b are in contact with each other at their ends, and the conductive layer 122b is It is preferable to process it so that it is not exposed.

[0251] The conductive films 121 and 123 are etched by an anisotropic etching method. Preferably, a dry etching method can be used. The conductive layers 121a, 121b, 123a, and 123b are formed so that their ends do not recede. This allows the conductive layer 121a to surround the conductive layer 122a. The conductive layer 121a can be formed so as to surround the conductive layer 122b. In addition, the conductive layer 123b can be formed. This can suppress adhesion.

[0252] In addition, the conductive layer 121a, the conductive layer 121b, the conductive layer 123a, and the conductive layer 123b are provided with the same conductive layer. The conductive layer 121 can be easily etched. a) The conductive layer 121b, the conductive layer 123a, and the conductive layer 123b are less likely to have unevenness at their ends. This is preferable because

[0253] After that, the resist mask 132 is removed. A layer 112b can be formed (FIG. 12(B)).

[0254] [Formation of insulating layers 114 and 116] Next, a conductive layer 112a, a conductive layer 112b, a metal oxide layer 108, etc. are covered with the conductive layer 112a, the conductive layer 112b, and the metal oxide layer 108. Insulating layer 114 and insulating layer 116 are formed.

[0255] The insulating layer 114 is preferably formed in an atmosphere containing oxygen. It is preferable to form it by the VD method.

[0256] The insulating layer 114 may be an oxide film such as a silicon oxide film or a silicon oxynitride film. It is preferable to form the film using a PECVD apparatus in an atmosphere containing oxygen. This allows the insulating layer 114 to have fewer defects. It is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of silane include silane, disilane, trisilane, and fluorosilane. Examples of the gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide. A stacked structure of the insulating layer 114a and an insulating layer 114b over the insulating layer 114a can be used.

[0257] In forming the insulating layer 114a, the flow rate of the oxidizing gas is increased by 20 times compared to the deposition gas. The pressure in the processing chamber is set to 10 The pressure is less than 0 Pa, preferably 50 Pa or less.

[0258] In this embodiment, the insulating layer 114a is formed by heating the substrate 102 at a temperature of 220 ° C., and silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm were used as raw material gases. The pressure in the processing chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 MHz, 100W (power density is 1.6 x 10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using the above.

[0259] The insulating layer 114b is formed by depositing a substrate placed in a vacuum-evacuated processing chamber of a PECVD apparatus. The temperature is maintained at 180°C or higher and 280°C or lower, more preferably 200°C or higher and 240°C or lower. The raw material gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less. The pressure is preferably 100 Pa or more and 200 Pa or less, and the pressure is 0.17 W / cm 2 More than 0.5W / cm 2 or less, more preferably 0.25 W / cm 2 Over 0.3 5W / cm 2 Under the following conditions for supplying high frequency power, silicon oxide film or silicon oxynitride film is formed. Form a polymer membrane.

[0260] The insulating layer 114b is formed under the conditions of high frequency irradiation at the above-mentioned power density in a reaction chamber at the above-mentioned pressure. Supplying power increases the efficiency of decomposition of the source gas in the plasma, increasing the number of oxygen radicals. However, since the oxidation of the source gas progresses, the oxygen content in the insulating layer 114b becomes lower than the stoichiometric composition. On the other hand, in the film formed at the substrate temperature mentioned above, the bond between silicon and oxygen Because the force is weak, some of the oxygen in the film is released during the heat treatment in the subsequent process. An insulating material that contains more oxygen than the stoichiometric composition and in which some of the oxygen is released when heated. A film can be formed.

[0261] In the step of forming the insulating layer 114b, the insulating layer 114a protects the metal oxide layer 108. Therefore, the power density can be reduced while reducing damage to the metal oxide layer 108. High radio frequency power can be used to form the insulating layer 114b.

[0262] In the film formation conditions for the insulating layer 114b, the deposition property containing silicon in the oxidizing gas is By increasing the flow rate of the gas, it is possible to reduce the number of defects in the insulating layer 114b. As a result, the reliability of the transistor can be improved.

[0263] Regarding the configuration in which the insulating layer 114 has a two-layer structure of insulating layer 114a and insulating layer 114b, However, one embodiment of the present invention is not limited thereto. For example, the insulating layer 114 may be formed by Alternatively, the insulating layer 114 may have a single layer structure of either the insulating layer 114a or the insulating layer 114b. By using this structure, productivity can be improved, which is preferable. The laminated structure may be formed as follows.

[0264] Subsequently, an insulating layer 116 is formed to cover the insulating layer 114b. It can be formed in the same manner as the layer 106 .

[0265] For example, a silicon nitride film is preferably used as the insulating layer 116. The film 116 can be formed by using, for example, a sputtering method or a PECVD method. For example, when the insulating layer 116 is formed by the PECVD method, the substrate temperature is set to less than 400° C. The temperature is preferably less than 375°C, and more preferably 180°C or higher and 350°C or lower. By setting the substrate temperature in the above range when forming the film 116, a dense film can be formed. In addition, by setting the substrate temperature in the above range when forming the insulating layer 116, The oxygen or excess oxygen in the insulating layer 114a and the insulating layer 114b is converted into the metal oxide layer 108. It becomes possible to move it.

[0266] In addition, when a silicon nitride film is formed as the insulating layer 116 by the PECVD method, silicon It is preferable to use a deposition gas containing ammonium, nitrogen, and ammonia as source gases. By using a small amount of ammonia compared to the amount of oxygen, the ammonia dissociates in the plasma and becomes active. The activated species are formed by bonding silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the triple bond between silicon and nitrogen, promoting the bonding of silicon and nitrogen. It is possible to form a dense silicon nitride film with few silicon and hydrogen bonds and few defects. On the other hand, if the amount of ammonia relative to nitrogen is high, the deposition gas containing silicon and nitrogen The decomposition of the element does not proceed, silicon and hydrogen bonds remain, and there are many hydrogen atoms and defects, and A coarse silicon nitride film is formed. The flow rate ratio of nitrogen to water is preferably 5 to 50 times, and more preferably 10 to 50 times. By using the above flow ratio, dense silicon nitride with less hydrogen and defects can be formed. .

[0267] In this embodiment, the insulating layer 116 is formed by depositing silane, nitrogen, and the like using a PECVD apparatus. A silicon nitride film having a thickness of 100 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 1000 sccm for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the A 1000 W high-frequency power supply is used to supply 1000 W of high-frequency power to the parallel plate electrodes. D device has an electrode area of 6000 cm 2 It is a parallel plate type PECVD device, and we supplied When converted to power per unit area (power density), it is 1.7 x 10 -1 W / cm 2 Yes do.

[0268] The film formation temperature of the insulating layer 116 is set to a higher temperature than the insulating layers 114a and 114b. By using a high temperature, impurities such as hydrogen in the insulating layer 116 can be reduced. In addition, the substrate temperature during the formation of the insulating layer 116 can be adjusted to the same temperature as the insulating layer 114a and the insulating layer 114b. By using the same temperature, productivity can be increased. Cut.

[0269] After the insulating layer 114a is formed, the surface of the insulating layer 114a is heated in a vacuum without being exposed to the atmosphere. It is preferable to form the insulating layer 114b continuously. The insulating layer 114b can prevent impurities from being attached to the surface of the insulating layer 114a. After that, the insulating layer 116 is successively formed in a vacuum without exposing the surface of the insulating layer 114b to the atmosphere. By forming them continuously, the surface of the insulating layer 114b is protected from atmospheric components. The insulating layer 114a, the insulating layer 114b, and the insulating layer 114c can be prevented from adhering to the insulating layer 114a. It is more preferable to form the insulating layer 114a and 6 continuously. This can prevent impurities derived from atmospheric components from adhering to the surface of insulating layer 114b.

[0270] After the insulating layers 114a, 114b, and 116 are formed, a heat treatment (hereinafter, By the second heat treatment, the insulating layer 114a, Nitrogen oxide contained in the insulating layer 114b and the insulating layer 116 can be reduced. By the second heat treatment, part of oxygen contained in the insulating layers 114a and 114b is converted to gold. and the oxygen vacancies and VoH contained in the metal oxide layer 108 are reduced. It is possible.

[0271] The second heat treatment is typically performed at a temperature of less than 400°C, preferably less than 375°C. More preferably, the temperature is 150°C or higher and 350°C or lower.

[0272] The second heat treatment is carried out in an atmosphere of nitrogen, oxygen, or ultra-dry air (with a water content of 20 ppm or less, preferably air at 1 ppm or less, preferably 10 ppb or less), or rare gases (argon, helium The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas and water atmosphere can be used. It is preferable that the mixture does not contain oxygen, water, etc. For the heat treatment, an electric furnace, RTA, etc. may be used. can be done.

[0273] Through the above steps, the transistor 100C can be manufactured.

[0274] <Transistor manufacturing method 2> The following describes a method for manufacturing a transistor 100, which is different from the method for manufacturing a transistor 1 shown in Method 1. The method for forming the conductive layer 112a and the conductive layer 112b will be described. The manufacturing method is the same as the manufacturing method 1 of the transistor described above (see FIG. 12B).

[0275] [Formation of insulating layer 114] Next, an insulating film is formed to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, and the like. The insulating layer 114 is formed (FIG. 13(A)). Since the description of the manufacturing method 1 of the insulating layer 114 can be referred to, a detailed description thereof will be omitted. Alternatively, the insulating layer 114 may have a two-layer structure of the insulating layer 114a and the insulating layer 114b. For example, the insulating layer 114 may have a single layer structure of either the insulating layer 114a or the insulating layer 114b. The insulating layer 114 may have a single-layer structure, which is preferable because productivity can be improved. The insulating layer 114 may have a stacked structure of three or more layers.

[0276] [Heat Treatment] After the insulating layer 114 is formed, heat treatment is performed. This can reduce the amount of nitrogen oxide contained in the insulating layer 114. By this process, part of the oxygen contained in the insulating layer 114 is transferred to the metal oxide layer 108, and the metal oxide The oxygen vacancies and VoH contained in the oxide layer 108 can be reduced.

[0277] The heat treatment is typically carried out at a temperature of less than 400°C, preferably less than 375°C, More preferably, the temperature is 150°C or higher and 350°C or lower.

[0278] Heat treatment is carried out in a nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably 1 ppm). pm or less, preferably 10 ppb or less air), or rare gases (argon, helium, etc.) The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas, hydrogen, water It is preferable that the heat treatment does not include the above. An electric furnace, RTA, etc. may be used for the heat treatment. do.

[0279] [Formation of insulating layer 116] Next, the insulating layer 116 is formed so as to cover the insulating layer 114. Method for forming the insulating layer 116 Regarding the above, the description of the transistor manufacturing method 1 can be referred to, and therefore detailed description thereof will be omitted. .

[0280] The heat treatment after the formation of the insulating layer 116 can be performed by referring to the description of the manufacturing method 1 of the transistor. , detailed description will be omitted.

[0281] Through the above steps, the transistor 100C can be manufactured.

[0282] <Transistor manufacturing method 3> The following describes a method for manufacturing a transistor 100, which is different from the method for manufacturing a transistor 1 shown in Method 1. The method for forming the conductive layer 112a and the conductive layer 112b will be described. The manufacturing method is the same as the manufacturing method 1 of the transistor described above (see FIG. 12B).

[0283] [Formation of insulating layer 114] Next, an insulating film is formed to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, and the like. An edge layer 114a and an insulating layer 114b are formed (FIG. 13(A)). For the method for forming the layer 114b, the description of the manufacturing method 1 of the transistor can be referred to. Detailed description will be omitted.

[0284] After the insulating layer 114a is formed, the surface of the insulating layer 114a is heated in a vacuum without being exposed to the atmosphere. It is preferable to form the insulating layer 114b continuously. This can prevent impurities derived from atmospheric components from adhering to the surface of 14a.

[0285] [Formation of insulating layer 116] Next, an insulating layer 116 is formed to cover the insulating layer 114 .

[0286] The above-mentioned materials can be used for the insulating layer 116. For example, the insulating layer 116 can be made of For example, aluminum oxide can be used as the insulating layer 116. In-Ga-Zn oxide can be used. The proportion of Zn is larger than the proportion of In (for example, the atomic ratio is In:Ga:Zn=1: 3:2), the band gap of the insulating layer 116 becomes large, which is preferable. A sputtering device can be used for forming the insulating layer 116 on the insulating layer 114b. A cross-sectional view of the inside of the film forming apparatus when sputtering is performed is shown in FIG. The target 191 is installed inside the laser device, and the laser beam is formed below the target 191. Plasma 192 is shown schematically.

[0287] First, when forming the insulating layer 116, plasma is discharged in an atmosphere containing oxygen gas. At this time, oxygen 130b is added to the insulating layer 114b, which is the surface on which the insulating layer 116 is to be formed. When forming the insulating layer 116, in addition to oxygen gas, an inert gas (for example, helix Oxygen 130b may be mixed with other gases such as argon gas, xenon gas, etc. It may be provided with an edge layer 114a and an insulating layer 114b.

[0288] The ratio of oxygen gas in the entire deposition gas when forming the insulating layer 116 is from 0% to At most 100% or less, preferably 10% to 100%, and more preferably 30% or more It is less than 100%.

[0289] After the insulating layer 114a is formed, the surface of the insulating layer 114a is heated in a vacuum without being exposed to the atmosphere. It is preferable to form the insulating layer 114b continuously. The insulating layer 114b can prevent impurities from being attached to the surface of the insulating layer 114a. After that, the insulating layer 116 is successively formed in a vacuum without exposing the surface of the insulating layer 114b to the atmosphere. By forming them continuously, the surface of the insulating layer 114b is protected from atmospheric components. The insulating layer 114a, the insulating layer 114b, and the insulating layer 114c can be prevented from adhering to the insulating layer 114a. It is more preferable to form the insulating layer 114a and 6 continuously. This can prevent impurities derived from atmospheric components from adhering to the surface of insulating layer 114b.

[0290] After the insulating layers 114a, 114b, and 116 are formed, heat treatment is performed. The heat treatment is preferable. Alternatively, the heat treatment can reduce the amount of nitrogen oxide contained in the insulating layer 114a. A part of the oxygen contained in the insulating layer 114b is transferred to the metal oxide layer 108, and the metal oxide The oxygen vacancies and VoH contained in the layer 108 can be reduced.

[0291] The heat treatment after the formation of the insulating layer 116 can be performed by referring to the description of the manufacturing method 1 of the transistor. , detailed description will be omitted.

[0292] Through the above steps, the transistor 100C can be manufactured.

[0293] <Transistor manufacturing method 4> The following describes the manufacturing methods shown in Manufacturing Method 1 and Manufacturing Method 3 of a Transistor. The method for manufacturing the transistor 100C, which is different from the method for manufacturing the conductive layer 112a, will be described. The steps up to the formation of the conductive layer 112b are the same as those in the above-described method 1 for fabricating a transistor (FIG. 12). (See (B)).

[0294] [Formation of insulating layer 114] Next, an insulating film is formed to cover the conductive layer 112a, the conductive layer 112b, the metal oxide layer 108, and the like. An edge layer 114a and an insulating layer 114b are formed (FIG. 13(A)). For the method for forming the layer 114b, the description of the manufacturing method 1 of the transistor can be referred to. Detailed description will be omitted.

[0295] After the insulating layer 114a is formed, the surface of the insulating layer 114a is heated in a vacuum without being exposed to the atmosphere. It is preferable to form the insulating layer 114b continuously. This can prevent impurities derived from atmospheric components from adhering to the surface of 14a.

[0296] After the insulating layer 114b is formed, heat treatment may be performed. The nitrogen oxides contained in the insulating layer 114a and the insulating layer 114b can be reduced. By the heat treatment, part of the oxygen contained in the insulating layer 114a and the insulating layer 114b is oxidized to the metal oxide layer 1 Oxygen vacancies and VoH contained in the metal oxide layer 108 can be reduced by transferring the oxygen to O 8 .

[0297] The temperature of the heat treatment is typically 150°C or higher and 400°C or lower, preferably 300°C or higher. The temperature is set to 400°C or lower, preferably 320°C or higher and 370°C or lower. Ultra-dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 1 This can be done under an atmosphere of air (0 ppb or less) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. For the heat treatment, an electric furnace, an RTA device, or the like can be used.

[0298] [Oxygen supply treatment] Next, a conductive film 134 is formed to cover the insulating layer 114b (FIG. 14(A)).

[0299] The conductive film 134 may be a metal oxide film, a metal film, or an alloy film. The thickness of the conductive film 134 is preferably extremely thin, for example, between 1 nm and 20 nm. Preferably, the thickness is 2 nm or more and 15 nm or less, more preferably 3 nm or more and 10 nm or less. In practice, this can be set to about 5 nm.

[0300] Examples of metal oxides that can be used for the conductive film 134 include In—Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, Examples include In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide.

[0301] The conductive film 134 may be made of aluminum, titanium, chromium, iron, cobalt, or nickel. , copper, zinc, gallium, molybdenum, silver, indium, tin, tantalum, tungsten, etc. A metal film or an alloy film containing the above can be used.

[0302] The conductive film 134 may be formed of a compound semiconductor such as silicon or germanium, or a simple substance such as silicon or germanium. A semiconductor film containing a conductor or an oxide semiconductor may also be used.

[0303] Here, a metal oxide is used as the conductive film 134, and the conductive film 134 is formed by sputtering in an atmosphere containing oxygen. When the insulating layers 114a and 114b are formed by the method or the like, oxygen is not introduced into the insulating layers 114a and 114b even during the film formation. This is preferable because it can be supplied.

[0304] The maximum temperature in the process of forming the conductive film 134 is 350° C. or less, preferably 340° C. or less. The temperature is preferably 330°C or lower, and more preferably 300°C or lower.

[0305] Next, oxygen 130c is supplied to the insulating layer 114a and the insulating layer 114b through the conductive film 134. Then, a process of supplying oxygen (hereinafter also referred to as oxygen supply process) is performed (FIG. 14(B)).

[0306] The oxygen supply treatment is a plasma treatment under an oxygen atmosphere (also called oxygen plasma treatment). It is preferable to use oxygen radicals and oxygen atoms by converting oxygen into plasma. The electrons or oxygen ions are added to the insulating layer 114a and the insulating layer 114b through the conductive film 134. The higher the oxygen flow rate ratio in the gas introduced into the device, the better. or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 10 It is set to 0% or less, and more preferably 100%.

[0307] In particular, it is preferable to use a processing device having a pair of parallel plate type electrodes. At this time, the plasma processing is performed in a state where a bias voltage is applied between the pair of electrodes. This allows more oxygen to be supplied to the insulating layers 114a and 114b. The asphalt voltage is applied so that oxygen ions in the oxygen plasma can move easily to the substrate side. The oxygen ions in the oxygen plasma are, for example, O + or O 2+ Positively charged particles such as Therefore, when a bias voltage is applied so that the electrode on the substrate side has a negative potential, Oxygen ions move more easily to the plate side.

[0308] Here, oxygen is directly applied to the insulating layers 114a and 114b without providing the conductive film 134. When the supplying treatment is performed, part of the oxygen supplied to the insulating layers 114a and 114b is However, in this example of the manufacturing method, the insulating layer 114a The conductive film 134 is provided on the insulating layer 114a and the insulating layer 114b. This can prevent oxygen supplied to the insulating layer 114b from being released to the outside again. In addition, the conductive film 134 reduces damage to the insulating layer 114a and the insulating layer 114b. It is possible.

[0309] The conductive film 134 over the insulating layer 114a and the insulating layer 114b is When a bias voltage is applied between a pair of electrodes, it becomes easier to attract ionized oxygen. Therefore, by providing the conductive film 134, it is possible to apply a bias voltage. This can synergistically enhance the effects of

[0310] In addition, processing equipment includes dry etching equipment, ashing equipment, PECVD equipment, etc. It is preferable to use an ashing device because the device can be shared with other processes. It is preferable.

[0311] The oxygen supply treatment is carried out at a temperature of, for example, room temperature or higher and 350°C or lower, preferably 150°C or higher and lower than 350°C. It is more preferable to carry out the treatment at a temperature of 200°C or higher and 340°C or lower.

[0312] In addition, when a bias voltage is applied between a pair of electrodes of the processing device, the bias voltage Alternatively, the bias power density may be set to, for example, 10 V or more and 1 kV or less. W / cm 2 More than 5W / cm 2 The following would suffice.

[0313] The oxygen supply treatment is not limited to the above-described treatment. A method capable of supplying oxygen to the layer 114b can be used. For example, ion implantation, ion Doping or plasma immersion ion implantation is used. Oxygen may be supplied to the insulating film through the conductive film. Alternatively, heat treatment may be performed in an oxygen atmosphere. Even when such a treatment is performed, the conductive film 134 is formed by the insulating layer 114a and the insulating layer 114b) to function as a cap film that prevents oxygen supplied to the The insulating layer 114a and the insulating layer 114b are formed to function as a buffer layer for buffering damage to the insulating layer 114a and the insulating layer 114b. This can be done.

[0314] The conductive film 134 may become embrittled by the oxygen supply treatment. When metal or alloy is used for 134, it is oxidized by oxygen supply treatment and the resistance value becomes high. In such cases, the film may become thin or part of it may be etched. The conductive film 134 is preferably removed by etching.

[0315] FIG. 14C shows a cross-sectional view after the conductive film 134 is etched.

[0316] The maximum temperature for the etching process of the conductive film 134 is 350° C. or less, preferably 340° C. °C or less, more preferably 330 °C or less, and even more preferably 300 °C or less.

[0317] In addition, as the oxygen supply treatment, the conductive film 134 is not provided, and the plating is performed under an atmosphere containing oxygen. By not providing the conductive film 134, productivity can be improved. Cut.

[0318] [Formation of insulating layer 116] Next, the insulating layer 116 is formed so as to cover the insulating layer 114. Method for forming the insulating layer 116 Regarding the above, the description of the transistor manufacturing method 1 can be referred to, and therefore detailed description thereof will be omitted. .

[0319] Through the above steps, the transistor 100C can be manufactured.

[0320] This completes the description of the example of the method for manufacturing a transistor.

[0321] The configuration examples, manufacturing method examples, and corresponding drawings etc. illustrated in this embodiment mode are merely examples. In addition, a part of it may be implemented by appropriately combining it with other configuration examples, manufacturing method examples, drawings, etc. can be done.

[0322] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0323] (Embodiment 2) In this embodiment, a display device including the transistor described in the previous embodiment will be described. An example will be described.

[0324] <Configuration example> 15(A) is a top view showing an example of a display device. 00 is a pixel portion 702 provided on a first substrate 701 and a The source driver circuit section 704 and the gate driver circuit section 706 are connected to the pixel section 702 and the source driver circuit section 706. A shield is disposed to surround the gate driver circuit section 704 and the gate driver circuit section 706. The substrate 701 has a first substrate 701a and a second substrate 705a. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section The path portion 706 is sealed by the first substrate 701, the seal material 712, and the second substrate 705. Although not shown in FIG. 15A, the first substrate 701 and the second substrate 705 A display element is provided between them.

[0325] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel section 702, a source driver circuit section 704, a gate driver circuit section FPC terminals electrically connected to the wiring portion 706 and the gate driver circuit portion 706, respectively. A sub-unit 708 (FPC: Flexible printed circuit) is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and the FPC 716 Various signals are sent to the source driver circuit section 702, the source driver circuit section 704, and the gate driver circuit section 706. Also, a pixel section 702, a source driver circuit section 704, a gate driver circuit section A signal line 710 is connected to each of the path portion 706 and the FPC terminal portion 708. Various signals supplied by 716 are transmitted to the pixel section 702, the source driver 716, and the like via signal lines 710. 704, the gate driver circuit section 706, and the FPC terminal section 708. do.

[0326] The display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a crystalline semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0327] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0328] The display device 700 can also include various elements, such as: For example, electroluminescence (EL) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (which emit light according to the current) transistors), electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, Low-wetting element, plasma display panel (PDP), MEMS (micro- Electro-mechanical systems) displays (e.g., grating light bulbs) GLV (Glass Laser Diode), Digital Micromirror Device (DMD), Digital Microshaft Distributed Membrane Switching (DMS) element, Interferometric Modulation (IMOD) element ), piezoelectric ceramic displays, etc.

[0329] An example of a display device using an EL element is an EL display. An example of a display device using emission elements is a field emission display (FE D) or SED type flat panel display (SED: Surface-conductive n Electron-emitter Display) etc. An example of such a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). Displays, reflective LCD displays, direct-view LCD displays, projection LCD displays Examples of display devices using electronic ink elements or electrophoretic elements include: There are also semi-transmissive LCD displays and reflective LCD displays. In this case, a part or all of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption.

[0330] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. As in the column, two colors of RGB make up one color element, and different two You can also select a color and configure it by adding one or more colors such as yellow, cyan, magenta, etc. to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. It can also be applied to a display device.

[0331] Also, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color using (W), a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B), or the like. ), yellow (Y), etc. can be used in combination as appropriate. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. By placing the color layer in the display, the decrease in brightness caused by the color layer can be reduced during bright display, and power consumption can be reduced by 2. However, it may be possible to reduce the emission by approximately 100% to 30%. When using optical elements to display full color, R, G, B, Y, and W are emitted by each color. By using a self-luminous element, it is possible to make the light emitted from a colored layer. In some cases, power consumption can be further reduced.

[0332] In addition, as a colorization method, a part of the light emitted from the white light mentioned above is passed through a color filter. In addition to the color filter method, which converts red, green, and blue by filtering, A method that uses each color of light (three-color method), or a method that uses part of the light emitted from the blue light to emit red or A method of converting to green (color conversion method, quantum dot method) may also be applied.

[0333] The display device 700A shown in FIG. 15(B) is suitable for use in electronic devices having large screens. For example, television equipment, monitor equipment, digital signage equipment, etc. It can be suitably used for printing.

[0334] The display device 700A includes a plurality of source driver ICs 721 and a pair of gate driver circuits. It has 722.

[0335] The plurality of source driver ICs 721 are attached to respective FPCs 723. In addition, the plurality of FPCs 723 are arranged such that one terminal is connected to the substrate 701 and the other terminal is connected to the printed circuit board 72. 4. By bending the FPC 723, the printed circuit board 724 The LED can be disposed on the back side of the pixel portion 702 and mounted in an electronic device.

[0336] On the other hand, the gate driver circuit 722 is formed on the substrate 701. It is possible to realize electronic devices in a picture frame.

[0337] By adopting such a configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. It can be applied to the above display devices. This makes it possible to realize extremely high-resolution display devices such as 8K4K.

[0338] <Example of cross-sectional configuration> In the following, a configuration using a liquid crystal element and an EL element as a display element will be described with reference to FIGS. 16 to 18. 16 and 17 are diagrams showing the dashed line QR in FIG. 18 is a cross-sectional view of the display device, which uses a liquid crystal element as the display element. 16 is a cross-sectional view taken along the dashed line QR in FIG. 15, showing a structure in which an EL element is used as a display element. It is completed.

[0339] First, the common parts shown in FIGS. 16 to 18 will be explained, and then the different parts will be explained. This will be explained below.

[0340] [Explanation of common parts of the display device] The display device 700 shown in FIGS. 16 to 18 includes a wiring portion 711, a pixel portion 702, and a , a source driver circuit section 704, and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The source driver circuit portion 704 includes a transistor 752. Has.

[0341] The transistor 750 and the transistor 752 are the same as those described in Embodiment 1. can be applied.

[0342] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. This allows for a longer retention time for electrical signals such as signals, and the write interval can also be extended when the power is on. Therefore, the frequency of refresh operations can be reduced, resulting in reduced power consumption. It has the effect of suppressing force.

[0343] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using this in a device, the switching transistor in the pixel section and the driver used in the drive circuit section can be In other words, a separate driver circuit can be formed on the same substrate. Since it is not necessary to use a semiconductor device formed from a silicon wafer or the like, the semiconductor device part The number of parts can be reduced. Also, in the pixel section, transistors that can be driven at high speed are used. By using this data, high quality images can be provided.

[0344] The capacitor 790 includes a conductive film which functions as a first gate electrode of the transistor 750. The lower electrode formed through a process of processing the same conductive film and the It is formed through a process of processing the same conductive film as the conductive film that functions as the second gate electrode. A transistor 750 is provided between the lower electrode and the upper electrode. The insulating film is formed through a process of forming the same insulating film as the insulating film that functions as the first gate insulating film. The insulating film is the same as the insulating film that functions as a protective insulating film over the transistor 750. In other words, the capacitor element 790 is The semiconductor device has a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes.

[0345] 16 to 18, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the capacitor 790 .

[0346] 16 to 18, the transistor 750 and the The transistor 752 in the source driver circuit portion 704 has the same structure as the transistor 752 in the source driver circuit portion 704. However, the present invention is not limited to this. For example, the pixel section 702 and the source A transistor different from that of the driver circuit section 704 may be used. A top-gate transistor is used for the source driver circuit section 702, and a bottom-gate transistor is used for the source driver circuit section 704. Alternatively, a bottom-gate transistor may be used in the pixel portion 702. and a top-gate transistor is used in the source driver circuit section 704. The source driver circuit section 704 may be replaced with a gate driver circuit section. It may be read differently.

[0347] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing ZnO are used, signal delays caused by wiring resistance are minimal, making it possible to display on a large screen. It becomes Noh.

[0348] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the drain electrode. , and is electrically connected to a terminal of the FPC 716 via an anisotropic conductive film 780 .

[0349] The first substrate 701 and the second substrate 705 may be made of, for example, glass. The first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0350] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer, which determines the distance ( The structure 778 is provided to control the cell gap. It is also possible to use "sa".

[0351] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0352] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 16 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film The conductive film 774 is formed on the second substrate 705. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 772 and the conductive film 774. This controls whether light is transmitted or not, allowing images to be displayed.

[0353] The conductive film 772 serves as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is electrically connected to a conductive film that functions as a planarization insulating film 770. The pixel electrode functions as one electrode of the display element.

[0354] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a light-transmitting property in visible light can be used. For example, a material containing one of the elements selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum Alternatively, a material containing silver may be used.

[0355] When a conductive film that is reflective to visible light is used as the conductive film 772, the display device 700 The liquid crystal display device is a reflective type. When the liquid crystal display device 700 is used, the liquid crystal display device 700 becomes a transmissive liquid crystal display device. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided.

[0356] In addition, by changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. 17. The display device 700 shown in FIG. This is an example of a configuration using a horizontal electric field method (e.g., FFS mode) as the driving method. In the structure shown in FIG. 1, an insulating film 773 is provided over a conductive film 772, and a conductive film 773 is provided over the insulating film 773. In this case, the conductive film 774 is used as a common electrode. The insulating film 773 functions as a conductive film. The orientation state of the liquid crystal layer 776 can be controlled by the field.

[0357] Although not shown in FIGS. 16 and 17, either the conductive film 772 or the conductive film 774 An alignment film is provided on either one or both of the surfaces of the substrate 771 and the liquid crystal layer 776. 16 and 17, a polarizing member, a phase difference member, a reflecting member, etc. may be used. Optical members (optical substrates) such as a polarizing substrate and a positioning member may be provided as appropriate. Circularly polarized light produced by a retardation substrate may also be used. Either may be used.

[0358] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0359] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. Since the liquid crystal display has a short rotational speed and is optically isotropic, no alignment treatment is required. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent defects and damage to the liquid crystal display device during the manufacturing process. Furthermore, liquid crystal materials exhibiting a blue phase have little viewing angle dependency.

[0360] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0361] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0362] [Display device using light-emitting elements] The display device 700 shown in FIG. 18 includes a light-emitting element 782. The light-emitting element 782 is made of a conductive film 18 includes a pixel electrode 772, an EL layer 786, and a conductive film 788. The EL layer 786 of the light emitting element 782 provided for each element emits light, and an image is displayed. The EL layer 786 can be made of an organic compound or an inorganic material such as quantum dots. It has an organic compound.

[0363] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, Also, the elements of the 12th and 16th families, the 13th and 15th families, or the 14th and 16th families Materials containing the element group may also be used. Alternatively, cadmium (Cd), selenium (Se), Zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (P b) Quantum atoms with elements such as gallium (Ga), arsenic (As), and aluminum (Al). Dot material may also be used.

[0364] In the display device 700 shown in FIG. 18, an insulating film 770 is formed on the planarizing insulating film 770 and the conductive film 772. The insulating film 730 covers part of the conductive film 772. Therefore, the conductive film 788 has a light-transmitting property, and the EL layer 7 In this embodiment, the top emission structure For example, a bottom that emits light to the conductive film 772 side is shown. A dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 is also used. It can also be applied to mission structures.

[0365] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, the EL layer 786 may be formed in an island shape for each pixel, that is, by coloring. In this case, the colored film 736 may not be provided.

[0366] [Configuration example of providing an input / output device to a display device] Furthermore, the display device 700 shown in FIGS. 16 to 18 may be provided with an input / output device. An example of the force device is a touch panel.

[0367] 19 and 18 show a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 17. FIG. 20 shows a configuration in which a touch panel 791 is provided on a display device 700.

[0368] FIG. 19 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 20 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. be.

[0369] First, the touch panel 791 shown in FIGS. 19 and 20 will be described below.

[0370] The touch panel 791 shown in FIGS. 19 and 20 is provided between the substrate 705 and the colored film 736. The touch panel 791 is a so-called in-cell type touch panel. 736 and may be formed on the substrate 705 side before the colored film 736 is formed.

[0371] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. Capacitance between electrode 793 and electrode 794 that may occur when a detection target such as a stylus approaches It is possible to detect changes in

[0372] 19 and 20, an electrode 793 and The electrode 796 is formed through an opening in the insulating film 795. 19 is electrically connected to the two electrodes 793 that sandwich the electrode 794. 20 illustrates a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702. However, the present invention is not limited to this, and may be formed in the source driver circuit section 704, for example.

[0373] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown in FIG. 1, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. 20, the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By configuring the electrode 793 in this manner, the electrode 793 does not block the light emitted from the light emitting element 782. Alternatively, the electrode 793 may have a structure that does not block light that passes through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Since the number of pixels is small, a display device with high visibility and reduced power consumption can be realized. The pole 794 may have a similar configuration.

[0374] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 can be made of a metal material with low transmittance for visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, For example, a metal material having low transmittance of visible light can be used.

[0375] Therefore, compared with electrodes using oxide materials with high visible light transmittance, The resistance of the electrode 794 can be reduced, improving the sensor sensitivity of the touch panel. It is possible.

[0376] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The nanowires have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm. The size of the nanoparticles may be 5 nm or less, and more preferably 5 nm or more and 25 nm or less. The wires may be metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, the electrodes 664, 665 may be made of wires or carbon nanotubes. When Ag nanowires are used for either 65 or 667, or both, the The light transmittance is 89% or more, and the sheet resistance is 40Ω / □ or more and 100Ω / □ or less. can.

[0377] 19 and 20 illustrate the configuration of an in-cell type touch panel. For example, a so-called on-cell type transistor formed on the display device 700 may be used. a touch panel or a so-called out-cell type touch panel that is attached to the display device 700 It may also be possible to use the following.

[0378] In this way, the display device of one embodiment of the present invention can be used in combination with various types of touch panels. It can be used.

[0379] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0380] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0381] <Circuit configuration of display device> The display device shown in FIG. 21A has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504), and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. That's fine.

[0382] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0383] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0384] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a may also provide other signals.

[0385] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0386] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0387] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. Each of the pixel circuits 501 is connected to a gate driver 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0388] The protection circuit 506 shown in FIG. 21(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be formed by wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to a power supply and a line from an external circuit to the display device. This refers to the part where terminals for inputting control signals and image signals are provided.

[0389] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 This is a circuit that brings one wire into electrical continuity with another wire.

[0390] As shown in FIG. 21A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrents caused by electrostatic discharges and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which the protection circuit 506 is connected to the source driver 504b Alternatively, a configuration in which a protection circuit 506 is connected to the terminal portion 507 may be used. It can also be done as follows.

[0391] In FIG. 21(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is implemented. It may also be configured to be equipped with

[0392] Here, a configuration different from that of FIG. 21(A) is shown in FIG. 22. In FIG. 22, A pair of source lines (for example, source line DLa1 and source line DLb1) are arranged to sandwich the array of pixels. DLb1) are arranged. In addition, two adjacent gate lines (for example, gate line GL_1 and gate line GL_2) are electrically connected.

[0393] In addition, the pixel connected to the gate line GL_1 is connected to one of the source lines (source line DLa1, The pixels connected to the gate line GL_1 are connected to the other source line DLa2, etc. (source line DLb1, source line DLb2, etc.).

[0394] With this configuration, two gate lines can be selected at the same time. As a result, the length of one horizontal period can be doubled compared to the configuration shown in FIG. 21(A). This makes it easy to increase the resolution and size of the display device.

[0395] Furthermore, the plurality of pixel circuits 501 shown in FIG. 21(A) may be, for example, a configuration shown in FIG. 21(B). It can be said that:

[0396] The pixel circuit 501 shown in FIG. 21B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. can be applied.

[0397] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0398] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of materials can be used.

[0399] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is connected to a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the electrodes of the scan line G. L_m. The transistor 550 can be turned on or off. This provides a function of controlling the writing of data signals.

[0400] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0401] For example, in a display device having the pixel circuit 501 of FIG. 21(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 550 is turned on and data of the data signal is written.

[0402] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0403] Furthermore, the plurality of pixel circuits 501 shown in FIG. 21(A) may be, for example, a configuration shown in FIG. 21(C). It can be said that:

[0404] The pixel circuit 501 shown in FIG. 21C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either one or both of the above. .

[0405] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 55 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0406] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0407] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0408] The capacitor 562 functions as a storage capacitor for holding written data.

[0409] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0410] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0411] The light emitting element 572 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0412] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0413] In a display device having the pixel circuit 501 of FIG. 21(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0414] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0415] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0416] (Fourth embodiment) In this embodiment, an electronic device of one embodiment of the present invention will be described with reference to drawings.

[0417] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0418] The display unit of the electronic device according to one embodiment of the present invention may be configured to display, for example, full high-definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher. The display screen size must be 20 inches or more diagonally, or 30 inches or more diagonally, or The diagonal can be 50 inches or more, 60 inches or more, or 70 inches or more. Cut.

[0419] Examples of electronic devices include television sets, desktop or notebook PCs, etc. Personal computers, computer monitors, digital signage electronic signage), pachinko machines and other large game machines. In addition to electronic devices with screens, digital cameras, digital video cameras, digital photo cameras, Examples include cameras, mobile phones, portable game consoles, personal digital assistants, and sound reproduction devices. .

[0420] The electronic device or lighting device according to one embodiment of the present invention can be used for interior or exterior walls of a house or building, Alternatively, it can be incorporated along curved surfaces in the interior or exterior of a vehicle.

[0421] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0422] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Number, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared) It may have.

[0423] The electronic device of one embodiment of the present invention can have various functions. (still images, videos, text images, etc.) on the display, touch panel function, calendar Functions such as displaying date and time, running various software (programs) functions, wireless communication functions, and functions to read programs or data recorded on recording media. It can have functions etc.

[0424] FIG. 23A shows an example of a television device. The television device 7100 has a housing 7 The display unit 7000 is built into the housing 101. 101 is shown as a supported configuration.

[0425] The display device of one embodiment of the present invention can be applied to the display portion 7000.

[0426] The television device 7100 shown in FIG. 23A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or the display unit 70. The display unit 7000 may be provided with a touch sensor, and the operation can be performed by touching the display unit 7000 with a finger or the like. The remote control operator 7111 may display information to be output from the remote control operator 7111. The remote control unit 7111 may have a display unit that displays the operation keys or touch panel. The channel and volume can be controlled by the touch panel, and the information displayed on the display unit 7000 can be displayed. You can control the video that is displayed.

[0427] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. By connecting to a wireless communication network, it can be transmitted in one direction (sender to receiver) or It is also possible to communicate information in both directions (between sender and receiver, or between receivers). be.

[0428] FIG. 23B shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, and a The display unit 7000 is assembled in the housing 7211. It is embedded.

[0429] The display device of one embodiment of the present invention can be applied to the display portion 7000.

[0430] Figure 23 (C) and (D) show the digital signage. An example of a sub-sign is shown below.

[0431] The digital signage 7300 shown in FIG. 23C includes a housing 7301, a display unit 7000, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0432] FIG. 23(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7000.

[0433] 23C and 23D, the display device of one embodiment of the present invention is applied to the display portion 7000. It is possible.

[0434] The larger the display unit 7000, the more information can be displayed at once. The wider the display unit 7000, the more easily it will be noticed by people, which can increase the effectiveness of advertising, for example. can.

[0435] By applying a touch panel to the display unit 7000, images or videos can be displayed on the display unit 7000. It is not only a display but also allows users to operate it intuitively, which is desirable. Or when used to provide information such as traffic information, intuitive operation is required. This can improve usability.

[0436] Also, as shown in Figures 23(C) and 23(D), the digital signage 7300 or the digital The signage 7400 is a device that can be used on an information terminal 7311 such as a smartphone or other device owned by the user. It is preferable that the display unit 7411 can be connected to the information terminal 7411 by wireless communication. The advertisement information displayed on 7000 is displayed on the screen of information terminal 7311 or information terminal 7411. In addition, the information terminal 7311 or the information terminal 7411 can be operated. By operating the buttons, the display on the display unit 7000 can be switched.

[0437] In addition, the Digital Signage 7300 or Digital Signage 7400 can be used with an information terminal. 7311 or the screen of the information terminal 7411 is used as a control means (controller) to play the game. This allows an unspecified number of users to participate in the game at the same time and have fun. It can be done.

[0438] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0439] (Embodiment 5) In this embodiment, a television device to which the display device of one embodiment of the present invention can be applied is An example of the arrangement will be described with reference to the drawings.

[0440] FIG. 24A shows a block diagram of a television device 600. As shown in FIG.

[0441] In the drawings attached to this specification, the components are classified by function and are separated into blocks independent of each other. Although the block diagram is shown as a block, the actual components are completely separated by function. This can be difficult, and one component may be involved in multiple functions.

[0442] The television device 600 includes a control unit 601, a storage unit 602, a communication control unit 603, an image processing unit 604, and a video processing unit 605. processing circuit 604, decoder circuit 605, video signal receiving unit 606, timing controller 6 07, a source driver 608, a gate driver 609, a display panel 620, etc.

[0443] The display device exemplified in the above-described embodiment is applied to the display panel 620 in FIG. 24(A). This allows a large-sized, high-resolution television with excellent visibility to be produced. The device 600 can be realized.

[0444] The control unit 601 is, for example, a central processing unit (CPU). For example, the control unit 601 can function as a system bus 63. 0, the memory unit 602, the communication control unit 603, the image processing circuit 604, and the decoder circuit 605 and a function to control components such as a video signal receiving unit 606.

[0445] Signals are transmitted between the control unit 601 and each component via a system bus 630. The control unit 601 also receives information from each component connected via a system bus 630. It has functions to process the signals input from the This allows overall control of each component connected to the system bus 630. It is possible.

[0446] The storage unit 602 stores registers and keys that can be accessed by the control unit 601 and the image processing circuit 604. It functions as cache memory, main memory, secondary memory, etc.

[0447] Examples of storage devices that can be used as secondary memories include rewritable nonvolatile A storage device using a non-volatile memory element can be used. For example, a flash memory, MRAM(Magnetoresistive Random Access Memo ry), PRAM (Phase change RAM), ReRAM (Resisti ve RAM), FeRAM (Ferroelectric RAM), etc. can be done.

[0448] It can also be used as temporary memory such as a register, cache memory, or main memory. The memory devices that can do this are DRAM (Dynamic RAM) and SRAM (Static RAM). Even if a volatile memory element such as a volatile random access memory (RAM) is used, good.

[0449] For example, a DRAM is used as the RAM provided in the main memory. A virtual memory space is allocated and used as a working space for the memory unit 601. The operating system, application programs, and program modules stored in Modules, program data, etc. are loaded into RAM for execution. These data, programs, and program modules can be directly accessed by the control unit 601. are processed and manipulated.

[0450] On the other hand, ROM has a BIOS (Basic Input / Output) that does not require rewriting. It can store the ROM, such as the ROM (System Write) and firmware. Mask ROM and OTPROM (One Time Programmable Read Only Memory) d Only Memory), EPROM (Erasable Programmable EEPROM (Read Only Memory) can be used. UV-EPROM (Ultra-V) is a type of EEPROM that allows data to be erased by exposure to ultraviolet light. iolet Erasable Programmable Read Only Me mory), EEPROM (Electrically Erasable Program memory, and flash memory. can be.

[0451] In addition to the storage unit 602, a removable storage device may be connectable. For example, a hard disk drive (Hard Disk) acts as a storage device. Drive: HDD or Solid State Drive ve:SSD) and other recording media drives, flash memory, Blu-ray discs, It is preferable that the device has a terminal for connecting to a recording medium such as a DVD. It is possible.

[0452] The communication control unit 603 has the function of controlling communication performed via a computer network. For example, the control unit 601 may connect to a computer network in response to a command from the control unit 601. The control signal for the purpose of the control is transmitted to the computer network. The Internet, which is the foundation of the World Wide Web (WWW), Net, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network) Network), MAN(Metropolitan Area Network), WAN (Wide Area Network), GAN (Global Area N It can connect to computer networks such as the Internet and communicate with them.

[0453] The communication control unit 603 is also configured to use Wi-Fi (registered trademark), Bluetooth (registered trademark), ), ZigBee (registered trademark), or other communication standards are used to connect to a computer network or other The device may have a function to communicate with the electronic device.

[0454] The communication control unit 603 may have a function for wireless communication. For example, an antenna All you need to do is install a high frequency circuit (RF circuit) to transmit and receive RF signals. The electromagnetic signal is converted into an electric signal in the frequency band specified by the regulations and vice versa, and the electromagnetic signal is converted into an electric signal. It is a circuit for wireless communication between other communication devices using a practical frequency band. The frequency range from several tens of kHz to several tens of GHz is generally used. The high-frequency circuit has a high-frequency circuit section corresponding to a plurality of frequency bands, and the high-frequency circuit section includes an amplifier. (amplifier), mixer, filter, DSP, RF transceiver, etc. can.

[0455] The video signal receiving unit 606 includes, for example, an antenna, a demodulation circuit, and an AD conversion circuit (analog -Digital conversion circuit) and the like. The demodulation circuit demodulates the signal input from the antenna. The AD conversion circuit converts the demodulated analog signal into a digital signal. The signal processed by the video signal receiving unit 606 is sent to the decoder circuit 605. do.

[0456] The decoder circuit 605 receives the digital signal from the video signal receiving unit 606. The video data is decoded according to the broadcasting standard specifications and sent to the image processing circuit. For example, the broadcasting standard for 8K broadcasting is H.265 | MPEG-H High Efficiency Video Coding (abbreviation :HEVC) etc.

[0457] The broadcasting waves that can be received by the antenna of the video signal receiving unit 606 include terrestrial waves, Or radio waves transmitted from a satellite. Also, broadcasting signals that can be received by an antenna. There are analog broadcasts, digital broadcasts, and video and audio, or audio only. For example, UHF band (approximately 300MHz to 3GHz) or VHF band (3 Receives broadcast radio waves transmitted in a specific frequency band between 0 MHz and 300 MHz Furthermore, for example, by using multiple data received in multiple frequency bands, This allows for a higher transfer rate and more information to be obtained. Images with a resolution exceeding high definition can be displayed on the display panel 620. For example, video with a resolution of 4K2K, 8K4K, 16K8K, or higher can be displayed. It can be displayed.

[0458] The video signal receiving unit 606 and the decoder circuit 605 are connected to a computer network. The broadcast data transmitted by the data transmission technology is sent to the image processing circuit 604. In this case, if the received signal is a digital signal, In other words, the video signal receiving unit 606 does not need to have a demodulation circuit, an AD conversion circuit, and the like.

[0459] The image processing circuit 604 processes the time based on the video signal input from the decoder circuit 605. It has a function of generating a video signal to be output to the video controller 607.

[0460] The timing controller 607 also receives the video signal processed by the image processing circuit 604. 609 and the source driver 608 based on the synchronization signal included in the It has the function of generating signals (clock signals, start pulse signals, etc.). In addition to the above signals, the timing controller 607 outputs the video signals to the source driver 608. It has the function of generating a video signal.

[0461] The display panel 620 has a plurality of pixels 621. Each pixel 621 is connected to a gate driver 6 609 and is driven by signals supplied from the source driver 608. 8K4K standard. The resolution of the display panel 620 is not limited to this, and may be full high-definition (pixel 4K2K (pixel count 3840 x 2160) or 4K2K (pixel count 1920 x 1080) It may be a resolution.

[0462] The control unit 601 and the image processing circuit 604 shown in FIG. 24(A) may be implemented by, for example, a processor. For example, the control unit 601 may have a central processing unit (CPU) Using a processor that functions as a Central Processing Unit In addition, the image processing circuit 604 may be, for example, a DSP (Digital Sign al Processor), GPU(Graphics Processing Un) It is also possible to use other processors such as the control unit 601 and the image processing circuit 60. 4. The aforementioned processor is implemented as an FPGA (Field Programmable Gate Array). Array) and FPAA (Field Programmable Analog Array) and FPAA (Field Programmable Analog Array) PLD (Programmable Logic Device) The configuration may be realized as follows.

[0463] The processor performs various data processing by interpreting and executing instructions from various programs. The programs that can be executed by the processor are those that the processor is capable of It may be stored in a memory area provided in the computer or in a separately provided storage device. good.

[0464] Also, a control unit 601, a storage unit 602, a communication control unit 603, an image processing circuit 604, a decoder The image signal receiving circuit 605, the image signal receiving unit 606, and the timing controller 607 Two or more of these functions are integrated into one IC chip to form a system LSI. For example, a processor, a decoder circuit, a tuner circuit, an AD conversion circuit, , a DRAM, an SRAM, and the like.

[0465] In addition, the control unit 601 and ICs of other components have an oxide in the channel forming region. It is also possible to use a transistor that uses a nitride semiconductor and has an extremely low off-state current. Since the off-state current of the transistor is extremely low, the transistor can be used as a memory element. It can be used as a switch to hold the charge (data) that has flowed into the capacitance element that functions as a This allows the data to be retained for a long period of time. By using it as a register or cache memory, the control unit 601 can be operated only when necessary. In other cases, the information from the immediately preceding process is saved in the memory element, so that the normal This allows off-line computing, thereby reducing the power consumption of the television device 600. This will enable us to strengthen our capabilities.

[0466] The configuration of the television device 600 illustrated in FIG. 24(A) is an example, and all configurations The television device 600 does not need to include any of the components shown in FIG. The television device 600 may have any of the components necessary for the television set 600 shown in FIG. The present invention may have components other than those shown in the above.

[0467] For example, the television device 600 may have an external interface in addition to the configuration shown in FIG. It includes an interface, audio output unit, touch panel unit, sensor unit, camera unit, etc. For example, the external interface may be a USB (Universal Serial Bus) al Serial Bus) terminal, LAN (Local Area Network) Connection terminal, power supply terminal, audio output terminal, audio input terminal, video output terminal, video External connection terminals such as input terminals, and optical communication transmission and reception using infrared, visible light, ultraviolet light, etc. For example, the audio input / output section may be a sound These include a hand controller, microphone, and speaker.

[0468] The image processing circuit 604 will be described in more detail below.

[0469] The image processing circuit 604 processes an image based on the video signal input from the decoder circuit 605. It is preferable that the device has a function for executing the processing.

[0470] Image processing includes, for example, noise removal processing, tone conversion processing, color correction processing, and brightness correction processing. Examples of color correction processing and brightness adjustment processing include gamma correction. do.

[0471] The image processing circuit 604 also performs pixel interpolation processing associated with resolution up-conversion and It has the function to perform processing such as frame interpolation associated with frame frequency up-conversion. It is preferable that

[0472] For example, noise removal processing can be used to remove mosquito noise that occurs around the contours of characters, etc. Block noise that occurs in high-speed video, random noise that causes flickering, and increased resolution Removes various noises such as dot noise caused by conversion.

[0473] The gradation conversion process converts the gradation of the image into a gradation that corresponds to the output characteristics of the display panel 620. For example, when increasing the number of gradations, for an image input with a small number of gradations, The histogram is smoothed by interpolating and assigning a corresponding tone value to each pixel. It can also be used to widen the dynamic range, high dynamic range (HD R) processing is also included in the tone conversion processing.

[0474] In addition, pixel interpolation processing involves the creation of data that does not actually exist when the resolution is up-converted. For example, it refers to the pixels around the target pixel and displays the intermediate color between them. Interpolate the data to

[0475] The color correction process is a process for correcting the color tone of an image. For example, the television device 600 The type, brightness, or color purity of the lighting in the space in which the device is installed is detected, and the display panel is adjusted accordingly. The brightness and color tone of the image displayed on the panel 620 are corrected to be optimal. The image is compared with images of various scenes in a pre-stored image list, and the most similar The image display device may have a function of correcting the brightness and color tone of the displayed image to suit the image of the scene.

[0476] Inter-frame interpolation is used to increase the frame frequency of the displayed image, which is not inherently present. For example, two images can be generated from the difference between two images. Generate an interpolated frame image to be inserted between two images. It is also possible to generate an interpolated frame image. For example, When the frame frequency of the video signal is 60Hz, multiple interpolated frames can be generated. As a result, the frame frequency of the video signal output to the timing controller 607 is doubled to 1. It can be increased to 20Hz, or 4 times to 240Hz, or 8 times to 480Hz. Cut.

[0477] The image processing circuit 604 also uses a neural network to perform image processing. In FIG. 24(A), the image processing circuit 604 is 6 shows an example in which the network 610 is provided.

[0478] For example, the neural network 610 can generate a The image processing circuit 604 can then perform feature extraction. It is possible to select a suitable correction method or parameters to be used for correction.

[0479] Alternatively, the neural network 610 itself may be provided with the function of performing image processing. That is, by inputting image data before image processing into the neural network 610, The image data that has been subjected to image processing may be output.

[0480] The weighting coefficient data used in the neural network 610 is stored in a data table. The data table including the weighting coefficients is stored in the storage unit 602. The unit 603 can be updated to the latest version via a computer network. Alternatively, the image processing circuit 604 has a learning function and updates the data table including the weighting coefficients. This may be a possible configuration.

[0481] FIG. 24B shows a schematic diagram of a neural network 610 included in the image processing circuit 604. Shows.

[0482] In this specification, the term "neural network" refers to a network that imitates the neural circuit network of a living organism and is used for learning. The general model that determines the strength of connections between neurons through learning and gives them problem-solving ability is A neural network has an input layer, an intermediate layer (also called a hidden layer), and an output layer. Neural networks with two or more intermediate layers are called deep learning ( or deep neural networks (DNNs).

[0483] In addition, when describing neural networks in this specification, etc., Determining the connection strength (also called weight coefficient) between neurons from the information is called "learning." In this specification, the connection strength obtained by learning is used. The process of constructing a neural network using these data and deriving new conclusions from it is called "inference." There is a match.

[0484] The neural network 610 comprises an input layer 611, one or more hidden layers 612, and an output The input layer 611 receives input data, and the output layer 613 receives output data. The data is output.

[0485] The input layer 611, the hidden layer 612, and the output layer 613 each have neurons 615. Here, the neuron 615 indicates a circuit element (product-sum operation element) that can realize a product-sum operation. In Figure 24(B), the data input between two neurons 615 in two layers is The output direction is indicated by an arrow.

[0486] The calculation process in each layer is performed using the output of the neuron 615 in the previous layer and the weight coefficients. For example, the output of the i-th neuron in the input layer 611 is expressed as x i and the output x i The connection strength (weight coefficient) between the j-th neuron in the next hidden layer 612 and j i Then, the output of the jth neuron in the hidden layer is y j =f(Σw ji x i ) Note that i and j are integers equal to or greater than 1. Here, f(x) is the activation function, which is a sigmoid function. A threshold function or the like can be used. Similarly, the output of the neuron 615 in each layer is calculated by The activation function is calculated by multiplying and adding the output of the layer neuron 615 and the weighting coefficient. In addition, the connections between layers may be full connections in which all neurons are connected to each other, or Partial connections in which some neurons are connected to each other may also be used.

[0487] FIG. 24(B) shows an example having three intermediate layers 612. Note that the intermediate layers 612 The number of intermediate layers is not limited to this, and it is sufficient to have one or more intermediate layers. The number of neurons in the hidden layer 6 can be changed as needed depending on the specifications. The number of neurons 615 in the input layer 611 or the output layer 613 is The number of conductors may be greater or less than the number of conductors 615.

[0488] The weighting coefficients, which are indicative of the strength of connections between neurons 615, are determined by learning. The learning may be performed by a processor included in the television device 600, but may also be performed by a dedicated server. It is preferable to run it on a computer with high computing power, such as a server or the cloud. The weighting coefficients determined by the above are stored in the storage unit 602 as a table, and are then input to the image processing circuit 6 The table is used by being read by 04. It can be updated via a computer network.

[0489] This concludes the explanation of neural networks.

[0490] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0491] In this example, an insulating layer according to one embodiment of the present invention was evaluated. Samples A1, A2, and A3 were prepared. Samples A1 and A2 are embodiments of the present invention. This insulating layer corresponds to the insulating layer 106 and the region 106a shown in the embodiment. A3 is an insulating layer for comparison.

[0492] <Sample A1, Sample A2, Sample A3> First, the samples prepared in this example will be described.

[0493] Samples A1, A2, and A3 are each a 400 nm thick nitride silicon film on a glass substrate. The silicon nitride film was formed using a PECVD device. The plate temperature was set to 350°C, and silane gas with a flow rate of 200 sccm and nitrogen gas with a flow rate of 2000 sccm were used. Ammonia gas at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm were introduced into the chamber. The RF power was set to 2000 W between the parallel plate electrodes installed in the PECVD device. Deposited a 50 nm thick silicon nitride film, and then changed the flow rate of ammonia gas to 200 0 sccm to deposit a 300 nm thick silicon nitride film, and then changed the flow rate of ammonia gas to 100 sccm to deposit a 50 nm thick silicon nitride film.

[0494] Next, plasma treatment was performed in an atmosphere containing oxygen. The conditions of the plasma treatment performed on sample A1 were a temperature of 350 °C, a pressure of 40 Pa, a power supply power of 3000 W, an oxygen flow rate of 3000 sccm, and a treatment time of 300 seconds. The conditions of the plasma treatment performed on sample A2 were a temperature of 350 °C, a pressure of 40 Pa, a power supply power of 3000 W, a dinitrogen monoxide flow rate of 3000 sccm, and a treatment time of 300 seconds. Sample A3 was not subjected to plasma treatment. Note that samples A1 and A2 were each subjected to plasma treatment continuously in a vacuum after the deposition of the silicon nitride film.

[0495] The glass substrates used for each of the above samples had a size of 600 mm × 720 mm.

[0496] <X-ray Photoelectron Spectroscopy> Next, X-ray photoelectron spectroscopy (XPS) was performed on samples A1, A2, and A3.

[0497] The spectra of Si2p, O1s, and N1s obtained by XPS measurement are shown in Fig. 25. Fig. 2 5 shows the binding energy [eV] on the horizontal axis and the intensity of photoelectrons (arbitrary unit) on the vertical axis.

[0498] For XPS measurement, Quantera SXM manufactured by ULVAC-PHI was used. A monochromatized Al Kα ray (1486.6 eV) was used as the X-ray source and the detection area was 100 μmφ. It was performed. The extraction angle was set to 45°. The detection depth is considered to be about 4 nm to 5 nm.

[0499] As shown in Fig. 25, compared with sample A3, it was found that the peaks derived from the Si-N bond in samples A1 and A2 were small, and the peaks derived from the Si-O bond were large. Therefore, it was found that in samples A1 and A2, the vicinity of the silicon nitride film surface was oxidized by the above-described plasma treatment, and a region having more oxygen than silicon nitride was formed.

[0500] <TEM Observation> Next, samples A1 to A3 were thinned by a focused ion beam (FIB), and the cross-section of the sample was observed by TEM. For the TEM observation, a transmission electron microscope H-9500 manufactured by Hitachi High-Technologies Corporation was used, and the acceleration voltage was set to 300 kV.

[0501] The cross-sectional TEM images of sample A1 are shown in Fig. 26(A), sample A2 in Fig. 26(B), and sample A3 in Fig. 26(C). Figs. 26(A) to 26(C) are transmission electron images (TE images: Transmission Electron Image) at a magnification of 2 million times.

[0502] As shown in Figs. 26(A) and 26(B), regions with different concentrations (luminances) of the TEM image were confirmed near the surfaces of samples A1 and A2. In view of the above-described XPS measurement results, it is considered that the surfaces of samples A1 and A2 were oxidized, and regions having more oxygen than silicon nitride (hereinafter referred to as oxidation regions) were formed. No layer with different TEM image concentrations (luminances) was confirmed near the surface of sample A3.

[0503] ​​​​​​​​​​​The thickness of the oxidized region of sample A1 and sample A2 was measured. The measurement point of sample A1 is shown in FIG. ), and sample A2 are shown in Figure 27(B). In Figures 27(A) and 27(B), arrows indicate the measurement points. The length of each sample A1 and A2 was measured at three points. The results are shown in Table 1. In Table 1, the column labeled "oxidized area" shows the values for each measurement point. The column labeled "average" indicates the average value for each sample. It was found that the thickness of the oxidized region was about 6 nm in both Sample A1 and Sample A2.

[0504] [Table 1]

[0505] The configuration shown in this embodiment may be appropriately combined with configurations described in other embodiments or other embodiments. They can be used in combination. [Example]

[0506] In this example, the crystallinity of a metal oxide film according to one embodiment of the present invention was evaluated. In this example, samples B1 to B29 and samples C1 to C25 were prepared. Samples B1 to B29 and Samples C1 to C25 are examples of the present invention. It is a metal oxide film similar to that of the SiO2 film.

[0507] <Samples B1 to B29, Samples C1 to C25> First, the samples prepared in this example will be described.

[0508] Samples B1 to B29 are glass substrates on which metal oxide films with a thickness of 100 nm are formed. The metal oxide film is formed using a sputtering device. The target was In-Ga-Zn oxide (In:Ga:Zn=4:2:3 [atomic ratio]). The sputtering process was carried out under a controlled pressure of 0.6 Pa and with an AC power of 2500 W. The substrate temperature (Tsub.) during film formation was set to 100°C for each of samples B1 to B29. The Ar flow rate and O2 flow rate were different. Table 2 shows the main film formation conditions.

[0509] Samples C1 to C25 are made of a glass substrate on which a metal oxide film having a thickness of 100 nm is formed. The metal oxide film is formed using a sputtering device. The target was In-Ga-Zn oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]) The sputtering process was carried out under a pressure controlled at 0.6 Pa and an AC power of 2500 W. The samples C1 to C25 were deposited at the substrate temperature (Tsub The main deposition conditions are shown in Table 3.

[0510] In Tables 2 and 3, the substrate temperature (Tsub.) is listed as room temperature (RT). indicates that the substrate was not heated during film formation. indicates the ratio of the O2 flow rate to the total gas flow rate (the sum of the Ar flow rate and the O2 flow rate).

[0511] The samples B1 to B29 and the samples C1 to C25 were parallel plate type spars. The film was formed using a targeting device. An AC power supply was used as the power source. The glass substrate used for each sample was 600 mm thick. The size is m x 720 mm.

[0512] [Table 2]

[0513]

Table 3

[0514] <Crystallinity evaluation by XRD measurement> Next, X-ray diffraction (XRD) measurements were performed on Samples B1 to B29 and Samples C1 to C25. The coordinates of the glass substrates on which XRD was performed are shown in Fig. 28. Fig. 28 is the coordinates representing the locations where XRD was performed on a glass substrate with a size of 600 mm × 7 20 mm. The positions corresponding to B, E, and H indicated by white circles in Fig. 28 were used as the coordinates for XRD measurement.

[0515] The XRD spectra of Samples B1 to B17 are shown in Fig. 29, and Samples B18 to B29 are shown in Fig. 30. The XRD spectra of Samples C1 to C15 are shown in Fig. 31, and Samples C16 to Samples C25 are shown in Fig. 32.

[0516] Figs. 29 to 32 are spectra obtained by the θ-2θ scan method, which is a type of out-of-plane method. The horizontal axis indicates the diffraction angle 2θ [deg.], and the vertical axis indicates the diffracted X-ray intensity ( arbitrary unit). The θ-2θ scan method measures the X-ray diffraction intensity while changing the incident angle of the X-ray and setting the angle of the detector provided opposite the X-ray source to be the same as the incident angle. It is a method of measuring the X-ray diffraction intensity while changing the incident angle of the X-ray and setting the angle of the detector provided opposite the X-ray source to be the same as the incident angle. The θ-2θ scan method is sometimes called the powder method.

[0517] An X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used for XRD measurement. CuKα rays with a wavelength of 0.15418 nm were used as the X-ray source, the scanning range was 2θ = 15 de g. to 50 deg., the step width was 0.01 deg., and the scanning speed was 6.0 deg. / min. It was decided.

[0518] As shown in FIGS. 29 and 30, samples B2 to B29 show the CAAC-OS. A peak was confirmed near θ = 31°. Samples B2 to B29 have good crystallinity. It was found that, for sample B1, no clear peak was observed near 2θ=31°. It was found that Sample B1 had lower crystallinity than Samples B2 to B29.

[0519] 29 and 30, the substrate temperature during film formation is increased, or By increasing the oxygen gas flow rate ratio, the peak intensity around 2θ=31° increases. In addition, samples B1 to B29 show a tendency to exhibit 2-phase morphology, which is suggested to be due to the spinel phase. No peak was observed near θ=36°.

[0520] As shown in FIGS. 31 and 32, samples C3 to C5, samples C7 to C10, In samples C12 to C25, a peak indicating CAAC-OS was confirmed near 2θ = 31°. Samples C3 to C5, C7 to C10, and C12 to C25 were good. It was found that the samples C2 and C11 had good crystallinity. A small peak was confirmed near 2θ=31°, which indicates crystalline structure. Samples C2 and C11 also showed crystalline structure. Samples C1 and C6 showed a clear peak near 2θ = 31°. It was not possible to confirm the results. Samples C1 and C6 were not as good as samples C2 to C5, samples C7 to C8. It was found that the crystallinity was lower than that of C25.

[0521] As shown in FIGS. 31 and 32, the substrate temperature during film formation is increased, or By increasing the oxygen gas flow rate ratio, the peak intensity around 2θ=31° increases. In addition, samples C3 to C5, samples C8 to C10, samples C12 to C16 Samples C15, C17 to C20, and C22 to C25 are spinel phase-induced crystals. A peak was confirmed near 2θ=36°, which is suggested to be due to the

[0522] The configuration shown in this embodiment may be appropriately combined with configurations described in other embodiments or other embodiments. They can be used in combination. [Example]

[0523] In this example, a transistor was fabricated and the electrical characteristics of the transistor were evaluated. In this example, the following samples D1 to D4 were prepared and evaluated. The samples D1 to D4 each have a different configuration of the metal oxide layer 108. In sample D4, the channel width W of the transistor was set to 50 μm, and the channel length L was set to 2 μm and 3 μm. The samples D1 to D4 each had 10 transistors with each channel length L. are formed one by one.

[0524] <Method for preparing sample D1> First, a conductive layer 104 was formed on a substrate 102. A glass substrate was used as the substrate 102. In addition, a tungsten film with a thickness of 100 nm was formed using a sputtering device. This was processed to form the conductive layer 104 .

[0525] Next, an insulating layer 106 was formed on the substrate 102 and the conductive layer 104. The silicon nitride film is 400 nm thick and a silicon oxynitride film is 5 nm thick on the silicon nitride film. The SiO2 film was formed using a PECVD apparatus.

[0526] The conditions for forming the insulating layer 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000 W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50 nm. Next, the flow rate of ammonia gas was changed to 2000 sccm, and a nitride silicon layer with a thickness of 300 nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 After the silicon nitride film was formed, the A silicon oxynitride film was continuously formed in the chamber. The substrate temperature was set to 350°C, and the flow rate of silane gas was 20 sccm. ccm of nitrous oxide gas was introduced into the chamber, the pressure was set to 40 Pa, and the PECVD equipment The film was formed by supplying 500 W of RF power between parallel plate electrodes placed in the apparatus.

[0527] Next, a metal oxide layer 108 was formed on the insulating layer 106. Note that the metal oxide of sample D1 The layer 108 includes a first metal oxide layer IGZOa1 and a first metal oxide layer IGZOa The first metal oxide layer IGZOb1 was formed on the first metal oxide layer IGZOb1. The ZOa1 and the second metal oxide layer IGZOb1 were formed in a vacuum using a sputtering device. The laminated metal oxide layers were processed to obtain the metal oxide layer 108. .

[0528] For IGZOa1, a 20 nm thick In-Ga-Zn oxide film was formed. The deposition conditions for IGZOa1 were: substrate temperature at room temperature, argon gas at a flow rate of 180 sccm. Gas and oxygen gas at a flow rate of 20 sccm (oxygen flow rate ratio 10%) were introduced into the chamber, and the pressure The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:Ga:Zn = 1:1:1.2 [atomic ratio]) and an AC power of 2500 W was applied to form the film.

[0529] For IGZOb1, an IGZO film with a thickness of 30 nm was formed. The film formation conditions were as follows: the substrate temperature was room temperature, and the flow rate of argon gas was 100 sccm and the flow rate of 1 00 sccm of oxygen gas (oxygen flow rate ratio 50%) was introduced into the chamber, and the pressure was set to 0.6P a) and a polycrystalline metal oxide sputtering target (In:Ga:Zn=1:1:1 The film was formed by applying 2500 W of AC power to a sample containing 1.2 [atomic ratio].

[0530] Next, the sample was heated at 350°C for 1 hour in a nitrogen atmosphere, and then cooled in a mixed gas of nitrogen and oxygen. The sample was subjected to a heat treatment at 350°C for 1 hour in a nitrogen atmosphere.

[0531] Next, a conductive film is formed over the insulating layer 106 and the metal oxide layer 108, and the conductive film is processed. The conductive layers 112a and 112b were formed by this method. A first titanium film with a thickness of 30 nm and a copper film with a thickness of 200 nm were deposited in this order using a sputtering device. Next, the copper film was etched by photolithography, and then a 100 mm thick film was formed. A second titanium film with a thickness of nm was formed using a sputtering system. The first titanium film and the second titanium film are etched by etching, and the conductive layer 112a and the conductive layer 112b are formed. The conductive layer 112b was formed.

[0532] Next, the exposed surface of the metal oxide layer 108 (on the back channel side) is washed with phosphoric acid. For phosphoric acid cleaning, 85% phosphoric acid was diluted to 1 / 100 with water. The solution was applied for 15 seconds at room temperature.

[0533] Next, a first plasma treatment was carried out in an atmosphere containing oxygen gas. The first plasma treatment was carried out under the conditions of a temperature of 350°C, a pressure of 40 Pa, and Power supply power 3000W, oxygen flow rate 3000sccm (oxygen flow rate ratio 100%), treatment time 30 It was set to 0 seconds.

[0534] Next, an insulating layer is formed on the insulating layer 106, the metal oxide layer 108, the conductive layer 112a, and the conductive layer 112b. The insulating layer 114 was formed using a silicon oxynitride film having a thickness of 50 nm. It was formed using a PECVD device.

[0535] The conditions for forming the insulating layer 114 were a substrate temperature of 350° C. and a flow rate of 100 sccm. The run gas and nitrous oxide gas at a flow rate of 2500 sccm were introduced into the chamber, and the pressure was The pressure was 400 Pa, and 500 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. was supplied to form a film.

[0536] After forming the insulating layer 114, a second plasma is successively formed in the chamber of the PECVD apparatus. The second plasma treatment was carried out under the conditions of a temperature of 350°C, a pressure of 40 Pa, and a power supply voltage of 100 V. 3000W, oxygen flow rate 3000sccm (oxygen flow rate ratio 100%), treatment time 600 seconds Ta.

[0537] Next, a third plasma treatment was carried out in an atmosphere containing oxygen gas. The third plasma treatment was carried out under the conditions of a temperature of 220°C, a pressure of 40 Pa, and Power supply power 3000W, oxygen flow rate 3000sccm (oxygen flow rate ratio 100%), treatment time 60 It was set to 0 seconds.

[0538] Next, an insulating layer 116 was formed on the insulating layer 114. The insulating layer 116 had a thickness of 100 A silicon nitride film with a thickness of 100 nm was formed using a PECVD apparatus.

[0539] The conditions for forming the insulating layer 116 are a substrate temperature of 350° C. and a flow rate of 50 sccm. Silane gas with a flow rate of 5000 sccm, nitrogen gas with a flow rate of 100 sccm, and ammonia gas with a flow rate of 100 sccm. The gas was introduced into the chamber, the pressure was set to 100 Pa, and the The film was formed by supplying 1000 W of RF power between the parallel plate electrodes.

[0540] Thereafter, an acrylic resin film having a thickness of about 1.5 μm is formed on the insulating layer 116, and then processed. The acrylic resin film was made of an acrylic photosensitive resin and was heated under a nitrogen atmosphere. Then, the substrate was baked at 250°C for 1 hour. Heat treatment was carried out at 250°C for 1 hour.

[0541] Through the above steps, sample D1 of this example was fabricated.

[0542] <Preparation method of sample D2> Sample D2 differs from Sample D1 in the deposition conditions for the metal oxide layer 108. The process was the same as that for sample D1.

[0543] The metal oxide layer 108 of sample D2 was composed of a third metal oxide layer IGZOc2 and a third a first metal oxide layer IGZOa2 on the metal oxide layer IGZOc2; The layer structure was a stack of IGZOa2 and a second metal oxide layer, IGZOb2. a first metal oxide layer IGZOc2, a second metal oxide layer IGZOa2, and a third metal oxide layer IGZO b2 was formed continuously in a vacuum using a sputtering device. The oxide layer was processed to obtain a metal oxide layer 108 .

[0544] For IGZOc2, an IGZO film with a thickness of 5 nm was formed. The film conditions were as follows: the substrate temperature was room temperature, and the flow rate of argon gas was 100 sccm, and the flow rate of 10 0 sccm of oxygen gas (oxygen flow rate ratio 50%) was introduced into the chamber, and the pressure was set to 0.6 Pa. and a polycrystalline metal oxide sputtering target (In:Ga:Zn=1:1:1. 2 [atomic ratio]) and an AC power of 2500 W was applied to form the film.

[0545] For IGZOa2, a 20 nm thick In-Ga-Zn oxide film was formed. The deposition conditions for IGZOa2 were: substrate temperature at room temperature, argon gas at a flow rate of 180 sccm. Gas and oxygen gas at a flow rate of 20 sccm (oxygen flow rate ratio 10%) were introduced into the chamber, and the pressure The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:Ga:Zn = 1:1:1.2 [atomic ratio]) and an AC power of 2500 W was applied to form the film.

[0546] For IGZOb2, an IGZO film with a thickness of 30 nm was formed. The film formation conditions were as follows: the substrate temperature was room temperature, and the flow rate of argon gas was 100 sccm and the flow rate of 1 00 sccm of oxygen gas (oxygen flow rate ratio 50%) was introduced into the chamber, and the pressure was set to 0.6P a) and a polycrystalline metal oxide sputtering target (In:Ga:Zn=1:1:1 The film was formed by applying 2500 W of AC power to a sample containing 1.2 [atomic ratio].

[0547] Sample D2 of this example was fabricated through the above steps.

[0548] <Method for preparing sample D3> Sample D3 differs from Sample D1 in the deposition conditions for the metal oxide layer 108. The process was the same as that for sample D1.

[0549] The metal oxide layer 108 of sample D3 was composed of a first metal oxide layer IGZOa3 and a first A laminated structure was formed of a metal oxide layer IGZOa3 and a second metal oxide layer IGZOb3 on top of it. The first metal oxide layer IGZOa3 and the second metal oxide layer IGZOb3 are formed by sputtering. The metal oxide layers were processed to form a gold film. A metal oxide layer 108 was obtained.

[0550] For IGZOa3, a 20 nm thick In-Ga-Zn oxide film was formed. The deposition conditions for IGZOa3 were a substrate temperature of 70°C and an argon gas flow rate of 180 sccm. A gas containing 10% oxygen and a flow rate of 20 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:Ga:Z The film was formed by applying 2500 W of AC power to a mixture of 1:1:1.2 (atomic ratio).

[0551] For IGZOb3, an IGZO film with a thickness of 30 nm was formed. The film formation conditions were a substrate temperature of 70°C, argon gas at a flow rate of 100 sccm, and 100 sccm of oxygen gas (oxygen flow rate 50%) was introduced into the chamber, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn=1:1: The film was formed by applying 2500 W of AC power to a sample with an atomic ratio of 1.2.

[0552] Sample D3 of this example was fabricated through the above steps.

[0553] <Preparation method of sample D4> Sample D4 differs from Sample D1 in the deposition conditions for the metal oxide layer 108. The process was the same as that for sample D1.

[0554] The metal oxide layer 108 of sample D4 was composed of a third metal oxide layer IGZOc4 and a third A first metal oxide layer IGZOa4 on the metal oxide layer IGZOc4, and a first metal oxide layer The layer structure was a stack of IGZOa4 and a second metal oxide layer, IGZOb4. a first metal oxide layer IGZOc4, a second metal oxide layer IGZOa4, and a third metal oxide layer IGZO b4 was formed continuously in a vacuum using a sputtering device. The oxide layer was processed to obtain a metal oxide layer 108 .

[0555] For IGZOc4, an IGZO film with a thickness of 5 nm was formed. The film conditions were a substrate temperature of 70°C, argon gas at a flow rate of 100 sccm, and 00 sccm of oxygen gas (oxygen flow rate ratio 50%) was introduced into the chamber, and the pressure was set to 0.6P a) and a polycrystalline metal oxide sputtering target (In:Ga:Zn=1:1:1 The film was formed by applying 2500 W of AC power to a sample containing 1.2 [atomic ratio].

[0556] For IGZOa4, a 20 nm thick In-Ga-Zn oxide film was formed. The deposition conditions for IGZOa4 were a substrate temperature of 70°C and an argon gas flow rate of 180 sccm. A gas containing 10% oxygen and a flow rate of 20 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:Ga:Z The film was formed by applying 2500 W of AC power to a mixture of 1:1:1.2 (atomic ratio).

[0557] For IGZOb4, an IGZO film with a thickness of 30 nm was formed. The film formation conditions were a substrate temperature of 70°C, argon gas at a flow rate of 100 sccm, and 100 sccm of oxygen gas (oxygen flow rate 50%) was introduced into the chamber, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn=1:1: The film was formed by applying 2500 W of AC power to a sample with an atomic ratio of 1.2.

[0558] Sample D4 of this example was fabricated through the above steps.

[0559] <Transistor electrical characteristics> Next, the Id-Vg characteristics of the transistors were measured for the fabricated samples. The measurement conditions for the Id-Vg characteristics of the transistor are as follows: gate voltage (Vg) is set to -15V The source voltage (Vs) was set to 0 V and the voltage was applied from +20 V to +20 V in 0.25 V steps. The drain voltage (Vd) was set to 0.1 V and 15 V. The number of measurements was The result was 10.

[0560] Next, the Id-Vg characteristics of the above-prepared samples D1 to D4 were measured. The d-Vg characteristics results are shown in Figs. 33(A) and 33(B), and the results for sample D2 are shown in Figs. 34(A) and 34(B). (B), sample D3 in Fig. 35(A) and Fig. 35(B), sample D4 in Fig. 36(A) and Fig. 36(B). (B) shows the channel. The results for a transistor with a channel length L of 2 μm and a channel width W of 50 μm are shown in Figure 33(B). 34(B), 35(B) and 36(B) show the results when the channel length L is 3 μm and the channel The results for a transistor with a width W of 50 μm are shown. B), Fig. 34(A), Fig. 34(B), Fig. 35(A), Fig. 35(B), Fig. 36(A) and Fig. In 36(B), the first vertical axis is Id [A] and the second vertical axis is μFE [cm 2 / Vs], The horizontal axis indicates Vg [V].

[0561] Figure 33(A), Figure 33(B), Figure 34(A), Figure 34(B), Figure 35(A), Figure 35( As shown in FIGS. 36(A) and 36(B), all of the samples D1 to D4 were It was confirmed that the electrical characteristics were good with little variation at a channel length of L = 3 μm. In addition, samples D2 and D4 exhibited good performance with little variation even at a channel length L of 2 μm. It was confirmed that the electrical properties were excellent.

[0562] Next, the reliability of the samples D1 to D4 was evaluated. A bias-thermal stress test (hereinafter referred to as a GBT test) was used.

[0563] In this example, the GBT test conditions were a gate voltage (Vg) of ±30 V and a drain voltage of ±10 V. The on-voltage (Vd) and source voltage (Vs) were set to 0V (comm), and the stress temperature was set to 70°C. The stress application time was set to 1 hour, and the measurement environment was set to a dark environment and a light irradiation environment (white LED). The experiment was carried out in two environments: one with a light source at 10,000 lx and the other with a light source at 10,000 lx. The source and drain electrodes of the transistor are set to the same potential, and the gate electrode is connected to the source and drain electrodes. A potential different from that of the gate electrode was applied for a certain period of time (here, 1 hour). The transistor has a channel length L of 3 μm and a channel width W of 50 μm.

[0564] In addition, when the potential applied to the gate electrode is higher than the potentials of the source electrode and the drain electrode, The potential applied to the gate electrode is set to a positive stress, and the potential applied to the gate electrode is set to a value higher than the potential of the source electrode and the drain electrode. Therefore, in accordance with the measurement environment, the positive GBT (dark), minus GBT (dark), plus GBT (light exposure), and minus GBT The reliability evaluation was carried out under four conditions: P (light irradiation) and P (dark). BTS (Positive Bias Temperature Stress) Negative GBT (Dark) is called NBTS (Negative Bias Temperature) ture Stress), and positive GBT (light irradiation) is PBITS (Positive e Bias Illumination Temperature Stress) and And, negative GBT (light irradiation) is NBITS (Negative Bias Illum Ination Temperature Stress) may be written as follows: be.

[0565] The GBT test results for samples D1 to D4 are shown in FIG. 37. In FIG. 37, the vertical axis The change in the threshold voltage of the transistor (ΔVth) is shown on the axis, and the sample name is shown on the horizontal axis.

[0566] As shown in FIG. 37, all of the samples D1 to D4 had a threshold voltage of 0.01 V in the GBT test. The change in voltage (ΔVth) was within ±2 V. It has been confirmed that transistors having oxide films have high reliability.

[0567] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. [Explanation of symbols]

[0568] 100A transistor 100B transistor 100C transistor 100D transistor 100E transistor 100F transistor 100G transistor 102 Circuit Board 104 Conductive layer 106 Insulating layer 106a area 108 Metal Oxide Layer 108a Metal oxide layer 108b Metal oxide layer 108c metal oxide layer 112a conductive layer 112b Conductive layer 112c conductive layer 114 Insulating layer 114a Insulating layer 114b insulating layer 116 Insulating Layer 120a Conductive layer 120b conductive layer 121 Conductive film 121a Conductive layer 121b Conductive layer 121c conductive layer 122 Conductive film 122a conductive layer 122b Conductive layer 122c conductive layer 123 Conductive Film 123a conductive layer 123b Conductive layer 123c conductive layer 128a Metal oxide film 128b Metal oxide film 130a Oxygen 130b Oxygen 130c oxygen 131 Resist mask 132 Resist mask 134 Conductive film 142a Connection 142b Connection 150 insulating layer 152a Connection 152b Connection 180 Void 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 600 Television equipment 601 Control Unit 602 Storage section 603 Communication Control Unit 604 Image Processing Circuit 605 Decoder Circuit 606 Video signal receiving unit 607 Timing Controller 608 Source Driver 609 Gate Driver 610 Neural Networks 611 Input Layer 612 Middle Class 613 Output Layer 615 neurons 620 Display Panel 621 pixels 630 System Bus 664 Electrode 665 Electrode 667 Electrode 700 Display device 700A display device 701 PCB 702 pixel section 704 Source driver circuit section 705 PCB 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 721 Source Driver IC 722 Gate driver circuit 723 FPC 724 Printed Circuit Board 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrode 770 Planarization insulating film 772 Conductive film 773 insulating film 774 Conductive film 775 Liquid Crystal Elements 776 Liquid Crystal Layer 778 Structure 780 Anisotropic Conductive Film 782 Light-emitting element 786 EL layer 788 Conductive Film 790 Capacitor 791 Touch Panel 792 insulating film 793 Electrode 794 Electrode 795 insulating film 796 Electrode 797 Insulating Film 7000 Display 7100 Television equipment 7101 Housing 7103 Stand 7111 Remote control device 7200 Notebook Personal Computer 7211 Case 7212 keyboard 7213 Pointing Device 7214 External connection port 7300 Digital Signage 7301 Housing 7303 Speaker 7311 Information terminals 7400 Digital Signage 7401 Pillar 7411 Information terminals

Claims

1. A substrate; a first conductive layer having a region in contact with the upper surface of the substrate and functioning as a gate electrode; a first insulating layer having a region in contact with an upper surface of the first conductive layer and functioning as a gate insulating film; a second insulating layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate insulating film; a metal oxide layer having a region in contact with an upper surface of the second insulating layer and functioning as a channel formation region; a third insulating layer having a region in contact with an upper surface of the metal oxide layer; a second conductive layer having a region in contact with an upper surface of the metal oxide layer through a first opening provided in the third insulating layer and a region in contact with the upper surface of the third insulating layer, the second conductive layer functioning as one of a source electrode and a drain electrode; a third conductive layer having a region in contact with an upper surface of the metal oxide layer through a second opening provided in the third insulating layer and a region in contact with the upper surface of the third insulating layer, the third conductive layer having a function as the other of the source electrode and the drain electrode; a fourth insulating layer having a region in contact with an upper surface of the third insulating layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; a fifth insulating layer having a region located above the fourth insulating layer; the first conductive layer comprises copper and titanium; the first insulating layer comprises silicon and nitrogen; the second insulating layer has a region having a higher oxygen concentration than the first insulating layer, the second conductive layer includes a first titanium film and a first copper film having a region in contact with an upper surface of the first titanium film; the third conductive layer includes a second titanium film and a second copper film having a region in contact with an upper surface of the second titanium film; the fourth insulating layer comprises silicon and oxygen; the fifth insulating layer comprises silicon and nitrogen; an end of the first titanium film has a region that protrudes more than an end of the first copper film in a cross-sectional view in a channel length direction; In a cross-sectional view in the channel length direction, the end of the second titanium film has a region that protrudes further than the end of the second copper film.

2. A substrate; a first conductive layer having a region in contact with the upper surface of the substrate and functioning as a gate electrode; a first insulating layer having a region in contact with an upper surface of the first conductive layer and functioning as a gate insulating film; a second insulating layer having a region in contact with an upper surface of the first insulating layer and functioning as a gate insulating film; a metal oxide layer having a region in contact with an upper surface of the second insulating layer and functioning as a channel formation region; a third insulating layer having a region in contact with an upper surface of the metal oxide layer; a second conductive layer having a region in contact with an upper surface of the metal oxide layer through a first opening provided in the third insulating layer and a region in contact with the upper surface of the third insulating layer, the second conductive layer functioning as one of a source electrode and a drain electrode; a third conductive layer having a region in contact with an upper surface of the metal oxide layer through a second opening provided in the third insulating layer and a region in contact with the upper surface of the third insulating layer, the third conductive layer having a function as the other of the source electrode and the drain electrode; a fourth insulating layer having a region in contact with an upper surface of the third insulating layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the third conductive layer; a fifth insulating layer having a region located above the fourth insulating layer; a fourth conductive layer having a region in contact with an upper surface of the second conductive layer or the third conductive layer through a third opening provided in the fourth insulating layer and the fifth insulating layer, and having a function as a pixel electrode; the first conductive layer comprises copper and titanium; the first insulating layer comprises silicon and nitrogen; the second insulating layer has a region having a higher oxygen concentration than the first insulating layer, the second conductive layer includes a first titanium film and a first copper film having a region in contact with an upper surface of the first titanium film; the third conductive layer includes a second titanium film and a second copper film having a region in contact with an upper surface of the second titanium film; the fourth insulating layer comprises silicon and oxygen; the fifth insulating layer comprises silicon and nitrogen; an end of the first titanium film has a region that protrudes more than an end of the first copper film in a cross-sectional view in a channel length direction; In a cross-sectional view in the channel length direction, the end of the second titanium film has a region that protrudes further than the end of the second copper film.

3. In claim 1 or claim 2, The metal oxide layer includes In, Ga, and Zn.

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