Semiconductor device

Abstract

To provide a highly reliable semiconductor device which prevents yield deterioration caused by ESD damage.SOLUTION: A semiconductor device has: a gate electrode layer; a gate insulation layer on the gate electrode layer; an oxide insulation layer on the gate insulation layer; an oxide semiconductor layer which contacts a surface of the oxide insulation layer and overlaps the gate electrode layer; and a source electrode layer and a drain electrode layer which are electrically connected with the oxide semiconductor layer. The gate insulation layer is composed to include a nitrogen-containing silicon film; and the oxide insulation layer contains one or a plurality of metal elements selected from constituent elements of the oxide semiconductor layer; and a film thickness of the gate insulation layer is thicker than that of the oxide insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed in this specification and the like relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices, light-emitting displays, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). These are widely used in electronic devices such as semiconductors that can be applied to transistors. Silicon-based semiconductor materials are widely known as thin film semiconductors, but other materials include oxide semiconductors. Conductors are attracting attention.

[0004] For example, zinc oxide or an In-Ga-Zn-based oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] In the case of mass-producing semiconductor devices using oxide semiconductors (hereinafter abbreviated as "mass production") Considering the development cost and development speed, the amorphous silicon, which is a mass production technology that has been put into practical use, Transistor configurations using silicon-based semiconductor materials such as silicon and polycrystalline silicon, It is desirable to utilize process conditions or production equipment.

[0007] However, the carrier generation mechanism of oxide semiconductors is significantly different from that of silicon-based semiconductor materials. The physical properties of oxide semiconductors have a significant effect on the characteristics and reliability of transistors. It has a significant impact.

[0008] In particular, the gate insulating layer used for silicon-based semiconductor materials is now applied to oxide semiconductors. Therefore, the oxide semiconductor does not have a sufficient interface characteristic. There is a need for the development of gate insulating layers suitable for semiconductor devices using conductors.

[0009] In addition, transistors using silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon are being developed. The semiconductor device composed of the 8th generation (2160mm wide x 2460mm long) or higher Since it can be used on glass substrates, it has the advantage of high productivity and low cost. When a glass substrate is used, it has high insulating properties and a large surface area, so it is difficult to apply static electricity. The problem of damage caused by ESD (Electro-Static Discharge) is particularly serious. This is also a problem that must be taken into consideration when using oxide semiconductor materials.

[0010] In light of the above-mentioned technical background, one aspect of the present invention is to There are few changes in transistor configuration, process conditions, or production equipment, and the like, making it stable for semiconductor devices. Another object of the present invention is to provide a highly reliable semiconductor device having good electrical characteristics.

[0011] Another embodiment of the present invention is a semiconductor device that can prevent a decrease in yield due to electrostatic breakdown. One of our goals is to provide the following. [Means for solving the problem]

[0012] One embodiment of the disclosed invention is a method for forming a gate electrode layer and an oxide semiconductor layer between the gate electrode layer and the oxide semiconductor layer. a silicon film containing nitrogen and one or more metals selected from the constituent elements of the oxide semiconductor layer; and an oxide insulating layer containing an element.

[0013] The silicon film containing nitrogen has a higher dielectric constant than the silicon oxide film, so it has the same capacitance. Therefore, a silicon film containing nitrogen is used to obtain the gate insulation. By forming an insulating layer, the gate insulating layer can be physically thickened, which increases the dielectric strength. Therefore, it is possible to suppress the decrease in the dielectric strength and preferably improve the dielectric strength. Therefore, electrostatic breakdown of a semiconductor device including a protective insulating layer can be suppressed.

[0014] The thickness of the nitrogen-containing silicon film is preferably 325 nm or more and 550 nm or less, It is more preferable that the thickness is 355 nm or more and 550 nm or less. As the film, a silicon nitride film can be preferably used.

[0015] Nitrogen-containing silicon films are silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon. Since it has also been put to practical use as a gate insulating layer for semiconductor materials, the process conditions or production equipment can be easily diverted. Therefore, by applying a silicon film containing nitrogen to the gate insulating layer, it is possible to form an oxide semiconductor. This makes it possible to mass-produce transistors using conductors at low cost.

[0016] In addition, one or more elements selected from the constituent elements of the oxide semiconductor layer are in contact with the oxide semiconductor layer. By providing an oxide insulating layer of the metal element, the interface between the oxide insulating layer and the oxide semiconductor layer can be improved. In particular, the oxide insulating layer and the oxide semiconductor layer can be kept in good condition and the interface deterioration can be prevented. By suppressing the capture of carriers at the interface with the semiconductor layer, the light degradation of the transistor (e.g., photo-induced This reduces bias degradation and provides a highly reliable transistor.

[0017] That is, according to one aspect of the present invention, a mass production technique for silicon-based semiconductor materials that has been put into practical use The present invention provides a method for forming a silicon film containing nitrogen and an oxide semiconductor layer using a silicon oxide film containing nitrogen and an oxide semiconductor layer containing nitrogen. a stacked structure of an oxide insulating layer containing one or more metal elements and an oxide semiconductor layer; By using this structure, new effects different from those of semiconductor devices using silicon-based semiconductor materials can be achieved. Specifically, for example, the following configuration can be provided. do.

[0018] One embodiment of the present invention is a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate insulating layer. an oxide insulating layer; an oxide semiconductor layer which is over and in contact with the oxide insulating layer and overlaps with the gate electrode layer; a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer; The insulating layer is configured to include a silicon film containing nitrogen, and the oxide insulating layer is configured to include a silicon film containing nitrogen. The gate insulating layer contains one or more metal elements selected from the constituent elements, and the thickness of the gate insulating layer is The semiconductor device is thicker than the edge layer.

[0019] In the semiconductor device, the edge of the oxide semiconductor layer and the edge of the oxide insulating layer are aligned. In this specification, the term "match" also includes "approximate match." For example, The edge of layer A and the edge of layer B of the laminated structure etched using the same mask are aligned. It is considered to be.

[0020] a layer selected from the constituent elements of the oxide semiconductor layer, the layer being in contact with a lower layer of the oxide semiconductor layer; Alternatively, in addition to a stacked structure of an oxide insulating layer containing a plurality of metal elements and a silicon film containing nitrogen, The stacked layer structure may be provided in contact with an upper layer of the oxide semiconductor layer. , to give more stable electrical characteristics to the semiconductor device, and / or to reduce electrostatic breakdown of the semiconductor device. It is possible to prevent this.

[0021] That is, another embodiment of the present invention is a gate electrode layer, a gate insulating layer on the gate electrode layer, a first oxide insulating layer on the gate insulating layer; a gate electrode layer on the first oxide insulating layer; The oxide semiconductor layer overlapping the source electrode layer and the drain electrode layer electrically connected to the oxide semiconductor layer. a second electrode layer covering the source and drain electrode layers and in contact with a part of the oxide semiconductor layer; a second oxide insulating layer and a protective insulating layer on the second oxide insulating layer, The protective insulating layer is formed by including a silicon film containing nitrogen, and the first oxide insulating layer and the second oxide insulating layer are formed by The oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is thicker than the thickness of the first oxide insulating layer, and the thickness of the protective insulating layer is This is a semiconductor device having a thickness greater than that of the second oxide insulating layer.

[0022] In the semiconductor device, the oxide semiconductor layer and the first oxide insulating layer are aligned at the same edge. It is preferable that they are in agreement.

[0023] In any one of the above semiconductor devices, the thickness of the gate insulating layer is 325 nm or more. It is preferable that the thickness is 550 nm or less. In addition, a silicon nitride film is suitably used as the gate insulating layer. It is preferable to use

[0024] In addition, the oxide insulating layer in contact with the oxide semiconductor layer contains oxygen in excess of the stoichiometric composition. The oxide insulating layer preferably includes an oxide semiconductor layer and an oxide insulating layer that is in contact with the oxide semiconductor layer. When the layer includes an oxygen-excess region, oxygen can be supplied to the oxide semiconductor layer. For oxide semiconductors, oxygen vacancies act as donors, generating electrons that become carriers in the oxide semiconductor. Therefore, oxygen is supplied to the oxide semiconductor layer to compensate for oxygen vacancies, resulting in a highly reliable It may be a transistor. [Effects of the Invention]

[0025] The semiconductor device provided by one aspect of the present invention is a semiconductor device that is not modified from mass production techniques that have been put into practical use. Highly reliable semiconductor devices with stable electrical characteristics manufactured using a manufacturing method with minimal damage It is a location.

[0026] In addition, according to one embodiment of the present invention, it is possible to prevent a decrease in yield due to electrostatic breakdown. A body device can be provided. [Brief explanation of the drawings]

[0027] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 3] 1A to 1C illustrate an example of a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 5] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 6] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A and 1B are diagrams illustrating electronic devices. [Figure 9] 1A and 1B are diagrams illustrating electronic devices. [Figure 10] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] ESR measurement results. [Figure 13] TDS measurement results. [Figure 14] FIG. 10 is an energy band diagram of a stacked layer structure included in a transistor of one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0029] In the configuration of the present invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a part having a specific function, the hatch pattern shall be the same and no specific symbol shall be attached. There is a match.

[0030] In each drawing described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0031] In this specification, ordinal numbers such as first, second, etc. are used for convenience. It does not indicate the order of processes or stacking layers. It does not indicate a specific name for the purpose of identification.

[0032] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. 10 and 11. In this embodiment, an oxide semiconductor device is used as an example of a semiconductor device. 1 shows a bottom-gate transistor having a nitride semiconductor layer.

[0033] <Configuration Example 1 of Semiconductor Device> 1A to 1C show examples of a transistor 300. 1(B) is a plan view of the resistor 300, and FIG. 1(B) is a cross-sectional view taken along the chain line X1-Y1 in FIG. 1(A). 1(C) is a cross-sectional view taken along the chain line V1-W1 in FIG. 1(A).

[0034] The transistor 300 includes a gate electrode layer 402 provided on a substrate 400 having an insulating surface. a gate insulating layer 404 on the gate electrode layer 402; and an oxide insulating layer on the gate insulating layer 404. a layer 406, an oxide semiconductor layer that is on and in contact with the oxide insulating layer 406 and overlaps with the gate electrode layer 402, the source electrode layer 410a and the drain electrode layer 410b electrically connected to the oxide semiconductor layer 408; and a gate electrode layer 410b.

[0035] In the transistor 300, the gate insulating layer 404 includes a silicon film containing nitrogen. The silicon film containing nitrogen has a higher dielectric constant than the silicon oxide film, and Because the film thickness required to obtain capacitance is large, it is difficult to physically thicken the gate insulating layer. Therefore, the decrease in the dielectric strength voltage of the transistor 300 can be suppressed, and further, the dielectric strength voltage can be improved. This makes it possible to suppress electrostatic breakdown of the semiconductor device.

[0036] The gate insulating layer 404 is formed to have a thickness at least larger than that of the oxide insulating layer 406. The wavelength is preferably 325 nm or more and 550 nm or less, and more preferably 355 nm or more and 550 nm or less. It is more preferable that the length is m or less.

[0037] Examples of silicon films containing nitrogen include silicon nitride films, silicon nitride oxide films, and silicon oxynitride films. However, the higher the nitrogen content, the higher the relative dielectric constant. It is preferable to use a silicon film. In addition, the energy gap of silicon oxide is 8 eV In contrast, the energy gap of silicon nitride is as small as 5.5 eV. Since the specific resistance is also small, using a silicon nitride film provides higher ESD resistance. Furthermore, when a silicon nitride film is formed by the CVD method, the silicon nitride oxide The greenhouse gas that is applied when forming silicon films containing oxygen and nitrogen, such as silicon films, by the CVD method It is not necessary to use N2O gas, which is a gas source. The film refers to a film whose composition contains more oxygen than nitrogen, and is called a silicon nitride oxide film. refers to a film whose composition contains more nitrogen than oxygen.

[0038] In the transistor 300, the oxide insulating layer 406 is formed of an oxide semiconductor layer 408. The oxide is formed by using such a material containing one or more metal elements selected from the group consisting of: By providing the insulating layer 406, the interface with the oxide semiconductor layer 408 can be stabilized. Therefore, it is possible to prevent charges from being trapped at the interface. Deterioration, particularly light-induced deterioration, can be prevented, and a highly reliable transistor can be obtained.

[0039] Specifically, the oxide insulating layer 406 is formed of, for example, a gallium oxide film (GaO x Also written as (Note that x is not necessarily a natural number and includes non-natural numbers), gallium zinc oxide film (Ga2Zn x O y (also written as x=1~5), Ga2O3 (Gd2O3) film, gallium content Insulating In-Ga-Zn oxide films with a high content of Zn and a low content of indium It is preferable to provide such a function.

[0040] The oxide insulating layer 406 and the oxide semiconductor layer 408 are formed using the same elements, and the compositions of the layers are the same. For example, the oxide semiconductor layer 408 may be an In—Ga—Zn-based oxide semiconductor layer. When using gallium (Ga), the energy gain is determined by the ratio of indium (In) and gallium (Ga). Since the atomic ratio of the oxide semiconductor layer 408 can be controlled, the atomic ratio of In:Ga: The oxide insulating layer 406 is formed by using In:Ga:Zn=1:1:1 or In:Ga:Zn=3:1:2. The atomic ratio of In:Ga:Zn may be set to 1:3:2. The oxide semiconductor layer 408 can be formed by a sputtering method. If the target contains indium, it is possible to reduce the generation of particles during film formation. Therefore, the oxide insulating layer 406 containing indium and the oxide semiconductor containing indium can be Preferably, it is layer 408.

[0041] Note that in the transistor 300 in FIG. 1, when the oxide semiconductor layer 408 is processed into an island shape, This example shows that the oxide insulating layer 406 is also processed into an island shape by etching. The edges of the oxide semiconductor layer 408 and the oxide insulating layer 406 are flush with each other.

[0042] The structure of the oxide semiconductor layer will be described below.

[0043] Oxide semiconductor layers are roughly classified into single-crystal oxide semiconductor layers and non-single-crystal oxide semiconductor layers. The single-crystal oxide semiconductor layer includes an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, and a polycrystalline oxide semiconductor layer. physical semiconductor layer, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor film, etc.

[0044] The amorphous oxide semiconductor layer has an irregular atomic arrangement in the film and is an oxide layer that does not contain a crystalline component. The entire film has a completely amorphous structure, with no crystalline parts even in microscopic areas. A typical example is an oxide semiconductor layer.

[0045] The microcrystalline oxide semiconductor layer is made of, for example, microcrystals (nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor layer has a lower atomic number than the amorphous oxide semiconductor layer. Therefore, the microcrystalline oxide semiconductor layer has a higher order of order than the amorphous oxide semiconductor layer. The defect level density is also low.

[0046] The CAAC-OS film is one of the oxide semiconductor layers having multiple crystal parts. The crystal part is so large that it fits inside a cube with a side length of less than 100 nm. The crystals contained in the S film are cubic with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than the microcrystalline oxide semiconductor layer. The CAAC-OS film has a low density of recessed states. .

[0047] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a crystalline microscope, clear boundaries between the crystals, i.e., crystal boundaries, are clearly visible. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0048] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer has a surface on which the CAAC-OS film is formed (also referred to as a surface on which the CAAC-OS film is formed) or an uneven surface on which the CAAC-OS film is formed. The shape reflects this and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0049] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0050] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, it was found that the metal atoms were arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. stomach.

[0051] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0052] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0053] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a compound semiconductor layer, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0054] From the above, it is concluded that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. Although it is regular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0055] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0056] The crystallinity of the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area near the surface may have a higher degree of crystallinity than the area near the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0057] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0058] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0059] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0060] The oxide semiconductor layer 408 may be, for example, an amorphous oxide semiconductor layer or a microcrystalline oxide semiconductor layer. The film may have any of the structures of a CAAC-OS film, a CAAC-OS film, or a mixed film of these. Alternatively, it may be a laminated film having two or more of these structures.

[0061] Note that the oxide insulating layer 406 might have lower crystallinity than the oxide semiconductor layer 408. The oxide insulating layer 406 may have, for example, an amorphous portion or a nanocrystalline portion.

[0062] The transistor 300 includes a source electrode layer 410a and a drain electrode layer 410b. The oxide insulating layer 412 and / or the oxide insulating layer 412 are in contact with the oxide semiconductor layer 408 and cover the oxide semiconductor layer 408. A protective insulating layer 414 on layer 412 may also be included.

[0063] The oxide insulating layer 412 has the same structure as the oxide semiconductor layer 408, as the oxide insulating layer 406. It is preferable to apply a layer comprising one or more metal elements selected from the group consisting of By using such a material, the boundary between the oxide insulating layer 412 and the oxide semiconductor layer 408 can be easily formed. The oxide insulating layer 412 can stabilize the surface of the oxide semiconductor layer 408. Since it is an insulating layer that contacts the channel side, it can suppress charge trapping at the interface between the two layers. This makes it possible to suppress the occurrence of parasitic channels.

[0064] In addition, oxide semiconductor layers 408 are provided above and below the oxide semiconductor layer 408 so as to sandwich the oxide semiconductor layer 408. By providing an oxide insulating layer containing one or more metal elements selected from the above, it is possible to externally Prevents the diffusion of impurities (such as nitrogen and metal elements) that may affect the body layer. Therefore, the oxide semiconductor layer can be sandwiched between the oxide semiconductor layers or between the oxide semiconductor layers. By providing the oxide insulating layer so as to surround the oxide semiconductor layer, the composition and It is possible to maintain the purity at a constant level and realize a semiconductor device having stable electrical characteristics.

[0065] The protective insulating layer 414 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, a nitride film, or the like. silicon nitride film, silicon oxynitride film, aluminum oxynitride film, or silicon nitride oxide A membrane or the like can be used.

[0066] <Configuration Example 2 of Semiconductor Device> 2A to 2C show examples of the structure of the transistor 310. 2(B) is a plan view of the resistor 310, and FIG. 2(B) is a cross-sectional view taken along the chain line X2-Y2 in FIG. 2(A). 2(C) is a cross-sectional view taken along the chain line V2-W2 in FIG. 2(A).

[0067] The transistor 310 shown in FIG. 2 has an insulating surface, similar to the transistor 300 shown in FIG. A gate electrode layer 402 is provided on a substrate 400, and a gate insulating film is provided on the gate electrode layer 402. a layer 404, an oxide insulating layer 406 on the gate insulating layer 404, and a layer 406 The oxide semiconductor layer 408 overlapping with the gate electrode layer 402 and the oxide semiconductor layer 408 are electrically connected to each other. The source electrode layer 410a and the drain electrode layer 410b are electrically connected to each other. The oxide semiconductor layer 408 is in contact with the source electrode layer 410a and the drain electrode layer 410b. The oxide insulating layer 412 and the protective insulating layer 414 on the oxide insulating layer 412 are formed on the transistor 3. It may also be 10 components.

[0068] The transistor 310 has a structure in which the gate insulating layer 404 and the oxide semiconductor layer 408 are The gate insulating layer 404 in the transistor 310 is different from the transistor 300. A gate insulating layer 404a in contact with the gate electrode layer 402, and a gate insulating layer 404a and an oxide insulating layer and a gate insulating layer 404b provided between the insulating layer 404 and the gate insulating layer 404b. In the transistor 310, the oxide semiconductor layer 408 is in contact with the oxide insulating layer 406. the oxide semiconductor layer 408a and the oxide semiconductor layer 408b in contact with the oxide insulating layer 412. Note that in the transistor 310, the gate insulating layer 404 and the oxide semiconductor The configuration other than the layer 408 is the same as that of the transistor 300. The explanation can be taken into consideration.

[0069] In the transistor 310, the gate insulating layer 404a and the gate insulating layer 404b are made of nitride. It includes a silicon film.

[0070] The gate insulating layer 404a has a thickness greater than that of the gate insulating layer 404b, and defects in the film are reduced. For example, the thickness of the gate insulating layer 404a is set to 300 The wavelength is between 100 nm and 400 nm. The signal that appears at the Nc center (g value is 2.003) in the spin resonance The spin density corresponding to the signal is preferably 1×10 17 spins / cm3 The following is more preferred: Or 5 x 10 16 spins / cm 3 The following silicon nitride film is applied. A silicon nitride film with reduced defects is formed with a thick film thickness (for example, 300 nm or more). This makes it possible to make the withstand voltage of the gate insulating layer 404a, for example, 300 V or more. It is Noh.

[0071] In addition, the gate insulating layer 404b is in contact with the oxide semiconductor layer 408 and therefore has a low hydrogen concentration. The hydrogen concentration of the silicon nitride film is at least equal to that of the gate insulating layer 40. For example, the gate insulating layer 404a and the gate insulating layer 404b are formed by plasma CVD. When forming the gate insulating layer 404b, the hydrogen concentration in the supply gas is reduced. As a result, the hydrogen concentration in the gate insulating layer 404b can be reduced more than that in the gate insulating layer 404a. Specifically, silicon nitride can be used as the gate insulating layer 404a and the gate insulating layer 404b. When forming a silicon film, the ammonia gas is used in place of the gas supplied for forming the gate insulating layer 404a. The gate insulating layer 404b may be formed by reducing the flow rate or without using ammonia.

[0072] The thickness of the gate insulating layer 404b is set to 25 nm or more and 150 nm or less. By providing a silicon nitride film with a reduced hydrogen concentration as 404b, an oxide insulating layer 406 and the oxide semiconductor layer 408, hydrogen or a hydrogen compound (for example, water) is reduced. Hydrogen generates carriers in the oxide semiconductor, The reduction of hydrogen concentration is a factor that causes the threshold voltage to shift in the negative direction. By providing the silicon nitride film as the gate insulating layer 404b, the electrical characteristics of the transistor can be improved. Furthermore, the silicon nitride film with reduced hydrogen concentration can be used as a gate insulator. By providing the insulating layer 404b as the insulating layer, hydrogen or hydrogen compounds contained in the gate insulating layer 404a can be effectively removed. A barrier that prevents impurities such as silicon dioxide from diffusing into the oxide insulating layer 406 and the oxide semiconductor layer 408. It also acts as a membrane.

[0073] In this embodiment, both the gate insulating layer 404a and the gate insulating layer 404b are made of nitride. The interface between each gate insulating layer may be unclear depending on the material and film formation conditions. Therefore, in FIG. 2, the gate insulating layer 404a and the gate insulating layer 404 The interface of b is shown schematically by a dotted line, and this is the same in the subsequent drawings.

[0074] The oxide semiconductor layer 408a and the oxide semiconductor layer 408b included in the oxide semiconductor layer 408 are It is preferable that the oxide semiconductor layer 408a and the oxide semiconductor layer 408b have the same constituent elements but different compositions. An oxide semiconductor layer containing indium and gallium is formed as the oxide semiconductor layer 408b. In this case, the oxide semiconductor layer 408a on the side closer to the gate electrode layer 402 (on the channel side) is The content ratio of In to Ga is preferably set to In>Ga. The indium and gallium content of the oxide semiconductor layer 408b on the back channel side is set to I It is preferable to set n≦Ga.

[0075] In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and the s orbitals of indium Increasing the content tends to increase the overlap of s orbitals, so In> Oxides with a Ga composition have higher mobility than oxides with an In≦Ga composition. In addition, compared to In, Ga has a higher oxygen vacancy formation energy, making it less likely for oxygen vacancies to occur. Therefore, oxides with a composition of In≦Ga are more stable than oxides with a composition of In>Ga. It has the following characteristics.

[0076] An oxide semiconductor with a composition of In>Ga is applied to the channel side, and In≦ By using an oxide semiconductor with a Ga composition, the mobility and reliability of the transistor can be improved. For example, the atomic ratio of the oxide semiconductor layer 408a can be increased by The atomic ratio of In:Ga:Zn was 3:1:2, and the atomic ratio of In:Ga:Zn was 1 :1:1 is also acceptable.

[0077] Note that the constituent elements of the oxide insulating layer 406 in contact with the oxide semiconductor layer 408a are The oxide insulating layer 406 is made to have insulating properties by using the same material as the oxide insulating layer 408a but changing the composition. This is preferable because the interface between the oxide semiconductor layer 408b and the oxide semiconductor layer 408b can be further stabilized. The same is true for the oxide insulating layer 412 in contact with the first insulating layer 412.

[0078] In addition, the oxide semiconductor layer 408a and the oxide semiconductor layer 408b are formed by using oxide semiconductors having different crystallinity. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a nanocrystalline oxide A structure in which an amorphous oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS is appropriately combined However, amorphous oxide semiconductors are prone to absorbing impurities such as hydrogen and oxygen deficiency. Therefore, the oxide semiconductor layer 408a on the channel side is easily made n-type. It is preferable to use a crystalline oxide semiconductor such as CAAC-OS.

[0079] In addition, when an amorphous oxide semiconductor is used for the oxide semiconductor layer 408b on the back channel side, The source electrode layer 410a and the drain electrode layer 410b are formed by an etching process, and oxygen deficiency occurs. Therefore, the oxide semiconductor layer 408b is formed of an oxide semiconductor having crystallinity. It is preferable to apply a compound semiconductor.

[0080] FIG. 14 shows the structure of the gate insulating layer GI and the oxide insulating layer OI in the transistor of this embodiment. 1. Oxide semiconductor layers OS1 and OS2, oxide insulating layer OI2, and protective insulating layer Passi FIG. 14 shows the energy band diagram (schematic diagram) of the stacked structure. In an ideal configuration, all of the insulating layer, the oxide insulating layer, the oxide semiconductor layer, and the protective insulating layer are intrinsic. Assuming a situation where the gate insulating layer GI and the protective insulating layer PASS1 are made of silicon nitride film ( The oxide insulating layer OI1 and the oxide insulating layer OI2 have a band gap Eg of 5 eV. In-Ga-Zn oxide insulating layer with In:Ga:Zn=1:3:2 (band gap Eg is 3.6 eV) as the oxide semiconductor layer OS1, An In-Ga-Zn oxide semiconductor layer (with a band gap Eg of 2.8 eV) is The semiconductor layer OS2 is an In-Ga-Zn oxide with In:Ga:Zn=1:1:1. The figure shows the case where a semiconductor layer (having a band gap Eg of 3.2 eV) is used.

[0081] In FIG. 14, the oxide insulating layer OI1, the oxide insulating layer OI2, the oxide semiconductor layer OS The relative dielectric constants of the oxide insulating layer OI and the oxide semiconductor layer OS2 were all assumed to be 15. The mobility of the oxide insulating layer OI1 and the oxide insulating layer OI2 is 4 cm. 2 / Vs, and the transition Movement: 25cm 2 / Vs, and the mobility of the oxide semiconductor layer OS2 is 10 cm 2 / Vs and The thickness of the gate insulating layer GI was set to 325 nm, and the thickness of the oxide insulating layer OI1 was set to 3 The thickness of the oxide semiconductor layer OS1 is set to 10 nm, the thickness of the oxide semiconductor layer OS2 is set to 10 nm, and the thickness of the oxide semiconductor layer OS3 is set to 10 nm. The thickness of the oxide insulating layer OI2 is set to 10 nm, the thickness of the protective insulating layer Passi is set to 30 nm, and the thickness of the oxide insulating layer OI3 is set to 10 nm. The calculation was performed with a thickness of 300 nm.

[0082] As shown in FIG. 14, the oxide semiconductor layer OS1 has an oxide semiconductor layer on the gate electrode side (channel side). There is an energy barrier at the interface between the conductor layer OS1 and the oxide insulating layer OI1. The oxide semiconductor layer OS2 is also formed on the back channel side (opposite to the gate electrode) of the oxide semiconductor layer OS2. An energy barrier exists at the interface between S2 and the oxide insulating layer OI2. The existence of such an energy barrier at the interface with the insulating layer Since the movement of carriers is hindered, carriers move from the oxide semiconductor layer to the oxide insulating layer. In other words, the oxide semiconductor layer is made of a material that moves in the oxide semiconductor layer without being affected by the oxide semiconductor. By forming a layered structure sandwiching the material with a gradually increasing band gap, The carriers move through the oxide semiconductor layer OS1 and the oxide semiconductor layer OS2.

[0083] <Method for manufacturing semiconductor device> An example of a method for manufacturing the transistor 310 will be described below with reference to FIGS.

[0084] First, a gate electrode layer 402 is formed over a substrate 400 having an insulating surface.

[0085] There are no major restrictions on the substrate that can be used for the substrate 400 having an insulating surface, but at least In both cases, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, and quartz substrates Alternatively, a single crystal such as silicon or silicon carbide may be used. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates A substrate having a semiconductor element mounted thereon is called a substrate 400. It may also be used as such.

[0086] The gate electrode layer 402 may be made of molybdenum, titanium, tantalum, tungsten, aluminum, Metallic materials such as copper, chromium, neodymium, scandium, etc., or alloy materials containing these as the main components The gate electrode layer 402 can be formed using a silicon dioxide film containing an impurity element such as phosphorus. Semiconductor films, such as doped polycrystalline silicon films, and silicide films, such as nickel silicide The gate electrode layer 402 may have a single-layer structure or a stacked-layer structure. The gate electrode layer 402 may have a tapered shape, and the taper angle may be, for example, 30° to 70°. Here, the taper angle is the angle between the side surface of the layer having the tapered shape and the surface of the layer. Refers to the angle between the base and the surface.

[0087] The material of the gate electrode layer 402 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, acid Conductive materials such as silicon dioxide doped indium tin oxide can also be applied.

[0088] Alternatively, the gate electrode layer 402 may be made of a nitrogen-containing In—Ga—Zn-based oxide, ... or a nitrogen-containing In—Ga—Zn-based oxide. In-Sn oxides containing nitrogen, In-Ga oxides containing nitrogen, In-Zn oxides containing nitrogen oxides, Sn-based oxides containing nitrogen, In-based oxides containing nitrogen, metal nitrides (indium nitride , zinc nitride, tantalum nitride, tungsten nitride, etc.) may also be used. Since these materials have a work function of 5 eV or more, the gate electrode layer 402 can be formed using these materials. By doing so, the threshold voltage of the transistor can be made positive, and the transistor becomes a normally-off switch. A switching transistor can be realized.

[0089] Next, a gate insulating layer 404a and a gate insulating layer 402 are formed to cover the gate electrode layer 402. A gate insulating layer 404 including 4b is formed (see FIG. 3A). In this embodiment, a silicon film containing nitrogen can be used. A gate insulating layer 404a made of a silicon nitride film and a gate insulating layer 404b made of a silicon nitride film are laminated. The gate insulating layer 404 is formed by the above-mentioned method. The gate insulating layer 404 is formed by the above-mentioned method. From the viewpoint of reducing the film formation tact time, it is effective to form the film using the CVD method. CVD is also effective for depositing films on large-area substrates.

[0090] In this embodiment, the gate insulating layer 404a and the gate insulating layer 4 First, the feed gas is silane (SiH4), nitrogen (N2), and argon. A silicon nitride film that becomes the gate insulating layer 404a is formed using a mixed gas of NH3 and NH4. After that, the supply gas was switched to a mixture of silane (SiH4) and nitrogen (N2). Then, a silicon nitride film is formed to become the gate insulating layer 404b.

[0091] The supply gases for the plasma CVD method were silane (SiH4), nitrogen (N2), and ammonia (NH 3) Silicon nitride film is formed by mixing silane (SiH4) and nitrogen. It is possible to reduce defects in the film compared to silicon nitride films formed using a mixed gas of nitrogen (N2). Therefore, the gate insulating layer 404a has a larger thickness in the film than the gate insulating layer 404b. It is a film with reduced defects, and for example, Nc centers are detected by electron spin resonance (ESR). The spin density corresponding to the signal appearing at (g value 2.003) is preferably 1 × 10 17 s pins / cm 3 , more preferably 5 × 10 16 spins / cm 3 The following can be done: In addition, silicon nitride films formed by mixing ammonia in the gas mixture can be obtained by silicide gas. This allows for a film with better coating properties than when using a mixture of orthogonal and nitrogen gases, so As a gate insulating layer in contact with the gate electrode layer 402, a silicon nitride film using the above-mentioned mixed gas is formed. It is also effective to provide a gate insulating layer 404a having reduced defects in the film with a thickness of 30 By providing the gate insulating layer 404 with a thickness of 0 nm or more and 400 nm or less, the dielectric strength voltage of the gate insulating layer 404 can be increased to 300 V or more. It can be above.

[0092] On the other hand, the gate insulating layer 404b formed without containing ammonia in the source gas has a gate insulating property. The film can have a lower hydrogen concentration than the edge layer 404a. The thickness of the oxide insulating layer 406 is set to 25 nm or more and 150 nm or less and is set between the oxide insulating layer 406 and the gate electrode layer 402. By this, the gate insulating layer 404b is In addition, the gate insulating layer 404b can reduce the amount of hydrogen mixed in the gate insulating layer 404. The hydrogen or a hydrogen compound contained in the oxide insulating layer 406 and the oxide semiconductor layer 408 It also functions as a barrier film to prevent contamination.

[0093] The gate insulating layer 404 is a thick gate insulating layer 404a having reduced defects in the film, and a hydrogen By stacking the gate insulating layer 404b with a reduced concentration, the dielectric strength is improved, Diffusion of impurities such as hydrogen into the oxide insulating layer 406 and the oxide semiconductor layer 408 is suppressed. Therefore, electrostatic breakdown of the transistor including the gate insulating layer 404 can be suppressed. Furthermore, it is possible to stabilize the electrical characteristics.

[0094] Next, an oxide insulating layer and an oxide semiconductor layer are formed over the gate insulating layer 404b, and then etched. The oxide insulating layer 406, the oxide semiconductor layer 408a, and the oxide insulating layer 408b are processed into an island shape by etching. The oxide semiconductor layer 408 including the oxide semiconductor layer 408b is formed (see FIG. 3B). The etching process can be performed using the same photomask, so that the oxide insulating The layer 406 and the oxide semiconductor layer 408 have the same pattern shape when viewed from above. The parts match.

[0095] The oxide insulating layer 406 is formed by using one or more elements selected from the constituent elements of the oxide semiconductor layer 408. An oxide insulating layer containing several metal elements is provided. For example, a gallium oxide film or a gallium zinc oxide film is provided. Film, gallium gadolinium oxide film, high gallium content and indium content It is preferable to use an insulating film such as an insulating In-Ga-Zn oxide film that has little resistance.

[0096] The oxide semiconductor layer 408 may have an amorphous structure or a crystalline structure. In the case where the oxide semiconductor layer has an amorphous structure, heat treatment is performed in a later manufacturing step. The amorphous oxide semiconductor layer 408 may be crystallized. The temperature of the heat treatment is 250°C or higher and 700°C or lower, preferably 400°C or higher, more preferably The temperature is set to 500° C. or higher, and more preferably 550° C. or higher. It is also possible to combine this with other heat treatments in the process.

[0097] The oxide insulating layer 406 and the oxide semiconductor layer 408 are formed by a sputtering method, an MBE method, or the like. (Molecular Beam Epitaxy), CVD, pulsed laser deposition Atomic Layer Deposition (ALD) and other methods can be used as appropriate. can.

[0098] When the oxide insulating layer 406 and the oxide semiconductor layer 408 are formed, the oxide insulating layer 406 and the oxide semiconductor layer 408 are formed by It is preferable to reduce the hydrogen concentration. In order to reduce the hydrogen concentration, for example, sputtering When forming a film using the sputtering method, the atmosphere gas supplied into the film forming chamber of the sputtering device is As a source, a high-purity rare gas (alternative gas) from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed is used. Typically, argon, oxygen, and a mixed gas of a rare gas and oxygen are used as appropriate.

[0099] In addition, the residual moisture in the film formation chamber is removed and sputtering gas from which hydrogen and moisture have been removed is introduced. By forming the oxide insulating layer and the oxide semiconductor layer in this manner, the hydrogen concentrations in the oxide insulating layer and the oxide semiconductor layer can be reduced. To remove the residual moisture in the deposition chamber, an adsorption type vacuum pump, e.g. It is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Alternatively, a turbo molecular pump with a cold trap may be used. The pump may be, for example, a hydrogen molecule, a compound containing a hydrogen atom such as water (H2O), etc. (more preferably Because of its high pumping capacity, it is possible to pump compounds containing carbon atoms using a cryopump. The concentration of impurities contained in the film formed in the film chamber can be reduced.

[0100] Note that the oxide insulating layer and the oxide semiconductor layer are preferably formed successively without exposure to the air. The oxide insulating layer and the oxide semiconductor layer are successively formed without exposure to the atmosphere, thereby reducing the amount of oxygen. Adhesion of hydrogen or hydrogen compounds to the surface of an oxide insulating layer or the surface of an oxide semiconductor layer to be laminated (e.g. This prevents the inclusion of impurities (e.g., adsorption of water) and reduces the risk of contamination. .

[0101] In addition, when the oxide insulating layer or the oxide semiconductor layer is formed by a sputtering method, The relative density (filling rate) of the metal oxide target is 90% or more and 100% or less, preferably The relative density is 95% or more and 99.9% or less. By using a metal oxide target with a high relative density, As a result, the deposited film can be made dense.

[0102] It is also possible to form an oxide semiconductor layer while the substrate 400 is kept at a high temperature. This is effective in reducing the concentration of impurities that may be contained in the silicon dioxide layer. The substrate temperature is preferably 150°C or higher and 450°C or lower, and more preferably 200°C or higher and 300°C or lower. The temperature should be 50°C or less. In addition, by heating the substrate at a high temperature during film formation, the crystalline oxide semiconductor A conductor layer can be formed.

[0103] When a CAAC-OS film is used as the oxide semiconductor layer 408, the CAAC-OS film is As a method for this, for example, the film formation temperature is set to 200° C. or more and 450° C. or less, and the oxide semiconductor layer Alternatively, a thin oxide semiconductor layer can be formed on the surface of the substrate, and the c-axis can be oriented approximately perpendicular to the surface. After forming a thin film, it is heat-treated at 200°C to 700°C, and the c-axis is aligned approximately perpendicular to the surface. Alternatively, after forming a thin film as the first layer, the film may be heated to 200°C or higher and 700°C. The following heat treatment may be carried out to form a second layer, and the c-axis may be oriented approximately perpendicular to the surface.

[0104] The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). It is particularly preferable that the oxide semiconductor contains indium and zinc (Zn). As a stabilizer to reduce the variation in the electrical characteristics of the transistors used, In addition to this, it is preferable to have gallium (Ga). Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr) It is preferable to have one or more types.

[0105] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Tetrium) (Lu).

[0106] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, In-Mg oxides, In-Ga oxides, and ternary metal oxides Oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide Oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides , In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides, which are quaternary metal oxides Oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-S n-Hf-Zn based oxides and In-Hf-Al-Zn based oxides can be used.

[0107] For example, an In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements may also be included.

[0108] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn and Co. In addition, the oxide semiconductor is In2SnO 5(ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0109] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxides with atomic ratios of (=1 / 2:1 / 6:1 / 3) and their neighboring compositions Alternatively, an oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or is In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8). It is preferable to use a -Zn-based oxide or an oxide having a composition close to that.

[0110] However, the transistor using an oxide semiconductor containing indium is not limited to these. The appropriate composition is selected according to the required electrical characteristics (field effect mobility, threshold value, variation, etc.). In addition, in order to obtain the required electrical characteristics, the carrier concentration and impurity concentration can be adjusted. The degree of crystallization, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. must be appropriate. is preferred.

[0111] For example, transistors using In-Sn-Zn oxide semiconductors can be easily fabricated with high current. However, the field effect mobility of transistors using In-Ga-Zn oxide semiconductors is In transistors, the field-effect mobility can also be increased by reducing the defect density in the bulk. Cut.

[0112] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides.

[0113] In addition, the oxide insulating layer 406 and / or the oxide semiconductor layer 408 may be formed by Heat treatment is carried out to remove excess hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). The temperature of the heat treatment is preferably 300°C or higher and 700°C or lower, or lower than the strain point of the substrate. The heat treatment can be carried out under reduced pressure or in a nitrogen atmosphere. It is possible to remove hydrogen, an impurity that gives the mold conductivity.

[0114] Note that the heat treatment for dehydration or dehydrogenation is performed on the oxide insulating layer and / or the oxide semiconductor layer. The step may be performed at any timing in the manufacturing process of the transistor as long as it is performed after the film formation. The heat treatment for dehydration or dehydrogenation may be carried out multiple times or may be carried out in combination with other heat treatments. .

[0115] Note that in the case where the oxide insulating layer includes an oxygen excess region, the heat treatment for dehydration or dehydrogenation is When the oxide insulating layer and the oxide semiconductor layer are processed into islands, the oxide insulating layer This is preferable because it can prevent oxygen from being released by the heat treatment.

[0116] In heat treatment, nitrogen or rare gases such as helium, neon, and argon are mixed with water, hydrogen, etc. It is preferable that nitrogen, helium, or neon introduced into the heat treatment device is not included. The purity of the rare gas such as argon is 6N (99.9999%) or more, preferably 7N (99. 99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do so.

[0117] After the oxide semiconductor layer 408 is heated by the heat treatment, the heating temperature is maintained or the heating temperature is increased. While slowly cooling from the beginning, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air is added to the same furnace. The dew point was measured using a CRDS (cavity ring-down laser spectroscopy) method. In this case, the moisture content should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably Preferably, air (10 ppb or less) may be introduced. It is preferable that the gas does not contain oxygen, water, hydrogen, etc. The purity of the dinitrogen monoxide gas is 6N or more, preferably 7N or more (i.e., oxygen gas or dinitrogen monoxide It is preferable to keep the impurity concentration in the nitrogen gas at 1 ppm or less, preferably 0.1 ppm or less. The action of oxygen gas or nitrous oxide gas is effective in eliminating the unwanted effects of dehydration or dehydrogenation treatment. The main component material of the oxide semiconductor, which was also reduced during the process of removing the impurities, By supplying oxygen, the oxide semiconductor layer is highly purified and made into an i-type (intrinsic) oxide semiconductor layer. can be done.

[0118] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. Since there is a risk that the amount of The oxide semiconductor layer is doped with oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions). ) may be introduced to supply oxygen into the film.

[0119] Oxygen is introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor layer can be highly purified and made to be i-type (intrinsic). A transistor having a purified i-type (intrinsic) oxide semiconductor has low fluctuations in electrical characteristics. It is controlled and electrically stable.

[0120] When oxygen is introduced into the oxide semiconductor layer 408, it may be introduced directly into the oxide semiconductor layer 408. Alternatively, oxygen (at least a small amount) may be introduced into the oxide semiconductor layer 408 through an insulating layer that is formed later. As a method for introducing oxygen radicals, oxygen atoms, or oxygen ions, , ion implantation method, ion doping method, plasma immersion ion implantation method, plasma treatment In addition, a gas containing oxygen can be used for the oxygen introduction process. Gases containing oxygen include oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, and Carbon or the like can be used. In addition, in the oxygen introduction process, a rare gas can be added to the gas containing oxygen. may be included.

[0121] For example, when oxygen ions are implanted into the oxide semiconductor layer 408 by an ion implantation method, the dose 1×10 13 ions / cm 2 5x10 or more 16 ions / cm 2 The following would suffice.

[0122] Alternatively, the oxide insulating layer 406 in contact with the oxide semiconductor layer may be a layer including an oxygen excess region. Heat treatment is performed in the state where the oxide insulating layer 406 and the oxide semiconductor layer 408 are in contact with each other, Excess oxygen contained in the oxide insulating layer 406 is diffused into the oxide semiconductor layer 408, and the oxide semiconductor Oxygen may be supplied to the conductor layer 408. The heat treatment may be performed in the other steps in the manufacturing process of the transistor. This can also be used as the heat treatment for the above.

[0123] To provide an oxygen-excess region in the oxide insulating layer 406, for example, Alternatively, oxygen may be introduced into the oxide insulating layer after the film formation to form the oxide insulating layer 40. An oxygen excess region may be formed in 6.

[0124] The supply of oxygen to the oxide insulating layer 406 or the oxide semiconductor layer 408 is The timing of the introduction of oxygen is not particularly limited as long as it is after the deposition of the compound semiconductor layer. This may be done multiple times.

[0125] Next, a conductive film is formed over the oxide semiconductor layer 408 and processed to form a source electrode layer 410 Then, a drain electrode layer 410a and a drain electrode layer 410b are formed (see FIG. 3C).

[0126] The source electrode layer 410a and the drain electrode layer 410b are made of, for example, Al, Cr, or Cu. a metal film containing an element selected from the group consisting of Ta, Ti, Mo, and W, or a film containing the above-mentioned elements as components; Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) can be used. In addition, Ti, M, etc. can be deposited on either or both of the upper and lower sides of the metal film such as Al, Cu, etc. High-melting metal films such as titanium nitride and molybdenum nitride A stack of a source electrode layer 410a and a tungsten nitride film may be used. The drain electrode layer 410b may be formed of a conductive metal oxide. The oxides include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide (In2O3-SnO2), indium oxide zinc oxide (In 2O3-ZnO) or these metal oxide materials containing silicon oxide are used. It is possible.

[0127] The source electrode layer 410a and the drain electrode layer 410b are made of In—Ga— Zn-O film, In-Sn-O film containing nitrogen, In-Ga-O film containing nitrogen, I Metal nitride films such as n-Zn-O film, nitrogen-containing Sn-O film, and nitrogen-containing In-O film are used. These films contain the same constituent elements as the oxide semiconductor layer 408, and therefore, The interface between the source electrode layer 410a and the compound semiconductor layer 408 can be stabilized. and the drain electrode layer 410b is made of a nitrogen-containing I A laminated structure of an n-Ga-Zn-O film and a tungsten film can be applied.

[0128] Next, the source electrode layer 410a, the drain electrode layer 410b, and the exposed oxide semiconductor layer 4 The oxide insulating layer 412 is formed to cover the oxide insulating film 08. It can be formed from the same material and by the same manufacturing method as the layer 406 .

[0129] After that, the protective insulating layer 414 is formed over the oxide insulating layer 412 (see FIG. 3D).

[0130] The protective insulating layer 414 can be formed by plasma CVD or sputtering. Silicon oxide film, gallium oxide film, aluminum oxide film, silicon nitride film, oxynitride film A silicon film, an aluminum oxynitride film, a silicon nitride oxide film, or the like can be used. However, the protective insulating layer 414 is preferably a silicon film containing nitrogen, more preferably a silicon nitride film. By forming the layer containing the compound, static electricity to the semiconductor device during or after the manufacturing process of the semiconductor device can be reduced. This is preferable because it is possible to further reduce electrical breakdown.

[0131] Through the above steps, the transistor 310 of this embodiment can be formed.

[0132] <Configuration Example 3 of Semiconductor Device> 10A to 10C show examples of the structure of the transistor 320. 10B is a plan view of the transistor 320, and FIG. 10B is a plan view of the transistor 320 along the dashed line X3-Y3 in FIG. 10(A) is a cross-sectional view taken along the chain line V3-W3 in FIG. 10(A), and FIG. 10(C) is a cross-sectional view taken along the chain line V3-W3 in FIG. Figure.

[0133] The transistor 320 shown in FIG. 10 has an insulating surface, similar to the transistor 300 of FIG. A gate electrode layer 402 is provided on a substrate 400, and a gate insulating layer is provided on the gate electrode layer 402. an edge layer 404, an oxide insulating layer 406 on the gate insulating layer 404, and an oxide insulating layer 406 on the oxide insulating layer 406; an oxide semiconductor layer 408 which is in contact with and overlaps with the gate electrode layer 402; The source electrode layer 410a and the drain electrode layer 410b are electrically connected to each other. The oxide semiconductor layer 408 is formed by covering the source electrode layer 410a and the drain electrode layer 410b. The oxide insulating layer 412 and the protective insulating layer 414 on the oxide insulating layer 412 are formed as a transistor. It may be a component of 320.

[0134] The transistor 320 has a structure in which the gate insulating layer 404 and the oxide semiconductor layer 408 are the same as those of the transistor 320. The gate insulating layer 404 in the transistor 320 is different from the transistor 300. A gate insulating layer 404c in contact with the gate electrode layer 402 and a gate insulating layer 404c on the gate insulating layer 404c The insulating layer 404a and the gate insulating layer 404b provided between the gate insulating layer 404a and the oxide insulating layer 406 The transistor 320 includes an oxide semiconductor layer 404b. The conductor layer 408 is an oxide semiconductor layer in contact with the oxide insulating layer 406, similar to the transistor 310. and an oxide semiconductor layer 408b in contact with the oxide insulating layer 412. will be done.

[0135] Note that in the transistor 320, other than the gate insulating layer 404 and the oxide semiconductor layer 408 The configuration of this transistor is the same as that of the transistor 300, and the description of the transistor 300 should be referred to. It is possible.

[0136] The oxide semiconductor layer 408 included in the transistor 320 has the same structure as the oxide semiconductor layer 408 included in the transistor 31 0, and the description of the transistor 310 can be referred to. In the transistor 320, the oxide semiconductor layer 408b is The thickness of the contact region is The region with a smaller thickness is the source electrode layer 410a. In addition, when the conductive film to be the drain electrode layer 410b is processed, a part of the conductive film is etched. Alternatively, after forming the source electrode layer 410a and the drain electrode layer 410b, the oxide semiconductor layer The thin film is formed by etching the exposed area of 408b. The small region is a region that functions as a channel forming region of the transistor 320. By reducing the film thickness of the hole formation region, the source electrode layer 410a and the drain electrode layer 410 The resistance of the region in contact with b can be reduced compared to the channel formation region. The contact resistance between the source electrode layer 410a and the drain electrode layer 410b can be reduced. It becomes Noh.

[0137] The gate insulating layer 404 included in the transistor 320 is a gate insulating layer that is in contact with the gate electrode layer 402. a gate insulating layer 404c, a gate insulating layer 404a in contact with the gate insulating layer 404c, and an oxide The gate insulating layer 404b is in contact with the insulating layer 406.

[0138] In this embodiment, the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b are A silicon nitride film is used as 4b, and each gate insulating layer is formed successively by plasma CVD. First, the supply gas is a mixture of silane (SiH4) and nitrogen (N2) gas. After forming a silicon nitride film that will become the insulating layer 404c, the supply gas is changed to silane (SiH4), The gas was switched to a mixture of nitrogen (N2) and ammonia (NH3) to form the gate insulating layer 404a. After that, the supply gas was changed to silane (SiH4) and nitrogen (N2 ) to form a silicon nitride film that will become the gate insulating layer 404b.

[0139] A gate insulating layer 404 formed by supplying a mixture gas of silane (SiH4) and nitrogen (N2) c is a mixed gas of at least silane (SiH4), nitrogen (N2) and ammonia (NH3). The gate insulating layer 404a is formed by supplying ammonia to the atmosphere and the film. Ammonia can reduce the amount of metal oxide due to the lone pair of electrons on the nitrogen atom. Therefore, for example, when copper is used as the gate electrode layer 402, When a gate insulating layer with a high content of monia is provided in contact with the gate electrode layer, the following formula ( The reaction shown in 1) may cause copper to diffuse into the gate insulating layer.

[0140]

number

[0141] In the transistor 320 shown in FIG. 10, at least the ammonia is more soluble than the gate insulating layer 404a. The gate insulating layer 404c having a low content of silicon is provided in contact with the gate electrode layer 402. As a result, the material (e.g., copper) of the gate electrode layer 402 diffuses into the gate insulating layer 404. That is, the gate insulating layer 404c can suppress the The gate insulating layer 404c can function as a barrier film against the metal material. This can further improve the reliability of the transistor.

[0142] In the gate insulating layer 404 included in the transistor 320, The structures of the insulating layer 404a and the gate insulating layer 404b can be similar to those of the transistor 310. By including the gate insulating layer having the above structure, electrostatic breakdown of the transistor can be prevented, and Therefore, stable electrical characteristics can be imparted to the transistor, resulting in a highly reliable semiconductor device. This makes it possible to

[0143] The thickness of the gate insulating layer 404c is 30 nm or more and 100 nm or less, preferably 30 nm or more. The thickness is set to 50 nm or less. As mentioned above, the gate provided as a countermeasure against electrostatic breakdown of the transistor The thickness of the insulating layer 404a is preferably 300 nm or more and 400 nm or less. A gate insulating layer 404 that functions as a barrier film to prevent hydrogen diffusion into the compound semiconductor layer 408. The thickness of the gate insulating layer 4b is preferably 25 nm or more and 150 nm or less. The thickness of the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b The thickness of each gate insulating layer is set so that the total thickness (thickness) is 355 nm or more and 550 nm or less. It is preferable to adjust it appropriately.

[0144] <Configuration Example 4 of Semiconductor Device> 11A to 11C show examples of the structure of the transistor 330. 11B is a plan view of the transistor 330, and FIG. 11B is a plan view of the transistor 330 along the dashed line X4-Y4 in FIG. 11(A) is a cross-sectional view taken along the dashed line V4-W4 in FIG. 11(C). Figure.

[0145] The transistor 330 shown in FIG. 11 has a gate electrode provided on a substrate 400 having an insulating surface. An electrode layer 402, a gate insulating layer 404 on the gate electrode layer 402, and a gate insulating layer 404 on the gate insulating layer 404. the oxide insulating layer 406, which is in contact with the oxide insulating layer 406 and overlaps with the gate electrode layer 402; an oxide semiconductor layer 408 and a source electrode layer 410 electrically connected to the oxide semiconductor layer 408; and the source electrode layer 410a and the drain electrode layer 410b. The oxide insulating layer 412 is in contact with the oxide semiconductor layer 408 and is a protective layer on the oxide insulating layer 412. and a protective insulating layer 414.

[0146] In the transistor 330, the protective insulating layer 414 is a protective insulating layer in contact with the oxide insulating layer 412. The insulating layer 414a has a laminated structure of a protective insulating layer 414b on the insulating layer 414a. A silicon nitride film can be applied to each of them.

[0147] The protective insulating layer 414a has a structure similar to that of the gate insulating layer 404b of the transistor 310. By providing the protective insulating layer 414a, the oxide insulating layer 412 and the oxide insulating layer 414b can be Therefore, the incorporation of hydrogen or hydrogen compounds into the oxide semiconductor layer 408 can be suppressed. This makes it possible to further stabilize the electrical characteristics of the transistor.

[0148] The protective insulating layer 414b has a structure similar to that of the gate insulating layer 404a of the transistor 310. By providing the protective insulating layer 414b, It is possible to further reduce electrostatic damage to the semiconductor device.

[0149] The other components of the transistor 330 are configured similarly to those of the transistor 310. The description of the transistor 310 can be referred to.

[0150] The transistors shown in FIGS. 1, 2, 10, and 11 have partially different configurations. However, one embodiment of the present invention is not particularly limited, and various combinations are possible.

[0151] The transistor described in this embodiment has a thick silicon film containing nitrogen as a gate insulating layer ( For example, 325 nm or more and 550 nm or less), and the gate insulating layer and the oxide semiconductor The oxide semiconductor layer is formed by adding one or more metal elements selected from the constituent elements of the oxide semiconductor layer between the oxide semiconductor layer and the layer. The silicon film containing nitrogen is composed of an oxide insulating layer. It is possible to form the film by applying industrial technology, and the silicon film containing nitrogen can be set as a thick film. By doing so, the gate insulating layer is physically thickened, preventing a decrease in the dielectric strength voltage of the transistor. Furthermore, the dielectric strength can be improved, and electrostatic breakdown of the semiconductor device can be suppressed. By including the oxide insulating layer, the interface with the oxide semiconductor layer can be stabilized. This can prevent charge trapping on the surface, thereby preventing transistor degradation. This prevents the transistor from becoming unstable, resulting in a highly reliable transistor.

[0152] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0153] (Embodiment 2) A semiconductor device (also referred to as a display device) having a display function using the transistor described in Embodiment 1 In addition, a part or the whole of a driver circuit including a transistor can be manufactured by It can be formed integrally on the same substrate as the pixel section to form a system-on-panel.

[0154] In FIG. 4A, a substrate 4001 is provided on a substrate 4001 so as to surround a pixel portion 4002. A sealing material 4005 is provided and sealed with a substrate 4006. is deposited in an area different from the area surrounded by the sealing material 4005 on the substrate 4001. C chip or a separately prepared substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted. Various signals and signals are given to the pixel portion 4002 through a line 4003 and a scanning line driver circuit 4004. The potential is FPC (Flexible printed circuit) 4018a, 4 Powered by 018b.

[0155] In FIG. 4B and FIG. 4C, a pixel portion 4002 is provided on a substrate 4001, and A sealant 4005 is provided so as to surround the scanning line driver circuit 4004. A substrate 4006 is provided on the element portion 4002 and the scanning line driver circuit 4004. The pixel portion 4002 and the scanning line driver circuit 4004 are formed by a substrate 4001, a sealing material 4005 and a substrate. The display element is sealed by a plate 4006. is deposited in an area different from the area surrounded by the sealing material 4005 on the substrate 4001. C chip or a separately prepared substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film A signal line driver circuit 4003 is mounted. Various signals are applied to the pixel portion 4002 through a line driver circuit 4003 and a scanning line driver circuit 4004. Signals and potentials are supplied from FPC4018.

[0156] In addition, in FIG. 4B and FIG. 4C, a signal line driver circuit 4003 is formed separately, and 4001, but the present invention is not limited to this configuration. It may be formed separately and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be mounted. It may be formed separately and mounted.

[0157] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A The C This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 4(B) shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 4(C) shows an example in which a signal line driver circuit 4003 is mounted by the COG method. ) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0158] The display device is a panel in which a display element is sealed, and a controller connected to the panel. This includes modules in which ICs including lasers are mounted. The display device refers to an image display device, a display device, or a light source (including a lighting device). In addition to the panel in which the display element is sealed, connectors, such as FP A module with a C or TCP attached, a printed wiring board is attached to the end of the TCP or a module in which an IC (integrated circuit) is directly mounted on the display element using the COG method. All modules are included in the display device.

[0159] The pixel portion and the scanning line driver circuit provided on the substrate each have a plurality of transistors. The transistor described in Embodiment 1 can be applied.

[0160] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element can change its brightness depending on the current or voltage. This category includes elements that are controlled by the Also included are electronic ink displays (e-page displays), organic EL displays, etc. It can also be used for display media in which the contrast changes due to electrical effects, such as LCD. .

[0161] One embodiment of a semiconductor device will be described with reference to FIGS. 4A to 6. FIG. 6 shows the M Equivalent to the cross-sectional view at -N.

[0162] As shown in FIGS. 4 and 6, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are connected to the FPC 4018, 4018b. The anisotropic conductive layer 4019 is electrically connected to a terminal of the semiconductor device.

[0163] The connection terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4034, and the terminal electrode 4 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. The conductive layer is formed of a conductive material.

[0164] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a substrate 4001. In FIG. 6, the pixel portion 4002 includes a transistor 4010 and a 6(A) and a transistor 4011 included in the scan line driver circuit 4004. ) an oxide insulating layer 4030 and a protective insulating layer 4040 are formed over the transistors 4010 and 4011. 6B, an insulating layer 4032 is provided, which functions as a planarizing insulating layer. 21 is provided.

[0165] The transistors 4010 and 4011 may be the transistors described in Embodiment 1. In this embodiment, a transistor similar to the transistor 300 described in Embodiment 1 can be used. The transistors 4010 and 4011 are applied to a transistor having a boron nitride structure. This is a transistor with a TomGate structure.

[0166] The transistors 4010 and 4011 are made of an oxide insulating film, which is an insulating layer in contact with an oxide semiconductor layer. The oxide insulating layer 4020b and the oxide insulating layer 4030 are formed of an oxide semiconductor layer. an oxide insulating layer containing one or more metal elements and a gate insulating layer 4020a; and a thick silicon film containing nitrogen (for example, a film thickness of 325 nm or more and 550 nm or less). Therefore, the transistors 4010 and 4011 are transistors in which fluctuations in electrical characteristics are suppressed. The electrical resistance is controlled and electrostatic breakdown is suppressed.

[0167] In addition, the oxide semiconductor layer of the transistor 4011 for the driver circuit overlaps with the channel formation region of the oxide semiconductor layer. A conductive layer may be further provided at a position overlapping with the channel formation region of the oxide semiconductor layer. By providing the transistor 4011 at a position where the threshold voltage of the transistor 4011 is higher than the threshold voltage of the transistor 4011, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. In addition, the conductive layer has a potential equal to that of the gate electrode layer of the transistor 4011. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer may be in a floating state.

[0168] The conductive layer also shields external electric fields, i.e., prevents external electric fields from reaching the internal It also has a function (particularly an electrostatic shielding function against static electricity) to prevent it from acting on the circuitry (including the circuit section). The shielding function of the conductive layer prevents the transistor from being electrically damaged by external electric fields such as static electricity. Fluctuations in characteristics can be prevented.

[0169] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. can be used.

[0170] FIG. 6(A) shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer The liquid crystal layer 4008 is sandwiched between insulating layers 4008, which function as alignment layers. The second electrode layer 4031 is provided on the substrate 4006 side. The first electrode layer 4034 and the second electrode layer 4031 are laminated with a liquid crystal layer 4008 interposed therebetween. It has become a success.

[0171] The spacers 4035 are columnar spacers obtained by selectively etching the insulating layer. and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Spherical spacers may also be used.

[0172] When liquid crystal elements are used as display elements, thermotropic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, These liquid crystal materials can be low molecular weight compounds or high molecular weight compounds. These liquid crystal materials (liquid crystal compositions) may exhibit a cholesteric phase, a smectic phase, or the like depending on the conditions. These phases include nematic, cubic, chiral, and isotropic phases.

[0173] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4034, and the second electrode layer 4031 The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric liquid crystal is increased, The blue phase is the phase that appears just before the transition from the cholesteric phase to the isotropic phase. It can be expressed by using a liquid crystal composition in which a chiral agent and a blue colorant are mixed. In order to widen the temperature range in which the blue phase appears, a polymerizable monomer is added to the liquid crystal composition that appears the blue phase. A polymerization initiator may also be added to form a liquid crystal layer by carrying out a polymer stabilization process. The liquid crystal composition exhibiting the blue phase has a short response time and is optically isotropic, so Since alignment treatment is not required, the viewing angle dependency is small. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This makes it possible to reduce defects and damage to the liquid crystal display device during the manufacturing process. This makes it possible to improve the productivity of the display device.

[0174] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values in this document are those measured at 20°C.

[0175] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the oxide film may be set in consideration of the off-state current of the transistor. By using a transistor with a semiconductor layer, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0176] The transistor including the oxide semiconductor layer disclosed in this specification has a current value ( Therefore, the retention time of electrical signals such as image signals can be controlled to be low. The refresh interval can be set to a longer value. This reduces the power consumption.

[0177] In addition, the transistor including the oxide semiconductor layer disclosed in this specification has a relatively high field effect For example, such a transistor can be used in a liquid crystal display. By using it in a display device, it can be used as a switching transistor in the pixel section and a transistor in the driver circuit section. The driver transistor can be formed on the same substrate. By using such a transistor, high-quality images can be provided.

[0178] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0179] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0180] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0181] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. is not limited to color display devices, but also applies to monochrome display devices. It is also possible.

[0182] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0183] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element. An example using an organic EL element is shown below.

[0184] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0185] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0186] 5(A), (B) and 6(B) show examples of light-emitting devices using light-emitting elements as display elements. .

[0187] FIG. 5A is a plan view of the light emitting device, and dashed lines S1-T1 and S2-T2 in FIG. , and the cross section cut along S3-T3 corresponds to FIG. 5(B). 1, the electroluminescent layer 542 and the second electrode layer 543 are omitted and are not shown.

[0188] The light-emitting device shown in FIG. 5 includes a transistor 510, a capacitor 520, a wiring layer 530, and a capacitor 540 disposed on a substrate 500. The transistor 510 has an intersection 530, and is electrically connected to a light emitting element 540. 5 shows a bottom emission type in which light from the light emitting element 540 is extracted through the substrate 500. It is a light emitting device having the following structure.

[0189] The transistor described in Embodiment 1 can be used as the transistor 510. In this embodiment, a transistor having a structure similar to that of the transistor 300 described in Embodiment 1 is used. An example of applying a transistor is shown. The transistor 510 is a bottom gate transistor. It is a star.

[0190] The transistor 510 includes gate electrode layers 511a and 511b, a gate insulating layer 502, and an oxide insulating layer. an insulating layer 512, an oxide semiconductor layer 514, and a conductive layer serving as a source electrode layer or a drain electrode layer. The conductive layers 513a and 513b are included.

[0191] The transistor 510 includes an oxide insulating layer 51 which is an insulating layer in contact with the oxide semiconductor layer 514. 2, which contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer 514. An oxide insulating layer is applied, and a thick layer (for example, 32 mm thick) is used as the gate insulating layer 502. The silicon film containing nitrogen is 5 nm or more and 550 nm or less. In addition, charge trapping at the interface between the oxide semiconductor layer 514 and the oxide insulating layer 512 can be suppressed. This can improve the electrical characteristics of the transistor 510. Therefore, highly reliable semiconductor devices can be manufactured with a high yield. Note that the insulating layer 524 in contact with the oxide semiconductor layer 514 can be formed by It is preferable to use an oxide insulating layer having a structure similar to that of the oxide insulating layer 512. In addition, an insulating layer 525 in contact with the insulating layer 524 has a structure similar to that of the gate insulating layer 502. It is preferable to apply an insulating layer to the substrate.

[0192] The capacitor 520 includes conductive layers 521a and 521b, a gate insulating layer 502, and an oxide insulating layer 52 2, the oxide semiconductor layer 526, the conductive layer 523, the conductive layers 521a and 521b, and the conductive layer 5 23 sandwiches the gate insulating layer 502, the oxide insulating layer 522, and the oxide semiconductor layer 526. By combining these, capacitance is formed.

[0193] The wiring layer intersection 530 is an intersection between the gate electrode layers 511a and 511b and the conductive layer 533. The gate electrode layers 511a and 511b and the conductive layer 533 are provided with a gate insulating layer 502 therebetween. Intersect via.

[0194] In this embodiment, the gate electrode layer 511a and the conductive layer 521a are formed to a thickness of 30 nm. A titanium film of 200 nm thick was used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

[0195] The oxide semiconductor layers 514 and 526 are made of In-Ga-Zn-O films with a thickness of 25 nm. .

[0196] An interlayer insulating layer 504 is formed on the transistor 510, the capacitor element 520, and the wiring layer intersection 530. A color filter is formed on the interlayer insulating layer 504 in an area overlapping the light emitting element 540. A flat insulating layer 504 is provided on the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 is provided which functions as a protective insulating layer.

[0197] A first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order on an insulating layer 506. The light emitting element 540 includes a stacked structure. 510 is an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. At this point, the first electrode layer 541 and the conductive layer 513a are in contact with each other, thereby forming an electrical connection. A partition wall 507 is provided to cover a part of the first electrode layer 541 and the opening. It is being done.

[0198] The insulating layer 506 is a photosensitive acrylic film with a thickness of 1500 nm, and the partition wall 507 is a nm photosensitive polyimide film can be used.

[0199] The color filter layer 505 may be made of, for example, a transparent resin of a chromatic color. As the colored light-transmitting resin, photosensitive or non-photosensitive organic resins can be used. The use of a functional organic resin layer reduces the number of resist masks, simplifying the process. And preferable.

[0200] Chromatic colors are colors other than achromatic colors such as black, gray, and white. It is made of materials that transmit only colored light. Chromatic colors include red, green, and blue. Also, cyan, magenta, yellow, etc. may be used. The color filter layer transmits only light of the selected chromatic color. The color filter layer has a peak at the wavelength of light of It is advisable to appropriately control the optimum film thickness taking into consideration the relationship between the concentration of the color and the light transmittance. The thickness of the filter layer 505 may be set to 1500 nm or more and 2000 nm or less.

[0201] In the light-emitting device shown in FIG. 6B, the light-emitting element 4513 is provided in the pixel portion 4002. The light-emitting element 4513 is electrically connected to the transistor 4010. The first electrode layer 4034, the electroluminescent layer 4511, and the second electrode layer 4031 are stacked. The light emitting element 4513 may be configured to emit light in accordance with the direction of light extracted from the light emitting element 4513. The configuration of the element 4513 can be changed as appropriate.

[0202] The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4034, 541 using a flexible resin material, and the opening It is preferable that the sidewall be formed as an inclined surface having a continuous curvature.

[0203] The electroluminescent layers 4511 and 542 may be formed of a single layer or a plurality of layers stacked. It doesn't matter whether it's configured as follows:

[0204] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting elements 4513 and 540, A protective film may be formed over the electrode layers 4031 and 543 and the partition walls 4510 and 507. As the film, a silicon nitride film, a silicon nitride oxide film, a DLC film, etc. can be formed. .

[0205] In addition, oxygen, hydrogen, moisture, carbon dioxide, etc. must be prevented from entering the light emitting elements 4513 and 540. A layer containing an organic compound that covers the light-emitting elements 4513 and 540 may be formed by evaporation.

[0206] In addition, in the space sealed by the substrate 4001, the substrate 4006, and the sealant 4005, Filler 4514 is provided and sealed. In this way, the airtightness is ensured so that the container is not exposed to the outside air. High-performance protective films with low degassing (lamination films, UV-curable resin films, etc.) It is preferable to package (enclose) the product in a protective covering.

[0207] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, and poly Imide, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) For example, nitrogen can be used as a filler. That's good enough.

[0208] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0209] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is a paper It is possible to make it as easy to read as a digital camera, consume less power than other display devices, and have a thinner and lighter form factor. This has the advantage that

[0210] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge, and a plurality of microcapsules containing the first particle and the second particle having a negative charge are dispersed in a solvent. By applying an electric field to the microcapsules, the particles in the microcapsules The particles are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye and do not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless).

[0211] The microcapsules dispersed in a solvent are called electronic ink. Color display is also possible by using color filters or particles containing pigments.

[0212] 4 to 6, the substrates 4001, 500, and 4006 are glass substrates. In addition to the plate, a flexible substrate can also be used, for example, a light-transmitting plastic substrate. As for plastic, FRP (Fiberglass- Reinforced Plastics (PVF) plate, PVF (Polyvinyl Fluoride) film Film, polyester film or acrylic resin film can be used. If light resistance is not required, a metal substrate (metal film) such as aluminum or stainless steel can be used. For example, aluminum foil may be sandwiched between PVF film or polyester film. A soldered sheet can also be used.

[0213] The insulating layers 4021 and 506 functioning as planarizing insulating layers are made of acrylic resin, polyimide, or the like. Heat-resistant organic materials such as benzocyclobutene resins, polyamides, and epoxy resins In addition to the above organic materials, siloxane resins, PSG (ring galvanized silica gel) and other materials can be used. By using low-k materials such as BPSG (Boron Phosphate Glass), In addition, by laminating multiple insulating layers made of these materials, the insulating layer 4 can be formed. 021, 506 may be formed.

[0214] The method for forming the insulating layers 4021 and 506 is not particularly limited. Depending on the material, sputtering may be used. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method), Lean printing, offset printing, etc. can be used.

[0215] The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 are made of tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter , denoted as ITO), indium zinc oxide, indium tin oxide doped with silicon oxide A light-transmitting conductive material such as graphene can be used.

[0216] The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 are made of tungsten ( W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium ( V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel Ni (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver ( Using one or more of metals such as Ag, their alloys, or their metal nitrides It can be formed.

[0217] In this embodiment, the light emitting device shown in FIG. 5 is a bottom emission type, so the first electrode layer 541 The first electrode layer 541 has a light-transmitting property, and the second electrode layer 543 has a reflective property. When using a conductive film, the film thickness is thin enough to maintain light transmission, and the second electrode layer 543 is made thin enough to maintain light transmission. When a conductive layer is used, it is preferable to laminate a conductive layer having reflectivity.

[0218] The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 are made of highly conductive The conductive layer can be formed using a conductive composition containing conductive molecules (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, , polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof derivatives, or copolymers of two or more of aniline, pyrrole and thiophene Examples include hydroxybenzoates and their derivatives.

[0219] A protection circuit for protecting the drive circuit may be provided. The protection circuit is configured using a nonlinear element. It is preferable to do so.

[0220] As described above, by using the transistor described in Embodiment 1, A semiconductor device can be provided.

[0221] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0222] (Embodiment 3) An image sensor device that reads information about an object using the transistor shown in the first embodiment Therefore, a semiconductor device having such a function can be manufactured.

[0223] FIG. 7A shows an example of a semiconductor device having an image sensor function. 7(A) is an equivalent circuit of the photosensor, and FIG. 7(B) is a cross-sectional view showing a part of the photosensor.

[0224] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode is electrically connected to the gate of transistor 640. One of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other terminal is electrically connected to one of the source and drain terminals of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The signal line 671 is electrically connected to the sensor output signal line 671.

[0225] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor layer is not clearly shown. To make it easier to distinguish, the symbol for a transistor using an oxide semiconductor layer is written as “OS.” In FIG. 7A, a transistor 640 and a transistor 656 are the same as those in Embodiment 1. The transistor shown in FIG. 1 can be applied to the present invention, which is a transistor including an oxide semiconductor layer. In this embodiment, a transistor having a structure similar to that of the transistor 300 described in Embodiment 1 is used. The transistor 640 is a bottom-gate transistor.

[0226] FIG. 7B shows the photodiode 602 and the transistor 640 in the photosensor. 6 is a cross-sectional view showing a substrate 601 (element substrate) having an insulating surface on which a sensor functioning as a sensor is formed. A photodiode 602 and a transistor 640 are provided. 602, a substrate 613 is provided on the transistor 640 using an adhesive layer 608. .

[0227] On the transistor 640, an insulating layer 631, an insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are formed. The photodiode 602 is formed on the interlayer insulating layer 633. An electrode layer 641b, a first semiconductor film 606a and a second semiconductor film 606b stacked in this order on the electrode layer 641b. The first to third semiconductor films 606b and 606c are provided on the interlayer insulating layer 634. An electrode layer 642 electrically connected to the electrode layer 641b via a third semiconductor film, and an electrode layer 64 1b and an electrode layer 641a electrically connected to the electrode layer 642. There are.

[0228] The electrode layer 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating layer 634. The layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641a. is electrically connected to the gate electrode layer of the transistor 640, and 2 is electrically connected to transistor 640.

[0229] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high resistance semiconductor film (i-type semiconductor film), and the third semiconductor film 606c is an n-type A pin-type photodiode in which semiconductor films having different conductivity types are stacked is shown as an example.

[0230] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed from a group 13 silicon film. Using semiconductor material gas containing impurity elements (e.g., boron (B)), plasma CVD is used. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, the film is formed by diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by using a method such as ion implantation. It is preferable to diffuse the impurity element by heating or the like after introducing the impurity element. In this case, the amorphous silicon film can be formed by LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a is 10 nm or more and 5 nm or less. It is preferable to form it so that the thickness is 0 nm or less.

[0231] The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by amorphous silicon using a semiconductor material gas. A thick silicon film is formed by plasma CVD. The semiconductor material gas is silane. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S The second semiconductor film 606b may be formed by LPCVD. The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0232] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous film containing an impurity element that imparts n-type. The third semiconductor film 606c is formed of a thick silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g., phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain elements, the film is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon film can be formed by LPCVD, vapor phase growth, or sputtering. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that it faces downward.

[0233] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, it may be formed using a polycrystalline semiconductor, or a microcrystalline (semi-amorphous) semiconductor. Rufus (Semi Amorphous Semiconductor: SAS) Semiconductor It may also be formed using a conductor.

[0234] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type The photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed to the photodiode 602 This shows an example of converting the light received by the semiconductor film into an electrical signal. Since light from the semiconductor film side having a pattern becomes disturbance light, a conductive layer with light blocking properties is used for the electrode layer. It is also possible to use the n-type semiconductor film side as the light-receiving surface.

[0235] The transistor 640 includes an oxide insulating layer 621 which is an insulating layer in contact with the oxide semiconductor layer 623. an oxide semiconductor layer 623 containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer 623; Therefore, a charge is generated at the interface between the oxide semiconductor layer 623 and the oxide insulating layer 621. This can prevent trapping of the ions, thereby stabilizing the electrical characteristics of the transistor 640. In addition, the transistor 640 has a thick gate insulating layer 620 (for example, The film thickness is 325 nm to 550 nm and includes a silicon film containing nitrogen. It is possible to prevent electrostatic breakdown of the transistor 640. As a result, highly reliable semiconductor devices can be provided with a high yield.

[0236] The insulating layer 631, the insulating layer 632, the interlayer insulating layer 633, and the interlayer insulating layer 634 are made of insulating materials. Depending on the material, sputtering, plasma CVD, spin coating, Dip, spray coating, droplet ejection method (inkjet method), screen printing, offset It can be formed by using inkjet printing or the like.

[0237] Note that the insulating layer 631 in contact with the oxide semiconductor layer 623 is formed of the same material as the oxide semiconductor layer 623. It is preferable to apply an oxide insulating layer containing one or more metal elements selected from the group consisting of In addition, a silicon film containing nitrogen is provided as an insulating layer 632 in contact with the insulating layer 631. It is preferable that

[0238] The interlayer insulating layers 633 and 634 function as planarizing insulating layers to reduce surface irregularities. The interlayer insulating layers 633 and 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic resins such as resins, benzocyclobutene-based resins, polyamides, and epoxy resins In addition to the organic insulating materials, low-dielectric-constant materials (low- k material), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass), etc. A single layer or a laminated layer can be used.

[0239] By detecting light 622 incident on the photodiode 602, information on the object to be detected is obtained. When reading the information of the detected object, a light source such as a backlight is used. It can be used.

[0240] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0241] (Fourth embodiment) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). As electronic equipment, television equipment (also known as television or television receiver) (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound players, gaming machines (Pachinko machines, slot machines, etc.) and game cabinets. An example is shown in Figure 8.

[0242] FIG. 8A shows a table 9000 having a display unit. A display unit 9003 is built into the body 9001, and images are displayed on the display unit 9003. It is possible to support the housing 9001 with four legs 9002. The housing 9001 also has a power cord 9005 for power supply.

[0243] The semiconductor device described in any of the above embodiments can be used for the display portion 9003. This makes it possible to provide high reliability to electronic devices.

[0244] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, making it possible to It may also be a control device that controls other home appliances by operation. If a semiconductor device having an image sensor function as shown in FIG. 3 is used, the display portion 9003 can be touched. It can have input functionality.

[0245] In addition, the screen of the display unit 9003 can be vertically fixed to the floor by a hinge provided in the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrow, but it is possible to install it on a table. If the display unit is built in, the space in the room can be used more effectively.

[0246] 8B shows a television device 9100. The television device 9100 includes: A display unit 9103 is incorporated in the housing 9101, and images are displayed on the display unit 9103. In this example, the housing 9101 is supported by a stand 9105. This shows the progress.

[0247] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote control operation device 9110. The channel and volume can be controlled by the 9109, and the information displayed on the display 9103 is In addition, the remote control unit 9110 can be used to operate the video. A display unit 9107 for displaying information output from 9110 may be provided.

[0248] The television device 9100 shown in FIG. 8(B) includes a receiver, a modem, and the like. The vision device 9100 can receive general television broadcasts using a receiver, and also By connecting to a wired or wireless communication network via a modem, Information from sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to carry out communication.

[0249] The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107. This makes it possible to provide high reliability to the television set and the remote control. Cut.

[0250] FIG. 8C shows a computer, which includes a main body 9201, a housing 9202, a display unit 9203, and a keyboard. It includes a board 9204, an external connection port 9205, a pointing device 9206, and the like.

[0251] The semiconductor device described in any of the above embodiments can be used for the display portion 9203. This makes it possible to give computers high reliability.

[0252] Figures 9(A) and 9(B) show tablet terminals that can be folded in half. The tablet terminal is in a state where the display unit 9631a is in a housing 9630. 1b, display mode switch 9034, power switch 9035, power saving mode switch It has a replacement switch 9036, a fastener 9033, and an operating switch 9038.

[0253] The semiconductor device described in any of the above embodiments has a display portion 9631a and a display portion 9631b. It is possible to use it as a tablet terminal with high reliability.

[0254] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638, data can be input. In 1a, for example, half of the area has a display function only, and the other half The display unit 963 has a touch panel function, but is not limited to this. The entire area of the display unit 96 may have a touch panel function. The entire surface of 31a is displayed as a keyboard button to serve as a touch panel, and the display part 9631b is displayed. It can be used as a screen.

[0255] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard can be displayed on the display portion 9631b.

[0256] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0257] A display mode changeover switch 9034 is used to change the display orientation between portrait and landscape. You can select between black and white and color display. The 9036 is a tablet device that detects external light during use using a built-in light sensor. The display brightness can be optimized according to the amount of light. In addition, other detection devices such as gyro, acceleration sensor, etc. that detect tilt are also included. It may be stored.

[0258] FIG. 9A shows an example in which the display area of the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. The quality may also be different. For example, one display panel may be capable of displaying images with higher resolution than the other. You may do so.

[0259] FIG. 9B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 963 3, a charge / discharge control circuit 9634. Note that in FIG. 9B, the charge / discharge control circuit 9634 As an example, a configuration having a battery 9635 and a DC-DC converter 9636 is shown. are.

[0260] In addition, the tablet device can be folded in half, so when not in use, the housing 9630 can be folded. Therefore, the display portions 9631a and 9631b can be protected, and thus the display portions 9631a and 9631b can be withstood. This makes it possible to provide a tablet terminal that is highly durable and reliable even from the perspective of long-term use.

[0261] In addition, the tablet terminals shown in Fig. 9(A) and Fig. 9(B) can also display various information ( Functions that display still images, videos, text images, etc., calendars, dates, or times, etc. A function to display information on the display unit, and a touch input device to operate or edit the information displayed on the display unit by touch input. It can have functions such as the ability to control processing by various software (programs), etc. can.

[0262] The solar cell 9633 attached to the surface of the tablet terminal supplies power to the touch panel, The solar cell 9633 can be supplied to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by the battery 9630. If a lithium-ion battery is used as the battery 9635, it can be used in a small This has the advantage of allowing for standardization.

[0263] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 9B will be described with reference to FIG. 9C. A block diagram is shown and explained. In FIG. 9(C), a solar cell 9633, a battery 9635, DC-DC converter 9636, converter 9637, switches SW1 to SW3, display unit The figure shows the 9631, the battery 9635, the DC-DC converter 9636, 9B. This corresponds to 4.

[0264] First, an example of operation when power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The voltage is increased or decreased by a C converter 9636. When power is being used from the battery 9633, the switch SW1 is turned on and the converter 96 37 increases or decreases the voltage to the voltage required for the display unit 9631. When not displaying in 31, turn SW1 off and SW2 on to charge the battery. 35 charging configuration.

[0265] The solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto. Other power generation methods such as piezoelectric elements (piezoelectric elements) and thermoelectric elements (Peltier elements) For example, it may be configured to transmit and receive power wirelessly (contactlessly). A configuration that combines a non-contact power transmission module that charges by transmitting power, or other charging means. It may also be possible to use the following.

[0266] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination. [Example]

[0267] In this example, the evaluation results of the film quality of silicon nitride films formed by plasma CVD method are shown. Specifically, silicon nitride film is formed by using a mixture of silane and nitrogen gas as the supply gas. and silicon nitride films formed using a mixture of silane, nitrogen, and ammonia as the supply gas. , the results of ESR measurements are shown.

[0268] In this example, the method for preparing the samples used in the ESR measurements will be described below.

[0269] For the ESR measurement, samples 1 to 3 were prepared, each of which had a silicon nitride film of 300 nm thick formed on a quartz substrate. The silicon nitride film was formed by placing a quartz substrate in the film-forming chamber of a plasma CVD device. The pressure in the deposition chamber was controlled to 100 Pa, and a high frequency power supply of 27.12 MHz was used to generate 2000 The plasma CVD apparatus was supplied with a power of 100 W. The substrate temperature was set to 350° C. Electrode area is 6000cm 2 The sample 1 is a parallel plate type plasma CVD apparatus. The supply gas was a mixture of silane and nitrogen. The gas mixture was a mixture of nitrogen and ammonia. The film formation conditions for each sample are shown in Table 1 below.

[0270] [Table 1]

[0271] ESR measurements were carried out on the prepared samples 1 to 5. The ESR measurements were carried out under the following conditions: The measurement temperature was -170°C, and the 9.2GHz high frequency power (microwave power) was The magnetic field was set to 1 mW, and the direction of the magnetic field was set parallel to the surface of the silicon nitride film of Samples 1 to 5. , which corresponds to the signal appearing at g=2.003 originating from the Nc center contained in the silicon nitride film. The detection limit for the spin density is 8.1 × 10 15 spins / cm 3 is.

[0272] The results of the ESR measurement are shown in Figure 12(A). The spin density of the Nc center in sample 1 is 2.7 × 10 17 spins / cm 3 It was confirmed that the silicon nitride film had many defects. In Samples 2 to 5 containing ammonia, the spin density derived from the Nc center was 5.1 x10 16 spins / cm 3 (Sample 2), 5.2 × 10 16 spins / cm 3 (sample 3), 6.0 × 10 16 spins / cm 3 (Sample 4), 5.5 × 10 16 spins / cm 3 (Sample 5) showed a uniformly low value independent of the ammonia flow rate, indicating a low level of defects in the film. It was confirmed that the silicon nitride film was reduced.

[0273] The first derivative curve obtained by ESR measurement is shown in Figure 12(B). At a g value of 2.003, the signal originating from defects in the film (Nc center) was observed in sample 1. On the other hand, in samples 2 to 5, the g value was 2.003. The signal strength was confirmed to be small.

[0274] From the above, it was found that the supply gases when forming a silicon nitride film by plasma CVD were silane and nitrogen. By using a mixed gas of silicon and ammonia, it is possible to form a silicon nitride film with reduced defects in the film. By using this silicon nitride film as a gate insulating layer, It is possible to realize a gate insulating layer with good breakdown voltage, and a transistor including the gate insulating layer is This suggests that it is possible to produce a transistor with good D tolerance. [Example]

[0275] In this example, the characteristics of the silicon nitride film formed by the plasma CVD method as a barrier film were investigated. The evaluation results are shown in Figure 13. Thermal Desorption Spectroscopy (TDS) Used.

[0276] In this example, a silicon nitride film was formed on a quartz substrate by plasma CVD. Evaluation was carried out using Samples 1 to 8. The method for preparing the samples is described below.

[0277] To form a silicon nitride film, a quartz substrate is placed in the film formation chamber of a plasma CVD device. The pressure is controlled to 100 Pa, and 2000 W of power is supplied by a 27.12 MHz high frequency power source. The substrate temperature was set to 350°C. 00cm 2 This is a parallel plate type plasma CVD device.

[0278] For sample 6, the supply gas was a mixture of silane, nitrogen, and ammonia (SiH4 flow rate 200 scc m: N2 flow rate 2000sccm: NH3 flow rate 2000sccm) and the film thickness is 300nm A silicon nitride film was formed.

[0279] For sample 7, the supply gas was a mixture of silane, nitrogen, and ammonia (SiH4 flow rate 200 scc m: N2 flow rate 2000sccm: NH3 flow rate 2000sccm) and the film thickness was 275nm After forming the first silicon nitride film, the supply gas was changed to a mixture of silane and nitrogen in the same film formation chamber. Gas (SiH4 flow rate 200sccm: N2 flow rate 5000sccm) A second silicon nitride film was formed.

[0280] For sample 8, the supply gas was a mixture of silane, nitrogen, and ammonia (SiH4 flow rate 200 scc m: N2 flow rate 2000sccm: NH3 flow rate 2000sccm) and the film thickness was 275nm After the first silicon nitride film is formed, the flow rate of ammonia is reduced in the same film formation chamber. SiH4 flow rate 200sccm: N2 flow rate 2000sccm: NH3 flow rate 100sccm Then, a second silicon nitride film was formed to a thickness of 50 nm.

[0281] Figure 13 shows the evaluation results of the TDS measurement for each sample at M / z = 2 (H2). ) is the result of TDS measurement of sample 6 and sample 7 prepared in this example at M / z = 2 (H2). The evaluation results are shown in FIG. 13(B). TD at M / z=2 (H2) of Sample 6 and Sample 8 This is the evaluation result of the S measurement.

[0282] 13A and 13B, a silicon nitride film with a high hydrogen concentration is provided as a single layer. In sample 6, hydrogen was released by the heat treatment. In Sample 7 and Sample 8, which have a silicon nitride film with reduced concentration stacked on top, the hydrogen concentration is No hydrogen release was observed at around 450°C, where hydrogen release is confirmed. Even so, it can be confirmed that hydrogen release is extremely reduced.

[0283] Therefore, a silicon nitride film with a reduced hydrogen concentration in contact with a silicon nitride film with a high hydrogen concentration It was shown that providing an upper layer of .

[0284] As shown in Example 1, the plasma CVD method was performed using silane, nitrogen, and ammonia as the supply gas. The silicon nitride film formed by this method has reduced defects in the film and has a high dielectric strength. The silicon nitride film having reduced defects is then coated with a silicon nitride film having reduced hydrogen concentration. The stacked structure maintains high ESD resistance while retaining the ability to act as a donor for the oxide semiconductor layer. Since the release of hydrogen can be reduced, the gate insulating layer of a transistor is preferably made of silicon dioxide. can be applied. [Explanation of symbols]

[0285] 300 transistors 310 Transistor 320 transistors 330 Transistor 400 boards 402 gate electrode layer 404 Gate insulating layer 404a Gate insulating layer 404b Gate insulating layer 404c Gate insulating layer 406 Oxide insulating layer 408 Oxide semiconductor layer 408a Oxide semiconductor layer 408b Oxide semiconductor layer 410a Source electrode layer 410b drain electrode layer 412 Oxide insulating layer 414 Protective Insulation Layer 414a Protective insulating layer 414b Protective insulating layer 500 boards 502 Gate insulating layer 504 Interlayer insulation layer 505 Color filter layer 506 Insulation Layer 507 Bulkhead 510 Transistor 511a gate electrode layer 511b gate electrode layer 512 Oxide insulating layer 513a conductive layer 513b Conductive layer 514 Oxide semiconductor layer 520 Capacitive element 521a conductive layer 521b Conductive layer 522 Oxide insulating layer 523 Conductive Layer 524 Insulation Layer 525 Insulation Layer 526 Oxide semiconductor layer 530 Wiring layer intersection 533 Conductive Layer 540 Light-emitting element 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 620 Gate insulating layer 621 Oxide insulating layer 622 light 623 Oxide semiconductor layer 631 Insulating Layer 632 Insulating layer 633 Interlayer insulation layer 634 Interlayer insulation layer 640 transistors 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive layer 4020a Gate insulating layer 4020b oxide insulating layer 4021 Insulation layer 4030 oxide insulating layer 4031 Electrode layer 4032 Protective insulation layer 4033 Insulation layer 4034 Electrode layer 4035 Spacer 4038 Insulation layer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9000 tables 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fasteners 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9100 Television equipment 9101 Housing 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote control device 9201 Main Unit 9202 Housing 9203 Display section 9204 keyboard 9205 External connection port 9206 Pointing Device 9630 chassis 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC / DC Converter 9637 Converter 9638 Operation Key 9639 Button

Claims

[Claim 1] a gate electrode layer; a gate insulating layer on the gate electrode layer; a first oxide insulating layer on the gate insulating layer; an oxide semiconductor layer which is on and in contact with the first oxide insulating layer and overlaps with the gate electrode layer; a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer; a second oxide insulating layer covering the source electrode layer and the drain electrode layer and in contact with a part of the oxide semiconductor layer; a protective insulating layer on the second oxide insulating layer, the gate insulating layer and the protective insulating layer are configured to include a silicon film containing nitrogen, the first oxide insulating layer and the second oxide insulating layer contain one or more metal elements selected from the constituent elements of the oxide semiconductor layer, the gate insulating layer has a thickness greater than the thickness of the first oxide insulating layer; the protective insulating layer has a thickness greater than the thickness of the second oxide insulating layer; The semiconductor device has edges of the oxide semiconductor layer and the first oxide insulating layer aligned with each other.

Images