Power conversion device

Abstract

To provide a power conversion device suppressing increases of a size and cost of a device, and failure risk, and applying phase shift PWM control.SOLUTION: A first and a second legs Leg1 and Leg2 have a DC electric power supply and a first to N-th units 41-4N of a full-bridge circuit connected in parallel to the DC electric power supply. One ends of reactors L11-L(2N)2 are connected respectively to u-phase and v-phase of the first to the N-th units 41-4N. The other ends of the reactors connected to the u-phase of the first to the N-th units 41-4N of the first leg Leg1 are connected each other to form an output terminal. Furthermore, the other ends of the reactors connected to the v-phase of each unit of the second leg are connected each other to form an output terminal. A control unit controls switching elements of the first to the N-th units 41-4N of the first and the second legs Leg1 and Leg2 by phase shift PWM control.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a power conversion device that reduces output current ripple by applying phase-shift PWM control to a chopper circuit that has been increased in capacity through series-parallel connection. [Background technology]

[0002] Figure 1 shows the circuit configuration of the power conversion device disclosed in Patent Document 1. In Figure 1(a), units 21 to 2N, each connected to a DC voltage 2a and a cell 2b, are connected in series and parallel to form a large-capacity power conversion device. In addition, by applying a full-bridge circuit as shown in Figure 1(b) to cell 2b and phase-shift PWM control to the control, the current ripple flowing through output capacitor C is reduced, and the voltage ripple of the output capacitor C is also reduced.

[0003] However, in the configuration shown in Figure 1, each unit requires a DC voltage 2a, and the number of parts per unit is large. Therefore, there are concerns that increasing the number of units to accommodate larger capacity will result in larger equipment, higher costs, and an increased risk of failure.

[0004] Therefore, a circuit configuration of a power conversion device in which a plurality of cells 21 to 2N are connected in parallel to one DC voltage 2a can be considered, as shown in Fig. 2. However, while Fig. 1 shows a configuration in which a group of N units (DC voltage + cells) connected in series is called a leg and the legs are connected in parallel, Fig. 2 shows a configuration in which a group of N units (cells only) 21 to 2N connected in parallel and one DC voltage 2a is called a leg and the legs are connected in series.

[0005] This configuration makes it possible to set the number of cells and the number of DC voltages separately, reducing the number of parts by optimizing the device configuration.However, commonizing the DC voltage can cause arm shorts between different units, which can destroy the device, so phase-shift PWM control cannot be applied to the circuit configuration shown in Figure 2.

[0006] Therefore, overcurrent is suppressed by inserting reactors L11 to L42 in all output parts of each cell, as in the circuit configuration of Patent Document 2 shown in Figure 3. These reactors can serve as both output reactors for the power conversion device and cross-current suppression reactors. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2022-12104 [Patent Document 2] Japanese Patent Publication No. 2022-74610 Summary of the Invention [Problem to be solved by the invention]

[0008] However, Patent Document 2 aims for high-speed switching and does not apply phase-shift PWM control, so arm short circuits between units are not considered, and therefore the inductance values of reactors L11 to L42 are small.

[0009] On the other hand, when phase-shift PWM control is applied, there is always a switching pattern that generates an arm short-circuit loop, so the inductance values of reactors L11 to L42 must be large enough to prevent the current from rising too much during the period when the loop current is generated.

[0010] In view of the above, the challenge is to provide a power conversion device that applies phase-shift PWM control while suppressing increases in the size and cost of the device and the risk of failure. [Means for solving the problem]

[0011] The present invention has been devised in view of the above-mentioned problems of the related art, and one aspect of the present invention is a power supply comprising first and second legs each having a DC power supply and first to Nth (N: a natural number of 2 or more) units of a full bridge circuit connected in parallel to the DC power supply; reactors each having one end connected to a u phase and a v phase of the first to Nth units; and a control unit that controls switching elements of the first to Nth units of the first and second legs by phase-shift PWM control, wherein output terminals include a terminal connecting the other ends of the reactors connected to the u phase of the first to Nth units of the first leg and a terminal connecting the other ends of the reactors connected to the v phase of each unit of the second leg, and the other end of the reactor connected to the v phase of the first to Nth units of the first leg is connected to the other end of the reactor connected to the u phase of the first to Nth units of the second leg.

[0012] In another aspect, the inverter includes first and second legs each having a DC power supply and first to Nth (N: a natural number of 2 or more) units of a full bridge circuit connected in parallel to the DC power supply; reactors each having one end connected to a u phase and a v phase of the first to Nth units; and a control unit that controls switching elements of the first to Nth units of the first and second legs by phase-shift PWM control, wherein a terminal connecting the other ends of the reactors connected to the u phase of the first to Nth units of the first leg and a terminal connecting the other ends of the reactors connected to the v phase of the first to Nth units of the second leg are used as output terminals, and the other end of the reactor connected to the v phase of the kth (k: an integer of 1 to N) unit of the first leg and the other end of the reactor connected to the u phase of the kth unit of the second leg are connected to each other.

[0013] In one embodiment, the control unit calculates the u-phase current average value and the v-phase current average value in each leg, calculates the difference between the u-phase current measurement value of each unit in each leg and the u-phase current average value in each leg, and the difference between the v-phase current measurement value of each unit in each leg and the v-phase current average value in each leg, multiplies each of the differences by a cross current suppression gain to calculate a cross current suppression correction value, corrects the duty by adding the cross current suppression correction value, and controls the switching elements of the first to Nth units based on the corrected duty.

[0014] In one aspect, the control unit corrects the duty by adding a negative dead time compensation amount during a period when the slope of the triangular wave carrier is positive when current is flowing into the first to Nth units, and corrects the duty by adding a positive dead time compensation amount during a period when the slope of the triangular wave carrier is negative when current is flowing out of the first to Nth units, and controls the switching elements of the first to Nth units based on the corrected duty. [Effects of the Invention]

[0015] This makes it possible to provide a power conversion device that applies phase-shift PWM control while suppressing increases in device size, costs, and risk of failure. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of a conventional power conversion device. [Figure 2] FIG. 1 is a diagram showing a circuit configuration of a conventional power conversion device in which the number of DC voltages is reduced. [Figure 3] FIG. 1 is a diagram showing a circuit configuration of a conventional parallel-connected chopper circuit. [Figure 4] 1 is a diagram showing a circuit configuration of a power conversion device according to a first embodiment. [Figure 5] FIG. 10 is a diagram showing the state of the switching element and the voltage of each part in Mode 0. [Figure 6] FIG. 10 is a diagram showing the state of the switching element and the voltage of each part in Mode 1. [Figure 7]FIG. 10 is a diagram showing the state of the switching element and the voltage of each part in Mode 2. [Figure 8] 10 is a diagram showing the state of the switching element and the voltage of each part in Mode 3. [Figure 9] 10 is a diagram showing the state of the switching element and the voltage of each part in Mode 4. [Figure 10] A diagram showing the state of the switching element and the voltage of each part in Mode 5. [Figure 11] A diagram showing the state of the switching element and the voltage of each part in Mode 6. [Figure 12] A diagram showing the state of the switching elements and the voltages of each part in Mode 7. [Figure 13] A diagram showing the state of the switching elements and the voltages of each part in Mode 8. [Figure 14] A diagram showing gate signal generation and voltage output mode per unit. [Figure 15] FIG. 10 is a diagram showing a change in output voltage Vout due to interleaving operation. [Figure 16] FIG. 10 is a diagram showing the circuit configuration of a power conversion device according to a second embodiment. [Figure 17] FIG. 10 is a diagram showing the state of the switching elements and the voltages of the various parts in Mode 0'. [Figure 18] FIG. 10 is a diagram showing the state of the switching element and the voltage of each part in Mode 1'. [Figure 19] FIG. 10 is a diagram showing the state of the switching elements and the voltages of the various parts in Mode 2'. [Figure 20] FIG. 10 is a diagram showing the state of the switching elements and the voltages of the various parts in Mode 3'. [Figure 21] 10 is a diagram showing the state of the switching elements and the voltages of the various parts in Mode 4'. FIG. [Figure 22] FIG. 10 is a diagram showing the state of the switching elements and the voltages of the various parts in Mode 5'. [Figure 23] FIG. 10 is a diagram showing the state of the switching elements and the voltages of each part in Mode 6'. [Figure 24] 10 is a diagram showing the state of the switching elements and the voltages of each part in Mode 7'. FIG. [Figure 25] A diagram showing the state of the switching elements and the voltages of each part in Mode 8'. [Figure 26] FIG. 10 is a block diagram showing a control unit according to a third embodiment. [Figure 27] FIG. 10 is a diagram showing waveforms in the cases with and without dead time compensation. [Figure 28] FIG. 10 is a block diagram showing a control unit according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, first to fourth embodiments of the power converter of the present invention will be described in detail with reference to FIGS.

[0018] [Embodiment 1] The circuit configuration of the power conversion device according to the first embodiment is shown in Fig. 4. Here, the bold lines indicate three-phase AC.

[0019] Reference numeral 1 denotes a three-phase AC power supply (system voltage), to which a first leg leg1 and a second leg leg2 are connected.

[0020] Each of legs leg1 and leg2 includes an insulating three-phase transformer 3, a three-phase PWM rectifier AC / DC, and first to Nth units 41 to 4N connected in parallel to the three-phase PWM rectifier AC / DC. The three-phase transformer 3 and the three-phase PWM rectifier AC / DC generate a DC voltage. In FIG. 4, the DC voltage is shown as the three-phase transformer 3 and the three-phase PWM rectifier AC / DC, but other configurations are also possible. The first to Nth units 41 to 4N are configured only with chopper circuits, omitting the DC voltage 2a in FIG. 1.

[0021] The first unit 41 is a full-bridge circuit, with the left device defined as the u-phase and the right device defined as the v-phase. The u-phase has first and second switching elements SW11 and SW12 connected in series, and the v-phase has third and fourth switching elements SW13 and SW14 connected in series. The same applies to the second unit 42 to the Nth unit 4N.

[0022] One end of reactors L11 to L(2N)2, which act as both short-circuit prevention and output, is connected to the u-phase output and v-phase output of each unit, respectively. N is a natural number equal to or greater than 2. When phase-shift PWM control is performed between units connected in parallel to the same power supply, arm short circuits occur between different units. To prevent this, reactors L11 to L(2N)2 are inserted in the outputs of all units. In addition, in this first embodiment, reactors with large inductance values are used so that no problems arise even if an arm short circuit occurs.

[0023] The other ends of reactors L11 to LN1 connected to the u-phase of the 1st to Nth units 41 to 4N of the first leg leg1 are connected together to form an output terminal. Also, the other ends of reactors L(N+1)2 to L(2N)2 connected to the v-phase of the 1st to Nth units 41 to 4N of the second leg leg2 are connected together to form an output terminal. Also, the other ends of reactors L12 to LN2 connected to the v-phase of the 1st to Nth units 41 to 4N of the first leg leg1 and reactor L(N+1)1 connected to the u-phase of the 1st to Nth units 41 to 4N of the second leg leg2 are connected together.

[0024] An output capacitor C is connected between both output terminals. A load 5 is connected in parallel to the output capacitor C.

[0025] The current of the u-phase output of the first unit 41 of the first leg leg1 is I11, and the current of the v-phase output of the first unit 41 of the first leg leg1 is I12. The same applies to the currents of the other reactors. The output voltage (the voltage of the output capacitor C) is Vout.

[0026] The operation of the power conversion device in the first embodiment can be explained by the voltage division of reactors L11 to L42 in each switching mode. FIGS. 5 to 13 show the states of the switching elements and the voltages of each section in each mode. To make the current paths easier to understand, FIGS. 5 to 13 do not show non-conducting switching elements, but only the conducting switching elements. The two three-phase PWM rectifiers AC / DC are controlled to output voltage E [V], and the inductance values of the reactors L11 to L42 connected to each unit are all equal. In FIGS. 5 to 13, the number of units in each leg is two. Switching elements SW11 to SW14 are the first unit of the first leg leg1, switching elements SW21 to SW24 are the second unit of the first leg leg1, switching elements SW31 to SW34 are the first unit of the second leg leg2, and switching elements SW41 to SW44 are the second unit of the second leg leg2.

[0027] [Mode 0] As shown in Figure 5, the switching elements of the lower arms of all units are in the ON state. All voltages are 0 [V].

[0028] [Mode 1] As shown in Figure 6, the state changes from Mode 0 to Mode 1, where switching element SW11 of the upper arm of the u-phase of the first unit of the first leg (leg1) is turned on. The voltage E [V] of the upper three-phase PWM rectifier AC / DC is divided by reactors L11 and L21, and current flows through the path from SW11 to SW22. The voltage division ratio is determined by the inductance value, and a voltage of E / 2 [V] is generated across reactors L11 and L21. The output voltage Vout is E / 2 [V].

[0029] [Mode 2] As shown in Figure 7, from the state in Mode 1, switching element SW21 of the upper arm of the u-phase of the second unit of the first leg (leg1) is turned ON. The circuit in Mode 1 (SW11 → SW22) is disconnected, and the voltage of reactors L11 and L21 becomes 0 [V]. The output voltage Vout directly reflects the voltage of the upper three-phase PWM rectifier AC / DC, becoming E [V].

[0030] [Mode 3] As shown in Figure 8, the state changes from Mode 2 to Mode 3, where switching element SW31 of the upper arm of the u-phase of the first unit of the second leg (leg2) is turned on. The voltage E [V] of the lower three-phase PWM rectifier AC / DC is divided by reactors L31 and L41, and current flows through the path from SW31 to SW42. The output voltage of the second leg becomes E / 2 [V], and the output voltage E of the first leg (leg1) is added to this, so the output voltage Vout of the entire power conversion device becomes 3E / 2 [V].

[0031] [Mode 4] As shown in Figure 9, from the state of Mode 3, switching element SW41 of the upper arm of the u-phase of the second unit of the second leg (leg2) is turned on. The circuit in Mode 3 (SW31 → SW42) is disconnected, and the voltage of reactors L31 and L41 becomes 0 [V]. Each leg outputs the voltage of the three-phase PWM rectifier AC / DC as is, so the output voltage Vout of the entire power conversion system becomes 2E [V].

[0032] [Mode 5] As shown in Figure 10, the state changes from Mode 4 to Mode 5, where switching element SW13 of the upper arm of the v-phase of the first unit of the first leg (leg1) is turned on. The voltage E [V] of the upper three-phase PWM rectifier AC / DC is divided by reactors L12 and L22, and current flows through the path from SW13 to SW24. The output voltage of the first leg (leg1) decreases to E / 2 [V], so the output voltage Vout of the entire power conversion device becomes 3E / 2 [V].

[0033] [Mode 6] As shown in Figure 11, from the state of Mode 5, the switching element SW23 of the upper arm of the v-phase of the second unit of the first leg leg1 is turned on. The circuit in Mode 5 (SW13 → SW24) is disconnected, and the voltage of reactors L12 and L22 becomes 0 [V]. Since the output voltage of the first leg leg1 becomes 0 [V], the output voltage Vout of the entire power conversion device becomes E [V].

[0034] [Mode 7] As shown in Figure 12, the state changes from Mode 6 to Mode 7, where switching element SW33 of the upper arm of the v-phase of the first unit of the second leg (leg2) is turned on. The voltage E [V] of the lower three-phase PWM rectifier AC / DC is divided by reactors L32 and L42, and current flows through the path from SW33 to SW44. The output voltage of the second leg (leg2) decreases to E / 2 [V], and the output voltage Vout of the entire power conversion device becomes E / 2 [V].

[0035] [Mode 8] As shown in Figure 13, from the state of Mode 7, the switching element SW43 of the upper arm of the v-phase of the second unit of the second leg (leg2) is turned ON, and the switching elements of the upper arms of all units are turned ON. The circuit in Mode 7 (SW33 → SW44) is cut off, and the voltage of each part becomes 0 [V].

[0036] From the above, the state in which the switching element of the upper arm of the u phase is ON and the switching element of the lower arm of the v phase is ON is the positive voltage output mode, and the state in which the switching elements of the upper arms of both the u phase and the v phase are ON or the switching elements of the lower arms are ON is the zero voltage mode. The output voltage Vout of the entire power conversion device is determined by the number of units in the positive voltage output mode. When the number of legs is N, reg , the total number of units is N unit , the number of units in positive voltage output mode is N on Then, the output voltage of the entire power converter V out is expressed by the following equation (1).

[0037]

number

[0038] This circuit uses phase-shift PWM control to synchronize the triangular wave carrier between units. unit Operate with a phase shift of [rad].

[0039] Furthermore, since a full-bridge circuit is applied to the unit, in the case of a ±1 triangular wave carrier, the v-phase duty uses a value that is -1 times the u-phase duty (see Figure 14). By applying this type of control, the current ripple frequency flowing through the output capacitor C can be reduced to 2 × N reg ×N unit It can be doubled.

[0040] Figure 14 shows the gate signal (on / off command signal for the switching element SW) and voltage output mode per unit, and Figure 15 shows the output voltage V out The figure shows how the duty ratio is determined. However, the duty ratio is 7 / 8 = 0.875, and V1 to V4 indicate whether each unit is in positive voltage output mode or zero voltage mode. From Figure 15, if the duty ratio is D, the average value V of the output voltage Vout of the entire power conversion device is mean is expressed by the following equation (2).

[0041]

number

[0042] As described above, according to the first embodiment, it is possible to suppress an increase in the size and cost of the device, and an increase in the risk of failure, and also to apply phase shift PWM control.

[0043] In other words, by sharing the DC voltage (for example, three-phase transformer 3, three-phase PWM rectifier AC / DC, etc.) in each leg, the volume of the device can be reduced by the difference with the additional reactor. Also, by reducing the number of parts used (such as the number of transformers), costs, the risk of failure, and manufacturing man-hours can be reduced.

[0044] In addition, by applying phase-shift PWM control, the current ripple and voltage ripple of the output capacitor C can be reduced.

[0045] [Embodiment 2] The power conversion device of the second embodiment is shown in Fig. 16. Here, the bold lines represent three-phase AC. The same parts as those of the first embodiment are given the same reference numerals, and the description thereof will be omitted. The following points are different from the first embodiment.

[0046] The neutral line is divided to separate units within the same leg. That is, the other ends of reactors L11 to LN1 connected to the u-phases of the first to N-th units 41 to 4N of the first leg leg1 are connected together to form an output terminal. Also, the other ends of reactors L(N+1)2 to L(2N)2 connected to the v-phases of the first to N-th units 41 to 4N of the second leg leg2 are connected together to form an output terminal. Also, the other ends of reactor Lk2 connected to the v-phase of the k-th unit (k = an integer from 1 to N) of the first leg leg1 and reactor L(N+k)1 connected to the u-phase of the k-th unit of the second leg leg2 are connected together.

[0047] Reactor Lk2 connected to the v-phase of the k-th unit in the first leg leg1 and reactor L(N+k)1 connected to the u-phase of the k-th unit in the second leg leg2 may be two components, and may be a common component with reactor L11, etc., or may be a single component with double the withstand voltage and inductance. It is preferable to determine which to use based on the cost incurred for the reactor, the level of voltage used, the load current, etc.

[0048] The operation of the power conversion device of the second embodiment can be explained in terms of the voltage division of reactors L11 to L42 in each switching mode, as in the first embodiment. Figures 17 to 25 show the states of the switching elements and the voltages of each part in each mode. In order to make the current path easier to understand, Figures 17 to 25 do not show non-conducting switching elements, but only conductive switching elements.

[0049] [Mode 0'] As shown in Fig. 17, this is the same as Mode 0. The output voltage Vout is 0 [V].

[0050] [Mode 1'] As shown in Figure 18, this is the same as Mode 1. The voltage E [V] of the upper three-phase PWM rectifier AC / DC is divided and applied to reactors L11 and L21 at E / 2 [V] each. The output voltage Vout is E / 2 [V].

[0051] [Mode 2'] As shown in Fig. 19, this is the same as Mode 2. The output voltage Vout is E [V].

[0052] [Mode 3'] As shown in Figure 20, from Mode 2', switching element SW31 of the upper arm of the u-phase of the first unit of the second leg (leg2) is turned on. The voltage E [V] of the lower three-phase PWM rectifier AC / DC is divided by L12, L22, L31, and L41, and current flows through the path SW31 → SW14 → SW24 → SW42. The voltage of each reactor becomes E / 4 [V], and the output voltage Vout of the entire power conversion device becomes 3E / 2 [V].

[0053] [Mode 4'] As shown in Fig. 21, this is the same as Mode 4. The output voltage Vout is 2E [V].

[0054] [Mode 5'] As shown in Figure 22, from Mode 4', switching element SW13 of the upper arm of the v-phase of the first unit of the first leg (leg1) is turned on. The voltage E [V] of the upper three-phase PWM rectifier AC / DC is divided by L12, L22, L31, and L41, and current flows through the path SW13 → SW31 → SW41 → SW24. The voltage of each reactor becomes E / 4 [V], and the output voltage Vout of the entire power conversion device becomes 3E / 2 [V].

[0055] [Mode 6'] As shown in Fig. 23, this is the same as Mode 6. The output voltage Vout is E [V].

[0056] [Mode 7'] As shown in Figure 24, this is the same as Mode 7. The voltage E [V] of the lower three-phase PWM rectifier AC / DC is divided and applied to reactors L32 and L42 at E / 2 [V] each. The output voltage Vout is E / 2 [V].

[0057] [Mode 8'] As shown in Fig. 25, this is the same as Mode 8. The output voltage Vout becomes 0 [V].

[0058] When current flows between units via the neutral wire, as in Mode 3 and Mode 5, voltage is divided by two reactors in the same leg in Embodiment 1. In contrast, in Embodiment 2, voltage is divided by a total of four reactors, including other legs, as in Mode 3' and Mode 5', so the voltage generated per reactor is halved.

[0059] Furthermore, when monitoring the output current of a unit for reasons such as overcurrent detection, current sensors for measuring current values at eight locations, I11 to I42, were required in embodiment 1. In contrast, in embodiment 2, I12 and I31, and I22 and I41, are the same current, so the number of required current sensors is as small as six, allowing the function to be implemented.

[0060] According to the second embodiment, the same effects as those of the first embodiment can be achieved. Furthermore, compared to the first embodiment, the withstand voltage of the reactor provided in the neutral line can be halved. Therefore, when two reactors with the same withstand voltage and inductance are provided, it is possible to reduce the size of the reactor and the device. Furthermore, it is also possible to use one reactor with double the withstand voltage and inductance. In this case, the number of reactors can be reduced.

[0061] Furthermore, compared to the first embodiment, the number of current sensors required to measure the unit output current can be reduced.

[0062] [Embodiment 3] The control unit of this embodiment 3, which is applied to the circuit configurations shown in the embodiments 1 and 2, is shown in Fig. 26. The control unit generates duties and controls the switching elements of the first to Nth units 41 to 4N of each leg based on the duties. The control unit of this embodiment 3 performs cross current suppression control. The method of cross current suppression control is as follows.

[0063] (1) Measure the u-phase current and v-phase current of each leg and each unit.

[0064] (2) Calculate the average u-phase current and the average v-phase current for each leg. Calculate the difference between the u-phase current measurement value for each unit in each leg and the average u-phase current for each leg, and the difference between the v-phase current measurement value for each unit in each leg and the average v-phase current for each leg. Apply the cross current control gain K C The cross current suppression correction value is calculated by multiplying the above by .

[0065] (3) The cross current suppression correction value calculated in (2) is added to the duty of each unit to correct the duty.

[0066] The control unit controls the switching elements of the first to Nth units 41 to 4N of each leg based on the corrected duty.

[0067] A specific example will be described with reference to Fig. 26. The controller 6 determines the duty cycle based on the command value and the measured value. 11~N1 , duty (N+1)1 ~duty (2N)1 The multiplier 11 outputs the duty 11~N1 , duty (N+1)1~(2N)1 Multiply by -1 and duty 12~N2 , duty (N+1)2~(2N)2 This duty is output. 11~N1 , duty 12~N2 , duty (N+1)1~(2N)1 , duty (N+1)2~(2N)2 is the duty before correction.

[0068] The summation calculation unit 7 calculates the u-phase current measurement value I of the first leg leg1. 11~N1 The sum of the measured v-phase current of the first leg (leg1) I 12~N2 The sum of the measured u-phase current of the second leg (leg2) I (N+1)1~(2N)1 The sum of the measured v-phase current of the second leg (leg2) I (N+1)2~(2N)2 Calculate the sum of

[0069] Multiplier 8 multiplies the above-mentioned sum by the reciprocal of the number of units in each leg to calculate the u-phase current average value and v-phase current average value for each leg.

[0070] The subtractor 9 subtracts the u-phase current measurement value and the v-phase current measurement value of each leg and each unit from the u-phase current average value and the v-phase current average value of each leg to calculate the difference.

[0071] The gain multiplier 10 multiplies the difference by a cross current suppression gain Kc to calculate a cross current suppression correction value.

[0072] The adder 12 adds the cross current suppression correction value to the duty before correction to obtain the cross current suppression corrected duty=duty 11~N1 * , duty 12~N2 * , duty (N+1)1~(2N)1 * , duty (N+1)2~(2N)2 * Output as

[0073] In this circuit configuration, because the parallel units share a power supply, the u-phase current and the v-phase current are not equal, and cross current suppression control must be performed separately. In the configuration of embodiment 1, the number of current measurement points required for cross current suppression control is 4N (twice the number of units), but in embodiment 2, because the neutral wire current is common between legs, the number of current measurement points required is 3N (1.5 times the number of units). However, in this case, N is an even number.

[0074] By applying each cross current suppression corrected duty* corrected according to FIG. 24 to FIG. 14, a gate signal for each switching element is generated.

[0075] According to the third embodiment, the same effects as those of the first and second embodiments can be achieved. In addition, the power supply (DC voltage) is shared, and cross current suppression becomes possible even in a state where the u-phase current and the v-phase current are not equal.

[0076] Furthermore, when the third embodiment is applied to the second embodiment, the number of necessary current sensors can be reduced compared to when the third embodiment is applied to the first embodiment.

[0077] [Embodiment 4] In the circuits of Embodiments 1 and 2, a loop current is generated between each parallel unit due to the sharing of a power supply (DC voltage) and phase-shift PWM control. The loop current component is superimposed on the unit's DC current component, resulting in a current ripple at the carrier frequency. When the DC current component is larger than the ripple current component, the polarity of the unit current remains constant, but when the ripple current component becomes larger than the DC current component, the unit current polarity fluctuates.

[0078] The unit current polarity affects the soft switching operation of each unit, as well as the output voltage pulse width and average output voltage. When the current polarity is constant, the fluctuations in the output voltage pulse width generated by each unit are constant, and the controller can absorb the fluctuations.

[0079] However, if the current polarity of each unit is different, the fluctuation amount of the output voltage pulse width also differs for each unit, causing the average output voltage to pulsate and deteriorating the control accuracy. Therefore, in this fourth embodiment, a dead time compensator shown in Figures 27 and 28 is introduced as a countermeasure against the output voltage pulsation that occurs when the output current is small.

[0080] Figure 27 shows the dead time compensation method when current is flowing out of the unit. When current is flowing out, the rise of the voltage Vunit is within the dead time period T deadtime Therefore, during the period when the slope of the triangular wave carrier is negative, a positive correction is made to the duty by the amount of the delay. Conversely, when current flows in, compensation is made by a negative correction to the duty during the period when the slope of the triangular wave carrier is positive. When the current value is large enough, the amount of compensation is as shown in Figure 27 (4T deadtime / T f ) is sufficient. Here, T f is the carrier period, and the dead time period T deadtime and T fThe duty cycle deviation is calculated from the ratio of 1 / 4. When the current value is near 0A, the compensation amount varies depending on the time required to charge the output capacitance of the device (switching element) used (C_oes for IGBTs, C_oss for MOSFETs, or the corresponding capacitance for the switching element used). Here, C_oes is used for IGBTs and is expressed as C_oes = C_CE (collector-emitter capacitance) + C_GC (collector-gate capacitance), while C_oss is used for MOSFETs and is expressed as C_oss = C_DS (drain-source capacitance) + C_DG (drain-gate capacitance). Therefore, the compensation amount is calculated from the output capacitance, current value, and voltage value, and the compensation amount corresponding to the current and voltage value is determined. For example, the compensation amount is calculated by dividing the product of the voltage to be applied when the device is OFF and the output capacitance by the current (measured value or command value). If the calculation of the compensation amount becomes complicated, a predicted value can also be used. This compensation amount calculation can be performed using a conventionally known method.

[0081] The control unit of the fourth embodiment is as shown in Fig. 28. The cross current suppression control unit 13 in Fig. 28 includes the summation calculation unit 7, multiplier 8, subtractor 9, gain multiplier 10, multiplier 11, and adder 12 in Fig. 26.

[0082] The multiplier 14 multiplies the slope of the triangular wave carrier by −1. The dead time compensation calculator 15 calculates the current measurement I 11~(2N)2 , the output capacitance of the device used, and the carrier period T f , dead time T deadtime The multiplier 16 multiplies the dead time compensation amount by the output of the multiplier 14. The adder 17 calculates the duty after cross current suppression correction = duty 11~(2N)2 * Add the output of multiplier 16 to the duty 11~(2N)2 ** 28 shows a control in which dead time compensation is performed after the cross current suppression control unit 13 of the third embodiment corrects the duty, but the present invention is also applicable to a control in which the cross current suppression control of the third embodiment does not correct the duty.

[0083] As described above, according to the fourth embodiment, the same effects as those of the first to third embodiments can be achieved. In addition, the output voltage pulsation at low output can be reduced.

[0084] Although the present invention has been described in detail above only with respect to the specific examples, it will be apparent to those skilled in the art that various modifications and variations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and variations fall within the scope of the claims. [Explanation of symbols]

[0085] 1...Three-phase AC power supply (system voltage) leg1, leg2...first and second legs 3...Three-phase transformer AC / DC…Three-phase PWM rectifier 41~4N...1st to Nth units L11~L(2N)2...Reactor C: Output capacitor SW11 to SW44: Switching elements 5...Load

Claims

1. a first leg and a second leg each including a DC power supply and first to N-th (N: a natural number equal to or greater than 2) units of a full bridge circuit connected in parallel to the DC power supply; reactors each having one end connected to a u-phase and a v-phase of the first to Nth units; a control unit that controls the switching elements of the first to Nth units of the first and second legs by phase shift PWM control; Equipped with a terminal connecting the other ends of the reactors connected to the u-phases of the first to N-th units of the first leg and a terminal connecting the other ends of the reactors connected to the v-phases of the units of the second leg are set as output terminals, A power conversion device characterized in that the other end of the reactor connected to the v-phase of the first to N-th units of the first leg is connected to the other end of the reactor connected to the u-phase of the first to N-th units of the second leg.

2. a first leg and a second leg each including a DC power supply and first to N-th (N: a natural number equal to or greater than 2) units of a full bridge circuit connected in parallel to the DC power supply; reactors each having one end connected to a u-phase and a v-phase of the first to Nth units; a control unit that controls the switching elements of the first to Nth units of the first and second legs by phase shift PWM control; Equipped with a terminal connecting the other ends of the reactors connected to the u-phases of the first to N-th units of the first leg and a terminal connecting the other ends of the reactors connected to the v-phases of the first to N-th units of the second leg are set as output terminals, A power conversion device characterized in that the other end of the reactor connected to the v phase of the kth unit (k: an integer from 1 to N) of the first leg and the other end of the reactor connected to the u phase of the kth unit of the second leg are connected to each other.

3. The control unit Calculating the average u-phase current and the average v-phase current in each leg; calculating a difference between a u-phase current measurement value of each unit in each leg and the u-phase current average value in each leg, and a difference between a v-phase current measurement value of each unit in each leg and the v-phase current average value in each leg; Each difference is multiplied by a cross current suppression gain to calculate a cross current suppression correction value; 3. The power conversion device according to claim 1, wherein the cross current suppression correction value is added to the duty to correct it, and the switching elements of the first to Nth units are controlled based on the corrected duty.

4. The control unit 3. The power conversion device according to claim 1, wherein when a current is flowing into the first to Nth units, a negative dead time compensation amount is added to the duty for a period when the slope of the triangular wave carrier is positive, and when a current is flowing out of the first to Nth units, a positive dead time compensation amount is added to the duty for a period when the slope of the triangular wave carrier is negative, and the switching elements of the first to Nth units are controlled based on the corrected duty.

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