Semiconductor optical element and method for manufacturing semiconductor optical element

Abstract

To provide a semiconductor optical element capable of improving heat dissipation, and a method for manufacturing the semiconductor optical element.SOLUTION: A semiconductor optical element includes a substrate having a silicon layer, and a semiconductor element that is formed of a III-V compound semiconductor, has an optical gain, and has a mesa. The silicon layer has a waveguide, a recess portion, and a first slab portion. The recess portion is a portion that is recessed beyond the surfaces of the waveguide and the first slab portion, and is provided on both sides of the waveguide. The first slab portion is connected to the waveguide. The semiconductor element is bonded to the first slab portion. The mesa is located on the first slab portion.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor optical device and a method for manufacturing the semiconductor optical device. [Background technology]

[0002] A hybrid semiconductor optical device can be formed by bonding a semiconductor device made of a compound semiconductor and having optical gain to a substrate such as an SOI (Silicon On Insulator) substrate (silicon photonics) on which a waveguide is formed (see, for example, Non-Patent Document 1). After bonding, the semiconductor device is etched, etc. Light is transferred between the silicon waveguide and the semiconductor device. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Alexander W.Fang,et al. “Electrically pumped hybrid AlGaInAs-silicon evanescent laser” OPTICS EXPRESS Vol.14,No.20,pp.9203-9210 (2 October 2006) [Non-patent document 2] Javad Rahimi,et al. “Demonstration of a High-Efficiency Short-Cavity III-V-on-Si C-Band DFB Laser Diode” IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS,Vol.28,No.3,820406 (May / June 2022) Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor element bonded to the substrate is an active element that generates heat when it is operated. Grooves (trenches) are provided on both sides of the waveguide in the substrate. The inside of the grooves is filled with air or a dielectric. The grooves have lower heat dissipation properties than the other parts of the substrate. An increase in temperature can cause deterioration of the characteristics. Therefore, the object is to provide a semiconductor optical element that can improve heat dissipation properties, and a method for manufacturing a semiconductor optical element. [Means for solving the problem]

[0005] The semiconductor optical device according to the present disclosure comprises a substrate having a silicon layer, and a semiconductor device formed of a III-V compound semiconductor, having optical gain, and having a mesa, wherein the silicon layer has a waveguide, a recess, and a first slab portion, the recess being recessed below the surfaces of the waveguide and the first slab portion and provided on both sides of the waveguide, the first slab portion being connected to the waveguide, the semiconductor device being bonded to the first slab portion, and the mesa being located on the first slab portion. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a semiconductor optical device capable of improving heat dissipation and a method for manufacturing the semiconductor optical device. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating the semiconductor optical device according to the first embodiment. [Figure 2A] FIG. 2A is an enlarged plan view of the transition structure and its vicinity. [Figure 2B] FIG. 2B is a plan view illustrating the substrate. [Figure 3A] FIG. 3A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 3B] FIG. 3B is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 4A] FIG. 4A is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 4B]FIG. 4B is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 5] FIG. 5 is a cross-sectional view illustrating an example of a semiconductor optical device. [Figure 6] FIG. 6 is a diagram illustrating the optical output. [Figure 7] 7A to 7C are cross-sectional views illustrating a method for manufacturing a semiconductor optical device. [Figure 8] 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor optical device. [Figure 9] 9A to 9C are cross-sectional views illustrating a method for manufacturing a semiconductor optical device. [Figure 10] FIG. 10 is a cross-sectional view illustrating the semiconductor optical device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure includes (1) a substrate having a silicon layer; and a semiconductor device formed of a III-V compound semiconductor, having optical gain, and having a mesa, wherein the silicon layer has a waveguide, a recess, and a first slab portion, the recess being a portion recessed below the surfaces of the waveguide and the first slab portion and provided on both sides of the waveguide, the first slab portion being connected to the waveguide, the semiconductor device being bonded to the first slab portion, and the mesa being a semiconductor optical device located on the first slab portion. Bonding the semiconductor device to the first slab portion improves heat dissipation. Heat generated in the semiconductor device is dissipated through the first slab portion. Suppressing temperature rise suppresses deterioration of the characteristics of the semiconductor optical device. The mesa of the semiconductor device controls the mode shape of light. Optical loss can be suppressed. (2) In the above (1), the first slab portion may extend directly below the mesa and within a range of 3 μm or more from the edge of the mesa. Heat is generated in the mesa. Since the first slab portion is located directly below the mesa and within a range of 3 μm or more from the edge of the mesa, heat dissipation is improved. The mode shape of light propagating through the first slab portion is maintained. Light loss can be suppressed. (3) In the above (1) or (2), the semiconductor element may have a second slab portion, the second slab portion may be bonded to the first slab portion, and the mesa may be located on the second slab portion. The first slab portion and the second slab portion are bonded to each other, increasing the contact area. This improves heat dissipation and bonding strength. (4) In the above (3), the semiconductor element may have a first semiconductor layer, an active layer, and a second semiconductor layer, stacked in this order from the side closest to the substrate, the first semiconductor layer having a first conductivity type, the second semiconductor layer having a second conductivity type, the mesa including the second semiconductor layer, and the second slab portion including the first semiconductor layer and the active layer. Current flows through the mesa, carriers are injected into the active layer, and light is generated. Heat is generated by the current flowing through the mesa. Because the first slab portion is located below the mesa, heat dissipation is high and temperature rise can be suppressed. (5) In the above (4), a first electrode spaced apart from the mesa and electrically connected to the first semiconductor layer, and a second electrode provided on the mesa and electrically connected to the second semiconductor layer may be provided, and the first slab portion may extend from under the mesa to under the second electrode. Current flows between the first electrode and the second electrode. The first slab portion is located below the current path. This improves heat dissipation and allows heat to be dissipated effectively. (6) In any one of (3) to (5) above, the semiconductor element may have a protrusion, and the protrusion may protrude from the second slab portion onto the waveguide. This can improve the coupling efficiency between the semiconductor element and the substrate and reduce optical loss. (7) In any one of the above (1) to (6), the semiconductor element may have a dummy mesa, and the two dummy mesas may be located on both sides of the mesa. This makes it possible to suppress stress concentration on the mesa. (8) In any of the above (1) to (7), the semiconductor element may be in contact with the silicon layer, thereby improving heat dissipation. (9) A method for manufacturing a semiconductor optical device, comprising the steps of: bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain to a silicon layer of a substrate; and forming a mesa on the bonded semiconductor element, wherein the silicon layer has a waveguide, a recess, and a slab portion; the recess is a portion recessed below the surfaces of the waveguide and the slab portion and provided on both sides of the waveguide; the slab portion is connected to the waveguide; and in the bonding step, the semiconductor element is bonded to the slab portion and the mesa is located on the slab portion. Bonding the semiconductor element to the slab portion improves heat dissipation. Heat generated in the semiconductor element is dissipated through the slab portion. Suppressing temperature rise suppresses deterioration of the semiconductor optical device's characteristics. The mesa of the semiconductor element controls the mode shape of the light. Optical loss can be suppressed.

[0010] [Details of the embodiments of the present disclosure] Specific examples of semiconductor optical devices and methods for manufacturing semiconductor optical devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] First Embodiment (semiconductor optical element) FIG. 1 is a plan view illustrating a semiconductor optical device 100 according to the first embodiment. The semiconductor optical device 100 is a hybrid-type tunable laser device, and includes a substrate 10, a semiconductor device 30, an electrode 48 (second electrode), and an electrode 49 (first electrode). The semiconductor device 30 has optical gain and is bonded to one surface of the substrate 10. The Z-axis direction is the normal direction to the top surface of the substrate 10. The X-axis direction is a direction parallel to the waveguide. The Y-axis direction is perpendicular to the X-axis and Z-axis directions.

[0012] The semiconductor optical device 100 has a transition structure 101, a transition structure 102, two ring resonators 103, and two loop mirrors 104. In the X-axis direction, the loop mirror 104, the ring resonator 103, the transition structure 102, the semiconductor device 30, the transition structure 101, the ring resonator 103, and the loop mirror 104 are arranged in this order. This configuration forms a laser resonator.

[0013] The ring resonator 103 and the loop mirror 104 are provided on the substrate 10. The transition structure 101 and the transition structure 102 are portions that cause light to transition between the substrate 10 and the semiconductor element 30, and are formed by the substrate 10 and the semiconductor element 30.

[0014] Fig. 2A is an enlarged plan view of the transition structure 101 and its vicinity. Fig. 2B is a plan view illustrating the substrate 10, with the semiconductor element 30 removed from Fig. 2A. Figs. 3A to 5 are cross-sectional views illustrating the semiconductor optical element 100, showing cross sections along lines A1, A2, A3, and A4 in Fig. 2A and line L in Fig. 1, respectively. In Figs. 3A to 5, light distribution is illustrated by dashed lines.

[0015] As shown in FIGS. 3A to 5, substrate 10 is an SOI (Silicon on Insulator) substrate and includes substrate 12, box layer 14, and silicon (Si) layer 16, which are stacked in this order in the Z-axis direction. Substrate 12 is made of, for example, Si. Box layer 14 is made of, for example, silicon oxide (SiO2). Box layer 14 has a thickness of, for example, 3 μm. Silicon layer 16 has a thickness of, for example, 220 nm. The upper surface of substrate 10 and the surface of semiconductor element 30 are covered with insulating film 11. Insulating film 11 is made of, for example, SiO2 and has a thickness of 1 μm. Silicon layer 16 has a refractive index of 3.45. The refractive index of box layer 14 and insulating film 11 is 1.45, which is lower than that of silicon layer 16. Functional parts such as a waveguide are provided in silicon layer 16 of substrate 10.

[0016] 1, 2A, and 2B, the substrate 10 has a waveguide 20, a recess 24, a terrace 27, and a slab portion 28 (first slab portion). As shown in Fig. 1, the waveguide 20 is connected to both ends of the slab portion 28 in the X-axis direction. The slab portion 28 extends from the transition structure 101 to the transition structure 102.

[0017] As shown in Fig. 2B, the waveguide 20 is parallel to the X-axis direction. The waveguide 20 has a tapered portion 21. The width of the tapered portion 21 increases as it approaches the slab portion 28 and decreases as it moves away from the slab portion 28. The width W1 of the tip of the waveguide 20 shown in Fig. 2B is, for example, 420 nm.

[0018] In the Y-axis direction, a recess 24 and a terrace 27 are provided in this order on both sides of the waveguide 20. That is, the recess 24 is arranged next to the waveguide 20. The terrace 27 is arranged on the opposite side of the waveguide 20 from the recess 24. The recess 24 extends along the waveguide 20 and has a tapered shape corresponding to the tapered portion 21 of the waveguide 20.

[0019] As shown in Figures 3A to 4B, the waveguide 20 and the terrace 27 are portions of the silicon layer 16 that protrude in the Z-axis direction (upward) beyond the recess 24. The surface of the waveguide 20 is located at the same height as the surface of the terrace 27. The recess 24 is a portion that is recessed below the surfaces of the waveguide 20 and the terrace 27. The silicon layer 16 forms the bottom surface of the recess 24. The thickness of the silicon layer 16 in the recess is, for example, 30 nm. The recess 24 may extend partway through the silicon layer 16 in the Z-axis direction, or may extend through the silicon layer 16 to the box layer 14. An insulating film 11 is buried in the recess 24.

[0020] As shown in FIG. 2B, slab portion 28 has a width greater than that of waveguide 20 in the Y-axis direction, and is connected to terraces 27 on both sides of waveguide 20. In other words, no recess is provided between slab portion 28 and terrace 27. As shown in FIG. 5, slab portion 28 is a plate-shaped portion. The surface of slab portion 28 is located at the same height as the surface of terrace 27. Slab portion 28 is integrated with terrace 27, extends parallel to the XY plane, and forms the surface of silicon layer 16.

[0021] 1, the semiconductor device 30 has a slab portion 32 (second slab portion), two protrusions 33, and a mesa 35. The protrusion 33, the slab portion 32, and the protrusion 33 are arranged in this order in the X-axis direction. The slab portion 32 and the mesa 35 extend from one transition structure 101 to another transition structure 102.

[0022] As shown in FIG. 2A , the slab portion 32 is bonded to the slab portion 28 of the substrate 10. The lower surface of the slab portion 32 is in contact with the upper surface of the slab portion 28. The slab portion 32 is plate-shaped and has a width greater than that of the protrusion 33 and the mesa 35. The planar shape of the slab portion 32 is rectangular. In a planar view, the slab portion 32 does not protrude beyond the slab portion 28. The slab portion 28 extends outside the slab portion 32 from the position where it overlaps with the slab portion 32.

[0023] The protrusion 33 extends parallel to the X-axis, protrudes from the slab portion 32 onto the waveguide 20, and is located on the tapered portion 21 of the waveguide 20. The protrusion 33 has a tapered portion 34. In the example of FIG. 2A , the entire protrusion 33 is the tapered portion 34. The width of the tapered portion 34 increases the closer it is to the slab portion 32 and decreases the farther it is from the slab portion 32. The protrusion 33 has a width greater than that of the mesa 35. The width of the protrusion 33 at the portion where the protrusion 33 is connected to the slab portion 32 is, for example, 5.7 μm.

[0024] 2A , mesa 35 extends parallel to the X-axis, from a position overlapping waveguide 20 to a position overlapping slab portion 28. Mesa 35 is located on slab portion 28, slab portion 32, and protruding portion 33. Mesa 35 has portion 36 and portion 37. Portion 36 protrudes out of slab portion 32 in the X-axis direction and is located on protruding portion 33 and waveguide 20. Portion 37 is located on slab portion 32.

[0025] Portion 36 of mesa 35 has tapered portion 38 (third tapered portion). Tapered portion 38 is located on protrusion 33. The width of tapered portion 38 increases as it approaches slab portion 32 and decreases as it is farther from slab portion 32. The width of the tip of mesa 35 is, for example, 400 nm.

[0026] The protrusion 33 and the mesa 35 do not protrude outward from the waveguide 20 in plan view, but are located inside the waveguide 20. The waveguide 20 protrudes outward from below the protrusion 33 and the mesa 35 to the outside of the protrusion 33.

[0027] Tapered portion 31 of semiconductor element 30 protrudes from slab portion 32 in the X-axis direction, is located on both sides of mesa 35 in the Y-axis direction, and is located between slab portion 32 and tapered portion 38 of mesa 35 in the X-axis direction. The width of the portion of tapered portion 31 connected to slab portion 32 is, for example, 3 μm.

[0028] 3B to 5, the semiconductor element 30 has a cladding layer 40 (first semiconductor layer), an active layer 42, a cladding layer 44, and a contact layer 46 (these two layers are second semiconductor layers). As shown in FIGS. 3B to 4A, the protruding portion 33 of the semiconductor element 30 is formed of the cladding layer 40. As shown in FIG. 4A, the tapered portion 31 is formed of the active layer 42.

[0029] Mesa 35 includes an active layer 42, a cladding layer 44, and a contact layer 46. As shown in Figures 4A and 4B, portion 36 of mesa 35 includes active layer 42, cladding layer 44, and contact layer 46, and has a deep ridge structure. As shown in Figure 5, portion 37 of mesa 35 does not include active layer 42, but includes cladding layer 44 and contact layer 46, and has a shallow ridge structure. Width W of portion 37 of mesa 35 is, for example, not less than 1 µm and not more than 3 µm.

[0030] 5, the semiconductor device 30 has two dummy mesas 39. The two dummy mesas 39 are located on either side of the mesa 35 in the Y-axis direction and are spaced apart from the mesa 35. The dummy mesa 39 includes a cladding layer 44 and a contact layer 46. The height of the dummy mesa 39 is equal to the height of the mesa 35. The length of the dummy mesa 39 in the X-axis direction is equal to the length of the portion 37 of the mesa 35, for example.

[0031] As shown in FIG. 5 , the slab portion 32 includes a cladding layer 40 and an active layer 42. A slab portion 28 of the silicon layer 16 is provided below the slab portion 32. The slab portion 28 is provided at least directly below the mesa 35 and within a range of a distance D1 or more from both ends of the mesa 35 in the Y-axis direction. D1 may be, for example, 3 μm or 5 μm. In the example of FIG. 5 , the slab portion 32 is provided directly below the portion 37 of the mesa 35 in the Z-axis direction, between the mesa 35 and two dummy mesas 39, below the dummy mesas 39, and outside the dummy mesas 39. That is, the slab portion 32 extends from below the portion 37 of the mesa 35 to outside the two dummy mesas 39. The slab portion 28 may extend to the ends of the semiconductor optical device 100 in the Y-axis direction.

[0032] The cladding layer 40 is located between the active layer 42 and the silicon layer 16 of the substrate 10, and extends outward in the Y-axis direction beyond the active layer 42. The cladding layer 40 is in contact with the silicon layer 16. The slab portion 28 may extend from directly below the mesa 35 to the outside of the dummy mesa 39.

[0033] The insulating film 11 covers the substrate 10, the slab portion 32, the protruding portion 33, the mesa 35, and the dummy mesa 39. As shown in FIG. 5 , the insulating film 11 has an opening on the mesa 35. The electrode 48 is a p-type electrode, and is provided on the surface of the insulating film 11 and on the upper surface of the mesa 35. The electrode 48 contacts the surface of the contact layer 46 in the opening of the insulating film 11 and is electrically connected to the contact layer 46.

[0034] The electrode 48 extends from the top surface of the mesa 35 to one of the dummy mesas 39, covers the top and side surfaces of the dummy mesa 39, and extends to the outside of the slab portion 32. An insulating film 11 is provided between the electrode 48 and the dummy mesa 39 and slab portion 32. The electrode 48 is electrically connected to the contact layer 46 of the mesa 35, but is not connected to the contact layer 46 of the dummy mesa 39 or the cladding layer 40.

[0035] The insulating film 11 also has openings at positions spaced apart from the mesa 35 and the dummy mesa 39. The electrode 49 is an n-type electrode, and is electrically connected to the cladding layer 40 through the openings. The electrode 49 is located on the slab portion 32 and the slab portion 28.

[0036] The cladding layer 40 is formed of, for example, n-type (first conductivity type) indium phosphide (n-InP). The thickness of the cladding layer 40 is, for example, 400 nm. The active layer 42 has a multiple quantum well (MQW) structure and includes barrier layers and well layers. Multiple barrier layers and multiple well layers are alternately stacked. The barrier layers and well layers are formed of, for example, i-type gallium indium arsenide phosphide (GaInAsP). The thickness of the active layer 42 is, for example, 200 nm. Guide layers may be provided between the active layer 42 and the cladding layer 40 and between the active layer 42 and the cladding layer 44. The cladding layer 44 is formed of, for example, p-type (second conductivity type) indium phosphide (p-InP). The thickness of the cladding layer 44 is, for example, 2 μm. The contact layer 46 is formed of, for example, p-type gallium indium arsenide (p-GaInAs). The semiconductor layers of the semiconductor element 30 may be formed of III-V compound semiconductors other than those mentioned above.

[0037] The electrodes 48 and 49 are made of metal. The electrode 48 is made of, for example, a laminate of titanium (Ti), platinum (Pt), and gold (Au) stacked from the side closest to the mesa 35. The electrode 49 is made of, for example, an alloy of gold, germanium, and nickel (AuGeNi).

[0038] Transition structure 102 has the same configuration as transition structure 101. Slab portion 28 of silicon layer 16 and slab portion 32 of semiconductor device 30 extend from transition structure 101 to transition structure 102.

[0039] A voltage is applied to the semiconductor element 30 using electrodes 48 and 49, and carriers are injected into the active layer 42. The active layer 42 has optical gain and generates light through carrier injection. The wavelength of the light is, for example, 1.55 μm. The semiconductor element 30 and the substrate 10 are evanescently optically coupled. Light generated in the semiconductor element 30 is transferred to the waveguide 20 through the transition structures 101 and 102. The light resonates in the ring resonator 103 and is reflected by the loop mirror 104. The reflected light propagates toward the semiconductor element 30 and is transferred from the waveguide 20 to the semiconductor element 30 through the transition structures 101 and 102. The light is repeatedly reflected, resulting in laser oscillation.

[0040] The diameter of one of the two ring resonators 103 is different from the diameter of the other. The oscillation wavelength is determined by the Vernier effect of the two ring resonators 103. The transmittance of one of the two loop mirrors 104 is higher than that of the other. Part of the laser light passes through the loop mirror 104 and is emitted to the outside of the semiconductor optical device 100.

[0041] In Figures 3A to 5, the shape of light is schematically illustrated by a closed dashed curve. The mode of light is determined by the waveguide 20 and the mesa 35. As shown in Figure 3A, light is concentrated in the waveguide 20 before the tapered portion 21. In the transition structure 101, the light transfers from the waveguide 20 to the semiconductor element 30. Because the protruding portion 33 and the mesa 35 of the semiconductor element 30 have tapered shapes, the light transfers gradually, and the mode of the light is converted gradually. As shown in Figure 5, the silicon layer 16 has a slab portion 28. The mesa 35 is located on top of the slab portion 28. Light is confined near the mesa 35 of the semiconductor element 30 and does not easily spread. While the light propagates through the semiconductor element 30, the converted mode of the light is maintained. This reduces optical loss.

[0042] When a voltage is applied to the semiconductor device 30, a current flows between the electrode 48 and the electrode 49. The current flows through the contact layer 46, the cladding layer 44, the active layer 42, and the cladding layer 40 of the semiconductor device 30. The current flow generates heat. As shown in FIG. 5, a slab portion 28 of the silicon layer 16 is provided below the electrode 48 and the electrode 49. In other words, in the portion below the current path, the silicon layer 16 does not have a cavity such as a groove, and the slab portion 28 is provided. The thermal resistance of silicon is lower than that of air. The presence of the slab portion 28 improves heat dissipation. The silicon layer 16 functions as a heat dissipation path. Heat generated when the semiconductor optical device 100 is operated is dissipated from the silicon layer 16. Deterioration of characteristics due to temperature rise is suppressed.

[0043] FIG. 6 is a diagram illustrating optical output. The horizontal axis represents the current flowing through the semiconductor element 30. The vertical axis represents the optical output emitted from the semiconductor optical element. The solid line represents the measurement results of the optical output in the first embodiment. The dotted line represents the measurement results in the comparative example. In the comparative example, the waveguide and recess in the silicon layer 16 extend from outside the semiconductor element 30 to below the semiconductor element 30. The width of the waveguide is 1 μm. The wavelength of the light is 1.55 μm.

[0044] As shown in Fig. 6, the optical output increases as the current increases. When the current is 100 mA or more, the optical output of the first embodiment is higher than the optical output of the comparative example when compared at the same current.

[0045] In the comparative example, a recess in the silicon layer 16 is also provided below the semiconductor element 30. The recess is filled with air. The recess has poor heat dissipation properties, making it difficult for heat generated by the semiconductor element 30 to be released. This causes the temperature to easily rise, resulting in deterioration of characteristics. As shown in Figure 5, the light output is difficult to increase.

[0046] In the first embodiment, no recess is provided under the semiconductor element 30, and a slab portion 28 is provided. Because of its high heat dissipation properties, heat is easily released and the temperature does not easily rise. This suppresses deterioration of characteristics due to temperature rise. Since the amount of heat generated increases with increasing current, high heat dissipation properties are required. As shown in Figure 5, the difference in optical output between the first embodiment and the comparative example increases with increasing current. The optical output of the first embodiment is approximately 1.3 times that of the comparative example.

[0047] (Manufacturing method) 7 to 9 are cross-sectional views illustrating a method for manufacturing the semiconductor optical device 100, and show cross sections at positions corresponding to FIG.

[0048] 7, the silicon layer 16 of the substrate 10 is subjected to, for example, dry etching. The portions exposed by the mask (not shown) are etched to form recesses 24. The portions covered by the mask (not shown) are not etched. A waveguide 20, a terrace 27, and a slab portion 28 are formed.

[0049] A contact layer 46, a cladding layer 44, an active layer 42, and a cladding layer 40 are epitaxially grown in this order on an InP substrate separate from the SOI substrate (substrate 10) by metal organic chemical vapor deposition (MOCVD) or the like. This InP substrate is then diced to form a semiconductor element 30. Immediately after dicing, the semiconductor element 30 is a rectangular parallelepiped, and does not have a slab portion 32, a protrusion 33, or a mesa 35.

[0050] As shown in FIG. 7, a semiconductor element 30 is bonded to the upper surface of the substrate 10. One surface of the silicon layer 16 and the surface of the cladding layer 40 of the semiconductor element 30 are irradiated with plasma to activate these surfaces. The surface of the cladding layer 40 is brought into contact with the surface of the silicon layer 16, and the semiconductor element 30 is bonded to the silicon layer 16. The semiconductor element 30 covers the upper surface of the silicon layer 16, for example, and is located on the waveguide 20, recess 24, terrace 27, and slab portion 28. After bonding, wet etching is performed to remove the InP substrate. The semiconductor layers from the contact layer 46 to the cladding layer 40 remain.

[0051] As shown in FIG. 8 , a mesa 35 and a dummy mesa 39 are formed in the semiconductor device 30. The mesa 35 and the dummy mesa 39 are located above the slab portion 28. Specifically, a mask (not shown) is provided on the upper surface of the contact layer 46. The contact layer 46 and the cladding layer 44 are etched in the areas not covered by the mask. The mesa 35 and the dummy mesa 39 are formed in the areas covered by the mask. For example, the contact layer 46 and the cladding layer 44 may be removed by wet etching using a hydrochloric acid-based etchant. Dry etching may be performed partially on the contact layer 46 and the cladding layer 44, and the remaining portions may be wet-etched. The active layer 42 and the cladding layer 40 remain in the etched areas and are located below the mesa 35 and the dummy mesa 39, forming the slab portion 32.

[0052] 9, the active layer 42 and the cladding layer 40 are etched. A part of the cladding layer 40 is exposed from the active layer 42. The protrusions 33 shown in FIG. 2B and the like are also formed.

[0053] An insulating film 11 is formed by plasma CVD (PECVD, Plasma Enhanced Chemical Vapor Deposition) or the like, as shown in FIGS. 3A to 5. An opening is formed in the insulating film 11 above the mesa 35, and an opening is also formed above the cladding layer 40. An electrode 48 and an electrode 49 are formed in the openings by vacuum deposition or the like. Through the above steps, the semiconductor optical device 100 is formed.

[0054] According to the first embodiment, the silicon layer 16 of the substrate 10 has a waveguide 20, a recess 24, and a slab portion 28. Since the semiconductor element 30 is bonded to the slab portion 28, heat dissipation is high. Heat generated in the semiconductor element 30 is dissipated through the slab portion 28. By suppressing temperature rise, deterioration of the characteristics of the semiconductor optical element 100 is suppressed. For example, as shown in FIG. 6, high optical output can be obtained.

[0055] The mesa 35 of the semiconductor device 30 is located on the slab portion 28. Light is distributed near the mesa 35, and the mode shape is controlled by the mesa 35. The optical mode is distributed across the lower part of the mesa 35, the slab portion 32, and the slab portion 28. The slab portion 28 is provided directly below the mesa 35 and at a distance D1 or more from the end of the mesa 35. The distance D1 is 3 μm or more. By setting the distance D1 to 3 μm or more, the mode of the light entering from the waveguide 20 is stably maintained near the mesa 35. The mesa 35, the slab portion 32, and the slab portion 28 can propagate, for example, single-mode light. Optical loss can be suppressed.

[0056] The semiconductor element 30 is bonded to the slab portion 28. The contact area between the semiconductor element 30 and the silicon layer 16 is increased compared to when the semiconductor element 30 is bonded onto the recess 24, resulting in higher bonding strength. The mechanical strength of the semiconductor optical element 100 is improved. The etchant used in wet etching is blocked by the slab portion 28. Etching of the semiconductor element 30 from the bonding interface side is suppressed. Damage to the semiconductor element 30 can be suppressed.

[0057] When a voltage is applied, a current flows through the mesa 35, generating heat. The slab portion 28 of the silicon layer 16 is provided at least directly below the mesa 35 and over a range of at least a distance D1 from the edge of the mesa 35. The distance D1 is, for example, at least 1 μm, at least 3 μm, or at least 5 μm. The slab portion 28 may be provided over a range wider than the width of the slab portion 32 in the Y-axis direction. The slab portion 28 functions as a heat dissipation path, dissipating heat generated in the mesa 35. This improves heat dissipation. The heat spreads in the X and Y directions within the slab portion 28 and the slab portion 32. In a plan view, a small recess may be provided in a portion of the slab portion 28 below the slab portion 32, provided it does not interrupt the heat dissipation path. Interrupting the heat dissipation path means that, in a plan view, the recess penetrates the slab portion 28 located below the slab portion 32. Even if a small recess that does not interrupt the heat dissipation path is provided, it is preferable that the small recess not be provided directly below the mesa 35 or within a distance D1 (for example, D1 is 3 μm) from the end of the mesa 35. This can suppress light loss.

[0058] As shown in FIG. 5, the slab portion 28 may extend from under the mesa 35 to the outside of the electrode 49. A current flows between the electrodes 48 and 49 provided on the mesa 35. Heat is generated along the current path. The slab portion 28 is provided at a position overlapping the current path. This improves heat dissipation and allows the heat to be dissipated effectively.

[0059] No resin or the like is provided between the semiconductor element 30 and the silicon layer 16, and the semiconductor element 30 is in contact with the silicon layer 16. This makes it easier for heat to be transferred from the semiconductor element 30 to the silicon layer 16, improving heat dissipation.

[0060] 1 and 5, the recess 24 is not provided at a position overlapping the semiconductor element 30, and the slab portion 28 is located therein. This improves heat dissipation. The slab portion 28 contacts the entire underside of the semiconductor element 30. This increases the contact area between the semiconductor element 30 and the silicon layer 16, resulting in higher bonding strength.

[0061] The semiconductor element 30 has a slab portion 32. The slab portion 32 of the semiconductor element 30 is bonded to the slab portion 28 of the silicon layer 16. Bonding the slab portions together increases the contact area, improving heat dissipation and bonding strength. The mesa 35 is located on the slab portion 32. The mesa 35 can control the optical mode, and can suppress optical loss.

[0062] The semiconductor device 30 has a cladding layer 40, an active layer 42, a cladding layer 44, and a contact layer 46. The slab portion 32 includes the cladding layer 40 and the active layer 42. The portion 37 of the mesa 35 includes the cladding layer 44 and the contact layer 46. The n-type cladding layer 40, the i-type active layer 42, the p-type cladding layer 44, and the contact layer 46 are stacked to form a pin (positive-intrinsic-negative) junction in the mesa 35. Carriers can be injected into the active layer 42 to generate light. Heat is generated when a current flows through the mesa 35. Because the slab portion 28 is located below the mesa 35, heat dissipation is high and temperature increases can be suppressed.

[0063] The semiconductor element 30 has a protrusion 33. The protrusion 33 is located on the waveguide 20. This increases the coupling efficiency between the semiconductor element 30 and the substrate 10, allowing for a gradual transition of light. A portion 37 of the mesa 35 is located on the slab portion 32 and includes a cladding layer 44 and a contact layer 46. Light is confined near the mesa 35, thereby suppressing light loss.

[0064] As shown in FIG. 2A, the waveguide 20 protrudes outside the protrusion 33 and the mesa 35. The protrusion 33 and the mesa 35 do not protrude, but are located inside the waveguide 20. This can suppress etching of the semiconductor element 30 from the bonding interface. The mesa 35 is located inside the protrusion 33. The protrusion 33 and the mesa 35 can be easily manufactured by etching. After the mesa 35 is formed, the protrusion 33 can be formed below the mesa 35.

[0065] The waveguide 20 has a tapered portion 21. The protruding portion 33 has a tapered portion 34. The mesa 35 has a tapered portion 38. The tapered portion 34 of the protruding portion 33 is joined to the tapered portion 21 of the waveguide 20. The tapered portion 38 of the mesa 35 is located on top of the tapered portion 34 of the protruding portion 33. The multi-step tapered structure can improve the coupling efficiency between the semiconductor element 30 and the substrate 10.

[0066] The two dummy mesas 39 are located on both sides of the mesa 35. This can prevent stress from concentrating on the mesa 35 during the manufacturing process, etc. This improves the mechanical strength and prevents breakage.

[0067] The insulating film 11 covers the silicon layer 16 of the substrate 10 and the semiconductor element 30. The insulating film 11 functions as a cladding layer, and therefore can suppress light loss.

[0068] 1 is a wavelength tunable laser element, but the semiconductor optical element 100 may be an optical device other than the wavelength tunable laser element.

[0069] Second Embodiment Fig. 10 is a cross-sectional view illustrating a semiconductor optical device 200 according to the second embodiment, showing the same position as in Fig. 5. Description of the same configuration as in the first embodiment will be omitted.

[0070] 10, the semiconductor element 30 of the semiconductor optical element 200 does not have a dummy mesa, but has a mesa 35. The slab portion 32 extends from below the mesa 35 to the outside of the mesa 35. The insulating film 11 covers the side surface of the mesa 35 and the top and side surfaces of the slab portion 32. The electrode 48 is provided on the top surface of the mesa 35 and extends to the top surfaces of the slab portion 32 and 28.

[0071] According to the second embodiment, the semiconductor element 30 is bonded to the slab portion 28, resulting in high heat dissipation. Heat generated in the semiconductor element 30 passes through the slab portion 28 and is released. Suppressing temperature rise suppresses deterioration of characteristics. The mesa 35 of the semiconductor element 30 is located on the slab portion 28. Light is distributed near the mesa 35, and the mode shape is controlled by the mesa 35. Light loss can be suppressed.

[0072] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0073] 10, 12 board 11. Insulating film 14 Box Layer 16 Silicon Layer 20 Waveguide 21, 31, 34, 38 Tapered section 24 recess 36, 37 parts 27 Terrace 28, 32 Slab section 30 Semiconductor elements 33 Protrusion 35 Mesa 39 Dummy Mesa 40, 44 Cladding layer 42 Active layer 46 Contact layer 48, 49 electrode 100, 200 Semiconductor optical element 101, 102 transition structure 103 Ring resonator 104 Loop Mirror

Claims

1. a substrate having a silicon layer; a semiconductor element formed of a III-V compound semiconductor, having optical gain, and having a mesa; the silicon layer has a waveguide, a recess, and a first slab portion; the recesses are recessed portions lower than the surfaces of the waveguide and the first slab portion, and are provided on both sides of the waveguide; the first slab portion is connected to the waveguide; the semiconductor element is bonded to the first slab portion; The mesa is a semiconductor optical device located on the first slab portion.

2. 2. The semiconductor optical device according to claim 1, wherein the first slab portion extends from directly below the mesa and within a range of 3 [mu]m or more from an end of the mesa.

3. the semiconductor device has a second slab portion; the second slab portion is joined to the first slab portion; 3. The semiconductor optical device according to claim 1, wherein the mesa is located on the second slab portion.

4. the semiconductor device has a first semiconductor layer, an active layer, and a second semiconductor layer; the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in this order from the side closest to the substrate; the first semiconductor layer has a first conductivity type; the second semiconductor layer has a second conductivity type; the mesa includes the second semiconductor layer; 4. The semiconductor optical device according to claim 3, wherein the second slab portion includes the first semiconductor layer and the active layer.

5. a first electrode spaced from the mesa and electrically connected to the first semiconductor layer; a second electrode provided on the mesa and electrically connected to the second semiconductor layer; 5. The semiconductor optical device according to claim 4, wherein the first slab portion extends from under the mesa to under the second electrode.

6. the semiconductor element has a protrusion, The semiconductor optical device according to claim 3 , wherein the protrusion protrudes from the second slab portion onto the waveguide.

7. the semiconductor element has a dummy mesa; 3. The semiconductor optical device according to claim 1, wherein the two dummy mesas are located on both sides of the mesa.

8. 3. The semiconductor optical device according to claim 1, wherein the semiconductor element is in contact with the silicon layer.

9. bonding a semiconductor element formed of a III-V compound semiconductor and having optical gain to the silicon layer of the substrate; forming a mesa in the bonded semiconductor element; the silicon layer has a waveguide, a recess, and a slab; the recesses are recessed portions lower than the surfaces of the waveguide and the slab portion, and are provided on both sides of the waveguide; the slab portion is connected to the waveguide; In the bonding step, the semiconductor element is bonded to the slab portion, The mesa is located on the slab portion.

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