Semiconductor device, method of designing semiconductor device and method of manufacturing semiconductor device

Abstract

To provide a semiconductor device that can suppress occurrence of an insulation breakdown.SOLUTION: A semiconductor device A1 comprises: a conduction support; a first semiconductor element 11; a second semiconductor element 12; and a sealing resin 5. The conduction support includes a first lead 31 and a second lead 32 that are arranged apart from each other in a first direction x. The first semiconductor element 11 includes a first function unit 115 and is supported by the first lead 31. The second semiconductor element 12 includes a second function unit 125 and is supported by the second lead 32. Each of the first function unit 115 and the second function unit 125 transmits an electric signal in an insulated state. A distance d1 between the first lead 31 and the second lead 32 in the first direction x is larger than a predetermined distance d0.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a method for designing a semiconductor device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor devices are used in inverter devices used in electric vehicles, hybrid vehicles, home appliances, and the like. The inverter device includes, for example, a semiconductor device and a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device has a control element and a drive element. In the inverter device, a control signal output from an ECU (Engine Control Unit) is input to the control element of the semiconductor device. The control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits it to the drive element. The drive element drives, for example, six switching elements at desired timing based on the PWM control signal. As a result, three-phase AC power for driving a motor is generated from DC power from an on-board battery.

[0003] In the semiconductor device, the power supply voltage supplied to the control element may be low (approximately 5 V), while the power supply voltage supplied to the drive element may be high (approximately 600 V or higher). In this way, an isolation element is used as a means for transmitting signals between multiple elements with different power supply voltages. For example, Patent Document 1 discloses an example of a semiconductor device (intelligent power module) equipped with an isolation element. The intelligent power module described in Patent Document 1 includes a control circuit, an arm circuit (upper arm or lower arm), and an isolation transformer. The control circuit is composed of a CPU or logic IC, or a system LSI equipped with a logic IC and a CPU. The arm circuit is equipped with a gate driver IC. The isolation transformer transmits signals between the control circuit and the arm circuit in an isolated state. The CPU of the control circuit generates gate drive PWM signals that instruct the switching elements to be conductive or non-conductive, and transmits these gate drive PWM signals to the gate driver IC of the arm circuit via the isolation transformer. The gate driver IC then generates gate signals based on the gate drive PWM signals and drives the control terminals of the switching elements, thereby causing the switching elements to perform switching operations. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-49035

[0005] [overview] A plurality of elements with different power supply voltages may be mounted in a single package, resulting in a mixture of relatively high-voltage and low-voltage components within the same package. Such semiconductor devices are susceptible to dielectric breakdown. For example, dielectric breakdown tends to occur more easily as the potential difference between the power supply voltages increases. Dielectric breakdown can cause semiconductor devices to fail and reduce their reliability.

[0006] The present disclosure has been made in view of the above circumstances, and has an object to provide a semiconductor device capable of suppressing the occurrence of dielectric breakdown, a method for designing a semiconductor device capable of suppressing the occurrence of dielectric breakdown, and a method for manufacturing the semiconductor device.

[0007] A semiconductor device provided by a first aspect of the present disclosure comprises a conductive support including a first lead and a second lead arranged apart from each other in a first direction perpendicular to the thickness direction, a first semiconductor element including a first functional portion and supported by the first lead, a second semiconductor element including a second functional portion and supported by the second lead, and a sealing resin covering a portion of the conductive support, the first semiconductor element, and the second semiconductor element, wherein each of the first functional portion and the second functional portion transmits an electrical signal in an electrically isolated state, and a distance d1 in the first direction between the first lead and the second lead is greater than a distance d0 determined by equation (1).

number

[0008] A second aspect of the present disclosure provides a method for designing a semiconductor device comprising: a conductive support including a first lead and a second lead arranged apart from each other in a first direction; a first semiconductor element including a first functional portion and supported by the first lead; a second semiconductor element including a second functional portion and supported by the second lead; and a sealing resin covering a portion of the conductive support, the first semiconductor element, and the second semiconductor element, wherein each of the first functional portion and the second functional portion transmits an electrical signal in an insulated state, the method comprising a design step including a first design process for designing so that a distance d1 between the first lead and the second lead in the first direction is greater than a distance d0 determined by equation (2).

number

[0009] A method for manufacturing a semiconductor device provided by a third aspect of the present disclosure includes the method for designing a semiconductor device provided by the second aspect. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of FIG. 1, in which the sealing resin is shown by imaginary lines. [Figure 3] FIG. 3 is a front view showing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a left side view showing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a right side view showing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a main part of FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view of a main part showing the internal structure of each of the first semiconductor element and the second semiconductor element of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 12] FIG. 12 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 13] FIG. 13 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 14] FIG. 14 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 15] FIG. 15 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view showing one step of the manufacturing method shown in FIG. [Figure 17] FIG. 17 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 18] FIG. 18 is a cross-sectional view showing a semiconductor device according to a first modified example of the first embodiment, and corresponds to the cross section of FIG. [Figure 19] FIG. 19 is a cross-sectional view showing a semiconductor device according to a second modification of the first embodiment, and corresponds to the cross section of FIG. [Figure 20] FIG. 20 is a plan view showing the semiconductor device according to the second embodiment, in which the sealing resin is indicated by imaginary lines. [Figure 21] 21 is an enlarged cross-sectional view of a main part taken along line XXI-XXI in FIG. 20, and corresponds to the cross section of FIG. [Figure 22] FIG. 22 is a plan view showing the semiconductor device according to the third embodiment, in which the sealing resin is indicated by imaginary lines. [Figure 23] 23 is an enlarged cross-sectional view of a main part taken along line XXIII-XXIII in FIG. 22, and corresponds to the cross section of FIG.

[0011] [Detailed explanation] Preferred embodiments of the semiconductor device, semiconductor device design method, and semiconductor device manufacturing method of the present disclosure will be described below with reference to the drawings. In the following, identical or similar components will be assigned the same reference numerals and redundant description will be omitted.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "object A overlaps object B when viewed from a certain direction" includes "object A overlaps the entirety of object B" and "object A overlaps part of object B." Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is primarily made of material C." Furthermore, unless otherwise specified, "a certain surface A faces in direction B (one side or the other)" does not necessarily mean that surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted relative to direction B. Furthermore, unless otherwise specified, "a certain surface A is perpendicular to surface B" does not necessarily mean that surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted relative to surface B.

[0013] 1 to 9 show a semiconductor device A1 according to a first embodiment. As shown in these figures, the semiconductor device A1 includes a first semiconductor element 11, a second semiconductor element 12, a third semiconductor element 13, a fourth semiconductor element 14, a conductive support 3, a plurality of connection members 4, and a sealing resin 5. The conductive support 3 has a first lead 31, a second lead 32, a plurality of third leads 33, and a plurality of fourth leads 34, and the plurality of connection members 4 include a plurality of first wires 41, a plurality of second wires 42, a plurality of third wires 43, a plurality of fourth wires 44, a plurality of fifth wires 45, a sixth wire 46, and a seventh wire 47.

[0014] In this disclosure, the following description will be made with reference to the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of each of the first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, the fourth semiconductor element 14, the conductive support 3, and the sealing resin 5. One side of the thickness direction z may be referred to as the upper side, and the other side as the lower side. Note that terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. In the following description, "planar view" refers to a view along the thickness direction z.

[0015] The semiconductor device A1 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The semiconductor device A1 controls the switching operation of a switching element such as an IGBT or a MOSFET. As can be seen from Fig. 1 and Figs. 3 to 5, the package format of the semiconductor device A1 is an SOP (Small Outline Package). However, the package format of the semiconductor device A1 is not limited to an SOP.

[0016] The first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14 are elements that form the functional core of the semiconductor device A1. The first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14 are each composed of individual elements. In the first direction x, the first semiconductor element 11 and the second semiconductor element 12 are located between the third semiconductor element 13 and the fourth semiconductor element 14. In the first direction x, the first semiconductor element 11 is located between the second semiconductor element 12 and the third semiconductor element 13, and the second semiconductor element 12 is located between the first semiconductor element 11 and the fourth semiconductor element 14. In a plan view, each of the first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14 has a rectangular shape with its longer side extending in the second direction y. The shapes of the first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14 in plan view are not limited to the example shown in the drawing.

[0017] The third semiconductor element 13 is a controller (control element) of a gate driver that drives switching elements such as IGBTs, MOSFETs, etc. The third semiconductor element 13 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the first semiconductor element 11, and a reception circuit that receives an electrical signal from the first semiconductor element 11.

[0018] 6, the third semiconductor element 13 has a main surface 13a and a back surface 13b. The main surface 13a and the back surface 13b are spaced apart in the thickness direction z. The main surface 13a is the top surface of the third semiconductor element 13, and the back surface 13b is the bottom surface of the third semiconductor element 13. The back surface 13b faces the first lead 31.

[0019] 2 and 6, the third semiconductor element 13 has a plurality of pads 131. The plurality of pads 131 are provided on the main surface 13a (the surface facing the same direction as the first mounting surface 311a of the first island portion 311 of the first lead 31, which will be described later). Each of the plurality of pads 131 contains, for example, aluminum (Al).

[0020] The fourth semiconductor element 14 is a gate driver (drive element) for driving the switching element. The fourth semiconductor element 14 has a receiving circuit for receiving a PWM control signal, a circuit for driving the switching element based on the PWM control signal, and a transmitting circuit for transmitting an electrical signal to the third semiconductor element 13. The electrical signal may be, for example, an output signal from a temperature sensor arranged near the motor.

[0021] 6, the fourth semiconductor element 14 has a main surface 14a and a back surface 14b. The main surface 14a and the back surface 14b are spaced apart in the thickness direction z. The main surface 14a is the top surface of the fourth semiconductor element 14, and the back surface 14b is the bottom surface of the fourth semiconductor element 14. The back surface 14b faces the second lead 32.

[0022] 2 and 6, the fourth semiconductor element 14 has a plurality of pads 141. The plurality of pads 141 are provided on the main surface 14a (the surface facing the same direction as the second mounting surface 321a of the second island portion 321 of the second lead 32, which will be described later). Each of the plurality of pads 141 contains, for example, aluminum.

[0023] The first semiconductor element 11 and the second semiconductor element 12 are elements (insulating elements) for transmitting PWM control signals and other electrical signals in an insulated state. The first semiconductor element 11 and the second semiconductor element 12 are each of an inductive type. An example of the inductive first semiconductor element 11 and the second semiconductor element 12 is an insulating transformer. The first semiconductor element 11 and the second semiconductor element 12 may each be of a capacitive type. An example of the capacitive first semiconductor element 11 and the second semiconductor element 12 is a capacitor. Alternatively, the first semiconductor element 11 and the second semiconductor element 12 may each be a photocoupler.

[0024] 6 to 9, the first semiconductor element 11 has a main surface 11a and a back surface 11b. The main surface 11a and the back surface 11b are spaced apart in the thickness direction z. The main surface 11a is the top surface of the first semiconductor element 11, and the back surface 11b is the bottom surface of the first semiconductor element 11. The back surface 11b faces the first lead 31.

[0025] The first semiconductor element 11 includes a first functional unit 115. The first functional unit 115 has multiple sets of first upper windings 115a and first lower windings 115b inside, with a first upper winding 115a and a first lower winding 115b as one set. That is, the first semiconductor element 11 has multiple first upper windings 115a and multiple first lower windings 115b. FIGS. 7 and 9 show one set of the multiple sets of first upper windings 115a and first lower windings 115b. For example, the multiple sets of first upper windings 115a and first lower windings 115b are arranged along the longitudinal direction (second direction y) of the first semiconductor element 11. The set of first upper windings 115a and first lower windings 115b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, each set of the first upper winding 115a and the first lower winding 115b is planarly wound in a spiral shape. The first upper winding 115a and the first lower winding 115b are magnetically coupled to each other. The third semiconductor element 13 inductively couples the first upper winding 115a and the first lower winding 115b in each set, thereby transmitting electrical signals in an insulated state.

[0026] As shown in FIGS. 2, 6, and 7, the first semiconductor element 11 has a plurality of pads 111 and 112. The pads 111 and 112 are each provided on the main surface 13a. As shown in FIG. 7, each pad 111 is electrically connected to one of the plurality of first lower windings 115b, and each pad 112 is electrically connected to one of the plurality of first upper windings 115a. The pads 111 and 112 each contain, for example, aluminum. As shown in FIGS. 2, 6, and 7, each of the plurality of pads 111 is bonded to one of the plurality of second wires 42, and each of the plurality of pads 112 is bonded to one of the plurality of first wires 41. As shown in FIGS. 2 and 7, the first semiconductor element 11 also includes a seal ring portion 113. The seal ring portion 113 is formed along each of the four outer peripheries of the first semiconductor element 11 in a plan view, and surrounds the outer periphery of the circuit formation region. The seal ring portion 113 is made of, for example, copper (Cu), aluminum (Al), or the like.

[0027] As shown in FIGS. 7 and 9, the first semiconductor element 11 has a semiconductor substrate 110, a stacked structure 117, and a wiring portion 118.

[0028] The semiconductor substrate 110 may be a Si (silicon) substrate, a SiC (silicon carbide) substrate, or the like. The first semiconductor element 11 may use an insulating substrate such as a ceramic substrate or a resin substrate instead of the semiconductor substrate 110. The seal ring portion 113 is provided upright on the semiconductor substrate 110 and penetrates the stacked structure 117 in the thickness direction z. In this embodiment, the potential of the seal ring portion 113 is approximately the same as the potential of the semiconductor substrate 110.

[0029] The stacked structure 117 is formed on the semiconductor substrate 110. As shown in FIG. 9, the stacked structure 117 includes a plurality of insulating layers 1171. The insulating layers 1171 are stacked on the upper surface of the semiconductor substrate 110. Except for the lowest insulating layer 1171 in contact with the upper surface of the semiconductor substrate 110, each insulating layer 1171 is formed of a stacked structure including an etching stopper film below and an interlayer insulating film above. The lowest insulating layer 1171 is formed only of an interlayer insulating layer. The etching stopper film may be, for example, a silicon nitride (SiN) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film. The interlayer insulating film may be, for example, a silicon oxide (SiO) film. The dimension of the insulating layers 1171 in the thickness direction z is not particularly limited, but may be, for example, 2.4 μm. The thicknesses of the insulating layers 1171 may be the same or different.

[0030] The first upper winding 115a and the first lower winding 115b are formed on different insulating layers 1171 in the laminated structure 117, and face each other with at least one insulating layer 1171 sandwiched between them. In the illustrated example, the first lower winding 115b is formed on the fourth insulating layer 1171 from the semiconductor substrate 110, and the first upper winding 115a is formed on the eleventh insulating layer 1171, with six insulating layers 1171 sandwiched between it and the first lower winding 115b. The number of insulating layers 1171 is not limited to the illustrated example, and can be changed as appropriate depending on, for example, the magnitude of the voltage applied to each pad 111 and each pad 112. The greater the number of insulating layers 1171 between the first upper winding 115a and the first lower winding 115b, the greater the breakdown voltage of the first semiconductor element 11, but the greater the thickness (dimension in the thickness direction z) of the first semiconductor element 11. On the other hand, the fewer the number of insulating layers 1171 between the first upper winding 115a and the first lower winding 115b, the smaller the breakdown voltage of the first semiconductor element 11, but the smaller the thickness (dimension in the thickness direction z) of the first semiconductor element 11. In this embodiment, in view of the relationship between the breakdown voltage of the first semiconductor element 11 and the thickness (of the first semiconductor element 11) (suppression of an increase in the thickness), it is preferable that the number of stacked insulating layers 1171 between the first upper winding 115a and the first lower winding 115b be four or more and six or less. Furthermore, the dimension in the thickness direction z of the multiple insulating layers 1171 between the first upper winding 115a and the first lower winding 115b (i.e., the separation distance along the thickness direction z between the first upper winding 115a and the first lower winding 115b) is not limited in any way, but is, for example, 9.6 μm to 14.4 μm. This example dimension (9.6 μm to 14.4 μm) corresponds to, for example, a case where the dimension in the thickness direction z of each insulating layer 1171 between the first upper winding 115a and the first lower winding 115b is 2.4 μm and the number of laminated insulating layers 1171 between the first upper winding 115a and the first lower winding 115b is 4 to 6.

[0031] The wiring section 118 electrically connects the pads 111 and 112 to the first upper winding 115a and the first lower winding 115b. The wiring section 118 includes a plurality of through wires 1181 and lead-out wires 1182. As shown in FIG. 9, each of the through wires 1181 penetrates one or more insulating layers 1171 in the thickness direction z. In the example shown in FIG. 9, the plurality of through wires 1181 includes one that connects the pad 111 to the lead-out wire 1182, one that connects the lead-out wire 1182 to the first lower winding 115b, and one that connects the pad 112 to the first upper winding 115a. The lead-out wire 1182 is formed on the lowest insulating layer 1171. The lead-out wire 1182 forms part of the conduction path between the pad 111 and the first lower winding 115b.

[0032] The structure of the first semiconductor element 11 is not limited to the above example. For example, the first semiconductor element 11 may also include a protective film (e.g., a SiO film) and a passivation film (e.g., a SiN film) laminated on the main surface 11a while exposing the pads 111 and 112, a coil protective film selectively covering the region directly above the first upper winding 115a, and the like, but these are not shown in the figure. Furthermore, the first upper winding 115a and the first lower winding 115b are not limited to being planarly wound on a single insulating layer 1171, but may be wound three-dimensionally across multiple insulating layers 1171. However, in order to prevent an increase in the thickness of the first semiconductor element 11, it is preferable that the first upper winding 115a and the first lower winding 115b be planarly wound on a single insulating layer 1171.

[0033] 6, 7, and 9, the second semiconductor element 12 has a main surface 12a and a back surface 12b. The main surface 12a and the back surface 12b are spaced apart in the thickness direction z. The main surface 12a is the top surface of the second semiconductor element 12, and the back surface 12b is the bottom surface of the second semiconductor element 12. The back surface 12b faces the second lead 32.

[0034] The second semiconductor element 12 includes a second functional unit 125. The second functional unit 125 includes a plurality of sets of second upper windings 125a and second lower windings 125b therein, each set consisting of a second upper winding 125a and a second lower winding 125b. That is, the second semiconductor element 12 includes a plurality of second upper windings 125a and a plurality of second lower windings 125b. In FIGS. 7 and 9, the plurality of sets of second upper windings 125a and second lower windings 125b are arranged along the longitudinal direction (second direction y) of the second semiconductor element 12. The set of second upper windings 125a and second lower windings 125b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, the set of second upper windings 125a and second lower windings 125b are each planarly wound in a spiral shape. The second upper winding 125a and the second lower winding 125b of each pair are magnetically coupled. The second semiconductor element 12 inductively couples the second upper winding 125a and the second lower winding 125b of each pair, thereby transmitting electrical signals in an insulated state.

[0035] As shown in FIGS. 2, 6, and 7, the second semiconductor element 12 has a plurality of pads 121 and 122. Each of the pads 121 and 122 is provided on the main surface 12a. As shown in FIG. 7, each pad 121 is electrically connected to one of the plurality of second lower windings 125b, and each pad 122 is electrically connected to one of the plurality of second upper windings 125a. Each of the pads 121 and 122 contains, for example, aluminum. As shown in FIGS. 2, 6, and 7, each of the plurality of pads 121 is bonded to one of the plurality of third wires 43, and each of the plurality of pads 122 is bonded to one of the plurality of first wires 41. Furthermore, as shown in FIGS. 2 and 7, the second semiconductor element 12 includes a seal ring portion 123. The seal ring portion 123 is formed along each of the four outer peripheries of the second semiconductor element 12 in a plan view, and surrounds the outer periphery of the circuit formation region. The seal ring portion 123 is made of, for example, copper (Cu), aluminum (Al), or the like.

[0036] As shown in FIGS. 7 and 9, the second semiconductor element 12 has a semiconductor substrate 120, a stacked structure 127, and a wiring portion 128.

[0037] The semiconductor substrate 120 may be a Si substrate, a SiC substrate, or the like. The second semiconductor element 12 may use an insulating substrate such as a ceramic substrate or a resin substrate instead of the semiconductor substrate 120. The seal ring portion 123 is provided upright on the semiconductor substrate 120 and penetrates the stacked structure 127 in the thickness direction z. In this embodiment, the potential of the seal ring portion 123 is approximately the same as the potential of the semiconductor substrate 120.

[0038] The stacked structure 127 is formed on the semiconductor substrate 120. As shown in FIG. 9 , the stacked structure 127 includes a plurality of insulating layers 1271. The insulating layers 1271 are stacked on the upper surface of the semiconductor substrate 120. Except for the lowest insulating layer 1271 in contact with the upper surface of the semiconductor substrate 120, each insulating layer 1271 is formed of a stacked structure including an etching stopper film below and an interlayer insulating film above. The lowest insulating layer 1271 is formed solely of an interlayer insulating layer. The etching stopper film may be, for example, a SiN film, a SiC film, or a SiCN film, and the interlayer insulating film may be, for example, a SiO2 film. The dimension of the insulating layers 1271 in the thickness direction z is not limited in any way, but may be, for example, 2.4 μm. The thicknesses of the insulating layers 1271 may be the same or different.

[0039] The second upper winding 125a and the second lower winding 125b are formed on different insulating layers 1271 in the laminated structure 127 and face each other with at least one insulating layer 1271 between them. In the illustrated example, the second lower winding 125b is formed on the fourth insulating layer 1271 from the semiconductor substrate 120, and the second upper winding 125a is formed on the eleventh insulating layer 1271, with six insulating layers 1271 between it and the second lower winding 125b. The number of insulating layers 1271 is not limited to the illustrated example and can be changed as appropriate depending on, for example, the magnitude of the voltage applied to each pad 121 and each pad 122. The greater the number of insulating layers 1271 between the second upper winding 125a and the second lower winding 125b, the greater the breakdown voltage of the second semiconductor element 12, but the greater the thickness (dimension in the thickness direction z) of the second semiconductor element 12. On the other hand, the fewer the number of insulating layers 1271 between the second upper winding 125a and the second lower winding 125b, the smaller the breakdown voltage of the second semiconductor element 12, but the smaller the thickness (dimension in the thickness direction z) of the second semiconductor element 12. In this embodiment, in view of the relationship between the breakdown voltage of the second semiconductor element 12 and the thickness (of the second semiconductor element 12) (suppression of an increase in the thickness), it is preferable that the number of stacked insulating layers 1271 between the second upper winding 125a and the second lower winding 125b be four or more and six or less. Furthermore, the dimension in the thickness direction z of the multiple insulating layers 1271 between the second upper winding 125a and the second lower winding 125b (i.e., the separation distance along the thickness direction z between the second upper winding 125a and the second lower winding 125b) is not limited in any way, but is, for example, 9.6 μm to 14.4 μm. This example dimension (9.6 μm to 14.4 μm) corresponds to, for example, a case where the dimension in the thickness direction z of each insulating layer 1271 between the second upper winding 125a and the second lower winding 125b is 2.4 μm and the number of laminated insulating layers 1271 between the second upper winding 125a and the second lower winding 125b is 4 to 6.

[0040] The wiring section 128 electrically connects the pads 121 and 122 to the second upper winding 125a and the second lower winding 125b. The wiring section 128 includes a plurality of through wires 1281 and lead-out wires 1282. As shown in FIG. 9, each of the through wires 1281 penetrates one or more insulating layers 1271 in the thickness direction z. In the example shown in FIG. 9, the plurality of through wires 1281 includes one that connects the pad 121 to the lead-out wire 1282, one that connects the lead-out wire 1282 to the second lower winding 125b, and one that connects the pad 122 to the second upper winding 125a. The lead-out wire 1282 is formed on the lowest insulating layer 1271. The lead-out wire 1282 forms part of the conduction path between the pad 121 and the second lower winding 125b.

[0041] The structure of the second semiconductor element 12 is not limited to the above example. For example, the second semiconductor element 12 may also include a protective film (e.g., a SiO film) and a passivation film (e.g., a SiN film) laminated on the main surface 12a while exposing the pads 121 and 122, a coil protective film selectively covering the region directly above the second upper winding 125a, and the like, but these are not shown. Furthermore, the second upper winding 125a and the second lower winding 125b are not limited to being planarly wound on a single insulating layer 1271, but may be wound three-dimensionally across multiple insulating layers 1271. However, in order to prevent an increase in the thickness of the second semiconductor element 12, it is preferable that the second upper winding 125a and the second lower winding 125b be planarly wound on a single insulating layer 1271.

[0042] In the semiconductor device A1, the fourth semiconductor element 14 requires a power supply voltage higher than that required for the third semiconductor element 13. This causes a potential difference between the third semiconductor element 13 and the fourth semiconductor element 14. Therefore, a first circuit including the third semiconductor element 13 as a component and a second circuit including the fourth semiconductor element 14 as a component are insulated from each other by the first semiconductor element 11 and the second semiconductor element 12. In addition to the third semiconductor element 13, the components of the first circuit include a first lead 31, a plurality of third leads 33, a plurality of second wires 42, a plurality of fourth wires 44, a sixth wire 46, and a portion of the first semiconductor element 11 (such as each pad 111 and each first lower winding 115b). In addition to the fourth semiconductor element 14, the components of the second circuit include the second lead 32, the multiple fourth leads 34, the multiple third wires 43, the multiple fifth wires 45 and seventh wires 47, and a portion of the second semiconductor element 12 (such as each pad 121 and each second lower winding 125b). The first circuit and the second circuit have relatively different potentials. In the semiconductor device A1, the potential of the second circuit is higher than the potential of the first circuit. Furthermore, the first semiconductor element 11 and the second semiconductor element 12 relay mutual signals between the first circuit and the second circuit. For example, in an inverter device for an electric vehicle or a hybrid vehicle, while the voltage applied to the ground of the third semiconductor element 13 is approximately 0 V, the voltage applied to the ground of the fourth semiconductor element 14 may transiently reach 600 V or higher. Depending on the specifications of the inverter device, the voltage applied to the ground of the fourth semiconductor element 14 may reach 3750 V or higher.

[0043] In the semiconductor device A1, the first circuit and the second circuit are electrically insulated by the first semiconductor element 11 and the second semiconductor element 12 (two insulating elements), thereby providing a third circuit whose potential is intermediate between the potentials of the first circuit and the second circuit. In other words, the semiconductor device A1 includes the third circuit in addition to the first circuit and the second circuit. In this embodiment, the third circuit includes a portion of the first semiconductor element 11 (such as the first upper windings 115a and the pads 112), a portion of the second semiconductor element 12 (such as the second upper windings 125a and the pads 122), and a plurality of first wires 41. In a configuration in which the potential of the second circuit is higher than the potential of the first circuit, the potential of the third circuit is higher than the potential of the first circuit and lower than the potential of the second circuit. In this embodiment, the first semiconductor element 11 and the second semiconductor element 12 are configured identically, and the voltage difference between the first circuit and the second circuit is equally shared to provide insulation. Therefore, the potential of the third circuit is half the potential difference between the first circuit and the second circuit. Unlike this example, the potential of the third circuit may be biased toward either the potential of the first circuit or the potential of the second circuit with respect to half the potential difference between the first circuit and the second circuit.

[0044] The conductive support 3 forms a conductive path between the first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14 and the wiring board on which the semiconductor device A1 is mounted. As will be described in detail later, the conductive support 3 is obtained, for example, from the same lead frame. The lead frame is made of, for example, copper or a copper alloy, but may be made of other metal materials. As described above, the conductive support 3 has a first lead 31, a second lead 32, a plurality of third leads 33, and a plurality of fourth leads 34.

[0045] 1 and 2, the first lead 31 and the second lead 32 are positioned apart from each other in the first direction x. In the semiconductor device A1, the first semiconductor element 11 and the third semiconductor element 13 are mounted on the first lead 31, and the second semiconductor element 12 and the fourth semiconductor element 14 are mounted on the second lead 32.

[0046] As shown in FIG. 2, the first lead 31 includes a first island portion 311 and two first terminal portions 312.

[0047] As shown in FIGS. 6 and 7 , the first island portion 311 has a first mounting surface 311a facing one side (upward) in the thickness direction z. As shown in FIG. 7 , the first semiconductor element 11 is bonded to the first mounting surface 311a via a conductive bonding material 119, and the third semiconductor element 13 is bonded to the first mounting surface 311a via a conductive bonding material 139. The semiconductor substrate 110 of the first semiconductor element 11 is at approximately the same potential as the first island portion 311 via the conductive bonding material 119. Each of the conductive bonding materials 119, 139 is, for example, solder, metal paste, or sintered metal. The first island portion 311 is covered with a sealing resin 5. In the illustrated example, the first island portion 311 has a rectangular shape in a plan view. The thickness of the first island portion 311 is, for example, 100 μm or more and 300 μm or less. Unlike the illustrated example, the first island portion 311 may have a through-hole penetrating in the thickness direction z. The through hole can be formed between the first semiconductor element 11 and the third semiconductor element 13, for example.

[0048] As shown in FIG. 2, the two first terminals 312 extend from both sides of the first island portion 311 in the second direction y. The two first terminals 312 are spaced apart from each other in the second direction y. At least one of the two first terminals 312 is electrically connected to the ground of the third semiconductor element 13 via a sixth wire 46. Each of the two first terminals 312 has a covered portion 312a and an exposed portion 312b. The covered portion 312a is connected to the first island portion 311 and is covered with the sealing resin 5. The exposed portion 312b is connected to the covered portion 312a and is exposed from the sealing resin 5. In a plan view, the exposed portion 312b extends along the first direction x. As shown in FIG. 3, the exposed portion 312b is bent in a gull-wing shape when viewed in the second direction y. The surface of the exposed portion 312b may be plated with, for example, tin (Sn).

[0049] As shown in FIG. 2, the second lead 32 has a second island portion 321 and two second terminal portions 322.

[0050] As shown in FIGS. 6 and 7 , the second island portion 321 has a second mounting surface 321a facing one side (upward) in the thickness direction z. As shown in FIG. 7 , the second semiconductor element 12 is bonded to the second mounting surface 321a via a conductive bonding material 129, and the fourth semiconductor element 14 is bonded to the second mounting surface 321a via a conductive bonding material 149. The semiconductor substrate 120 of the second semiconductor element 12 is at approximately the same potential as the second island portion 321 via the conductive bonding material 129. Each of the conductive bonding materials 129, 149 is, for example, solder, metal paste, or sintered metal. The second island portion 321 is covered with a sealing resin 5. In the illustrated example, the second island portion 321 has a rectangular shape in a plan view. The thickness of the second island portion 321 is, for example, 100 μm or more and 300 μm or less, similar to that of the first island portion 311. Unlike the illustrated example, the second island portion 321 may have a through-hole penetrating in the thickness direction z. The through hole can be formed between the second semiconductor element 12 and the fourth semiconductor element 14, for example.

[0051] As shown in FIG. 2, the two second terminals 322 extend from both sides of the second island portion 321 in the second direction y. The two second terminals 322 are spaced apart from each other in the second direction y. At least one of the two second terminals 322 is electrically connected to the ground of the fourth semiconductor element 14 via a seventh wire 47. Each of the two second terminals 322 has a covered portion 322a and an exposed portion 322b. The covered portion 322a is connected to the second island portion 321 and is covered with the sealing resin 5. The exposed portion 322b is connected to the covered portion 322a and is exposed from the sealing resin 5. In a plan view, the exposed portion 322b extends along the first direction x. As shown in FIG. 3, the exposed portion 322b is bent in a gull-wing shape when viewed in the second direction y. The surface of the exposed portion 322b may be, for example, tin-plated.

[0052] As shown in FIGS. 1 and 2 , the multiple third leads 33 are located on the opposite side of the first island portion 311 of the first lead 31 from the second island portion 321 of the second lead 32 in the first direction x. The multiple third leads 33 are arranged along the second direction y. At least one of the multiple third leads 33 is electrically connected to the third semiconductor element 13 via a fourth wire 44. The multiple third leads 33 include multiple (four in the illustrated example) intermediate leads 33A and two side leads 33B. The two side leads 33B are located on either side of the multiple intermediate leads 33A in the second direction y. Each of the two side leads 33B is located between one of the two first terminal portions 312 of the first lead 31 and the intermediate lead 33A located closest to that first terminal portion 312 in the second direction y.

[0053] As shown in FIGS. 2 and 6, each of the third leads 33 (the intermediate leads 33A and the two side leads 33B) has a covering portion 331 and an exposed portion 332. The covering portion 331 is covered with the sealing resin 5. In the illustrated example, the dimension of each of the covering portions 331 of the two side leads 33B in the first direction x is larger than the dimension of each of the covering portions 331 of the intermediate leads 33A in the first direction x. As shown in FIGS. 2 and 6, the exposed portion 332 is connected to the covering portion 331 and exposed from the sealing resin 5. In a plan view, the exposed portion 332 extends along the first direction x. As can be seen from FIGS. 2 to 4, the exposed portion 332 is bent in a gull-wing shape when viewed along the second direction y. The shape of the exposed portion 332 is the same as the shape of the exposed portion 312b of each first terminal portion 312 of the first lead 31. The surface of the exposed portion 332 may be plated with tin, for example.

[0054] The shape, arrangement, and number of the multiple third leads 33 are not limited to the example shown in the figure. For example, the number of the multiple third leads 33 may be more or less than the example shown (six). Also, for example, some of the multiple third leads 33 may be arranged outward from either of the two first terminal portions 312 of the first lead 31.

[0055] As shown in FIGS. 1 and 2 , the multiple fourth leads 34 are located on the opposite side of the multiple third leads 33 with respect to the first island portion 311 of the first lead 31 in the first direction x. The multiple fourth leads 34 are arranged along the second direction y. At least one of the multiple fourth leads 34 is electrically connected to the fourth semiconductor element 14 via a fifth wire 45. The multiple fourth leads 34 include multiple (four in the illustrated example) intermediate leads 34A and two side leads 34B. The two side leads 34B are located on either side of the multiple intermediate leads 34A in the second direction y. Each of the two side leads 34B is located between one of the two second terminal portions 322 of the second lead 32 and the intermediate lead 34A located closest to that second terminal portion 322 in the second direction y.

[0056] As shown in FIGS. 2 and 6, each of the multiple fourth leads 34 (the multiple intermediate leads 34A and the two side leads 34B) has a covering portion 341 and an exposed portion 342. The covering portion 341 is covered with the sealing resin 5. In the illustrated example, the dimension of each of the covering portions 341 of the two side leads 34B in the first direction x is larger than the dimension of each of the covering portions 341 of the multiple intermediate leads 34A in the first direction x. As shown in FIGS. 2 and 6, the exposed portion 342 is connected to the covering portion 341 and exposed from the sealing resin 5. In a plan view, the exposed portion 342 extends along the first direction x. As can be seen from FIGS. 2, 3, and 5, the exposed portion 342 is bent in a gull-wing shape when viewed along the second direction y. The shape of the exposed portion 342 is equal to the shape of each of the exposed portions 322b of the two second terminal portions 322 of the second lead 32. The surface of the exposed portion 342 may be, for example, tin-plated.

[0057] The shape, arrangement, and number of the multiple fourth leads 34 are not limited to the example shown in the figure. For example, the multiple fourth leads 34 may be more or less than the example shown (six). Also, for example, some of the multiple fourth leads 34 may be arranged outward from either of the two second terminal portions 322 of the second lead 32.

[0058] Each of the plurality of connection members 4 provides electrical continuity between two separate portions. As described above, the plurality of connection members 4 includes the plurality of first wires 41, the plurality of second wires 42, the plurality of third wires 43, the plurality of fourth wires 44, the plurality of fifth wires 45, the sixth wire 46, and the seventh wire 47.

[0059] The first wires 41, the second wires 42, the third wires 43, the fourth wires 44, the fifth wires 45, the sixth wires 46, and the seventh wires 47 are each made of a metal material, and the metal material includes, for example, gold, copper, or aluminum. The connection members 4 may be bonding ribbons or plate-shaped metal members instead of the first wires 41, the second wires 42, the third wires 43, the fourth wires 44, the fifth wires 45, the sixth wires 46, and the seventh wires 47.

[0060] As shown in FIGS. 2 and 7 , each of the multiple first wires 41 is bonded to one of the multiple pads 112 of the first semiconductor element 11 and one of the multiple pads 122 of the second semiconductor element 12. Each first wire 41 electrically connects the first semiconductor element 11 and the second semiconductor element 12. The multiple first wires 41 are arranged along the second direction y. Each of the multiple first wires 41 straddles the first island portion 311 of the first lead 31 and the second island portion 321 of the second lead 32 in a plan view.

[0061] As shown in FIG. 7 , each of the multiple first wires 41 includes a neck portion 411, a joint portion 412, and a loop portion 413. In each first wire 41, the neck portion 411 is a portion that is joined to one of the multiple pads 112 and extends in the thickness direction z. The joint portion 412 is a portion that is joined to one of the multiple pads 122. The loop portion 413 is a portion that connects the neck portion 411 and the joint portion 412. The loop portion 413 extends from the neck portion 411 toward the joint portion 412 while curving. Each first wire 41 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 112 and second bonded to one of the multiple pads 122. However, instead of this example, each first wire 41 may be formed by other methods, such as wedge bonding. When each first wire 41 is formed by wedge bonding, a joint having substantially the same shape as the joint 412 is bonded to the pad 112 instead of the neck portion 411.

[0062] 2 and 7, each of the multiple second wires 42 is bonded to one of the multiple pads 111 of the first semiconductor element 11 and one of the multiple pads 131 of the third semiconductor element 13. Each second wire 42 electrically connects the first semiconductor element 11 and the third semiconductor element 13. The multiple second wires 42 are arranged along the second direction y.

[0063] As shown in FIG. 7 , each of the multiple second wires 42 includes a neck portion 421, a joint portion 422, and a loop portion 423. In each second wire 42, the neck portion 421 is a portion that is joined to one of the multiple pads 111 and extends in the thickness direction z. The joint portion 422 is a portion that is joined to one of the multiple pads 131. The loop portion 423 is a portion that connects the neck portion 421 and the joint portion 422. The loop portion 423 extends from the neck portion 421 toward the joint portion 422 while curving. Each second wire 42 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 111 and second bonded to one of the multiple pads 131. However, instead of this example, each second wire 42 may be formed by another method, such as wedge bonding. When each second wire 42 is formed by wedge bonding, a joint having substantially the same shape as the joint 422 is bonded to the pad 111 instead of the neck portion 421.

[0064] 2 and 7, each of the multiple third wires 43 is bonded to one of the multiple pads 121 of the second semiconductor element 12 and one of the multiple pads 141 of the fourth semiconductor element 14. Each third wire 43 electrically connects the second semiconductor element 12 and the fourth semiconductor element 14. The multiple third wires 43 are arranged along the second direction y.

[0065] As shown in FIG. 7 , each of the multiple third wires 43 includes a neck portion 431, a joint portion 432, and a loop portion 433. In each third wire 43, the neck portion 431 is a portion bonded to one of the multiple pads 121 and extends in the thickness direction z. The joint portion 432 is a portion bonded to one of the multiple pads 141. The loop portion 433 is a portion connecting the neck portion 431 and the joint portion 432. The loop portion 433 extends from the neck portion 431 toward the joint portion 432 while curving. Each third wire 43 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 121 and second bonded to one of the multiple pads 141. However, each third wire 43 may be formed by other methods, such as wedge bonding. When each third wire 43 is formed by wedge bonding, a joint having a shape substantially the same as that of the joint 432 is bonded to the pad 121 instead of the neck portion 431 .

[0066] 2, each of the multiple fourth wires 44 is joined to one of the multiple pads 131 of the third semiconductor element 13 and to the covering portion 331 of one of the multiple third leads 33. Each fourth wire 44 electrically connects the third semiconductor element 13 and one of the multiple third leads 33.

[0067] 2, each of the plurality of fifth wires 45 is joined to one of the plurality of pads 141 of the fourth semiconductor element 14 and to the covering portion 341 of one of the plurality of fourth leads 34. Each of the fifth wires 45 electrically connects the fourth semiconductor element 14 and one of the plurality of fourth leads 34.

[0068] 2, the sixth wire 46 is joined to one of the pads 131 of the third semiconductor element 13 and the covering portion 312a of one of the two first terminal portions 312. The sixth wire 46 electrically connects the third semiconductor element 13 and the first lead 31. The number of sixth wires 46 is not limited to one, and there may be more than one.

[0069] 2, the seventh wire 47 is joined to one of the pads 141 of the fourth semiconductor element 14 and the covering portion 322a of one of the two second terminal portions 322. The seventh wire 47 electrically connects the fourth semiconductor element 14 and the second lead 32. The number of seventh wires 47 is not limited to one, and there may be more than one.

[0070] As shown in FIG. 1 , the sealing resin 5 covers the first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14, a portion of the conductive support 3, and the plurality of connecting members 4. The sealing resin 5 has electrical insulating properties. The sealing resin 5 insulates the components of the first circuit (e.g., the first lead 31) from the components of the second circuit (e.g., the second lead 32) from each other. The sealing resin 5 is made of a material containing, for example, a black epoxy resin. In the illustrated example, the sealing resin 5 is rectangular in plan view.

[0071] As shown in FIGS. 2 to 5, the sealing resin 5 has a top surface 51, a bottom surface 52, a pair of first side surfaces 53, and a pair of second side surfaces .

[0072] 3 to 5, top surface 51 and bottom surface 52 are spaced apart from each other in thickness direction z. Top surface 51 and bottom surface 52 face in opposite directions in thickness direction z. Each of top surface 51 and bottom surface 52 is substantially flat.

[0073] 3 to 5, the pair of first side surfaces 53 are connected to the top surface 51 and the bottom surface 52 and are spaced apart from each other in the first direction x. Of the pair of first side surfaces 53, the first side surface 53 located on one side in the first direction x exposes the exposed portions 312b of the two first terminal portions 312 (first leads 31) and the exposed portions 332 of the plurality of third leads 33. Of the pair of first side surfaces 53, the first side surface 53 located on the other side in the first direction x exposes the exposed portions 322b of the two second terminal portions 322 (second leads 32) and the exposed portions 342 of the plurality of fourth leads 34.

[0074] As shown in FIGS. 3 to 5 , each of the pair of first side surfaces 53 includes a first upper portion 531, a first lower portion 532, and a first intermediate portion 533. One side of the first upper portion 531 in the thickness direction z is connected to the top surface 51, and the other side in the thickness direction z is connected to the first intermediate portion 533. The first upper portion 531 is inclined with respect to the top surface 51. One side of the first lower portion 532 in the thickness direction z is connected to the bottom surface 52, and the other side in the thickness direction z is connected to the first intermediate portion 533. The first lower portion 532 is inclined with respect to the bottom surface 52. One side of the first intermediate portion 533 in the thickness direction z is connected to the first upper portion 531, and the other side in the thickness direction z is connected to the first lower portion 532. The in-plane directions of the first intermediate portion 533 are the thickness direction z and the second direction y. In a plan view, the first intermediate portion 533 is located outward from the top surface 51 and the bottom surface 52. From the first intermediate portion 533 of the pair of first side surfaces 53, the exposed portions 312b of the two first terminal portions 312 (first leads 31), the exposed portions 322b of the two second terminal portions 322 (second leads 32), the exposed portions 332 of the plurality of third leads 33, and the exposed portions 342 of the plurality of fourth leads 34 are exposed.

[0075] 3 to 5, the pair of second side surfaces 54 are connected to the top surface 51 and the bottom surface 52 and are spaced apart from each other in the second direction y. As shown in FIG. 1, the first lead 31, the second lead 32, the plurality of third leads 33, and the plurality of fourth leads 34 are spaced apart from the pair of second side surfaces 54.

[0076] As shown in FIGS. 3 to 5 , each of the pair of second side surfaces 54 includes a second upper portion 541, a second lower portion 542, and a second intermediate portion 543. One side of the second upper portion 541 in the thickness direction z is connected to the top surface 51, and the other side in the thickness direction z is connected to the second intermediate portion 543. The second upper portion 541 is inclined with respect to the top surface 51. One side of the second lower portion 542 in the thickness direction z is connected to the bottom surface 52, and the other side in the thickness direction z is connected to the second intermediate portion 543. The second lower portion 542 is inclined with respect to the bottom surface 52. One side of the second intermediate portion 543 in the thickness direction z is connected to the second upper portion 541, and the other side in the thickness direction z is connected to the second lower portion 542. The in-plane directions of the second intermediate portion 543 are the thickness direction z and the second direction y. In a plan view, the second intermediate portion 543 is located outward from the top surface 51 and the bottom surface 52.

[0077] A motor driver circuit in an inverter device typically includes a half-bridge circuit including a low-side (low potential side) switching element and a high-side (high potential side) switching element. The following description focuses on the case where these switching elements are MOSFETs. Here, for the low-side switching element, the reference potentials of the source of the switching element and the gate driver driving the switching element are both ground. For the high-side switching element, the reference potentials of the source of the switching element and the gate driver driving the switching element are both equivalent to the potential at the output node of the half-bridge circuit. The potential at the output node changes depending on the driving of the high-side and low-side switching elements, so the reference potential of the gate driver driving the high-side switching element also changes. When the high-side switching element is on, the reference potential is equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). In the semiconductor device A1, the ground of the third semiconductor element 13 and the ground of the fourth semiconductor element 14 are separated. Therefore, when the semiconductor device A1 is used as a gate driver for driving a high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element is transiently applied to the ground of the fourth semiconductor element 14.

[0078] In the semiconductor device A1, any two of the components of the first circuit, the second circuit, and the third circuit are arranged so that the distance between them is greater than the distance d0 [mm] determined by the following formula (3): In formula (3), Y is the insulation life [years] required for the semiconductor device A1, A and B are constants determined by the material of the sealing resin 5, and X is the voltage (effective value) [kVrms] used in the semiconductor device A1. The voltage X is, for example, the voltage difference applied between the two target parts. In the semiconductor device A1, an AC voltage is generated by driving a switching element, and the effective value is used for the voltage X. In an example where the sealing resin 5 is epoxy resin, the constant A is 1000×4 16 and the constant B is 16. Also, 0.15 is an offset value for calculating the distance d0 [mm]. The offset value is used to match the dimension of the right side of the following equation (3) with the dimension of the left side (distance d0) of the following equation (3), and its unit is, for example, [mm] / (( B As can be seen from equation (3), the distance d0 increases as the voltage increases, as the insulation life increases, and also increases as the insulation life increases, and varies depending on the material of the sealing resin 5. For example, the distance d0 can be calculated by setting the insulation life Y to 20 years, the voltage X to 1 kVrms, and the constant A to 1000 x 4 kVrms of epoxy resin. 16 Then, from equation (3), the calculated value is approximately 0.0294 [mm] (= 29.4 [μm]).

number

[0079] Specifically, the distance d1 (see FIG. 7) between the first lead 31 and the second lead 32 in the first direction x is greater than the distance d0. In setting the distance d1, the voltage X is, for example, the difference between the voltage applied to the first circuit (first lead 31) and the voltage applied to the second circuit (second lead 32). In the example shown in FIG. 7, the distance d1 is the distance between the closest portions of the first island portion 311 and the second island portion 321. The distance d1 is, for example, 10 mm or less. This prevents the semiconductor device A1 from becoming larger. In the semiconductor device A1, the distance d1 is approximately 300 μm, which is greater than the distance d0 (≈29.4 μm) in the example above.

[0080] Furthermore, the distance d2 (see FIG. 7 ) between each first wire 41 and the first semiconductor element 11 is greater than the distance d0. In the example shown in FIG. 7 , the distance d2 is the distance in the thickness direction z between the loop portion 413 and the seal ring portion 113 of the first semiconductor element 11 at the closest position. In this embodiment, each first wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d2, the voltage X used is, for example, the difference between the voltage applied to the third circuit (each first wire 41) and the voltage applied to the first circuit (the seal ring portion 113 of the first semiconductor element 11). In other words, the voltage X used in setting the distance d2 may be smaller than the voltage X used in setting the distance d1. Unlike this example, the voltage X used in setting the distance d2 may be greater than the voltage difference between the third circuit and the first circuit. For example, the voltage X may be the same as the voltage X used in setting the distance d1. The distance d2 is, for example, 10 mm or less. This makes it possible to prevent the semiconductor device A1 from becoming large. In the semiconductor device A1, the distance d2 is about 170 μm, which is greater than the distance d0 (=29.4 μm) in the example given above.

[0081] Furthermore, the distance d2' (see FIG. 7) between each first wire 41 and the first lead 31 is greater than the distance d0. In the example shown in FIG. 7, the distance d2' is the distance in the thickness direction z between each loop portion 413 and the first mounting surface 311a of the first island portion 311 at the closest position. As with the setting of the distance d2, the voltage X used to set the distance d2' may be, for example, the difference between the voltage applied to the third circuit (each first wire 41) and the voltage applied to the first circuit (first lead 31). Unlike this example, the voltage X used to set the distance d2' may be greater than the voltage difference between the third circuit and the first circuit. For example, it may be the same as the voltage X used to set the distance d1. The distance d2' is, for example, 10 mm or less. This prevents the semiconductor device A1 from becoming larger. In the semiconductor device A1, the distance d2' is approximately 470 μm, which is greater than the distance d0 (= 29.4 μm) in the example above.

[0082] Furthermore, a distance d3 (see FIG. 7 ) between each first wire 41 and the second semiconductor element 12 is greater than the distance d0. In the example shown in FIG. 7 , the distance d3 is the distance in the thickness direction z between each loop portion 413 and the seal ring portion 123 of the second semiconductor element 12 at the closest position. In this embodiment, each first wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d3, the voltage X is, for example, the difference between the voltage applied to the third circuit (each first wire 41) and the voltage applied to the second circuit (the seal ring portion 123 of the second semiconductor element 12). In other words, the voltage X used to set the distance d3 may be smaller than the voltage X used to set the distance d1. Unlike this example, the voltage X used to set the distance d3 may be greater than the voltage difference between the third circuit and the second circuit. For example, the voltage X may be the same as the voltage X used to set the distance d1. The distance d3 is, for example, 10 mm or less. This makes it possible to prevent the semiconductor device A1 from becoming large. In the semiconductor device A1, the distance d3 is about 170 μm, which is greater than the distance d0 (=29.4 μm) in the example given above.

[0083] Furthermore, the distance d3' (see FIG. 7) between each first wire 41 and the second lead 32 is greater than the distance d0. In the example shown in FIG. 7, the distance d3' is the distance in the thickness direction z between each loop portion 413 and the second mounting surface 321a of the second island portion 321 at the closest position. As with the setting of the distance d3, the voltage X used to set the distance d3' may be, for example, the difference between the voltage applied to the third circuit (each first wire 41) and the voltage applied to the second circuit (second lead 32). Unlike this example, the voltage X used to set the distance d3' may be greater than the voltage difference between the third circuit and the second circuit. For example, it may be the same as the voltage X used to set the distance d1. The distance d3' is, for example, 10 mm or less. This prevents the semiconductor device A1 from becoming larger. In the semiconductor device A1, the distance d3' is approximately 470 μm, which is greater than the distance d0 (= 29.4 μm) in the example above.

[0084] Furthermore, the distance d4 (see FIG. 7 ) between each first wire 41 and each second wire 42 is greater than the distance d0. In the example shown in FIG. 7 , the distance d4 is the distance in a direction perpendicular to the thickness direction z (the first direction x in FIG. 7 ) between the portions where each neck portion 411 and each neck portion 421 are closest to each other. In this embodiment, each first wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d4, for example, the difference between the voltage applied to the third circuit (each first wire 41) and the voltage applied to the first circuit (each second wire 42) is used as the voltage X. In other words, the voltage X used in setting the distance d4 may be smaller than the voltage X used in setting the distance d1. Unlike this example, the voltage X used in setting the distance d4 may be greater than the voltage difference between the third circuit and the first circuit. For example, the voltage X used in setting the distance d1 may be the same as the voltage X used in setting the distance d1. In the semiconductor device A1, the distance d4 is about 300 μm, which is greater than the distance d0 (=29.4 μm) in the example given above.

[0085] Furthermore, a distance d5 (see FIG. 7 ) between each first wire 41 and each third wire 43 is greater than the distance d0. In the example shown in FIG. 7 , the distance d5 is the distance in a direction perpendicular to the thickness direction z (the first direction x in FIG. 7 ) between the portions where each joint 412 and each neck portion 431 are closest to each other. In this embodiment, each first wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d5, for example, the difference between the voltage applied to the third circuit (each first wire 41) and the voltage applied to the second circuit (each third wire 43) is used as the voltage X. In other words, the voltage X used in setting the distance d5 may be smaller than the voltage X used in setting the distance d1. Unlike this example, the voltage X used in setting the distance d5 may be greater than the voltage difference between the third circuit and the second circuit. For example, the voltage X used in setting the distance d1 may be the same as the voltage X used in setting the distance d1. In the semiconductor device A1, the distance d5 is about 300 μm, which is greater than the distance d0 (=29.4 μm) in the example above.

[0086] Next, an example of a method for manufacturing the semiconductor device A1 will be described with reference to Figs. 10 to 17. Fig. 10 is a flowchart showing an example of the method for manufacturing the semiconductor device A1. Figs. 11 to 15 and Fig. 17 are plan views showing one step of the method for manufacturing the semiconductor device A1. Fig. 16 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device A1. The cross section of Fig. 16 is at the same cross-sectional position as Fig. 7.

[0087] 10, the manufacturing method of the semiconductor device A1 according to this embodiment includes a lead frame preparation step S11, a lead frame processing step S12, an element mounting step S13, a wire bonding step S14, a sealing step S15, and a singulation step S16. The manufacturing method of the semiconductor device A1 also includes a design method having a design step. The design step includes a first design process S101, a second design process S102, a third design process S103, a fourth design process S104, and a fifth design process S105, which will be described in detail later.

[0088] First, in the lead frame preparation step S11, a lead frame 81 shown in FIG. 11 is prepared. As shown in FIG. 11, the lead frame 81 includes a flat plate portion 810, a plurality of support leads 811b, 812b, a plurality of leads 813, 814, an outer frame 815, and a dam bar 816. The lead frame 81 is formed, for example, by stamping a copper plate having a rectangular shape in a plan view. As shown in FIG. 11, the plurality of support leads 811b, 812b are each connected to the flat plate portion 810. The plurality of support leads 811b, 812b and the plurality of leads 813, 814 are also connected by the outer frame 815 and the dam bar 816. Note that, of the lead frame 81, the outer frame 815 and the dam bar 816 do not constitute the semiconductor device A1.

[0089] Next, in the lead frame processing step S12, the flat plate portion 810 of the lead frame 81 is divided into a first island 811a and a second island 812a (see FIG. 13). In this embodiment, the flat plate portion 810 is divided into the first island 811a and the second island 812a in the lead frame processing step S12. In the lead frame processing step S12, first, a resist 82 is formed on the lead frame 81 as shown in FIG. 12. In FIG. 11, dots are drawn on the resist 82. Then, an etching process is performed on the lead frame 81 on which the resist 82 is formed. As a result, the portions of the lead frame 81 exposed from the resist 82 are removed, and as shown in FIG. 13, the flat plate portion 810 is divided into the first island 811a and the second island 812a. Thereafter, the resist 82 is removed to form the lead frame 81 shown in FIG. 13. 13, a plurality of support leads 811b are each connected to a first island 811a, forming a first lead 811 including the first island 811a and the plurality of support leads 811b. Also, in the lead frame 81 shown in FIG. 13, a plurality of support leads 812b are each connected to a second island 812a, forming a second lead 812 including the second island 812a and the plurality of support leads 812b.

[0090] In this embodiment, as shown in FIG. 10, a first design process S101 is performed in the lead frame processing step S12.

[0091] In the first design process S101, when dividing the flat plate portion 810 into the first island 811a and the second island 812a, the distance d1 (see FIGS. 12, 13, and 16) between the first island 811a (first lead 811) and the second island 812a (second lead 812) in the first direction x is designed to be larger than the distance d0. The distance d0 is determined by the above formula (3). As will be understood from the configuration described in detail later, the first island 811a (first lead 811) becomes the first island portion 311 (first lead 31), and the second island 812a (second lead 812) becomes the second island portion 321 (second lead 32). Therefore, in the process of designing the distance d1 in the first design process S101, the distance d1 between the first lead 31 and the second lead 32 in the first direction x is designed to be larger than the distance d0. In the first design process S101, it is preferable to design the distance d1 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the size of the semiconductor device A1 to be manufactured from increasing.

[0092] 14, the first semiconductor element 11, the second semiconductor element 12, the third semiconductor element 13, and the fourth semiconductor element 14 are each mounted on the lead frame 81. Specifically, the first semiconductor element 11 and the third semiconductor element 13 are each bonded to the first island 811a by a conductive bonding material (not shown), and the second semiconductor element 12 and the fourth semiconductor element 14 are bonded to the second island 812a by a conductive bonding material (not shown).

[0093] 15 and 16, in the wire bonding step S14, a plurality of first wires 41, a plurality of second wires 42, a plurality of third wires 43, a plurality of fourth wires 44, a plurality of fifth wires 45, a sixth wire 46, and a seventh wire 47 are formed. A well-known wire bonder may be used to form the wires 41 to 47. The order in which the wires 41 to 47 are formed is not particularly limited.

[0094] In this embodiment, as shown in FIG. 10, in the wire bonding step S14, a second design process S102, a third design process S103, a fourth design process S104, and a fifth design process S105 are performed.

[0095] In the second design process S102, when forming each first wire 41, the distance d2 between each first wire 41 and the first semiconductor element 11 in the thickness direction z is designed to be greater than the distance d0. Furthermore, the distance d2' between each first wire 41 and the first lead 811 in the thickness direction z is designed to be greater than the distance d0. For example, each first wire 41 is wire-bonded so that the loop portion 413 of each first wire 41 is spaced apart from the seal ring portion 113 of the first semiconductor element 11 by a distance greater than d0 and is also spaced apart from the first island 811a by a distance greater than d0. As will be understood from the configuration described in detail later, the first lead 811 becomes the first lead 31. Therefore, in the process of designing the distance d2' in the second design process S102, the distance d2' between each first wire 41 and the first lead 31 in the thickness direction z is designed to be greater than the distance d0. In the second design process S102, it is preferable to design the distance d2 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A1 from becoming larger in size. Also, in the second design process S102, it is preferable to design the distance d2' to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A1 from becoming larger in size.

[0096] In the third design process S103, when forming each first wire 41, the distance d3 between each first wire 41 and the second semiconductor element 12 in the thickness direction z is designed to be greater than the distance d0. Furthermore, the distance d3' between each first wire 41 and the second lead 812 in the thickness direction z is designed to be greater than the distance d0. For example, each first wire 41 is wire-bonded so that the loop portion 413 of each first wire 41 is spaced apart from the seal ring portion 123 of the second semiconductor element 12 by a distance greater than d0 and is also spaced apart from the second island 812a by a distance greater than d0. As will be understood from the configuration described in detail later, the second lead 812 becomes the second lead 32. Therefore, in the process of designing the distance d3' in the third design process S103, the distance d3' between each first wire 41 and the second lead 32 in the thickness direction z is designed to be greater than the distance d0. In the third design process S103, it is preferable to design the distance d2 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A1 from becoming larger in size. Also, in the third design process S103, it is preferable to design the distance d3' to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A1 from becoming larger in size.

[0097] In the fourth design process S104, when forming each first wire 41 and each second wire 42, the distance d4 between each first wire 41 and each second wire 42 is designed to be greater than the distance d0. For example, when each first wire 41 is wire-bonded before each second wire 42, each second wire 42 is wire-bonded such that the neck portion 421 of each second wire 42 is spaced apart from the neck portion 411 of each first wire 41 by more than the distance d0. Conversely, when each second wire 42 is wire-bonded before each first wire 41, each first wire 41 is wire-bonded such that the neck portion 411 of each first wire 41 is spaced apart from the neck portion 421 of each second wire 42 by more than the distance d0. In the fourth design process S104, it is preferable to design the distance d4 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A1 from becoming larger in size.

[0098] In the fifth design process S105, when forming each of the first wires 41 and each of the third wires 43, the distance d5 between each of the first wires 41 and each of the third wires 43 is designed to be greater than the distance d0. For example, when each of the first wires 41 is wire-bonded before each of the third wires 43, each of the third wires 43 is wire-bonded so that the neck portion 431 of each of the third wires 43 is spaced apart from the joint portion 412 of each of the first wires 41 by the distance d0. Conversely, when each of the third wires 43 is wire-bonded before each of the first wires 41, each of the first wires 41 is wire-bonded so that the joint portion 412 of each of the first wires 41 is spaced apart from the neck portion 421 of each of the second wires 42 by the distance d0. In the fifth design process S105, it is preferable to design the distance d5 to be greater than the distance d0 and, for example, 10 mm or less, in order to prevent the semiconductor device A1 from becoming larger in size.

[0099] Next, in the sealing step S15, sealing resin 5 is formed as shown in Fig. 17. In Fig. 17, sealing resin 5 is shown by an imaginary line (two-dot chain line). The sealing resin 5 is formed by transfer molding. The formed sealing resin 5 is made of, for example, epoxy resin.

[0100] Thereafter, in the singulation step S16, dicing is performed to singulate the substrate. As a result, the first lead 811, the second lead 812, and the plurality of leads 813 and 814, which have been connected to each other by the outer frame 815 and the dam bar 816, are appropriately separated. A first lead 31 is formed from the separated first lead 811. Here, the first island 811a becomes the first island portion 311, and each support lead 811b becomes each first terminal portion 312. Furthermore, a second lead 32 is formed from the separated second lead 812. Here, the second island 812a becomes the second island portion 321, and each support lead 812b becomes each second terminal portion 322. Furthermore, a plurality of third leads 33 are formed from the separated plurality of leads 813, and a plurality of fourth leads 34 are formed from the separated plurality of leads 814. The bending process of each of the plurality of third leads 33 (plurality of leads 813) and the plurality of fourth leads 34 (plurality of leads 814) may be performed in the singulation process S16, or may be performed during the punching process in the lead frame preparation process S11.

[0101] The semiconductor device A1 is manufactured through the steps described above. The manufacturing method of the semiconductor device A1 is not limited to the above example. For example, the first island 811a and the second island 812a may be formed by punching in the lead frame preparation step S11, thereby eliminating the need for the lead frame processing step S12. In this case, the first design process S101 is performed in the lead frame preparation step S11. However, the first island 811a and the second island 812a can be formed more accurately by etching in the lead frame processing step S12 than by punching in the lead frame preparation step S11, and the distance d1 can be made greater than the distance d0. In another manufacturing method, for example, in the lead frame preparation step S11, a copper plate having a rectangular shape in plan view is prepared, and in the lead frame processing step S12, a first lead 811 (first island 811a and multiple support leads 811b), a second lead 812 (second island 812a and multiple support leads 812b), multiple leads 813, 814, an outer frame 815, and a dam bar 816 may be formed all at once from the prepared copper plate by forming a resist 82 and etching the same.

[0102] The functions and effects of the semiconductor device A1, the method for designing the semiconductor device A1, and the method for manufacturing the semiconductor device A1 are as follows.

[0103] In the semiconductor device A1, the distance d1 between the first lead 31 and the second lead 32 in the first direction x is greater than the distance d0 determined by the above formula (3). As described above, the distance d0 is calculated using the insulation life Y of the semiconductor device A1, the voltage X used in the semiconductor device A1, and a constant A determined by the material of the sealing resin 5. Research by the present inventors has revealed that the above formula (3) makes it possible to design a dielectric strength voltage that satisfies actual usage conditions. Therefore, by making the distance d1 greater than the distance d0, the semiconductor device A1 can be designed to have a dielectric strength voltage that satisfies actual usage conditions between the first lead 31 and the second lead 32. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength voltage between the first lead 31 and the second lead 32, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the first design process S101 is performed to design the distance d1 to be greater than the distance d0. This enables the design and manufacture of a semiconductor device A1 that suppresses the occurrence of dielectric breakdown.

[0104] In the semiconductor device A1, the third semiconductor element 13 and the fourth semiconductor element 14 are electrically insulated by the first semiconductor element 11 and the second semiconductor element 12. In contrast to this configuration, in a configuration in which the third semiconductor element 13 and the fourth semiconductor element 14 are electrically isolated by a single semiconductor element (insulating element), a voltage difference between the first circuit and the second circuit occurs within the single insulating element. In contrast, in the semiconductor device A1, the voltage difference between the first circuit and the second circuit is shared by two insulating elements (the first semiconductor element 11 and the second semiconductor element 12). Therefore, the voltage difference occurring in each of the first semiconductor element 11 and the second semiconductor element 12 can be reduced. Therefore, the semiconductor device A1 can more effectively improve the dielectric strength voltage between the first lead 31 (the first island portion 311) and the first semiconductor element 11 compared to a configuration in which electrical isolation is achieved by a single insulating element. Furthermore, the dielectric strength between the second lead 32 (second island portion 321) and the second semiconductor element 12 can be improved more effectively.

[0105] Furthermore, since the voltage difference generated in the first semiconductor element 11 can be reduced, the number of insulating layers 1171 between the first upper winding 115a and the first lower winding 115b can be reduced. This allows the thickness (dimension in the thickness direction z) of the first semiconductor element 11 to be reduced, thereby enabling a thinner semiconductor device A1. Similarly, since the voltage difference generated in the second semiconductor element 12 can be reduced, the number of insulating layers 1271 between the second upper winding 125a and the second lower winding 125b can be reduced. This allows the thickness (dimension in the thickness direction z) of the second semiconductor element 12 to be reduced, thereby enabling a thinner semiconductor device A1. In other words, compared to a configuration in which electrical insulation is achieved with a single insulating element, the semiconductor device A1 can be made thinner while maintaining the same dielectric strength. Furthermore, when the thickness of the semiconductor device A1 is limited due to product specifications or the like, the semiconductor device A1 can improve the dielectric strength within the thickness limit of the semiconductor device A1 compared to a configuration in which electrical insulation is achieved with a single insulating element. This is because the first circuit and the second circuit can be insulated from each other by the multiple insulating layers 1171 between the first upper winding 115a and the first lower winding 115b of the first semiconductor element 11 and the multiple insulating layers 1271 between the second upper winding 125a and the second lower winding 125b of the second semiconductor element 12. In other words, when the first circuit and the second circuit are insulated from each other by the first semiconductor element 11 and the second semiconductor element 12, the number of insulating layers between the first circuit and the second circuit can be made larger than when a single insulating element is used for insulation.

[0106] In the semiconductor device A1, the distance d2 between each first wire 41 and the first semiconductor element 11 is greater than the distance d0 determined by the above formula (3). In this embodiment, the distance d2 is the distance in the thickness direction z between the loop portion 413 of each first wire 41 and the seal ring portion 113 of the first semiconductor element 11. As described above, each first wire 41 has an intermediate potential between the first circuit and the second circuit. Meanwhile, since the first semiconductor element 11 is joined to the first island portion 311 (first lead 31), the seal ring portion 113 can have the same potential as the first island portion 311. In other words, each first wire 41 has a relatively high voltage and the seal ring portion 113 has a relatively low voltage, so a potential difference occurs between each first wire 41 and the seal ring portion 113. In the semiconductor device A1, since the distance d2 is greater than the distance d0, it is possible to design a dielectric strength voltage between each first wire 41 and the seal ring portion 113 that satisfies actual use conditions. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength between each first wire 41 and the first semiconductor element 11, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the second design process S102 is performed to design the distance d2 to be greater than the distance d0. This makes it possible to design a semiconductor device A1 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A1.

[0107] In the semiconductor device A1, the distance d2' between each first wire 41 and the first lead 31 is greater than the distance d0 determined by the above formula (3). In this embodiment, the distance d2' is the distance in the thickness direction z between the loop portion 413 of each first wire 41 and the first mounting surface 311a of the first island portion 311 (first lead 31). The first wire 41 is electrically connected to the first upper winding 115a of the first semiconductor element 11 (first functional portion 115), and is therefore a component of the third circuit. On the other hand, the first lead 31 is a component of the first circuit. In other words, the first wire 41 has a relatively high voltage and the first lead 31 has a relatively low voltage, and therefore a potential difference occurs between the first wire 41 and the first lead 31. In the semiconductor device A1, the distance d2' is greater than the distance d0, and therefore it is possible to design a dielectric strength voltage between the first wire 41 and the first lead 31 that satisfies actual use conditions. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength voltage between the first wire 41 and the first lead 31, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the second design process S102 is performed so that the distance d2' is greater than the distance d0. This makes it possible to design a semiconductor device A1 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A1.

[0108] In the semiconductor device A1, the distance d3 between each first wire 41 and the second semiconductor element 12 is greater than the distance d0 determined by the above formula (3). In this embodiment, the distance d3 is the distance in the thickness direction z between the loop portion 413 of each first wire 41 and the seal ring portion 123 of the second semiconductor element 12. As described above, each first wire 41 has an intermediate potential between the first circuit and the second circuit. On the other hand, since the second semiconductor element 12 is joined to the second island portion 321 (second lead 32), the seal ring portion 123 can have the same potential as the second island portion 321. In other words, each first wire 41 has a relatively low voltage and the seal ring portion 123 has a relatively high voltage, so a potential difference occurs between each first wire 41 and the seal ring portion 123. In the semiconductor device A1, the distance d3 is greater than the distance d0, so it is possible to design a dielectric strength voltage between each first wire 41 and the seal ring portion 123 that satisfies actual use conditions. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength between each first wire 41 and the second semiconductor element 12, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the third design process S103 is performed to design the distance d3 to be greater than the distance d0. This makes it possible to design a semiconductor device A1 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A1.

[0109] In the semiconductor device A1, the distance d3' between each first wire 41 and the second lead 32 is greater than the distance d0 determined by the above formula (3). In this embodiment, the distance d3' is the distance in the thickness direction z between the loop portion 413 of each first wire 41 and the second mounting surface 321a of the second island portion 321 (second lead 32). The first wire 41 is electrically connected to the second upper winding 125a of the second semiconductor element 12 (second functional portion 125), and is therefore a component of the third circuit. On the other hand, the second lead 32 is a component of the second circuit. In other words, the first wire 41 has a relatively low voltage and the second lead 32 has a relatively high voltage, and therefore a potential difference occurs between the first wire 41 and the second lead 32. In the semiconductor device A1, the distance d3' is greater than the distance d0, and therefore it is possible to design a dielectric strength voltage between the first wire 41 and the second lead 32 that satisfies actual use conditions. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength voltage between the first wire 41 and the second lead 32, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the third design process S103 is performed so that the distance d3' is greater than the distance d0. This makes it possible to design a semiconductor device A1 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A1.

[0110] In the semiconductor device A1, the distance d4 between each first wire 41 and each second wire 42 is greater than the distance d0 determined by the above formula (3). In this embodiment, the distance d4 is the distance between the neck portion 411 of each first wire 41 and the neck portion 421 of each second wire 42 in a direction perpendicular to the thickness direction z. The first wire 41 is electrically connected to the first upper winding 115a of the first semiconductor element 11 (first functional unit 115), and is therefore a component of the third circuit. On the other hand, the second wire 42 is electrically connected to the first lower winding 115b of the first semiconductor element 11 (first functional unit 115), and is therefore a component of the first circuit. In other words, the first wire 41 has a relatively high voltage and the second wire 42 has a relatively low voltage, and therefore a potential difference occurs between the first wire 41 and the second wire 42. In the semiconductor device A1, because the distance d4 is greater than the distance d0, it is possible to design a dielectric strength voltage between the first wire 41 and the second wire 42 that satisfies actual use conditions. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength voltage between the first wire 41 and the second wire 42, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the fourth design process S104 is performed to design the distance d4 to be greater than the distance d0. This makes it possible to design a semiconductor device A1 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A1.

[0111] In the semiconductor device A1, the distance d5 between each first wire 41 and each third wire 43 is greater than the distance d0 determined by the above formula (3). In this embodiment, the distance d5 is the distance between the joint 412 of each first wire 41 and the neck portion 431 of each third wire 43 in a direction perpendicular to the thickness direction z. The first wire 41 is electrically connected to the second upper winding 125a of the second semiconductor element 12 (second functional unit 125), and is therefore a component of the third circuit. On the other hand, the third wire 43 is electrically connected to the second lower winding 125b of the second semiconductor element 12 (second functional unit 125), and is therefore a component of the second circuit. In other words, the first wire 41 has a relatively low potential and the third wire 43 has a relatively high potential, and therefore a potential difference occurs between the first wire 41 and the third wire 43. In the semiconductor device A1, because the distance d5 is greater than the distance d0, it is possible to design a dielectric strength voltage between the first wire 41 and the third wire 43 that satisfies actual use conditions. Therefore, the semiconductor device A1 can ensure an appropriate dielectric strength voltage between the first wire 41 and the third wire 43, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A1, the fifth design process S105 is performed to design the distance d5 to be greater than the distance d0. This makes it possible to design a semiconductor device A1 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A1.

[0112] In the semiconductor device A1, the potential of the first lower winding 115b of the first functional unit 115 in the first semiconductor element 11 is substantially the same as the potential of the first lead 31. In this embodiment, the first semiconductor element 11 is joined to the first lead 31, so the potential of the semiconductor substrate 110 is substantially the same as the potential of the first lead 31. As a result, in the semiconductor device A1, the potential of the semiconductor substrate 110 and the potential of the first lower winding 115b are substantially the same. Therefore, in the semiconductor device A1, the number of insulating layers 1171 between the semiconductor substrate 110 and the first lower winding 115b can be reduced, and an increase in the thickness of the first semiconductor element 11 can be suppressed.

[0113] In the semiconductor device A1, the first lower winding 115b is electrically connected to the third semiconductor element 13 by connecting the second wire 42 to the pad 111 that is conductive to the first lower winding 115b. The third semiconductor element 13 is also joined to the first lead 31. With this configuration, the first lower winding 115b and the first lead 31 are components of a first circuit that includes the third semiconductor element 13. That is, in the semiconductor device A1, the potential of the first lower winding 115b can be made substantially the same as the potential of the first lead 31.

[0114] In the semiconductor device A1, the potential of the second lower winding 125b of the second functional unit 125 in the second semiconductor element 12 is substantially the same as the potential of the second lead 32. In this embodiment, the second semiconductor element 12 is joined to the second lead 32, so the potential of the semiconductor substrate 120 is substantially the same as the potential of the second lead 32. As a result, in the semiconductor device A1, the potential of the semiconductor substrate 120 and the potential of the second lower winding 125b are substantially the same. Therefore, in the semiconductor device A1, the number of insulating layers 1271 between the semiconductor substrate 120 and the second lower winding 125b can be reduced, and an increase in the thickness of the second semiconductor element 12 can be suppressed.

[0115] In the semiconductor device A1, the second lower winding 125b is electrically connected to the fourth semiconductor element 14 by connecting a third wire 43 to a pad 121 that is conductive to the second lower winding 125b. The fourth semiconductor element 14 is also joined to the second lead 32. With this configuration, the second lower winding 125b and the second lead 32 become components of a second circuit that includes the fourth semiconductor element 14. That is, in the semiconductor device A1, the potential of the second lower winding 125b can be made substantially the same as the potential of the second lead 32.

[0116] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0117] Fig. 18 shows a semiconductor device A11 according to a first modified example of the first embodiment. Fig. 18 is an enlarged cross-sectional view of a main part of the semiconductor device A11, and corresponds to the cross section of Fig. 7. The semiconductor device A11 differs from the semiconductor device A1 in the shape of the first wire 41.

[0118] 18, in each first wire 41 of the semiconductor device A11, the loop portion 413 extends from the seal ring portion 113 to the seal ring portion 123 so as to be substantially parallel to each of the first mounting surface 311a and the second mounting surface 321a. By shaping the first wire 41 in this manner, the distance d2 and the distance d3 can be made substantially the same. Note that, as long as the distance d2 and the distance d3 are substantially the same, the loop portion 413 may be curved upward or downward in the thickness direction z.

[0119] The semiconductor device A11 has a common configuration with the semiconductor device A1 and thus exhibits the same effects as the semiconductor device A1. The semiconductor device A11 can increase the distance d3 compared to the semiconductor device A1, and therefore can further suppress the occurrence of dielectric breakdown compared to the semiconductor device A1.

[0120] Fig. 19 shows a semiconductor device A12 according to a second modified example of the first embodiment. Fig. 19 is an enlarged cross-sectional view of a main part of the semiconductor device A12, and corresponds to the cross section of Fig. 7. The semiconductor device A12 differs from the semiconductor device A1 in the following respect: the first wire 41 is first bonded to the pad 122 of the second semiconductor element 12, and second bonded to the pad 112 of the first semiconductor element 11.

[0121] 19 , in the semiconductor device A12, the neck portion 411 of each first wire 41 is bonded to the pad 122 of the second semiconductor element 12. Therefore, in the semiconductor device A12, the distance d5 is the distance between the neck portion 411 of each first wire 41 and the neck portion 431 of each third wire 43 in a direction perpendicular to the thickness direction z. Furthermore, the joint portion 412 of each first wire 41 is bonded to the pad 112 of the first semiconductor element 11. Therefore, in the semiconductor device A12, the distance d4 is the distance between the joint portion 412 of each first wire 41 and the neck portion 421 of each second wire 42 in a direction perpendicular to the thickness direction z.

[0122] The semiconductor device A12 has a common configuration with the semiconductor device A1 and thus achieves the same effects as the semiconductor device A1. As can be seen from the semiconductor device A12, in the semiconductor device of the present disclosure, there are no limitations on the bonding targets of the first bonding and second bonding of each first wire 41.

[0123] 19, the first bonding and second bonding may be reversed for each second wire 42 and each third wire 43, as with each first wire 41. In other words, in the semiconductor device of the present disclosure, the bonding targets of the first bonding and second bonding for each second wire 42 and each third wire 43 are not limited in any way.

[0124] 20 and 21 show a semiconductor device A2 according to the second embodiment. The semiconductor device A2 differs from the semiconductor device A1 in the following respect: the semiconductor device A2 does not include a third semiconductor element 13 and a fourth semiconductor element 14. Note that the connections of the multiple second wires 42 and the multiple third wires 43 are merely an example and are not limited to the example shown in FIG. 20 , and can be changed as appropriate depending on the configurations of the first semiconductor element 11 and the second semiconductor element 12.

[0125] In the semiconductor device A2, the second wires 42 are joined to any of the pads 111 and either one of the two first terminal portions 312 of the first lead 31 or any one of the third leads 33, thereby establishing electrical continuity between them. In other words, the second wires 42 establish electrical continuity between the first semiconductor element 11 and either the first lead 31 or the third leads 33.

[0126] In the semiconductor device A2, the multiple third wires 43 are joined to any of the multiple pads 121 and any of the two second terminal portions 322 of the second lead 32 or any of the multiple fourth leads 34, thereby establishing electrical continuity between them. In other words, the multiple third wires 43 establish electrical continuity between the second semiconductor element 12 and either the second lead 32 or the multiple fourth leads 34.

[0127] In the semiconductor device A2, for example, a third semiconductor element 13 may be disposed on a wiring board on which the semiconductor device A2 is mounted, and the third semiconductor element 13 may be electrically connected to the first semiconductor element 11 via the wiring board and a plurality of third leads 33. Furthermore, the first lead 31 may be electrically connected to the ground of a first circuit including the third semiconductor element 13 via the wiring board. Similarly, a fourth semiconductor element 14 may be disposed on a wiring board on which the semiconductor device A2 is mounted, and the fourth semiconductor element 14 may be electrically connected to the second semiconductor element 12 via the wiring board and a plurality of fourth leads 34. Furthermore, the second lead 32 may be electrically connected to the ground of a second circuit including the fourth semiconductor element 14 via the wiring board. In such a configuration, the semiconductor device A2 (the first semiconductor element 11 and the second semiconductor element 12) may be used to insulate the first circuit (the circuit including the third semiconductor element 13) from the second circuit (the circuit including the fourth semiconductor element 14).

[0128] The manufacturing method of the semiconductor device A2 configured as described above is the same as the manufacturing method of the semiconductor device A1 (see FIG. 10) except for the following steps: First, in the element mounting step S13, there is no process of mounting the third semiconductor element 13 and the fourth semiconductor element 14. Second, in the wire bonding step S14, there is no process of forming the plurality of fourth wires 44, the plurality of fifth wires 45, the sixth wire 46, and the seventh wire 47.

[0129] In the semiconductor device A2, similar to the semiconductor device A1, the distance d1 between the first lead 31 and the second lead 32 in the first direction x is greater than the distance d0 determined by the above formula (3). Therefore, similar to the semiconductor device A1, the semiconductor device A2 can ensure an appropriate dielectric strength between the first lead 31 and the second lead 32, thereby suppressing the occurrence of dielectric breakdown. Furthermore, the semiconductor device A2 achieves the same effects as the semiconductor device A1 by virtue of the common configuration with the semiconductor device A1. For example, similar to the semiconductor device A1, the semiconductor device A2 can ensure an appropriate dielectric strength between the first wires 41 and the first semiconductor element 11 because the distance d2 between each first wire 41 and the first semiconductor element 11 is greater than the distance d0 determined by the above formula (3). Furthermore, the distance d3 between each first wire 41 and the second semiconductor element 12 is greater than the distance d0 determined by the above formula (3). Therefore, an appropriate dielectric strength can be ensured between each first wire 41 and the second semiconductor element 12. Furthermore, since the distance d4 between each first wire 41 and each second wire 42 is greater than the distance d0 determined by the above formula (3), an appropriate dielectric strength voltage can be ensured between the first wire 41 and the second wire 42. Furthermore, since the distance d5 between each first wire 41 and each third wire 43 is greater than the distance d0 determined by the above formula (3), an appropriate dielectric strength voltage can be ensured between the first wire 41 and the third wire 43.

[0130] In the second embodiment, the semiconductor device A2 does not include both the third semiconductor element 13 and the fourth semiconductor element 14, but may include either one of them. In other words, the semiconductor device of the present disclosure does not need to include either or both of the third semiconductor element 13 and the fourth semiconductor element 14.

[0131] 22 and 23 show a semiconductor device A3 according to the third embodiment. The semiconductor device A3 differs from the semiconductor device A2 in the following respects. First, the first semiconductor element 11 of the semiconductor device A3 includes a third functional unit 116 in addition to the first functional unit 115. Second, the second semiconductor element 12 of the semiconductor device A3 includes a fourth functional unit 126 in addition to the second functional unit 125. Note that the connections of the multiple second wires 42 and the multiple third wires 43 are merely examples and are not limited to the example shown in FIG. 22 and can be changed as appropriate depending on the configurations of the first semiconductor element 11 and the second semiconductor element 12.

[0132] The third functional unit 116 functions as the third semiconductor element 13 (i.e., the control element). The third functional unit 116 can be formed on, for example, the semiconductor substrate 110. The third functional unit 116 is electrically connected to the first functional unit 115 inside the first semiconductor element 11. In the example shown in FIG. 23, the third functional unit 116 is electrically connected to the first lower winding 115b. In this example, the multiple pads 111 are electrically connected to the third functional unit 116, and the multiple pads 112 are electrically connected to the first functional unit 115 (first upper winding 115a). The first semiconductor element 11 of the semiconductor device A3 has a configuration in which a control element and an insulating element are integrated into a single chip.

[0133] The fourth functional unit 126 functions as the fourth semiconductor element 14 (i.e., the driving element). The fourth functional unit 126 can be formed on, for example, the semiconductor substrate 120. The fourth functional unit 126 is electrically connected to the second functional unit 125 inside the second semiconductor element 12. In the example shown in FIG. 23, the fourth functional unit 126 is electrically connected to the second lower winding 125b. In this example, the multiple pads 121 are electrically connected to the fourth functional unit 126, and the multiple pads 122 are electrically connected to the second functional unit 125 (the second upper winding 125a). The second semiconductor element 12 of the semiconductor device A3 has a configuration in which the driving element and the insulating element are integrated into a single chip.

[0134] In the semiconductor device A3 configured in this manner, the first circuit including the third functional unit 116 of the first semiconductor element 11 and the second circuit including the fourth functional unit 126 of the second semiconductor element 12 are insulated by the first functional unit 115 of the first semiconductor element 11 and the second functional unit 125 of the second semiconductor element 12.

[0135] The manufacturing method of the semiconductor device A3 is the same as the manufacturing method of the semiconductor device A2. That is, the manufacturing method of the semiconductor device A3 is the same as the manufacturing method of the semiconductor device A1 (see FIG. 10) except for the following processes: First, in the element mounting process S13, there is no process of mounting the third semiconductor element 13 and the fourth semiconductor element 14. Second, in the wire bonding process S14, there is no process of forming the plurality of fourth wires 44, the plurality of fifth wires 45, the sixth wire 46, and the seventh wire 47.

[0136] In the semiconductor device A3, similar to the semiconductor devices A1 and A2, the distance d1 between the first lead 31 and the second lead 32 in the first direction x is greater than the distance d0 determined by the above formula (3). Therefore, similar to the semiconductor devices A1 and A2, the semiconductor device A3 can ensure an appropriate dielectric strength between the first lead 31 and the second lead 32, thereby suppressing the occurrence of dielectric breakdown. Furthermore, the semiconductor device A3 achieves the same effects as the semiconductor devices A1 and A2 due to the common configuration with the semiconductor devices A1 and A2. For example, similar to the semiconductor devices A1 and A2, the semiconductor device A3 can ensure an appropriate dielectric strength between the first wires 41 and the first semiconductor element 11 because the distance d2 between the first wires 41 and the first semiconductor element 11 is greater than the distance d0 determined by the above formula (3). Furthermore, since the distance d3 between each first wire 41 and the second semiconductor element 12 is greater than the distance d0 determined by the above formula (3), an appropriate dielectric strength voltage can be ensured between each first wire 41 and the second semiconductor element 12. Furthermore, since the distance d4 between each first wire 41 and each second wire 42 is greater than the distance d0 determined by the above formula (3), an appropriate dielectric strength voltage can be ensured between the first wire 41 and the second wire 42. Furthermore, since the distance d5 between each first wire 41 and each third wire 43 is greater than the distance d0 determined by the above formula (3), an appropriate dielectric strength voltage can be ensured between the first wire 41 and the third wire 43.

[0137] In the semiconductor device A3 of the third embodiment described above, an example is shown in which the first semiconductor element 11 includes the first functional unit 115 and the third functional unit 116, and the second semiconductor element 12 includes the second functional unit 125 and the fourth functional unit 126, but it is also possible that the first semiconductor element 11 does not include the third functional unit 116, or the second semiconductor element 12 does not include the fourth functional unit 126.

[0138] In the above first to third embodiments (including each of the modified examples), the first semiconductor element 11 and the second semiconductor element 12 are described as examples in which the voltage difference between the first circuit and the second circuit is equally shared and insulated from each other. That is, the first semiconductor element 11 and the second semiconductor element 12 have the same insulation ratio with respect to the voltage difference between the first circuit and the second circuit. Unlike this configuration, the first semiconductor element 11 and the second semiconductor element 12 may have different insulation ratios with respect to the voltage difference between the first circuit and the second circuit. In this case, the number of insulating layers 1171 between the first upper winding 115a and the first lower winding 115b and the number of insulating layers 1271 between the second upper winding 125a and the second lower winding 125b differ depending on the insulation ratio between the first semiconductor element 11 and the second semiconductor element 12. For example, if the insulation ratio of first semiconductor element 11 is greater than that of second semiconductor element 12, the number of insulating layers 1171 will be greater than the number of insulating layers 1271. Thus, in the semiconductor device of the present disclosure, the insulation ratio between first semiconductor element 11 and second semiconductor element 12 is not limited in any way.

[0139] The semiconductor device, semiconductor device design method, and semiconductor device manufacturing method according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure, and the specific processing of each step of the semiconductor device design method and semiconductor device manufacturing method according to the present disclosure can be freely designed and modified in various ways. For example, the semiconductor device, semiconductor device design method, and semiconductor device manufacturing method according to the present disclosure include embodiments related to the following supplementary notes. Appendix 1. a conductive support including a first lead and a second lead spaced apart from each other in a first direction perpendicular to the thickness direction; a first semiconductor element including a first functional portion and supported by the first lead; a second semiconductor element including a second functional portion and supported by the second lead; a sealing resin covering a portion of the conductive support, the first semiconductor element, and the second semiconductor element; Equipped with each of the first functional unit and the second functional unit transmits an electrical signal in an electrically isolated state; A semiconductor device, wherein a distance d1 between the first lead and the second lead in the first direction is greater than a distance d0 determined by equation (1). Number 1. TIFF2025121430000005.tif22148Here, Y is the insulation life [years] required for the semiconductor device, A and B are constants determined by the material of the sealing resin, 0.15 is the offset value for calculating the distance d0 [mm], and X is the voltage [kVrms]. Appendix 2. a first wire connected to the first semiconductor element and the second semiconductor element; 2. The semiconductor device according to claim 1, wherein the first wire is electrically connected to each of the first functional unit and the second functional unit. Appendix 3. 3. The semiconductor device according to claim 2, wherein a distance d2 between the first wire and the first semiconductor element is greater than a distance d0 determined by equation (1). Appendix 4. 4. The semiconductor device according to claim 2, wherein a distance d3 between the first wire and the second semiconductor element is greater than a distance d0 determined by equation (1). Appendix 5. a second wire connected to the first semiconductor element; 5. The semiconductor device according to claim 2, wherein a distance d4 between the first wire and the second wire is greater than a distance d0 determined by equation (1). Appendix 6. a third semiconductor element covered with the sealing resin and electrically connected to the first semiconductor element on the opposite side to the second semiconductor element, the third semiconductor element is supported by the first lead together with the first semiconductor element; 6. The semiconductor device according to claim 5, wherein the second wire is connected to the third semiconductor element. Appendix 6-1. the conductive support includes a third lead spaced apart from the first lead and the second lead; 7. The semiconductor device according to claim 6, wherein the third lead is electrically connected to the third semiconductor element. Appendix 7. the first semiconductor element includes a third functional unit electrically connected to a side opposite to the second functional unit across the first functional unit, the conductive support includes a third lead spaced apart from the first lead and the second lead; 6. The semiconductor device according to claim 5, wherein the second wire is electrically connected to the third functional unit and to the third lead. Appendix 7-1. The semiconductor device according to claim 6-1 or 7, wherein the third lead protrudes from the sealing resin in the first direction. Appendix 8. a third wire connected to the second semiconductor element; 8. The semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 7, wherein a distance d5 between the first wire and the third wire is greater than a distance d0 determined by equation (1). Appendix 9. a fourth semiconductor element covered with the sealing resin and electrically connected to the second semiconductor element on the opposite side to the first semiconductor element, the fourth semiconductor element is supported by the second lead together with the second semiconductor element, 9. The semiconductor device according to claim 8, wherein the third wire is connected to the fourth semiconductor element. Appendix 9-1. the conductive support includes a fourth lead spaced apart from the first lead and the second lead; 10. The semiconductor device according to claim 9, wherein the fourth lead is electrically connected to the fourth semiconductor element. Appendix 10. the second semiconductor element includes a fourth functional unit electrically connected to a side opposite to the first functional unit across the second functional unit, the conductive support includes a fourth lead spaced apart from the first lead and the second lead; 9. The semiconductor device according to claim 8, wherein the third wire is electrically connected to the fourth functional unit and is connected to the fourth lead. Appendix 10-1. The semiconductor device according to claim 9-1 or 10, wherein the fourth lead protrudes from the sealing resin in the first direction. Appendix 11. the first functional unit includes a first upper winding and a first lower winding spaced apart in the thickness direction, 11. The semiconductor device according to claim 1, wherein the potential of the first lower winding is the same as the potential of the first lead. Appendix 12. the first semiconductor element includes a plurality of first insulating layers stacked between the first upper winding and the first lower winding in the thickness direction, 12. The semiconductor device according to claim 11, wherein the plurality of first insulating layers are four to six in number. Appendix 13. 13. The semiconductor device according to claim 11, wherein the dimension of the plurality of first insulating layers in the thickness direction is not less than 9.6 μm and not more than 14.4 μm. Appendix 14. the second functional unit includes a second upper winding and a second lower winding spaced apart in the thickness direction, 14. The semiconductor device according to claim 1, wherein the potential of the second lower winding is the same as the potential of the second lead. Appendix 15. the fourth semiconductor element includes a plurality of second insulating layers stacked between the second upper winding and the second lower winding in the thickness direction, 15. The semiconductor device according to claim 14, wherein the plurality of second insulating layers are four to six in number. Appendix 16. 16. The semiconductor device according to claim 14, wherein the dimension of the second insulating layers in the thickness direction is 9.6 μm or more and 14.4 μm or less. Appendix 17. 17. The semiconductor device according to claim 1, wherein a constituent material of the sealing resin includes an epoxy resin. Appendix 18. a conductive support including a first lead and a second lead spaced apart from each other in a first direction; a first semiconductor element including a first functional portion and supported by the first lead; a second semiconductor element including a second functional portion and supported by the second lead; a sealing resin covering a portion of the conductive support, the first semiconductor element, and the second semiconductor element; Equipped with A method for designing a semiconductor device in which each of the first functional unit and the second functional unit transmits an electrical signal in an insulated state, comprising: A semiconductor device design method, comprising a design process including a first design process for designing so that the distance d1 in the first direction between the first lead and the second lead is greater than the distance d0 determined by equation (2). Number 2. TIFF2025121430000006.tif22152Here, Y is the insulation life [years] required for the semiconductor device, A and B are constants determined by the material of the sealing resin, 0.15 is the offset value for calculating the distance d0 [mm], and X is the voltage [kVrms]. Appendix 19. the semiconductor device further includes a first wire connected to the first semiconductor element and the second semiconductor element; 19. The method for designing a semiconductor device according to claim 18, wherein the first wire is electrically connected to each of the first functional unit and the second functional unit. Appendix 20. The semiconductor device design method of claim 19, wherein the design process includes a second design process for designing a distance d2 between the first wire and the first semiconductor element to be greater than the distance d0 determined by equation (2). Appendix 21. The semiconductor device design method according to claim 19 or 20, wherein the design step includes a third design process for designing a distance d3 between the first wire and the second semiconductor element to be greater than a distance d0 determined by equation (2). Appendix 22. the semiconductor device further includes a second wire connected to the first semiconductor element; 22. The semiconductor device design method according to any one of appendix 19 to appendix 21, wherein the design step includes a fourth design process for designing so that a distance d4 between the first wire and the second wire is greater than a distance d0 determined by equation (2). Appendix 22-1. a third semiconductor element covered with the sealing resin and electrically connected to the first semiconductor element on the opposite side to the second semiconductor element, the third semiconductor element is supported by the first lead together with the first semiconductor element; 23. The method for designing a semiconductor device according to claim 22, wherein the second wire is connected to the third semiconductor element. Appendix 22-2. the first semiconductor element includes a third functional unit electrically connected to a side opposite to the second functional unit across the first functional unit, the conductive support includes a third lead spaced apart from the first lead and the second lead; 23. The semiconductor device according to claim 22, wherein the second wire is electrically connected to the third functional unit and to the third lead. Appendix 23. the semiconductor device further includes a third wire connected to the second semiconductor element; 23. The semiconductor device design method according to any one of appendix 19 to appendix 22, wherein the design step includes a fifth design process of designing so that a distance d5 between the first wire and the third wire is greater than a distance d0 determined by equation (1). Appendix 23-1. a fourth semiconductor element covered with the sealing resin and electrically connected to the second semiconductor element on the opposite side to the first semiconductor element, the fourth semiconductor element is supported by the second lead together with the second semiconductor element, 24. The semiconductor device of claim 23, wherein the third wire is connected to the fourth semiconductor element. Appendix 23-2. the second semiconductor element includes a fourth functional unit electrically connected to a side opposite to the first functional unit across the second functional unit, the conductive support includes a fourth lead spaced apart from the first lead and the second lead; The semiconductor device described in Appendix 238, wherein the third wire is electrically connected to the fourth functional unit and the fourth lead. Appendix 24. A method for manufacturing a semiconductor device, comprising the method for designing a semiconductor device according to any one of Supplementary Note 18 to Supplementary Note 23. [Explanation of symbols]

[0140] A1, A11, A12, A2, A3: semiconductor device 11: First semiconductor element 11a: Main surface 11b: Back side 110: Semiconductor substrate 111: Pad 112: Pad 113: Seal ring part 115: First functional section 115a: First upper winding 115b: First lower winding 116: Third Functional Section 117:Laminated structure 1171: Insulating layer 118:Wiring section 1181: Through wiring 1182: Pull-out wiring 119: Conductive bonding material 12: Second semiconductor element 12a: Main surface 12b: Back 120: Semiconductor substrate 121: Pad 122: Pad 123: Seal ring part 125: Second functional section 125a: Second upper winding 125b: Second lower winding 126: 4th Functional Section 127:Laminated structure 1271: Insulating layer 128:Wiring section 1281: Through wiring 1282: Pull-out wiring 129: Conductive bonding material 13: Third semiconductor element 13a: Main surface 13b: Back side 131: Pad 139: Conductive bonding material 14: Fourth semiconductor element 14a: Main surface 14b: Back 141: Pad 149: Conductive bonding material 3: Conductive support 31: First lead 311: Island 1 311a: 1st mounting surface 312: 1st terminal section 312a: Covering part 312b: Exposed part 32: Second lead 321: Second Island 321a: 2nd mounting surface 322: 2nd terminal section 322a: Covering part 322b:Exposed part 33: Third lead 33A: Intermediate lead 33B: Side lead 331: Covering part 332 :Exposed part 34: 4th lead 34A: Intermediate lead 34B: Side lead 341: Covering part 342 :Exposed part 4: Connection parts 41: First wire 411: Neck 412: Joint 413: Loop section 42: Second wire 421: Neck 422: Joint 423: Loop section 43: Third wire 431: Neck 432: Joint 433: Loop section 44: 4th wire 45: 5th wire 46: 6th wire 47: 7th wire 5: Sealing resin 51:Top surface 52: Bottom 53 :1st side 531: First upper section 532: Lower 1st 533: First intermediate section 54:Second side 541: Second upper section 542: Second Lower Section 543: Second intermediate section 81: Lead frame 810: Flat plate part 811: 1st lead 811a: Island 1 811b: Supporting Lead 812: Second Lead 812a: Second Island 812b: Supporting Lead 813: Lead 814: Lead 815: Outer frame 816: Dambar 82: Resist

Claims

1. a conductive support including a first lead and a second lead spaced apart from each other in a first direction perpendicular to the thickness direction; a first semiconductor element including a first functional portion and supported by the first lead; a second semiconductor element including a second functional portion and supported by the second lead; a sealing resin covering a portion of the conductive support, the first semiconductor element, and the second semiconductor element; Equipped with each of the first functional unit and the second functional unit transmits an electrical signal in an electrically isolated state; A semiconductor device, wherein a distance d1 between the first lead and the second lead in the first direction is greater than a distance d0 determined by equation (1). [Equation 1] Here, Y is the insulation life (years) required for the semiconductor device, A and B are constants determined by the material of the sealing resin, 0.15 is an offset value for calculating the distance d0 (mm), and X is the voltage (kVrms).

2. a first wire connected to the first semiconductor element and the second semiconductor element; The semiconductor device according to claim 1 , wherein the first wire is electrically connected to each of the first function unit and the second function unit.

3. 3. The semiconductor device according to claim 2, wherein a distance d2 between said first wire and said first semiconductor element is greater than a distance d0 determined by equation (1).

4. The semiconductor device according to claim 2 , wherein a distance d3 between said first wire and said second semiconductor element is greater than a distance d0 determined by equation (1).

5. 3. The semiconductor device according to claim 2, further comprising a second wire connected to the first semiconductor element, wherein a distance d4 between the first wire and the second wire is greater than a distance d0 determined by equation (1).

6. a third semiconductor element covered with the sealing resin and electrically connected to the first semiconductor element on the opposite side to the second semiconductor element, the third semiconductor element is supported by the first lead together with the first semiconductor element, The semiconductor device according to claim 5 , wherein the second wire is connected to the third semiconductor element.

7. the first semiconductor element includes a third functional unit electrically connected to a side opposite to the second functional unit across the first functional unit, the conductive support includes a third lead spaced apart from the first lead and the second lead; The semiconductor device according to claim 5 , wherein the second wire is electrically connected to the third function unit and is connected to the third lead.

8. a third wire connected to the second semiconductor element; 3. The semiconductor device according to claim 2, wherein a distance d5 between said first wire and said third wire is greater than a distance d0 determined by equation (1).

9. a fourth semiconductor element covered with the sealing resin and electrically connected to the second semiconductor element on the opposite side to the first semiconductor element, the fourth semiconductor element is supported by the second lead together with the second semiconductor element, The semiconductor device according to claim 8 , wherein the third wire is connected to the fourth semiconductor element.

10. the second semiconductor element includes a fourth functional unit electrically connected to a side opposite to the first functional unit across the second functional unit, the conductive support includes a fourth lead spaced apart from the first lead and the second lead; The semiconductor device according to claim 8 , wherein the third wire is electrically connected to the fourth function unit and is connected to the fourth lead.

11. the first functional unit includes a first upper winding and a first lower winding spaced apart in the thickness direction, 11. The semiconductor device according to claim 1, wherein the potential of said first lower winding is the same as the potential of said first lead.

12. the first semiconductor element includes a plurality of first insulating layers stacked between the first upper winding and the first lower winding in the thickness direction, The semiconductor device according to claim 11 , wherein the plurality of first insulating layers are four to six in number.

13. 12. The semiconductor device according to claim 11, wherein the dimension of the plurality of first insulating layers in the thickness direction is not less than 9.6 [mu]m and not more than 14.4 [mu]m.

14. the second functional unit includes a second upper winding and a second lower winding spaced apart in the thickness direction, The semiconductor device according to claim 11 , wherein the potential of the second lower winding is the same as the potential of the second lead.

15. the second semiconductor element includes a plurality of second insulating layers stacked between the second upper winding and the second lower winding in the thickness direction, The semiconductor device according to claim 14 , wherein the plurality of second insulating layers are four to six in number.

16. 15. The semiconductor device according to claim 14, wherein the dimension of the plurality of second insulating layers in the thickness direction is not less than 9.6 [mu]m and not more than 14.4 [mu]m.

17. 11. The semiconductor device according to claim 1, wherein the sealing resin comprises an epoxy resin.

18. a conductive support including a first lead and a second lead spaced apart from each other in a first direction; a first semiconductor element including a first functional portion and supported by the first lead; a second semiconductor element including a second functional portion and supported by the second lead; a sealing resin covering a portion of the conductive support, the first semiconductor element, and the second semiconductor element; Equipped with A method for designing a semiconductor device in which each of the first functional unit and the second functional unit transmits an electrical signal in an insulated state, comprising: A method for designing a semiconductor device, comprising a design process including a first design process for designing so that a distance d1 in the first direction between the first lead and the second lead is greater than a distance d0 determined by equation (2). [Equation 2] Here, Y is the insulation life (years) required for the semiconductor device, A and B are constants determined by the material of the sealing resin, 0.15 is an offset value for calculating the distance d0 (mm), and X is the voltage (kVrms).

19. the semiconductor device further includes a first wire connected to the first semiconductor element and the second semiconductor element; 20. The method for designing a semiconductor device according to claim 18, wherein the first wire is electrically connected to each of the first functional unit and the second functional unit.

20. 20. The method for designing a semiconductor device according to claim 19, wherein the design step includes a second design process for designing a distance d2 between the first wire and the first semiconductor element to be greater than a distance d0 determined by equation (2).

21. 20. The semiconductor device design method according to claim 19, wherein the design step includes a third design process for designing a distance d3 between the first wire and the second semiconductor element to be greater than a distance d0 determined by equation (2).

22. the semiconductor device further includes a second wire connected to the first semiconductor element; 20. The method for designing a semiconductor device according to claim 19, wherein the design step includes a fourth design process for designing so that a distance d4 between the first wire and the second wire is greater than a distance d0 determined by equation (2).

23. the semiconductor device further includes a third wire connected to the second semiconductor element; 20. The method for designing a semiconductor device according to claim 19, wherein the design step includes a fifth design process for designing so that a distance d5 between the first wire and the third wire is greater than a distance d0 determined by equation (1).

24. A method for manufacturing a semiconductor device, comprising the method for designing a semiconductor device according to any one of claims 18 to 23.

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