Three-phase gate driver circuit, motor drive device using the same, and electronic apparatus

Abstract

To provide a gate driver circuit operable at a 100% duty cycle.SOLUTION: A level shifter shifts a level of a high-side control signal for instructing ON / OFF of a high-side transistor of a corresponding phase, and can switch an operating current IOP in three stages of a first current amount I1, a second current amount I2, and a third current amount I3 satisfying I1>I2>I3 in accordance with a current control signal. While a charge pump circuit is on (CP_EN is H) in a certain phase (a U phase), a controller circuit generates the current control signal so that the operating current IOP of the level shifter of the U phase becomes the second current amount I2 when a transition of an output VOUTV, VOUTW of the other phase (a V or W phase) occurs.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a three-phase gate driver circuit. [Background technology]

[0002] Half-bridge circuits, H-bridge circuits, and three-phase bridge circuits (hereinafter collectively referred to as bridge circuits) using power transistors are widely used in motor driver circuits, DC / DC converters, power conversion devices, and the like.

[0003] When the high-side transistors in a bridge circuit are configured with N-type transistors, i.e., N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or NPN-type bipolar transistors, a bootstrap circuit is used. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-061663

[0005] [overview] Gate driver circuits using bootstrap circuits cannot hold the high-side transistor on for a long period of time, and therefore cannot hold the bridge circuit in a high output state, which means that 100% duty cycle operation (non-PWM mode) is not possible.

[0006] The present disclosure has been made in view of the above-mentioned problems, and one exemplary purpose of an embodiment thereof is to provide a gate driver circuit that can operate at a 100% duty cycle.

[0007] An aspect of the present disclosure relates to a three-phase gate driver circuit for driving a three-phase inverter, the three-phase gate driver circuit including a U-phase gate driver circuit, a V-phase gate driver circuit, a W-phase gate driver circuit, and a controller circuit. Each of the U-phase gate driver circuit, V-phase gate driver circuit, and W-phase gate driver circuit includes: a bootstrap line to be connected to a bootstrap capacitor; a charging circuit including a charge pump circuit that can be turned on and off and configured to supply a charging current to the bootstrap line when the charge pump circuit is on; a switching line to be connected to the output of the inverter of the corresponding phase; a level shifter that level-shifts a high-side control signal that instructs the high-side transistor of the corresponding phase to be turned on and off, and that can switch the operating current between three levels: first current amount I1, second current amount I2, and third current amount I3, where I1 > I2 > I3, in accordance with the current control signal; a high-side driver that drives the high-side transistor of the corresponding phase based on the high-side control signal level-shifted by the level shifter; and a low-side driver that drives the low-side transistor of the corresponding phase in accordance with a low-side control signal that instructs the low-side transistor to be turned on and off. The controller circuit, in one of the U, V, and W phases, (i) when the charge pump circuit is off, generates a current control signal so that the operating current of the level shifter is a first current amount I1; (ii) when a first state in which the high-side transistor is on and the low-side transistor is off continues for a predetermined first determination time, turns on the charge pump circuit and generates a current control signal so that the operating current of the level shifter is a third current amount I3; and (iii) when a transition in the output of another phase occurs while the charge pump circuit is on, generates a current control signal so that the operating current of the level shifter is a second current amount I2.

[0008] Any combination of the above components, or mutual substitution of the components or expressions of the present disclosure between methods, devices, systems, etc., are also valid aspects of the present invention. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a motor drive device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of a three-phase gate driver circuit according to the embodiment. [Figure 3] FIG. 3 is a time chart illustrating the operation of the three-phase gate driver circuit of FIG. [Figure 4] FIG. 4 is a time chart illustrating another operation of the three-phase gate driver circuit of FIG. [Figure 5] FIG. 5 is a state transition diagram of the three-phase gate driver circuit of FIG. [Figure 6] FIG. 6 is a diagram illustrating the operation of the three-phase gate driver circuit of FIG. 2 in 120-degree conduction control. [Figure 7] FIG. 7 is a state transition diagram according to a modification of the three-phase gate driver circuit of FIG. [Figure 8] FIG. 8 is a diagram illustrating the operation of the three-phase gate driver circuit according to the first modification under 120-degree conduction control. [Figure 9] FIG. 9 is a diagram illustrating control of the operating current of the U-phase level shifter in the three-phase gate driver circuit according to the embodiment. [Figure 10] FIG. 10 is a diagram illustrating control of the operating current IOP of the U-phase level shifter in the three-phase gate driver circuit according to the first comparative technique. [Figure 11] FIG. 11 is a diagram illustrating control of the operating current IOP of the U-phase level shifter in the three-phase gate driver circuit according to the comparative technique 2. In FIG. [Figure 12] FIG. 12 is a circuit diagram of a gate driver circuit according to an embodiment. [Figure 13] FIG. 13 is a circuit diagram of a charge pump circuit according to an embodiment.

[0010] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a basic understanding of one or more embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0011] This summary is not an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0012] A three-phase gate driver circuit according to one embodiment drives a three-phase inverter and includes a U-phase gate driver circuit, a V-phase gate driver circuit, a W-phase gate driver circuit, and a controller circuit. Each of the U-phase gate driver circuit, V-phase gate driver circuit, and W-phase gate driver circuit includes: a bootstrap line to be connected to a bootstrap capacitor; a charging circuit including a charge pump circuit that can be turned on and off and configured to supply a charging current to the bootstrap line when the charge pump circuit is on; a switching line to be connected to the output of the inverter of the corresponding phase; a level shifter that level-shifts a high-side control signal that instructs the high-side transistor of the corresponding phase to be turned on and off, and that can switch the operating current between three levels: first current amount I1, second current amount I2, and third current amount I3, where I1 > I2 > I3, in accordance with the current control signal; a high-side driver that drives the high-side transistor of the corresponding phase based on the high-side control signal level-shifted by the level shifter; and a low-side driver that drives the low-side transistor of the corresponding phase in accordance with a low-side control signal that instructs the low-side transistor to be turned on and off. The controller circuit, in one of the U, V, and W phases, (i) when the charge pump circuit is off, generates a current control signal so that the operating current of the level shifter is a first current amount I1; (ii) when a first state in which the high-side transistor is on and the low-side transistor is off continues for a predetermined first determination time, turns on the charge pump circuit and generates a current control signal so that the operating current of the level shifter is a third current amount I3; and (iii) when a transition in the output of another phase occurs while the charge pump circuit is on, generates a current control signal so that the operating current of the level shifter is a second current amount I2.

[0013] With this configuration, the charge pump circuit is operated intermittently instead of constantly, and the operating current of the level shifter is reduced, thereby reducing power consumption and obtaining an output with a 100% duty cycle. Also, if the output of one phase transitions while the charge pump circuit of another phase is operating, the operating current of the level shifter can be increased to prevent the output of the level shifter from changing due to switching noise generated by the other phase.

[0014] In one embodiment, the controller circuit may (iv) switch the operating current of the level shifter to the second current amount I2 in one of the U phase, V phase, and W phase, and then, after a predetermined time has elapsed, return the operating current of the level shifter to the third current amount I3, thereby reducing the operating current of the circuit.

[0015] In one embodiment, when (v) a third state in which the high-side transistor is off and the low-side transistor is off continues for a predetermined second determination time in one of the U phase, V phase, and W phase, the controller circuit may turn on the charge pump circuit and generate a current control signal so that the operating current of the level shifter becomes a third current amount I3.

[0016] In one embodiment, the first determination time may be longer than the switching period when operating in PWM mode.

[0017] In one embodiment, the high-side driver may include a current source and a current mirror circuit that mirrors a current generated by the current source and supplies the current to the gate of the high-side transistor. When the charge pump circuit is on, the amount of current from the current source may be smaller than when the charge pump circuit is off.

[0018] In one embodiment, the three-phase gate driver circuit may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on the semiconductor substrate, or where the main circuit components are monolithically integrated, and some resistors and capacitors for adjusting circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniform.

[0019] A motor drive device according to an embodiment may include a three-phase inverter and any one of the above-described three-phase gate driver circuits that drives the three-phase inverter.

[0020] An electronic device according to an embodiment may include a motor and the above-described motor drive device that drives the motor.

[0021] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be designated by the same reference numerals, and redundant descriptions will be omitted where appropriate. Furthermore, the embodiments are merely examples and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0022] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0023] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0024] 1 is a circuit diagram of a motor driving device 100 according to an embodiment. The motor driving device 100 drives a three-phase motor 2, which is a load, and controls the rotation state.

[0025] Motor drive device 100 includes a three-phase inverter 110 and a three-phase gate driver circuit 200. Three-phase inverter 110 includes a U-phase leg, a V-phase leg, and a W-phase leg connected in parallel between a power supply line 102 and an output line 104. The # (#=U, V, W)-phase leg includes a high-side transistor MH# which is an upper arm, and a low-side transistor ML# which is a lower arm.

[0026] The three-phase gate driver circuit 200 drives the three-phase inverter 110. The three-phase gate driver circuit 200 includes a control circuit 210, a U-phase gate driver circuit 220U, a V-phase gate driver circuit 220V, and a W-phase gate driver circuit 220W.

[0027] Each leg of the three-phase inverter 110 can be in a first state (high output state) φ1 in which the high-side transistor MH is on and the low-side transistor ML is off, a second state (low output state) φ2 in which the high-side transistor MH is off and the low-side transistor ML is on, and a third state (high impedance state) φ3 in which the high-side transistor MH is off and the low-side transistor ML is off. The output voltage of each leg is equal to or greater than the power supply voltage V IN and the ground voltage is 0V in the second state (low output) φ2.

[0028] The control circuit 210 controls the state of each leg of the three-phase inverter 110 based on the state of the three-phase motor 2.

[0029] Known motor control methods include 120-degree conduction control (rectangular wave control) and 180-degree conduction control (sine wave control). 180-degree conduction control uses PWM (Pulse Width Modulation) control, which controls the output voltage V of each leg. OUT#PWM modulation is performed so that the time average of becomes a sine wave, and the three-phase inverter 110 switches at the PWM frequency.

[0030] In 120-degree conduction control, the output voltage V of each leg OUT# is a square wave, and PWM control is not performed, operating in non-PWM mode. Even in the case of 120-degree conduction control, PWM control may be introduced for torque control (rotation speed), but in this case the duty cycle is constant.

[0031] In this embodiment, the control circuit 210 can switch between 120-degree conduction control and 180-degree conduction control, and therefore operates in either PWM mode or non-PWM mode, where the duty cycle is 100%.

[0032] The control circuit 210 generates the following signals: High-side control signal HIN_U that indicates the state of the U-phase high-side transistor MHU Low-side control signal LIN_U that indicates the state of the U-phase low-side transistor MLU High-side control signal HIN_V that indicates the state of the V-phase high-side transistor MHV Low-side control signal LIN_V that indicates the state of the V-phase low-side transistor MLV High-side control signal HIN_W that indicates the state of the W-phase high-side transistor MHW Low-side control signal LIN_W that indicates the state of the W-phase low-side transistor MLW

[0033] The U-phase gate driver circuit 220U drives the high-side transistor MHU in response to a high-side control signal HIN_U, and drives the low-side transistor MLU in response to a low-side control signal LIN_U.

[0034] The V-phase gate driver circuit 220V drives the high-side transistor MHV in response to a high-side control signal HIN_V, and drives the low-side transistor MLV in response to a low-side control signal LIN_V.

[0035] The W-phase gate driver circuit 220W drives the high-side transistor MHW in response to the high-side control signal HIN_W, and drives the low-side transistor MLW in response to the low-side control signal LIN_W.

[0036] Fig. 2 is a circuit diagram of a three-phase gate driver circuit 200 according to an embodiment. Since the gate driver circuits 220U, 220V, and 220W have the same configuration, Fig. 2 shows the configuration for one phase (referred to as # phase). The three-phase gate driver circuit 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate.

[0037] 2 shows leg 112# for one phase of three-phase inverter 110. Leg 112# includes high-side transistor MH# provided between power supply line (input line) 102 and output terminal (output line) 104, and low-side transistor ML# provided between output line 104 and ground line 106. Both high-side transistor MH# and low-side transistor ML# are N-type transistors. The N-type transistor may be an N-channel MOSFET, an NPN bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor), or the like. Depending on the application, a shunt resistor for current detection may be inserted between low-side transistor ML and ground line 106.

[0038] FIG. 2 shows the control circuit 210 and the #-phase gate driver circuit 220# of the three-phase gate driver circuit 200.

[0039] The three-phase gate driver circuit 200 has a high-side gate pin HG# connected to the gate of a high-side transistor MH#, and a low-side gate pin LG# connected to the gate of a low-side transistor ML#. A ground pin GND is connected to the source of the low-side transistor ML#. A switching pin (#-phase output pin) SW# is connected to the output line 104. A bootstrap capacitor C is connected between the bootstrap pin BST# and the switching pin SW#. BST# is attached externally.

[0040] The bootstrap line 202 is connected to the bootstrap pin BST#, the switching line 204 is connected to the switching pin SW, and the ground line 206 is connected to the GND pin. A constant voltage V REG is applied to the rectifying element 286 and the bootstrap capacitor C BST forms a bootstrap circuit, and the voltage (switching voltage) V of the switching line 204 is applied to the bootstrap line 202 by using the switching operation of the leg 112#. OUT# The bootstrap voltage V is higher than the BST# When the forward voltage of the rectifier element 286 is Vf, ΔV=V REG It becomes -Vf.

[0041] The gate driver circuit 220# includes a high-side driver 240, a level shifter 250, a low-side driver 260, and a charging circuit 280.

[0042] The level shifter 250 level-shifts up the high-side control signal HIN_#. The high-side driver 240 drives the high-side transistor MH# based on the level-shifted high-side control signal HIN'_#.

[0043] The upper power supply node 241 of the high-side driver 240 is connected to the bootstrap line 202 and supplies the bootstrap voltage V BST#The lower power supply node 242 is connected to the switching line 204 and is supplied with a switching voltage V OUT# The high-side driver 240 provides two voltage levels V BST# ,V OUT# Gate voltage V HG# occurs on the high-side gate pin HG.

[0044] The low-side driver 260 controls the gate voltage V of the low-side transistor ML in response to the low-side control signal LIN_#. LG The upper power supply node 261 of the low-side driver 260 is connected to a power supply voltage V DD is supplied to the low-side power supply node 262 of the low-side driver 260, and the ground voltage 0V is supplied to the low-side power supply node 262 of the low-side driver 260.

[0045] The charging circuit 280 includes a charge pump circuit 282 that can be controlled to be turned on and off. The charging circuit 280 is configured to charge the bootstrap line 202 when the charge pump circuit 282 is turned on (enabled). The charge pump circuit 282 is also called a trickle charge pump, and is integrated into the three-phase gate driver circuit 200. The power consumption of the charge pump circuit 282 is on the order of 1 mA or less, for example, about 100 μA. The charge pump circuit 282 converts an input voltage V IN voltage V CP occurs.

[0046] The charge pump circuit 282 is controlled to be turned on and off by the control circuit 210. The charge pump circuit 282 has an enable terminal EN, and is turned on when an enable signal CP_EN generated by the control circuit 210 is asserted (for example, high), and is turned off when the enable signal CP_EN is negated (for example, low).

[0047] The charging circuit 280 may further include a current source 284 that keeps the charging current constant.

[0048] When the control circuit 210 is in the first state φ1 for a predetermined first determination time τ1, that is, when the control circuit 210 is in the high state V OUT# =V IN# When this occurs, the enable signal CP_EN is asserted to turn on the charge pump circuit 282.

[0049] The control circuit 210 includes a logic circuit 212 and a timer circuit 214. The logic circuit 212 measures the first determination time τ1 using the timer circuit 214 and generates the enable signal CP_EN.

[0050] Although not limited thereto, the first determination time τ1 can be set to be longer than the pulse width modulation (PWM) period. This allows the charge pump circuit 282 to operate when the operation mode is set to a 100% duty cycle. As an example, the first determination time τ1 may be set to be between two and five times the PWM period. For example, when the PWM period is 50 μs (i.e., the PWM frequency is 20 kHz), the first determination time τ1 can be set to be between 100 μs and 250 μs, or may be set to 200 μs.

[0051] When the first state φ1 changes to the second state φ2 or the third state φ3, the control circuit 210 turns off the charge pump circuit 282.

[0052] When the control circuit 210 is in the third state φ3 for a predetermined second determination time τ2, that is, when the control circuit 210 is in the high impedance state V OUT# =HiZ, the charge pump circuit 282 is turned on. The second determination time τ2 may be equal to the first determination time τ1.

[0053] When the state changes from the third state φ3 to the first state φ1 or the second state φ2, the control circuit 210 turns off the charge pump circuit 282.

[0054] 3 is a time chart illustrating the operation of the three-phase gate driver circuit 200 of FIG. 2. FIG. 3 shows the operation of one phase (# phase). Before time t1, the three-phase gate driver circuit 200 operates in PWM mode, and leg 112# alternates between a first state φ1 and a second state φ2 at a PWM frequency, generating an output signal V OUT# is the high output state V IN The enable signal CP_EN is negated (low), the charge pump circuit 282 is stopped, and the bootstrap voltage V BST# is the switching voltage V OUT The voltage level is maintained at a voltage level that is higher by a predetermined voltage width ΔV than the voltage level.

[0055] At time t1, the PWM mode is switched to non-PWM mode and the first state φ1 is fixed. When switching at the PWM frequency stops, the bootstrap circuit switches the bootstrap capacitor C BST Since the bootstrap voltage V BST# decreases over time.

[0056] At time t2, which is the first determination time τ1 after time t1, the control circuit 210 asserts the enable signal CP_EN. This causes the charge pump circuit 282 to start operating, and the charging circuit 280 charges the bootstrap capacitor C BST# is charged, and the bootstrap voltage V BST# As a result, the high-side driver 240 can continue to maintain the high-side transistor MH in the on state.

[0057] At time t3, the state transitions to the second state φ2, whereupon the control circuit 210 negates the enable signal CP_EN and stops the charge pump circuit 282.

[0058] 4 is a time chart illustrating another operation of the three-phase gate driver circuit 200 of FIG. 2. Before time t1, the three-phase gate driver circuit 200 operates in PWM mode, and the leg 112# alternates between the first state φ1 and the second state φ2 at the PWM frequency, generating the output signal V OUT# is the high output state V IN The enable signal CP_EN is negated (low), the charge pump circuit 282 is stopped, and the bootstrap voltage V BST# is the switching voltage V OUT The voltage level is maintained at a voltage level that is higher by a predetermined voltage width ΔV than the voltage level.

[0059] At time t1, when the PWM mode is switched to the non-PWM mode, the third state φ3 is entered, and the high-side transistor MH and the low-side transistor ML are turned off, resulting in a high-impedance state. OUT# is the induced voltage generated in the coil of the three-phase motor 2.

[0060] When switching at the PWM frequency stops in the high-impedance state, the bootstrap circuitry turns on the bootstrap capacitor C BST# Since the bootstrap voltage V BST# decreases over time.

[0061] At time t2, which is the second determination time τ2 after time t1, the control circuit 210 asserts the enable signal CP_EN. This causes the charge pump circuit 282 to start operating, and the charging circuit 280 charges the bootstrap capacitor C BST is charged, and the bootstrap voltage V BST# As a result, the high-side driver 240 can continue to maintain the high-side transistor MH in the on state.

[0062] The above is the operation of the three-phase gate driver circuit 200. Next, its advantages will be explained.

[0063] 3, if the high output state continues, the bootstrap circuit is not activated. By activating the charge pump circuit 282 on the condition that this state continues for the first determination time τ1, the high-side transistor MH can be maintained in the on state during the high output state, and the bootstrap capacitor C BST You can keep it charged.

[0064] With reference to Figure 4, if the current sink is sustained in a high impedance state, the switching voltage V OUT# is the input voltage V IN Therefore, the bootstrap circuit does not operate because the voltage Vf is stuck to +Vf. Therefore, by operating the charge pump circuit 282 on the condition that the high impedance state has continued for the second determination time τ2, the bootstrap capacitor C BST# This allows a reliable transition to a high output state after a high impedance state.

[0065] Fig. 5 is a state transition diagram of the three-phase gate driver circuit 200 of Fig. 2. The three-phase gate driver circuit 200 transitions through five states S1 to S5.

[0066] State S1: High Output V OUT =V IN Charge pump circuit = Off CP_EN=L

[0067] State S2: High Output V OUT =V IN Charge pump circuit = ON CP_EN=H

[0068] State S3: Low Output V OUT =0V Charge pump circuit = Off CP_EN=L

[0069] State S4: High impedance V OUT =HiZ Charge pump circuit = Off CP_EN=L

[0070] State S5: Low Output V OUT =HiZ Charge pump circuit = ON CP_EN=H

[0071] The control circuit 210 can be implemented as a state machine that transitions between five states φ1 to φ5.

[0072] The conditions for each transition are as follows:

[0073] A transition T1 from state S1 to S2 occurs when the first state φ1 continues for a first determination time τ1.

[0074] A transition T2 from state S1 to S3 occurs on the condition that a transition to the second state φ2 has occurred.

[0075] A transition T3 from state S1 to S4 occurs on the condition that a transition to the third state φ3 has occurred.

[0076] A transition T4 from state S2 to S3 occurs on the condition that a transition to the second state φ2 has occurred.

[0077] A transition T5 from state S2 to S4 occurs on the condition that a transition to the third state φ3 has occurred.

[0078] A transition T6 from state S3 to S1 occurs on the condition that a transition to the first state φ1 has occurred.

[0079] A transition T7 from state S3 to S4 occurs on the condition that a transition to the third state φ3 has occurred.

[0080] A transition T8 from state S4 to S5 occurs on the condition that the third state φ3 has continued for the second determination time τ2.

[0081] A transition T9 from state S4 to S1 occurs on the condition that a transition to the first state φ1 has occurred.

[0082] A transition T10 from state S4 to S3 occurs on the condition that a transition to the second state φ2 has occurred.

[0083] A transition T11 from state S5 to S1 occurs on the condition that a transition to the first state φ1 has occurred.

[0084] A transition T12 from state S5 to S3 occurs on the condition that a transition to the second state φ2 has occurred.

[0085] 6 is a diagram illustrating the operation of the three-phase gate driver circuit 200 in 120-degree conduction control of FIG. OUTU , V phase output voltage V OUTV , W phase output voltage V OUTW , U-phase enable signal CP_EN and its state are shown.

[0086] (Variation) Fig. 7 is a state transition diagram according to a modification of the three-phase gate driver circuit 200 of Fig. 2. In this modification, a state S6 is added.

[0087] State S6: Low Output V OUT =0V Charge pump circuit = ON CP_EN=L

[0088] A transition T13 from state S3 to S6 occurs when the second state φ2 has continued for a third determination time τ3.

[0089] A transition T14 from state S6 to S1 occurs on the condition that a transition to the first state φ1 has occurred.

[0090] A transition T15 from state S6 to S4 occurs on the condition that a transition to the third state φ3 has occurred.

[0091] A transition T11 from state S5 to S1 occurs on the condition that a transition to the first state φ1 has occurred.

[0092] A transition T12 from state S5 to S3 occurs on the condition that a transition to the second state φ2 has occurred.

[0093] Low output state (V OUT = 0V), the bootstrap capacitor C BST However, a state S6 may be added to keep the charge pump circuit 282 operating.

[0094] 8 is a diagram illustrating the operation of the three-phase gate driver circuit 200 according to the first modification in 120-degree conduction control. OUTU , V phase output voltage V OUTV , W phase output voltage V OUTW , the state of the U-phase enable signal CP_EN and the U-phase are shown.

[0095] By adding state S6, the enable signal CP_EN is asserted in the hatched portion, enabling the charge pump circuit 282. The rest is the same as in FIG.

[0096] Returning to FIG. 2, the level shifter 250 is configured so that the amount of operating current can be switched based on the current control signal ICTRL generated by the control circuit 210. Specifically, the operating current can be switched between three levels: a first current amount I1, a second current amount I2, and a third current amount I3, where I1>I2>I3. The circuit format of the level shifter 250 is not specifically limited, and can be configured using publicly known technology or technology that will be available in the future.

[0097] When the charge pump circuit 282 is disabled, the control circuit 210 controls the operating current I OPis defined as the first current amount I1. That is, the first current amount I1 is defined so that the level shifter 250 can correctly transition between states in response to the high-side control signal HIN_# and can maintain the state after the transition in the PWM mode in which the three-phase inverter 110 switches at a PWM frequency.

[0098] When the control circuit 210 switches the charge pump circuit 282 to the enable state, the control circuit 210 also switches the operating current I OP is defined as the third current amount I3. As described above, the charge pump circuit 282 is enabled in the non-PWM mode (120-degree conduction control), and the high-side control signal HIN_# switches at a slow frequency according to the rotation speed of the motor. Therefore, the level shifter 250 does not require high driving capability, and the minimum operating current I OP The third current amount I3 is determined based on this minimum current amount.

[0099] When the charge pump circuit 282 of a certain phase is in an enabled state, the control circuit 210 controls the operating current I of the level shifter 250 when the output of the other phase changes. OP The operating current I is increased from the third current I3 to the second current I2. After a predetermined time τ4 has elapsed, the operating current I OP is returned to the third current amount I3. For example, the predetermined time τ4 may be set to several hundred μs, for example, 200 μs.

[0100] The above is the configuration of the three-phase gate driver circuit 200. Next, the operating current I OP The control of the above will be explained.

[0101] 9 is a diagram illustrating the control of the operating current of the U-phase level shifter 250 in the three-phase gate driver circuit 200 according to the embodiment. In this example, the three-phase gate driver circuit 200 performs 180-degree conduction control and operates in non-PWM mode. In FIG. 9, the U-phase output voltage V OUTU , V phase output voltage V OUTV, W phase output voltage V OUTW , the enable signal CP_EN of the U phase and the operating current I of the level shifter 250 of the U phase OP The enable signal CP_EN of the U phase is the same as that shown in FIG.

[0102] The operating current I of the U-phase level shifter 250 OP When the charge pump circuit 282 is stopped (CP_EN is low), the first current amount is I1. When the charge pump circuit 282 transitions to an operating state (CP_EN is high), the operating current I OP is reduced to the third current amount I3, thereby reducing the current consumption of the circuit.

[0103] When the output of the other V-phase or W-phase transitions while the charge pump circuit 282 is operating (CP_EN is high), the operating current I OP The current increases to the second current amount I2, and after a predetermined time τ4 has elapsed, returns to the third current amount I3.

[0104] The above is the operating current I of the level shifter 250 in the three-phase gate driver circuit 200. OP The advantage of this control becomes clear when compared with comparative technologies.

[0105] (Comparative Technology 1) FIG. 10 shows the operating current I of the U-phase level shifter 250 in the three-phase gate driver circuit according to the first comparative technique. OP In the comparative technique 1, the operating current I OP is fixed to the first current amount I1.

[0106] In the comparative technique 1, when the charge pump circuit 282 is enabled, the operating current I OP Therefore, the total operating current of the level shifter 250, the high-side driver 240, and other circuits may become larger than the charging current generated by the charging circuit 280. In such a situation, the bootstrap capacitor C BSTis discharged, and the high-side transistor MH cannot maintain the ON state (first state φ1), or the high-side transistor MH cannot transition from the OFF state to the ON state.

[0107] In contrast, in the embodiment, when the charge pump circuit 282 is enabled, the operating current I OP Therefore, the total operating current of the level shifter 250, the high-side driver 240, and other circuits becomes smaller than the charging current generated by the charging circuit 280, and the bootstrap capacitor C BST As a result, the high-side transistor MH can be maintained in the on state (first state φ1), and the high-side transistor MH can transition from the off state to the on state.

[0108] (Comparative Technology 2) FIG. 11 shows the operating current I of the U-phase level shifter 250 in the three-phase gate driver circuit according to the comparative technique 2. OP In the comparative technique 2, the operating current I OP The control circuit 210 controls the operating current I of the level shifter 250 when the charge pump circuit 282 of a certain phase is in an enabled state. OP is fixed to the third current amount I3.

[0109] When the U-phase output is fixed and a transition occurs in the V-phase or W-phase output (time t0), switching noise is mixed into the U-phase bootstrap line, causing the bootstrap voltage V BST In the comparative technology 2, the operating current I OP Since is small, the correct logical value cannot be maintained, and the logical value is inverted. OUTU is the high-level voltage V IN will no longer be able to maintain this.

[0110] In contrast to this, in the embodiment, when the output of the U phase is fixed, if a transition occurs in the output of the V phase or the W phase, the operating current I OP The current I2 increases to the second current amount I2. Therefore, the capability of the level shifter 250 is improved, and even if switching noise is mixed in, the correct logical value can be maintained, and the output voltage V OUTU is the high-level voltage V IN can be maintained.

[0111] 12 is a circuit diagram of a gate driver circuit 200 according to one embodiment. In FIG. 12, a high-side driver 240 and a low-side driver 260 are shown.

[0112] The high-side driver 240 and the low-side driver 260 are constant current drive types. The high-side driver 240 includes a variable current source CS11, a first current mirror circuit CM11, a second current mirror circuit CM12, switches SW11 and SW12, an on-fixed transistor M11, and an off-fixed transistor M12. The variable current source CS11, switches SW11 and SW12, and transistors M11 and M12 are controlled by a high-side control signal HCTRL (not shown) generated by a control circuit 210.

[0113] The variable current source CS11 generates a reference current I0. The amount of reference current I0 can be appropriately switched during the turn-on sequence of the high-side transistor MH. The variable current source CS11 includes current sources CS31, CS32, and CS33, and switches SW31 and SW32. The amount of reference current I0 changes depending on the on / off combination of switches SW31 and SW32. The number of current sources and switches can be designed according to the number of stages for switching the reference current I0.

[0114] The first current mirror circuit CM11 amplifies and mirrors the reference current I0 to generate the turn-on current I ON The high-side driver 240 generates a turn-on current I ONis sourced to the high-side gate pin HG through the switch SW11. CTRL =φ1, the turn-on current I ON The gate voltage V of the high-side transistor MH is HG rises, turning on the high-side transistor MH.

[0115] After the high-side transistor MH is turned on, the on-fixed transistor M11 is fully on, and the gate voltage of the high-side transistor MH becomes high level (bootstrap voltage V BST# ) is fixed.

[0116] The first current mirror circuit CM11 mirrors the reference current I0 to generate a current I1. The second current mirror circuit CM12 amplifies and mirrors the current I1 to generate a turn-off current I OFF The high-side driver 240 generates a turn-off current I OFF The switch SW12 sinks the current from the high-side gate pin LG. CTRL =φ2. The turn-off current I OFF The gate voltage V of the high-side transistor MH is HG drops, and the high-side transistor MH turns off.

[0117] After the low-side transistor MH is turned off, the off-fixed transistor M12 is fully on, and the gate voltage of the high-side transistor MH becomes low (switching voltage V OUT ) is fixed.

[0118] The current source CS31 of the variable current source CS11 is the minimum current amount I of the reference current I0 generated by the variable current source CS11. 0(MIN) This minimum current I 0(MIN) is set to be smaller than the current supply capacity of the charge pump circuit 282. For example, if the current supply capacity of the charge pump circuit 282 is 100 μA, the minimum current amount I 0(MIN)is preferably 10 μA or less, for example 1 μA.

[0119] In states S2 and S5 in which the charge pump circuit 282 is on, the control circuit 210 turns off the switches SW31 and SW32 and controls the variable current source CS11 to supply a minimum current I 0(MIN) This allows the circuit to operate at a low power consumption.

[0120] The low-side driver 260 is configured similarly to the high-side driver 240, and specifically includes a variable current source CS21, a first current mirror circuit CM21, a second current mirror circuit CM22, switches SW21 and SW22, an on-fixed transistor M21, and an off-fixed transistor M22. The variable current source CS21, the switches SW21 and SW22, and the transistors M21 and M22 are controlled by a low-side / high-side control signal LIN_# (not shown) generated by the control circuit 210.

[0121] The control circuit 210 is in a low output state (V OUT Even in the state S6 in which the charge pump circuit 282 is on, the switches SW41 and SW42 are turned off, and the variable current source CS21 is supplied with the minimum current amount I 0(MIN) This allows the circuit to operate at a low power consumption.

[0122] The high-side driver 240 and the low-side driver 260 may be of a constant voltage drive type.

[0123] 13 is a circuit diagram of a charge pump circuit 282 according to one embodiment. The charge pump circuit 282 includes inverters INV1 and INV2, flying capacitors Cf1 and Cf2, and an output capacitor C OUT , and includes switches SW51 to SW54. The charge pump circuit 282 is integrated into the gate driver circuit 200, so the capacitor is on the order of several pF. If the clock frequency is several MHz, for example, 8 MHz, the current supply capacity of the charge pump circuit 282 is about 100 μA. In this example, the output capacitor C OUTOne end of the charge pump circuit 282 is connected to the input of the charge pump circuit 282, and the input voltage V IN is supplied, but this is not the only option. OUT One end of the may be grounded.

[0124] Next, we will explain the uses of motor drive device 100. Motor drive device 100 can be used to control the spindle motor of a hard disk or the lens drive motor of an imaging device. It can also be used to drive a printer head drive motor or a paper feed motor. Motor drive device 100 can also be used to drive motors in electric vehicles, hybrid vehicles, etc.

[0125] The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and processing steps, and that such modifications are also within the scope of the present disclosure and the present invention. Such modifications will be described below.

[0126] The embodiments described using specific terms merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0127] (Addendum) The present specification discloses the following techniques.

[0128] (Item 1) A three-phase gate driver circuit for driving a three-phase inverter, comprising: a U-phase gate driver circuit; a V-phase gate driver circuit; a W-phase gate driver circuit; A controller circuit; Equipped with The U-phase gate driver circuit, the V-phase gate driver circuit, and the W-phase gate driver circuit each include: a bootstrap line to be connected to the bootstrap capacitor; a charging circuit including a charge pump circuit that can be controlled to be turned on and off, the charging circuit being configured to supply a charging current to the bootstrap line when the charge pump circuit is turned on; a switching line to be connected to the output of the inverter of the corresponding phase; a level shifter that level-shifts a high-side control signal that instructs the high-side transistor of a corresponding phase to be turned on or off, and that can switch the operating current among three levels of a first current amount I1, a second current amount I2, and a third current amount I3 that satisfy the relationship I1>I2>I3 according to a current control signal; a high-side driver that drives the high-side transistor of the corresponding phase based on the high-side control signal after level shift by the level shifter; a low-side driver that drives a low-side transistor of a corresponding phase in response to a low-side control signal that instructs the low-side transistor to be turned on or off; Equipped with The controller circuit, in one of the U phase, the V phase, and the W phase, (i) generating the current control signal so that the operating current of the level shifter becomes the first current amount I1 when the charge pump circuit is off; (ii) when a first state in which the high-side transistor is on and the low-side transistor is off continues for a predetermined first determination time, turning on the charge pump circuit and generating the current control signal so that the operating current of the level shifter becomes the third current amount I3; (iii) a three-phase gate driver circuit that generates the current control signal such that the operating current of the level shifter becomes the second current amount I2 when a transition of an output of another phase occurs while the charge pump circuit is on.

[0129] (Item 2) The controller circuit, in the one of the U phase, V phase, and W phase, (iv) The three-phase gate driver circuit according to item 1, wherein the operating current of the level shifter is switched back to the third current amount I3 after a predetermined time has elapsed since the operating current of the level shifter was switched to the second current amount I2.

[0130] (Item 3) The controller circuit, in one of the U phase, the V phase, and the W phase, (v) when a third state in which the high-side transistor and the low-side transistor are both off continues for a predetermined second determination time, the three-phase gate driver circuit turns on the charge pump circuit and generates the current control signal so that the operating current of the level shifter becomes the third current amount I3.

[0131] (Item 4) 4. The three-phase gate driver circuit according to any one of items 1 to 3, wherein the first determination time is longer than a switching period when operating in PWM mode.

[0132] (Item 5) the high-side driver includes a current source and a current mirror circuit that mirrors a current generated by the current source and supplies the current to the gate of the high-side transistor; 5. The three-phase gate driver circuit according to any one of items 1 to 4, wherein when the charge pump circuit is on, the amount of current from the current source is smaller than when the charge pump circuit is off.

[0133] (Item 6) 6. A three-phase gate driver circuit according to any one of items 1 to 5, monolithically integrated on a single semiconductor substrate.

[0134] (Item 7) a three-phase inverter; 7. A three-phase gate driver circuit according to any one of items 1 to 6, which drives the three-phase inverter; A motor drive device comprising:

[0135] (Item 8) A motor; Item 7: A motor driving device for driving the motor; An electronic device comprising: [Explanation of symbols]

[0136] 2 Three-phase motor 100 Motor drive device 102 Power Line 104 output lines 106 Ground Line 110 Three-phase inverter Leg 112 MH high-side transistor ML low-side transistor 200 Three-phase gate driver circuit 202 Bootstrap Line 204 Switching Line 206 Ground Line 210 Control Circuit 212 Logic Circuits 214 Timer Circuit 220 Gate driver circuit 280 charging circuit 282 Charge pump circuit 284 Current Source 286 Rectifier 240 High Side Driver 250 Level Shifter 260 Low Side Driver CS11 Variable Current Source CM11 1st current mirror circuit CM12 Second current mirror circuit SW11, SW12 switches M11 fixed on transistor M12 fixed off transistor CS21 Variable Current Source CM21 1st current mirror circuit CM22 Second current mirror circuit SW21, SW22 switches M21 fixed on transistor M22 fixed off transistor

Claims

1. A three-phase gate driver circuit for driving a three-phase inverter, comprising: a U-phase gate driver circuit; a V-phase gate driver circuit; a W-phase gate driver circuit; A controller circuit; Equipped with The U-phase gate driver circuit, the V-phase gate driver circuit, and the W-phase gate driver circuit each include: a bootstrap line to be connected to the bootstrap capacitor; a charging circuit including a charge pump circuit that can be controlled to be turned on and off, the charging circuit being configured to supply a charging current to the bootstrap line when the charge pump circuit is turned on; a switching line to be connected to the output of the inverter of the corresponding phase; The high-side control signal that instructs the high-side transistor of the corresponding phase to be turned on or off is level-shifted, and the operating current is controlled according to the current control signal. １ >I ２ >I ３ The first current amount I １ , second current amount I ２ , third current amount I ３ A level shifter that can be switched between three levels, a high-side driver that drives the high-side transistor of the corresponding phase based on the high-side control signal after level shift by the level shifter; a low-side driver that drives a low-side transistor of a corresponding phase in response to a low-side control signal that instructs the low-side transistor to be turned on or off; Equipped with The controller circuit is configured to: (i) when the charge pump circuit is off, the operating current of the level shifter is the first current amount I １ generating the current control signal so that (ii) When a first state in which the high-side transistor is on and the low-side transistor is off continues for a predetermined first determination time, the charge pump circuit is turned on, and the operating current of the level shifter is increased to the third current amount I ３ generating the current control signal so that (iii) when a transition of the output of another phase occurs while the charge pump circuit is on, the operating current of the level shifter is equal to or exceeds the second current amount I ２ and a three-phase gate driver circuit for generating the current control signals such that:

2. The controller circuit, in the one of the U phase, the V phase, and the W phase, (iv) adjusting the operating current of the level shifter to the second current amount I ２ After a predetermined time has elapsed since the switching to the third current amount I ３ 2. The three-phase gate driver circuit of claim 1, wherein

3. The controller circuit is configured to: (v) when a third state in which the high-side transistor is off and the low-side transistor is off continues for a predetermined second determination time, the charge pump circuit is turned on, and the operating current of the level shifter is set to the third current amount I ３ 3. The three-phase gate driver circuit according to claim 1, wherein the current control signals are generated so that:

4. 3. The three-phase gate driver circuit according to claim 1, wherein the first determination time is longer than a switching period when the three-phase gate driver circuit operates in a PWM (Pulse Width Modulation) mode.

5. the high-side driver includes a current source and a current mirror circuit that mirrors a current generated by the current source and supplies the current to the gate of the high-side transistor; 3. The three-phase gate driver circuit according to claim 1, wherein when said charge pump circuit is on, the amount of current from said current source is smaller than when said charge pump circuit is off.

6. 3. The three-phase gate driver circuit according to claim 1, wherein the three-phase gate driver circuit is monolithically integrated on a single semiconductor substrate.

7. a three-phase inverter; a three-phase gate driver circuit according to claim 1 or 2 that drives the three-phase inverter; A motor drive device comprising:

8. A motor; a motor drive device according to claim 7 that drives the motor; An electronic device comprising:

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