Multilayer capacitor and circuit board containing multilayer capacitor

Abstract

To provide a compact and low-resistance multilayer capacitor, and a circuit board and a package that contain the multilayer capacitor.SOLUTION: A main body 135 of a capacitor contains sets of alternating dielectric layers and internal electrode layers 105. Each internal electrode layer includes a top edge, an opposite bottom edge, and two side edges 105a, 105b that define a main body of the internal electrode layer, and includes at least one lead tab 120 extending from the top edge 105c and at least one lead tab 130 extending from the bottom edge. External terminals connected to the internal electrode layers are formed on a top surface and a bottom surface of the capacitor.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a U.S. Provisional Patent Application No. 62 / 50, filed May 15, 2017. This application claims the benefit of application No. 6,130, the entire contents of which are incorporated herein by reference. [Background technology]

[0002]

[0002] A multilayer capacitor is generally These capacitors are constructed by arranging multiple dielectric layers and internal electrode layers in a stack. During fabrication, the stacked dielectric and internal electrode layers are pressed and sintered to achieve a substantially unitary capacitor body. Various configurations and designs have been used for the dielectric and internal electrode layers in attempts to improve the performance of these capacitors.

[0003] However, rapid changes are occurring in the electronics industry that require new performance standards. and these configurations are commonly operated. In particular, various application design considerations have created a need to redefine capacitor parameters and their performance in high speed environments, especially in light of faster and higher density integrated circuits. For example, higher currents, higher density circuit boards, and rising costs have all led to an emphasis on the need for better and more efficient capacitors. In addition, the design of various electronic components has been driven by general industry trends toward miniaturization and increased functionality.

[0004]

[0004] Therefore, there is a need to provide a capacitor with improved operating characteristics. Therefore, some applications would also benefit from providing a capacitor that can have a smaller footprint on a circuit board. Summary of the Invention [Means for solving the problem]

[0005]

[0005] In accordance with one embodiment of the present invention, a multilayer capacitor is disclosed. The capacitor includes a body including a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set of alternating dielectric layers and internal electrode layers includes a first internal electrode layer and a second internal electrode layer. Each internal electrode layer includes an upper edge, a lower edge opposite the upper edge, and two side edges extending between the upper and lower edges that define the body of the internal electrode layer. Each internal electrode layer includes at least one lead tab extending from the upper edge of the body of the internal electrode layer and at least one lead tab extending from the lower edge of the body of the internal electrode layer. The lead tab extending from the upper edge of the body of the internal electrode layer is offset from the side edges of the body of the internal electrode layer. The lead tab extending from the lower edge of the body of the internal electrode layer is offset from the side edges of the body of the internal electrode layer. The capacitor includes external terminals electrically connected to the internal electrode layers, the external terminals being formed on the upper surface of the capacitor and on the lower surface of the capacitor opposite the upper surface of the capacitor.

[0006]

[0006] Other features and aspects of the present invention are described in more detail below.

[0007] a full and enabling disclosure of this invention, including the best mode thereof, to one of ordinary skill in the art; are more particularly described in the remainder of the specification with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0007] [Figure 1A]

[0008] 1 is a general top and side exterior perspective view of one embodiment of a two-row, two-column packaged capacitor in accordance with the present invention. [Figure 1B]

[0009] 1B is a top external perspective view of the internal electrode layers of the capacitor of FIG. 1A. FIG. [Figure 1C]

[0010] 1C is a three-dimensional top and side exterior perspective view of the internal electrode layers of the capacitor of FIGS. 1A and 1B. FIG. [Figure 1D]

[0011] 1B and 1C are top and side perspective views of the capacitor of FIG. 1A including the set of alternating dielectric and internal electrode layers of FIG. 1B and FIG. 1C. [Figure 2A]

[0012] 1 is a general top and side exterior perspective view of one embodiment of a two-row, four-column packaged capacitor in accordance with the present invention. [Figure 2B]

[0013] 2B is a top external perspective view of the internal electrode layers of the capacitor of FIG. 2A. FIG. [Figure 2C]

[0014] 2C is a three-dimensional top and side exterior perspective view of the internal electrode layers of the capacitor of FIGS. 2A and 2B. FIG. [Figure 2D]

[0015] 2B and 2C are top and side perspective views of the capacitor of FIG. 2A including the set of alternating dielectric and internal electrode layers of FIG. 2B and FIG. 2C. [Figure 3A]

[0016] 1 is a general top and side exterior perspective view of one embodiment of a four-by-four packaged capacitor in accordance with the present invention; [Figure 3B]

[0017] 3B and 3C are top and side perspective views of the capacitor of FIG. 3A including the set of alternating dielectric and internal electrode layers of FIGS. 2B and 2C. [Figure 4]

[0018] 1 is a side view of a printed circuit board and an integrated circuit package including the packaged capacitor of the present invention. [Figure 5]

[0019] 1 is a side view of a printed circuit board and an integrated circuit package including a plurality of prior art multilayer ceramic capacitors. DETAILED DESCRIPTION OF THE INVENTION

[0008]

[0020] It will be understood by those skilled in the art that this discussion is merely a description of exemplary embodiments and is not intended to limit the broad aspects of the present invention.

[0021] Generally speaking, the present invention is directed to a multilayer capacitor. The multilayer capacitor includes a plurality of capacitive elements within a body. That is, the multilayer capacitor includes a plurality of capacitive elements within a single, integrated package. In this regard, the multilayer capacitor includes a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers. Each set of alternating dielectric layers and internal electrode layers defines a capacitive element.

[0009]

[0022] The particular arrangement of the capacitive elements within a single, integrated package (i.e., a single body) can provide several advantages. For example, as illustrated in FIG. 4 and discussed further below, the capacitors of the present invention may be mounted on a circuit board as surface-mount capacitors, which can provide a smaller footprint on the circuit board. This, in turn, can also allow for a reduction in the size of the circuit board.

[0010]

[0023] Additionally, in certain applications, it is desirable to keep inductance (i.e., parasitic inductance) as low as possible. Use of the capacitor of the present invention allows for a substantial reduction in inductance. In particular, minimizing the distance or path of the ground connection can help reduce inductance. Generally, use of the capacitor of the present invention (as illustrated in FIG. 4) can allow for at least an order of magnitude reduction in inductance compared to using multiple individual multilayer ceramic capacitors (as illustrated in FIG. 5). For example, use of the capacitor of the present invention can result in an inductance on the order of picohenries, or even femtohenries, compared to prior art capacitors exhibiting greater inductance. Generally, the inductance may be less than 1 nanohenry. In particular, the inductance may be 900 picohenries or less, for example 750 picohenries or less, for example 500 picohenries or less, for example 400 picohenries or less, for example 250 picohenries or less, for example 100 picohenries or less, for example 50 picohenries or less, for example 25 picohenries or less, For example, it may be 15 picohenries or less, such as 10 picohenries or less. The inductance may be 1 femtohenries or more, such as 25 femtohenries or more, such as 50 femtohenries or more, such as 100 femtohenries or more, such as 250 femtohenries or more, such as 500 femtohenries or more, such as 750 femtohenries or more. Minimizing such inductance can contribute to good performance, especially good decoupling performance, especially under fast transient conditions.

[0011]

[0024] Additionally, the capacitor may provide a desired capacitance. In particular, the capacitance may be 1,000 μF or less, e.g., 750 μF or less, e.g., 500 μF or less, e.g., 250 μF or less, e.g., 100 μF or less, e.g., 50 μF or less, e.g., 25 μF or less, e.g., 10 μF or less, e.g., 5 μF or less, e.g., 2.5 μF or less, e.g., 1 μF or less, e.g., 0.75 μF or less, e.g., 0.5 μF or less. The capacitance may be 1 pF or more, e.g., 10 pF or more, e.g., 25 pF or more, e.g., 50 pF or more, e.g., 100 pF or more, e.g., 250 pF or more, e.g., 500 pF or more, e.g., 750 pF or more. Capacitance may be measured using common techniques known in the art.

[0012]

[0025] Furthermore, the capacitor may provide a desired resistance. In particular, the resistance may be 100 mOhm or less, such as 75 mOhm or less, such as 50 mOhm or less, such as 40 mOhm or less, such as 30 mOhm or less, such as 25 mOhm or less, such as 20 mOhm or less, such as 15 mOhm or less, such as 10 mOhm or less, such as 5 mOhm or less. The resistance may be 0.01 mOhm or more, such as 0.1 mOhm or more, such as 0.25 mOhm or more, such as 0.5 mOhm or more, such as 1 mOhm or more, such as 1.5 mOhm or more, such as 2 mOhm or more, such as 5 mOhm or more, such as 10 mOhm or more. Resistance may be measured using common techniques known in the art.

[0013]

[0026] 4 , capacitor 408 may be mounted (e.g., surface mounted) on circuit board 406, which includes a substrate (e.g., an insulating layer) having an upper surface and a lower surface. Circuit board 406 has a plurality of current paths (not shown) defined therein. The external terminals of capacitor 408 are each in electrical communication with a predetermined current path of circuit board 406. Additionally, the external terminals of capacitor 408 may be physically connected to circuit board 406 using any method commonly known in the art, such as common soldering techniques.

[0014]

[0027] 4, an integrated circuit package 402 may also be provided on a circuit board 406. The integrated circuit package 402 may be connected to the circuit board 406 using a ball grid array 404. The circuit board may further include a processor 400. The processor 400 may also be connected to the integrated circuit package 402 using a ball grid array 412.

[0015]

[0028] In general, the ball grid array 404 may be configured with a pitch of 1.5 mm or less, such as 1.25 mm or less, such as 1 mm or less, such as 0.8 mm or less, such as 0.6 mm or less, and 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more.

[0016]

[0029] Additionally, integrated circuit package 402 may also be connected to circuit board 406 using capacitor 408 as defined herein. In this regard, the internal electrode layers of the capacitor may be positioned such that they are orthogonal to the horizontal plane of circuit board 406 and integrated circuit package 402. In other words, the internal electrode layers of capacitor 408 may be positioned such that they are substantially non-parallel to circuit board 406. For example, capacitor 408 may be positioned such that capacitor 408 is "sandwiched" between integrated circuit package 402 and circuit board 406. In this regard, capacitor 408 is directly connected to integrated circuit package 402 and circuit board 406. For example, capacitor 408 may be connected (e.g., physically and / or electrically) to circuit board 406 and / or circuit package 402 using any commonly known method, such as common soldering techniques.

[0017]

[0030] By using capacitors in the above arrangement, capacitors 408 may allow for the removal of a portion of the original ball grid array 404. However, capacitors 408 may still be surrounded by ball grid array 404, as illustrated in FIG.

[0018]

[0031] In contrast, a prior art circuit board 506 is illustrated in Figure 5. Circuit board 506 includes processor 500, integrated circuit package 502, and ball grid arrays 504 and 512. However, rather than using a single integrated capacitor package like capacitor 408 of Figure 4, circuit board 506 of Figure 5 uses multiple discrete multilayer ceramic capacitors 508. However, for the reasons discussed above, this configuration using a single integrated capacitor may enable various advantages and benefits compared to circuit boards using multiple discrete multilayer ceramic capacitors.

[0019]

[0032] One notable advantage of the capacitor and configuration of the present invention compared to using multiple individual multilayer ceramic capacitors relates to direct power and ground connections. As illustrated in FIG. 4, a capacitor 408 of the present invention may be directly connected to an integrated circuit package 402 and a circuit board 406, such as a printed circuit board. This direct connection allows current 410 to flow through the capacitor, thereby providing a direct power and ground connection. In contrast, in the prior art, as illustrated in FIG. 5, certain multilayer capacitors 508 cannot make direct connections with the circuit board 506 and the integrated circuit package 502 for various reasons, including slight differences in height. Because of such non-uniformity issues, making connections using multiple individual multilayer capacitors can be difficult. As a result, as illustrated in FIG. 5, two current paths exist: (1) current 514 between the processor 500 and the individual capacitor 508, and (2) current 516 between the processor 500 and the circuit board 516. Such a configuration does not provide a direct power and ground connection.

[0020]

[0033] In addition to the above, although not illustrated herein, in one embodiment, the integrated circuit package itself may include a stacked capacitor. In this regard, the capacitor may be embedded directly within the package. Such incorporation of the capacitor may allow for a reduction in size, which may be beneficial for various electronic applications.

[0021]

[0034] As indicated above, the present invention includes a stacked capacitor including multiple capacitive elements within a single, integrated package. The capacitor includes a top surface and a bottom surface opposite the top surface. The capacitor also includes at least one side surface extending between the top and bottom surfaces. The capacitor may include at least three sides, e.g., at least four sides. In one embodiment, the capacitor includes a total of at least six surfaces (e.g., one top surface, one bottom surface, and four side surfaces). For example, the capacitor may have a parallelepiped shape, e.g., a rectangular parallelepiped.

[0022]

[0035] Additionally, the capacitor may have a desired height. For example, the height may be 10 microns or more, such as 25 microns or more, for example 50 microns or more, for example 100 microns or more, for example 200 microns or more, for example 250 microns or more, for example 300 microns or more, for example 350 microns or more, for example 500 microns or more, for example 1,000 microns or more, for example 2,000 microns or more. The height may be 5,000 microns or less, for example 4,000 microns or less, for example 2,500 microns or less, for example 2,000 microns or less. The height of the capacitor may be within 10%, such as within 7%, such as within 5%, such as within 3%, such as within 2%, such as within 1% of the height (or diameter) of the balls in the ball grid array. For example, such height may be the original height before any reflow.

[0023]

[0036] Generally, the multilayer capacitor includes a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers, and also includes external terminals electrically connected to the internal electrode layers, the external terminals being formed on a top surface of the capacitor and a bottom surface of the capacitor opposite the top surface of the capacitor.

[0024]

[0037] Generally, the capacitor includes at least two sets of alternating dielectric layers and internal electrode layers. The capacitor may include at least three sets, e.g., at least four sets, of alternating dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of sets of alternating dielectric layers and internal electrode layers and is not necessarily limited to this number. In addition, the sets of alternating dielectric layers and internal electrode layers may be separated from adjacent sets by a particular distance. For example, the distance may be greater than the thickness of an individual dielectric layer within the set. In particular, the distance may be at least two times, e.g., at least three times, e.g., at least five times, e.g., at least ten times the thickness of the dielectric layers within the set.

[0025]

[0038] The first set of alternating dielectric and internal electrode layers and the second set of alternating dielectric and internal electrode layers may form at least a portion of the body of the capacitor. By arranging the dielectric and internal electrode layers in a stacked or layered configuration, the capacitor may be referred to as a multilayer capacitor, particularly a multilayer ceramic capacitor, for example, when the dielectric layers comprise ceramic.

[0026]

[0039] Each set of alternating dielectric and internal electrode layers comprises dielectric layers alternating with the internal electrode layers, particularly including first and second internal electrode layers interleaved in opposing and spaced apart relationship with a dielectric layer located between each internal electrode layer.

[0027]

[0040] Generally, the thickness of the dielectric layers and the internal electrode layers is not limited and may be any thickness as desired depending on the performance characteristics. For example, the thickness of the internal electrode layers may be, but is not limited to, about 500 nm or more, e.g., about 1 μm or more, e.g., about 2 μm or more to about 10 μm or less, e.g., about 5 μm or less, e.g., about 4 μm or less, e.g., about 3 μm or less, e.g., about 2 μm or less. For example, the internal electrode layers may have a thickness of about 1 μm to about 2 μm.

[0028]

[0041] Additionally, the present invention is not necessarily limited by the number of internal electrode layers per set of alternating dielectric layers and internal electrode layers, or in the entire capacitor. For example, each set may include 10 or more, e.g., 25 or more, e.g., 50 or more, e.g., 100 or more, e.g., 200 or more, e.g., 300 or more, e.g., 500 or more, e.g., 600 or more, e.g., 750 or more, e.g., 1,000 or more internal electrode layers. Each set may have 5,000 or less, e.g., 4,000 or less, e.g., 3,000 or less, e.g., 2,000 or less, e.g., 1,500 or less, e.g., 1,000 or less, e.g., 750 or less, e.g., 500 or less, e.g., 400 or less, e.g., 300 or less, e.g., 250 or less, e.g., 200 or less, e.g., 175 or less, e.g., 150 or less internal electrode layers. The entire capacitor may also include the aforementioned number of electrode layers.

[0029]

[0042] The internal electrode layer has an upper edge and a lower edge opposite the upper edge. The inner electrode layer has two side edges extending between an upper edge and a lower edge. In one embodiment, the side edges, upper edge, and lower edge define a body of the inner electrode layer. Generally, the body can have a rectangular configuration or shape.

[0030]

[0043] Generally, the upper and lower edges may have the same dimension (e.g., length). The side edges may have the same dimension (e.g., height). Generally, the side edges may have a dimension (e.g., height) that is shorter than the dimension (e.g., length) of the upper and / or lower edges. In this regard, the height of the side edges of the internal electrode layers may be shorter because the height of the side edges extends between the upper and lower surfaces of the capacitor, since the length of the upper and / or lower edges of the internal electrode layers extends between the sides of the capacitor. In other words, the internal electrode layers may have upper and / or lower edges that are larger in dimension than the side edges that are smaller in dimension. In this regard, the "short" sides of the layers may be aligned in the height direction of the capacitor.

[0031]

[0044] The internal electrode layers have lead tabs extending from the body of the layer. The lead tabs extend from the top and bottom edges. In other words, the internal electrode layers may have lead tabs extending from the "long" sides or edges of the layer. The lead tabs may extend to the edge of the dielectric layer and / or to the surface of the capacitor. For example, when in a stacked configuration, the leading edge of the lead tab may extend to the edge of the dielectric layer. Such leading edge may be used to form an external terminal. Additionally, the edge may have at least one lead tab extending from the edge, e.g., at least two lead tabs, e.g., at least three lead tabs, e.g., at least four lead tabs.

[0032]

[0045] Each upper and lower edge of the internal electrode layer may have an equal number of lead tabs extending therefrom. For example, each edge may have at least one lead tab extending therefrom. In another embodiment, each edge may have at least two lead tabs extending therefrom. However, it should be understood that the present invention may include any number of lead tabs extending from an internal electrode layer and is not necessarily limited thereto.

[0033]

[0046] The lead tabs extend from inner portions of the upper and lower edges of the body of the internal electrode layer. In this regard, the lead tabs may not extend directly from the side edges of the internal electrode layer. In other words, the lead tabs may be offset from the side edges of the internal electrode layer. This offset may be such that the lead tabs are offset and positioned between the side edges of the internal electrode layer, particularly between the side edges of the internal electrode layer and the center of the internal electrode layer.

[0034]

[0047] The lead tabs extending from the upper edge of each internal electrode layer and the lower edge of the same internal electrode layer may be offset the same distance from the side edges. In this regard, at least one lateral edge (i.e., an edge aligned in the height direction) of the lead tabs may be substantially aligned.

[0035]

[0048] When each edge includes at least two lead tabs, the first lead tab on the top edge may be offset from the side edge by the same distance as the first lead tab on the bottom edge. Additionally, the second lead tab on the top edge may be offset from the side edge by the same distance as the second lead tab on the bottom edge. In this regard, the side edges of the respective lead tabs may be substantially aligned.

[0036]

[0049] Similarly, the length of the lead tab extending from the top edge (ie, extending longitudinally from one side to another) may be the same as the length of the lead tab extending from the bottom edge.

[0037]

[0050] By substantially aligned, it is meant that the offset of one lateral edge of the first lead tab and / or the second lead tab on the upper edge from the side edge is greater than the offset of the first lead tab and / or the second lead tab on the lower edge. means within + / - 10%, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5% of the offset from the side edge of the corresponding lateral edge of the second lead tab.

[0038]

[0051] However, it should be understood that the offset of a first lead tab on the top and / or bottom edge from a side edge may be different from the offset of a second lead tab on the same edge from the opposite side edge.

[0039]

[0052] The distance between adjacent exposed lead tabs of the internal electrode layers in a given row can be specifically designed to ensure inductive formation of the termination. Such a distance between exposed lead tabs of the internal electrode layers in a given row may be about 10 microns or less, for example, about 8 microns or less, for example, about 5 microns or less, for example, about 4 microns or less, for example, about 2 microns or less, for example, about 1.5 microns or less, for example, about 1 micron or less. This distance may be about 0.25 microns or more, for example, about 0.5 microns or more, for example, about 1 micron or more, for example, about 1.5 microns or more, for example, about 2 microns or more, for example, about 3 microns or more. However, it should be understood that such a distance is not necessarily limited.

[0040]

[0053] Additionally, the distance between adjacent columnar stacks of electrode tabs may be, but is not limited to, at least twice the distance between adjacent lead tabs in a given column to ensure that individual terminations do not intermingle. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is approximately four times the distance between adjacent exposed electrode tabs in a particular stack. However, such distances may vary depending on the desired capacitance performance and circuit board configuration.

[0041]

[0054] The lead tabs of the first and second internal electrode layers in a set of alternating dielectric and internal electrode layers are offset from each other in the longitudinal direction. That is, the lead tabs of each internal electrode layer may be symmetrically offset by a specific distance from the centerline of the internal electrode layer and / or dielectric layer (e.g., from the longitudinal centerline or with respect to a vertical line). That is, the lead tabs of each internal electrode layer may be symmetrically offset with respect to the vertical line of the internal electrode layer and / or dielectric layer. Nevertheless, a gap region is formed between the lead tabs of each internal electrode layer.

[0042]

[0055] Additionally, an internal electrode layer may be symmetrical in a given direction regardless of the number of lead tabs extending therefrom. For example, the lead tabs may be symmetrical about a horizontal line passing through the center of the body of the internal electrode layer (i.e., a line extending from the center of one side edge of the internal electrode layer to the center of the other side edge).

[0043]

[0056] As shown above, the capacitor includes a first set of alternating dielectric and internal electrode layers and a second set of alternating dielectric and internal electrode layers. In one embodiment, the distance between the first internal electrode layer of one set and the last internal electrode layer of another set may be greater than the distance between adjacent internal electrode layers within a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set may be greater than the distance between the first internal electrode layer of the first set and the second internal electrode layer.

[0044]

[0057] The capacitor of the present invention also includes external terminals on the top and bottom surfaces. In one particular embodiment, external terminals may not be present on the sides of the capacitor.

[0058] The external terminals include at least one first polarity terminal and at least one second opposite polarity terminal. The capacitor has at least one, e.g., at least two, e.g., at least four, For example, the capacitor may include at least six, e.g., at least eight, first polarity terminals and / or second opposite polarity terminals. Additionally, the capacitor may include the above-mentioned number of terminals on the underside of the capacitor.

[0045]

[0059] The capacitor may include an equal number of first polarity terminals and / or second polarity terminals on the upper surface and the lower surface of the capacitor. The number of first polarity terminals may be equal to the number of second, opposite polarity terminals on the upper surface of the capacitor. The number of first polarity terminals may be equal to the number of second, opposite polarity terminals on the lower surface of the capacitor. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second, opposite polarity terminals present on the upper and lower surfaces of the capacitor.

[0046]

[0060] Generally, like-polarity terminals on the lower surface of a capacitor corresponding to a particular set of alternating dielectric and internal electrode layers are electrically connected to like-polarity terminals on the upper surface of the capacitor. The like-polarity terminals located on the upper and lower surfaces of a capacitor need not be interdigitated. In this regard, corresponding like-polarity terminals on the upper and lower surfaces need not be offset by terminal position, but instead may be positioned directly above or below another like-polarity terminal on the opposing upper or lower surface. In other words, corresponding like-polarity terminals corresponding to a particular set of alternating dielectric and internal electrode layers, and in particular corresponding lead tabs of such a set, may be substantially aligned. By substantially aligned, it is meant that the offset of one lateral edge of a polarity terminal on the upper surface from a side edge is within + / −10%, e.g., within + / −5%, e.g., within + / −4%, e.g., within + / −3%, e.g., within + / −2%, e.g., within + / −1%, e.g., within + / −0.5%, of the offset of the corresponding polarity terminal on the lower surface from a side edge.

[0047]

[0061] In general, the pitch of the external terminals (i.e., the nominal distance between centers, also called center-to-center distance) may be dictated by the particular circuit board configuration. The pitch between external terminals in one direction (i.e., the x or y direction) may be the same as the pitch between adjacent external terminals in the other direction (i.e., the y or x direction, respectively). That is, the pitch between any two adjacent external terminals may be substantially the same as the pitch between any other two adjacent external terminals.

[0048]

[0062] The pitch may be about 0.1 mm or more, for example, about 0.2 mm or more, for example, about 0.3 mm or more, for example, 0.4 mm or more, for example, about 0.5 mm or more, for example, about 0.6 mm or more, for example, about 0.7 mm or more, for example, about 0.8 mm or more, for example, about 0.9 mm or more, for example, about 1.0 mm or more. The pitch may be about 2.0 mm or less, for example, about 1.5 mm or less, for example, about 1.4 mm or less, for example, about 1.3 mm or less, for example, about 1.2 mm or less, for example, about 1.1 mm or less, for example, about 1.0 mm or less. For example, the pitch may be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. In particular, the pitch may be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the pitch may be about 0.6 mm, such as 0.6 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%. In another embodiment, the pitch may be about 0.8 mm, such as 0.8 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%. In a further embodiment, the pitch may be about 1 mm, such as 1 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%.

[0049]

[0063] As shown above, the extension of the leading edge of the lead tab can aid in the formation of an external terminal. In this regard, the lead tab on the first internal electrode layer and the lead tab on the second internal electrode layer The pitch between the lead tabs on the first internal electrode layer and the lead tabs on the second internal electrode layer may be the same as that described above, i.e., the pitch between the lead tabs on the first internal electrode layer and the lead tabs on the second internal electrode layer may be substantially the same as the pitch between the corresponding external terminals that the lead tabs are used to form.

[0050]

[0064] Additionally, the external terminals may be positioned similarly to the configuration of the ball grid array. For example, the external terminals may be provided to make contacts typically used by ball grid arrays, particularly surrounding ball grid arrays. In this regard, the pitch of the external terminals may be the same as the pitch of the surrounding ball grid array. That is, the pitch may be within 10%, e.g., within 5%, e.g., within 2%, e.g., within 1%, e.g., within 0.5%, e.g., within 0.1%, of the pitch of the surrounding ball grid array.

[0051]

[0065] Additionally, like a ball grid array, the external terminals may be arranged in rows and columns. That is, the external terminals may be arranged so that they exist in at least two rows and at least two columns. For example, the external terminals may exist in at least two rows, e.g., at least three rows, e.g., at least four rows. The number of rows may be determined by the number of different sets of alternating dielectric layers and internal electrode layers. Additionally, the external terminals may exist in at least two columns, e.g., at least three columns, e.g., at least four columns. The number of columns may be determined by the number of different columnar tabs of the internal electrodes.

[0052]

[0066] The capacitor of the present invention can be further described according to the embodiments as illustrated in FIGS. 1A-1D, 2A-2D, and 3A-3B.

[0067] 1A illustrates capacitor 10 in a two-column, two-row configuration. That is, the capacitor includes two terminals along each dimension of the top and bottom surfaces. In this regard, capacitor 10 includes a total of four external terminals 12, 14 on the top surface and four corresponding external terminals (not shown) on the bottom surface, with the external terminals on the top surface electrically connected to the corresponding external terminals on the bottom surface.

[0053]

[0068] The capacitor 10 of Figure 1A includes external terminals 12, 14 and two sets of alternating dielectric and internal electrode layers 110 as illustrated in Figure 1D. As illustrated in Figures 1B and 1C, each set of alternating dielectric and internal electrode layers 110 includes alternating internal electrode layers 105, 115 and dielectric layers (not shown).

[0054]

[0069] Typically, the internal electrode layers 105, 115 include at least one lead tab 120, 130, 140, 150 extending from the upper and lower edges of the body of the internal electrode layer. Typically, the lead tabs 120, 130, 140, 150 of the internal electrode layers 105, 115 extend to the upper and lower surfaces of the capacitor to help form external terminals. In this regard, the lead tabs 120, 130, 140, 150 may be exposed at the upper and lower surfaces of the capacitor, enabling connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 120, 130, 140, 150 may include leading edges 123, 133, 143, 153 that extend to the edge of the dielectric layer to enable the formation of external terminals.

[0055]

[0070] 1B and 1C, the first internal electrode layer 105 includes one lead tab 120, 130 along the upper edge 105c and the lower edge 105d and extending from the body 135. The second internal electrode layer 115 includes one lead tab 140, 150 along the upper edge and the lower edge and extending from the body 145.

[0056]

[0071] The lead tabs 120, 130 on the upper and lower edges of the first internal electrode layer 105 may be aligned vertically. The edges 121, 122 may be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. In other words, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be offset from the side edges 105a-b by the same distance (indicated by "O") as the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c.

[0057]

[0072] However, it should be understood that both lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with both lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. In other words, both lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be offset from the side edges 105a-b by the same distance as both lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c.

[0058]

[0073] Similarly, the lead tabs 140, 150 on the upper and lower edges of the second internal electrode layer 115 may be aligned vertically. That is, the lateral edges 141, 142 of the first lead tab 140 along the upper edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the lower edge opposite the upper edge. In one embodiment, both lateral edges 141, 142 of the first lead tab 140 along the upper edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tab on the upper edge and the lateral edges of the first lead tab on the lower edge as described with respect to the internal electrode layer 105 may also apply to the internal electrode layer 115.

[0059]

[0074] In such an arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The size of each gap may be substantially the same.

[0060]

[0075] Lead tabs 120 and 140 may be arranged in parallel with lead tabs 130 and 150 extending from internal electrode layers 105 and 115, respectively, such that lead tabs extending from alternating electrode layers 105 and 115 may be aligned within respective rows. For example, lead tabs 120 and 130 of internal electrode layer 105 may be arranged in a stacked configuration, while lead tabs 140 and 150 of internal electrode layer 115 may be arranged in a stacked configuration, respectively.

[0061]

[0076] It will be appreciated that lead tab 120 connects to external terminal 12, while lead tab 140 connects to external terminal 14. Thus, each lead tab 120 is nested with its respective lead tab 140 in a manner similar to external terminals 12 and 14. The nested lead tabs can provide multiple adjacent current injection points on the associated primary electrode portion.

[0062]

[0077] Additionally, the capacitor 10 of Figure 1A includes at least one first polarity terminal and at least one second opposite polarity terminal on the top surface. Although not shown, the bottom surface also includes at least one first polarity terminal and a second opposite polarity terminal. In particular, Figure 1A includes two positive terminals 12 and two negative terminals 14 on the top surface.

[0063]

[0078] 1A-1D, the capacitor includes four external terminals on each surface, and each internal electrode layer includes at least one lead tab extending from an upper edge and a lower edge. However, as noted above, the present invention is not limited by the number of external terminals and / or the number of lead tabs extending from the upper and / or lower edges.

[0064]

[0079] For example, FIG. 2A illustrates a capacitor 20 that includes eight external terminals on each surface and two lead tabs extending from the top and bottom surfaces of each internal electrode layer.

[0080] 2A, capacitor 20 has a two-by-four configuration. That is, the capacitor includes two terminals along one dimension and four terminals along another dimension on the top and bottom surfaces. In this regard, the capacitor includes a total of eight external terminals 22a-b, 24a-b on the top surface and eight corresponding external terminals (not shown) on the bottom surface, with the external terminals on the top surface electrically connected to the corresponding external terminals 22a-b, 24a-b on the bottom surface.

[0065]

[0081] The capacitor 20 of Figure 2A includes external terminals 22a-b, 24a-b and two sets of alternating dielectric and internal electrode layers 210 as illustrated in Figure 2D. As illustrated in Figures 2B and 2C, each set of alternating dielectric and internal electrode layers 210 includes internal electrode layers 205, 215 and dielectric layers (not shown) in an alternating arrangement.

[0066]

[0082] Typically, the internal electrode layers 205, 215 include at least one lead tab 220a-b, 230a-b, 240a-b, 250a-b extending from upper and lower edges of the body of the internal electrode layer. Typically, the lead tabs 220a-b, 230a-b, 240a-b, 250a-b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor to help form external terminals. In this regard, the lead tabs 220a-b, 230a-b, 240a-b, 250a-b may be exposed at the upper and lower surfaces of the capacitor to enable connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 220a-b, 230a-b, 240a-b, 250a-b may include leading edges 223a-b, 233a-b, 243a-b, 253a-b that extend to the edge of the dielectric layer and allow for the formation of external terminals.

[0067]

[0083] 2B and 2C, the internal electrode layers 205, 215 include at least two lead tabs 220a-b, 230a-b, 240a-b, 250a-b along their upper and lower edges. As illustrated in FIGS. 2B and 2C, the first internal electrode layer 205 includes two lead tabs 220a-b, 230a-b along each of the upper and lower edges 205c, 205d and extending from the body 235. The second internal electrode layer 215 includes two lead tabs 240a-b, 250a-b along each of the upper and lower edges and extending from the body 245.

[0068]

[0084] The lead tabs 220a-b, 230a-b on the upper edge 205c and lower edge 205d of the first internal electrode layer 205 may be aligned vertically. That is, the lateral edges 221a, 222a of the first lead tab 220 along the upper edge 205c may be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the lower edge 205d opposite the upper edge 205c. In other words, the lateral edges 221a, 222a of the first lead tab 220 along the upper edge 205c may be offset from the side edges 205a-b by the same distance (indicated by "O") as the lateral edges 231a, 232a of the first lead tab 230 along the lower edge 205d opposite the upper edge 205c. Additionally, both lateral edges 221 a, 222 a of first lead tab 220 along top edge 205 c may be aligned with lateral edges 231 a, 232 a of first lead tab 230 along bottom edge 205 d opposite top edge 205 c, i.e., both lateral edges may be offset the same distance from side edges 205 a-b.

[0069]

[0085] When the upper edge 205c and the lower edge 205d include at least two lead tabs 220a-b, 230a-b, at least one lateral edge of each lead tab on the upper edge 205c may be aligned with a corresponding lateral edge of a lead tab on the lower edge 205d, and both lateral edges of each lead tab on the upper edge 205c may be aligned with a corresponding lateral edge of a lead tab on the lower edge 205d. Good too.

[0070]

[0086] Similarly, the lead tabs 240a-b, 250a-b on the upper and lower edges of the second internal electrode layer 215 may be aligned vertically. That is, the lateral edges 241a, 242a of the first lead tab 240 along the upper edge may be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the lower edge opposite the upper edge. Both lateral edges 241a, 242a of the first lead tab 240 along the upper edge may be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the lower edge opposite the upper edge. The relationship between the lateral edges of the first lead tab on the upper edge and the lateral edges of the first lead tab on the lower edge as described for the internal electrode layer 205 may also apply to the internal electrode layer 215.

[0071]

[0087] In such an arrangement, gaps may be formed between any of the lead tabs along the upper edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps may be formed between any of the lead tabs 220a-b, 240a-b extending from the upper edge of each internal electrode layer. In addition, gaps may be formed between any of the lead tabs along the upper edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, gaps may be formed between any of the lead tabs 230a-b, 250a-b extending from the upper edge of each internal electrode layer. Furthermore, the size of the gap between two respective tabs extending from the upper edge may be substantially the same as the size of the gap between two respective corresponding tabs extending from the lower edge, whether from the same internal electrode layer or an adjacent internal electrode layer. For example, the gap between lead tabs 220a and 220b may be substantially the same as the gap between lead tabs 230a and 230b. Similarly, the gap between lead tabs 220a and 240a may be substantially the same as the gap between lead tabs 230a and 250a.

[0072]

[0088] Any or all of the lead tabs 220a-b, 240a-b may be arranged in parallel with the lead tabs 230a-b, 250a-b extending from layers 205 and 215, respectively, such that the leads extending from alternating electrode layers 205 and 215 may be aligned in respective rows. For example, the lead tabs 220a-b and 230a-b of the inner electrode layer 205 may be arranged in a stacked configuration, while the lead tabs 240a-b and 250a-b of the inner electrode layer 215 may be arranged in a stacked configuration, respectively.

[0073]

[0089] It should be understood that lead tabs 220a-b connect to external terminals 22a-b, respectively, while lead tabs 240a-b connect to external terminals 24a-b, respectively. Thus, each lead tab 220a-b is nested with each lead tab 240a-b, respectively, in a manner similar to external terminals 22a-b and 24a-b. The nested lead tabs can provide multiple adjacent current injection points on the associated primary electrode portion.

[0074]

[0090] Additionally, the capacitor 20 of Figure 2A includes at least one first polarity terminal and at least one second opposite terminal on the top surface. Although not shown, the bottom surface also includes at least one first polarity terminal and a second opposite terminal. In particular, Figure 2A includes four positive terminals 22a-b and four negative terminals 24a-b on the top surface.

[0075]

[0091] 2A-2D, the capacitor includes eight external terminals on each surface, and the capacitor includes two sets of alternating dielectric and internal electrode layers. However, as noted above, the present invention is not limited by the number of external terminals and / or the number of sets of alternating dielectric and internal electrode layers.

[0076]

[0092] For example, FIG. 3A illustrates a capacitor 20 that includes 16 external terminals on each surface and four sets of alternating dielectric and internal electrode layers.

[0093] 3A, the capacitor 30 has a four-by-four configuration. That is, the capacitor includes four terminals along one dimension and four terminals along another dimension on the top and bottom surfaces. In this regard, the capacitor includes a total of 16 external terminals 32a-b, 34a-b on the top surface and 16 corresponding external terminals on the bottom surface, and the external terminals 32a-b, 34a-b on the top surface may be electrically connected to the corresponding external terminals on the bottom surface.

[0077]

[0094] The capacitor 30 of Figure 3A includes external terminals 32a-b, 34a-b and four sets of alternating dielectric and internal electrode layers 210 as illustrated in Figure 3B. As illustrated in Figures 2B and 2C, each set of alternating dielectric and internal electrode layers 210 includes internal electrode layers 205, 215 and dielectric layers (not shown) in an alternating arrangement.

[0078]

[0095] It will be appreciated that lead tabs 220a-b connect to external terminals 32a-b, respectively, while lead tabs 240a-b connect to external terminals 34a-b, respectively. Thus, each lead tab 220a-b is nested with each lead tab 240a-b, respectively, in a manner similar to external terminals 32a-b and 34a-b. Nested lead tabs can provide multiple adjacent current injection points on the associated primary electrode portion.

[0079]

[0096] Additionally, the capacitor 30 of Figure 3A includes at least one first polarity terminal and at least one second opposite terminal on the top surface. Although not shown, the bottom surface also includes at least one first polarity terminal and a second opposite terminal. In particular, Figure 3A includes four positive terminals 32a-b and four negative terminals 34a-b on the top surface.

[0080]

[0097] While the capacitors of Figures 2A, 2D, and 3A, 3B employ the set of alternating dielectric and internal electrode layers 210 of Figure 2B, it should be understood that other configurations may be employed. That is, the set of alternating dielectric and internal electrode layers 110 of Figures 1B, 1C may be employed in capacitors 20 and 30 of Figures 2A, 2D, and 3A, 3B. In this regard, rather than employing only two sets of alternating dielectric and internal electrode layers 210 in capacitor 20 of Figures 2A, 2D, the capacitor may employ up to four sets of alternating dielectric and internal electrode layers 110. In this regard, capacitor 20 of Figures 2A, 2D may employ two to four sets of alternating dielectric and internal electrode layers. Similarly, rather than using only four sets of alternating dielectric and internal electrode layers 210 in capacitor 30 of Figures 3A and 3B, the capacitor may use up to eight sets of alternating dielectric and internal electrode layers 110. In this regard, capacitor 30 of Figures 3A and 3B may use between two and eight sets of alternating dielectric and internal electrode layers.

[0081]

[0098] Additionally, although the illustrated embodiment uses only four internal electrode layers per set of alternating dielectric and internal electrode layers, it should be understood that the present invention may include any number of internal electrode layers per set and is not necessarily limited to this.

[0082]

[0099] Generally, the present invention provides a capacitor having a unique configuration that offers various benefits and advantages. In this regard, it should be understood that the materials used to construct the capacitor may be any of those commonly used in the art without limitation and may be formed using any of the methods commonly used in the art.

[0083]

[0100] Generally, the dielectric layer typically has a thickness of about 10 to about 40,000, in some embodiments In some embodiments, the dielectric constant (K) is formed from a material having a relatively high dielectric constant (K), such as from about 50 to about 30,000, and in some embodiments, from about 100 to about 20,000.

[0084]

[0101] In this regard, the dielectric material may be a ceramic. It may be provided in a variety of forms, such as a wafer (eg, pre-fired), or as a dielectric material that is co-fired with the device itself.

[0085]

[0102] Specific examples of high dielectric material types include, for example, NPO(COG) (up to approximately Examples of suitable materials include X7R (about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It is understood that the foregoing materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Association (EIA), and that the foregoing materials should be recognized as such by those skilled in the art. For example, such materials may include ceramics. Such materials may include perovskites such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium titanate zirconate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), and bismuth sodium titanate. In one particular embodiment, perovskites of the formula Ba x Sr 1-x Barium strontium titanate ("BSTO") of TiO3 may also be used, where x is 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites include, for example, Ba x Ca 1-x TiO3 (where x is from about 0.2 to about 0.8, and in some embodiments, from about 0.4 to about 0.6), Pb x Zr1-x TiO3 ("PZT") (where x ranges from about 0.05 to about 0.4), lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconate titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Still further complex perovskites may include A[B1 1 / 3 B2 2 / 3 ]O3 material, where A is Ba x Sr 1-x (x can be a value between 0 and 1), B1 is Mg y Zn 1-y (y can be a value between 0 and 1), B2 is Ta z Nb 1-z where z can be a value between 0 and 1. In one particular embodiment, the dielectric layer may include titanate.

[0086]

[0103] The internal electrode layers may be made of a variety of different metals as known in the art. The internal electrode layers may be formed from any of the following materials: a) nickel, b) nickel alloy, c) nickel alloy, d) nickel alloy, e) nickel alloy, f) chromium alloy, f) nickel alloy, g) chromium alloy, h) nickel alloy, i) chromium alloy, i) nickel alloy, ii) chromium alloy, i) nickel alloy, iii) tungsten alloy, iv) chromium alloy, i) nickel alloy, i) gold alloy, ii) nickel alloy, iii) chromium alloy, i) nickel alloy, i) gold alloy, iv) nickel alloy, iv) chromium alloy, i) nickel alloy, i) gold alloy, iv) nickel alloy, iv) chromium alloy, i) nickel alloy, i) gold alloy, iv) nickel alloy, iv) chromium alloy, i) nickel alloy, i) gold alloy, iv) nickel alloy, iv) chromium alloy, i) nickel alloy, i) gold alloy, iv) nickel alloy, iv) chromium alloy, i) nickel alloy, iv) chromium alloy, i) nickel alloy, iv) gold alloy, iv) nickel alloy, iv) chromium alloy, i) nickel alloy, iv) tungsten alloy, iv) chromium alloy, i) nickel alloy, iv) tungsten alloy, iv) chromium alloy, iv ...

[0087]

[0104] The external terminals may be made of any of a variety of different metals as known in the art. The external terminals may be formed from any of the following materials: a) a conductive metal; b) a noble metal (e.g., silver, gold, palladium, platinum, etc.); c) a base metal (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.); and d) various combinations thereof. In one particular embodiment, the external terminals may include copper or an alloy thereof.

[0088]

[0105] The external terminals may be connected by any method generally known in the art. The external terminals may be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electrolytic plating, plasma deposition, high-pressure gas spraying / air brushing, etc.

[0089]

[0106] The external terminals may be formed by thin metal plating. Such thin film plating may be formed by depositing a conductive material, such as a conductive metal, on exposed portions of the internal electrode layers. For example, the leading edge of the internal electrode layer may be exposed to allow for the formation of a plating termination.

[0090]

[0107] The external terminals are about 50 μm or less, for example, about 40 μm or less, for example, about 30 μm or less. For example, the external terminals may have an average thickness of about 5 μm to about 50 μm, for example, about 10 μm to about 40 μm, for example, about 15 μm to about 30 μm, for example, about 15 μm to about 25 μm.

[0091]

[0108] Generally, the external terminals may comprise plated terminals. For example, the external terminals may comprise electrolytic The terminals may include plated terminals, electroless plated terminals, or a combination thereof. For example, the electroplated terminals may be formed by electrolytic plating. The electroless plated terminals may be formed by electroless plating.

[0092]

[0109] When a plurality of layers constitute the external terminals, the external terminals may include electroplated terminals and wireless terminals. For example, electroless plating may be used first to deposit an initial layer of material. Then, the plating technique may be switched to an electrochemical plating system, which may allow for faster buildup of material.

[0093]

[0110] When using any plating method to form the plated terminals, the body of the capacitor The front edges of the lead tabs of the internal electrode layers exposed from the lead tabs are exposed to a plating solution. In one embodiment, the capacitor may be immersed in the plating solution.

[0094]

[0111] The plating solution contains a conductive material, such as a conductive metal, that is used to form the plating termination. The plating solution may include a conductive material. Such a conductive material may be any of the materials described above or any other material commonly known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution so that the plating layer and external terminals include nickel. Alternatively, the plating solution may be a cuprate bath or other suitable copper solution so that the plating layer and external terminals include copper.

[0095]

[0112] In addition, the plating solution may contain other metals as commonly known in the art. It should be understood that the plating solution may contain additives such as those listed above. For example, the additives may include other organic additives and mediators that can aid in the plating process. In addition, additives may be used to provide a desired pH for the plating solution. In one embodiment, a resistance-reducing additive may be used in the solution to aid in complete plating coverage and bonding of the plating material to the capacitor and the exposed leading edges of the lead tabs of the internal electrode layers.

[0096]

[0113] The capacitors will withstand exposure, immersion, or immersion in plating solutions for a specified amount of time. Such exposure time is not necessarily limited and may be a sufficient amount of time to allow deposition of sufficient plating material to form plated terminals. In this regard, the time must be sufficient to allow for the formation of continuous connections between the desired exposed adjacent leading edges of lead tabs of a given polarity of each internal electrode layer within a set of alternating dielectric and internal electrode layers.

[0097]

[0114] Generally, the difference between electrolytic plating and electroless plating is that electrolytic plating uses an external power source. Electroplating solutions typically operate in the high current density range, e.g., 10-15 amp / ft 2 (rated at 9.4 volts). Connections can be made with a negative connection to the capacitor, which requires the formation of a plating terminal, and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite that of the plating solution. Using such a method, the conductive material of the plating solution is applied to the exposed leading edge metal of the lead tab of the internal electrode layer.

[0098]

[0115] Before immersing or exposing the capacitor to the plating solution, various pretreatment steps are performed. Such a step may be performed for a variety of purposes, including catalyzing, accelerating, and / or improving the application of plating material to the leading edge of the lead tab.

[0099]

[0116] In addition, before plating or any other pretreatment step, an initial clean A pre-cleaning step may be used. Such a step may be used to remove any oxide buildup that forms on exposed lead tabs of the internal electrode layers. This cleaning step may be particularly useful to help remove any nickel oxide buildup when the internal electrodes or other conductive elements are formed from nickel. Component cleaning may be achieved by complete immersion in a pre-clean bath, such as one containing an acid cleaner. In one embodiment, exposure may be for a predetermined time, such as approximately 10 minutes. Cleaning may also alternatively be achieved by a chemical polishing or harperizing step.

[0100]

[0117] In addition, a solder paste is used to activate the exposed metal leading edges of the lead tabs of the internal electrode layers. A step may be performed to facilitate deposition of the conductive material. Activation may be achieved by immersion in palladium salts, photopatterned palladium organometallic precursors (via mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposits. It should be understood that palladium-based activation is disclosed as merely an example of an activation solution that often works well for activating exposed tab portions formed from nickel or its alloys. However, it should be understood that other activation solutions may also be utilized and are therefore not necessarily limiting.

[0101]

[0118] Alternatively, or in addition to the activation step described above, When forming the internal electrode layers, an activation dopant may be introduced into the conductive material. For example, when the internal electrode layers include nickel and the activation dopant includes palladium, a palladium dopant may be introduced into the nickel ink or composition that forms the internal electrode layers. This eliminates the palladium activation step. It should be further understood that some of the above activation methods, such as organometallic precursors, are also suitable for co-deposition of glass formers for increased adhesion to the generally ceramic body of the capacitor. When the activation step is performed as described above, traces of the activator material may often remain in the exposed conductive portions before and after termination plating.

[0102]

[0119] Additionally, post-plating steps may also be used if desired or necessary. Such a step may be performed for a variety of purposes, including strengthening and / or improving the adhesion of the material. For example, a heating (or annealing) step may be used after performing the plating step. Such heating may be performed by baking, laser subjection, UV exposure, microwave exposure, arcing, or the like. This may be done by welding or the like.

[0103]

[0120] As shown herein, the external terminals include at least one plating layer. In one embodiment, the external terminals may include only one plating layer. However, it should be understood that the external terminals may include multiple plating layers. For example, the external terminals may include a first plating layer and a second plating layer. In addition, the external terminals may also include a third plating layer. Furthermore, the materials of these plating layers may be any of those previously described and those generally known in the art.

[0104]

[0121] For example, one plating layer, such as the first plating layer, may include copper or an alloy thereof. Another plating layer, such as the second plating layer, may include nickel or an alloy thereof. Another plating layer, such as the third plating layer, may include tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, the first plating layer may include nickel, followed by a plating layer of tin or gold. In another embodiment, a first plating layer of copper may be formed, followed by a nickel layer.

[0105]

[0122] In one embodiment, the initial or first plating layer is a conductive metal (e.g., , copper). This area may then be coated with a second layer comprising a resistive polymeric material for sealing. This area may then be polished to selectively remove the resistive polymeric material, and then plated again with a third layer comprising a conductive metallic material (e.g., copper).

[0106]

[0123] The second layer above the first plating layer is a solder barrier layer, e.g., nickel. The third layer above the solder barrier layer may correspond to a conductive layer, such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder. In some embodiments, the third layer may be formed by electrolytic plating of an additional layer of metal (e.g., nickel) over an initial electrolessly or electrolytically plated layer (e.g., plated copper). Other exemplary materials for the solder barrier layer include nickel phosphorus, gold, and silver. The third layer above the solder barrier layer may correspond to a conductive layer, such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder, in some embodiments.

[0107]

[0124] In addition, a resistive alloy or a higher resistive metal alloy may be applied over such metal plating. The metal plating layer may be formed followed by an electrolytic plating step to provide a gold coating, e.g., an electroless Ni-P alloy, etc. However, it should be understood that any metal coating may be included as understood by one skilled in the art with the full disclosure herein.

[0108]

[0125] Any of the aforementioned steps may be performed using barrel plating, fluidized bed plating and / or flow plating. It should be understood that termination may also be performed as a bulk process, such as a flow-through plating termination process, all of which are commonly known in the art. Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is a particular advantage over traditional termination methods, such as printing thick film terminations, which require the processing of individual components.

[0109]

[0126] As described herein, the formation of the external terminals generally involves the formation of leads on the internal electrode layers. Such a phenomenon may be referred to as "self-determining" because the formation of the outer plated terminal is determined by the configuration of the exposed conductive metal of the inner electrode layers at selected peripheral locations on the capacitor.

[0110]

[0127] An additional aspect of the above technique for forming thin film plated terminations is that any No. 7,177,137 to Ritter et al., which is incorporated herein by reference for that purpose. It should be understood that additional techniques for forming capacitor terminations are also within the scope of the present technology. Exemplary alternatives include, but are not limited to, forming terminations by plating, magnetic, masking, electrophoretic / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming both thick-film or thin-film conductive layers. [Example]

[0111]

[0128] A multilayer capacitor as defined herein is one that meets the specifications disclosed herein. Specifically, a two-by-four stacked capacitor was fabricated, including two sets of alternating dielectric and internal electrode layers. Each internal electrode layer included two lead tabs extending from the top edge and two lead tabs extending from the bottom edge. The capacitor included eight external terminals on the top surface and eight external terminals on the bottom surface, with four external terminals on each surface having a first polarity and the remaining four external terminals on each surface having a second, opposite polarity. The capacitor included approximately 300 active internal electrode layers, each spaced approximately 4 microns apart from an adjacent internal electrode layer within the capacitor.

[0112] [Table 1]

[0113]

[0129] These and other modifications and variations of the present invention are within the spirit and scope of the present invention. It can be practiced by those skilled in the art without departing from the spirit and scope of the present invention. In addition, it should be understood that aspects of the various embodiments may be interchangeable both in whole or in part. Furthermore, those skilled in the art will appreciate that the foregoing description is merely exemplary and is not intended to limit the invention so further described in the appended claims.

Claims

1. A multilayer capacitor, A body including a first set of alternating dielectric layers and internal electrode layers and a second set of alternating dielectric layers and internal electrode layers, each set of alternating dielectric layers and internal electrode layers includes a first internal electrode layer and a second internal electrode layer; each internal electrode layer includes an upper edge, a lower edge opposite the upper edge, and two side edges extending between the upper and lower edges that define a body of the internal electrode layer; each internal electrode layer including at least one lead tab extending from the upper edge of the body of the internal electrode layer and at least one lead tab extending from the lower edge of the body of the internal electrode layer; the lead tab extending from the top edge of the body of the internal electrode layer is offset from the side edge of the body of the internal electrode layer; a main body, the lead tab extending from the bottom edge of the main body of the internal electrode layer being offset from the side edge of the main body of the internal electrode layer; external terminals electrically connected to the internal electrode layers, the external terminals being formed on an upper surface of the capacitor and a lower surface of the capacitor opposite to the upper surface of the capacitor.

2. 2. The capacitor of claim 1, wherein the first and second internal electrode layers are interleaved in an opposite relationship, and a dielectric layer is positioned between the first and second internal electrode layers.

3. 2. The capacitor of claim 1, wherein each internal electrode layer includes at least two lead tabs extending from the upper edge, the lower edge, or both the upper edge and the lower edge, the two lead tabs including a first lead tab and a second lead tab.

4. The capacitor of claim 1 , wherein at least one lateral edge of the lead tab on the top edge is substantially aligned with at least one lateral edge of the lead tab on the bottom edge.

5. The capacitor of claim 1 , wherein both lateral edges of the lead tab on the top edge are substantially aligned with both lateral edges of the lead tab on the bottom edge.

6. 4. The capacitor of claim 3, wherein at least one side edge of the first lead tab and at least one side edge of the second lead tab on an upper edge are substantially aligned with at least one side edge of the first lead tab and at least one side edge of the second lead tab on an upper edge, respectively.

7. 4. The capacitor of claim 3, wherein both side edges of the first lead tab and both side edges of the second lead tab on an upper edge are substantially aligned with both side edges of the first lead tab and both side edges of the second lead tab on the upper edge.

8. The capacitor of claim 2 wherein the dielectric layer comprises a ceramic.

9. The capacitor of claim 1 , wherein the internal electrode layers comprise a conductive metal.

10. The capacitor according to claim 1 , wherein the external terminals include an electrolytic plating layer.

11. The capacitor according to claim 1 , wherein the external terminals include an electroless plating layer.

12. The capacitor according to claim 1 , wherein the external terminals include an electroless plated layer and an electrolytic plated layer.

13. The capacitor of claim 1 , wherein the external terminals include a first electrolessly plated layer, a second electrolytically plated layer, and a third electrolytically plated layer.

14. 14. The capacitor of claim 13, wherein the first electrolessly plated layer comprises copper, the second electrolytically plated layer comprises nickel, and the third electrolytically plated layer comprises tin.

15. The capacitor of claim 1 , wherein the capacitor comprises at least three sets of alternating dielectric and internal electrode layers.

16. 10. A circuit board including the capacitor of claim 1, said capacitor being positioned on said circuit board.

17. 17. The circuit board of claim 16, wherein the circuit board further comprises an integrated circuit package, the capacitor being positioned vertically between the circuit board and the integrated circuit package such that the circuit board, the capacitor, and the integrated circuit package are in a stacked arrangement.

18. 20. The circuit board of claim 17, wherein the capacitor is directly connected to the circuit board and the integrated circuit package.

19. 10. An integrated circuit package comprising the capacitor of claim 1.

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