Image sensor

Abstract

To provide an image sensor with improved reliability.SOLUTION: An image sensor according to the present invention includes a substrate having a first surface and a second surface and including a plurality of pixel regions, and a deep element separation pattern that defines the pixel regions. The deep element separation pattern includes a horizontal part that is parallel to a first surface of the substrate and a vertical part. The vertical part of the deep element separation pattern includes a lowermost part, an uppermost part, a central part, a lower middle part, and an upper middle part. The ratio between the width of the uppermost part and the width of the central part is 1:0.9 to 1:1.1. The deep element separation pattern is separated from the first surface of the substrate.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to image sensors, and more particularly to CMOS image sensors. [Background technology]

[0002] Image sensors convert optical images into electrical signals. With the recent development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in a variety of fields, including digital cameras, video cameras, PCS (Personal Communication Systems), game consoles, security cameras, and medical micro cameras.

[0003] Image sensors include charge coupled devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors have a simple driving method and can integrate signal processing circuits on a single chip, allowing for product miniaturization. CMOS image sensors also have very low power consumption, making them easy to apply to products with limited battery capacity. Furthermore, CMOS image sensors can be used interchangeably with CMOS process technology, reducing manufacturing costs. Therefore, the use of CMOS image sensors is rapidly increasing as technological developments make it possible to achieve higher resolutions. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 1,154,513 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor with improved reliability. [Means for solving the problem]

[0006] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a substrate having first and second surfaces facing each other and including a plurality of pixel areas into which light is incident from the second surface; a gate electrode on the first surface; a photoelectric conversion region disposed within the pixel areas; and a deep device isolation pattern defining the pixel areas, wherein the deep device isolation pattern includes a horizontal portion parallel to the first surface of the substrate and a vertical portion extending from the horizontal portion toward the first surface of the substrate, and the vertical portion of the deep device isolation pattern includes a bottom portion defined on a bottom surface of the vertical portion, a top portion defined on a top surface of the vertical portion, a central portion defined at a center of the vertical portion, a central bottom portion defined between the bottom portion and the central portion, and a central top portion defined between the top portion and the central portion, wherein a ratio of a width of the top portion to a width of the central portion is 1:0.9 to 1:1.1, and the deep device isolation pattern is spaced apart from the first surface of the substrate.

[0007] In order to achieve the above object, another aspect of the present invention provides an image sensor comprising: a substrate having a first surface in contact with a gate electrode and a second surface opposite to the first surface onto which light is incident, the image sensor comprising a plurality of pixel regions; a photoelectric conversion region disposed within the pixel region; and a deep device isolation pattern defining the pixel region, the deep device isolation pattern including a horizontal portion parallel to the first surface of the substrate and a vertical portion disposed within a vertical trench extending from the horizontal portion toward the first surface of the substrate, the sidewalls of the vertical trench being perpendicular to the first surface of the substrate, and the depth of the vertical trench being smaller than the thickness of the substrate.

[0008] According to one embodiment, an image sensor includes a substrate having a first surface and a second surface facing each other, the substrate including a plurality of pixel regions into which light is incident from the second surface; a gate electrode disposed on the first surface of the substrate and extending into the substrate; a photoelectric conversion region disposed in the pixel region; a floating diffusion region disposed in the pixel region and spaced apart from the photoelectric conversion region; and a deep device isolation pattern defining the pixel region, the deep device isolation pattern having a horizontal portion parallel to the first surface of the substrate and a floating diffusion region extending forward from the horizontal portion. a vertical portion disposed in a vertical trench extending toward the first surface of the substrate, wherein the vertical portion of the deep device isolation pattern includes a bottom portion defined on a bottom surface of the vertical portion, a top portion defined on a top surface of the vertical portion, a central portion defined at a center of the vertical portion, a central bottom portion defined between the bottom portion and the central portion, and a central top portion defined between the top portion and the central portion, wherein a ratio of a width of the top portion to a width of the central portion is 1:0.9 to 1:1.1, and the deep device isolation pattern is spaced from the first surface of the substrate. [Effects of the Invention]

[0009] In the image sensor according to the present invention, since a trench is formed vertically in a substrate to form an isolation pattern, bowing of the isolation pattern and voids therein can be reduced, resulting in improved reliability of the image sensor. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention; [Figure 2] 2 is a circuit diagram of a unit pixel of an image sensor according to an embodiment of the present invention; [Figure 3] 1 is a plan view of an image sensor according to an embodiment of the present invention; [Figure 4] FIG. 4 is a cross-sectional view of the first example taken along line AA' in FIG. [Figure 5]FIG. 5 is an enlarged view of X in FIG. 4. [Figure 6] 4 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention, corresponding to a cross section of a second example taken along line AA' in FIG. 3. FIG. [Figure 7] 4 is a cross-sectional view of a first example of an image sensor taken along line AA' in FIG. 3, illustrating a method for manufacturing the image sensor according to an embodiment of the present invention. [Figure 8] 4 is a cross-sectional view of a first example of an image sensor taken along line AA' in FIG. 3, illustrating a method for manufacturing the image sensor according to an embodiment of the present invention. [Figure 9] 4 is a cross-sectional view of a first example of an image sensor taken along line AA' in FIG. 3, illustrating a method for manufacturing the image sensor according to an embodiment of the present invention. [Figure 10] 4 is a cross-sectional view of a first example of an image sensor taken along line AA' in FIG. 3, illustrating a method for manufacturing the image sensor according to an embodiment of the present invention. [Figure 11] 4 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention, corresponding to a cross section of a third example taken along line AA' in FIG. 3. [Figure 12] 4 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention, corresponding to a cross section of a fourth example taken along line AA' in FIG. 3; DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1 is a block diagram of an image sensor according to one embodiment of the present invention.

[0013] Referring to FIG. 1 , the image sensor includes an active pixel sensor array 1, a row decoder 3, a row driver 2, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog to digital converter (ADC) 7, and an input / output buffer 8.

[0014] The active pixel sensor array 1 includes a plurality of pixels arranged two-dimensionally and converts optical signals into electrical signals. The active pixel sensor array 1 is driven by a plurality of drive signals, such as a pixel select signal, a reset signal, and a charge transfer signal, provided by a row driver 3. The electrical signals converted by the active pixel sensor array 1 are provided to a correlated double sampler 6.

[0015] The row driver 2 provides a number of drive signals for driving a plurality of pixels to the active pixel sensor array 1 according to the results of decoding by the row decoder 3. When a plurality of pixels are arranged in a matrix, a drive signal is provided for each row.

[0016] A timing generator 5 provides timing and control signals to the row decoder 3 and the column decoder 4 .

[0017] The correlated double sampler (CDS) 6 receives, holds, and samples the electrical signal generated by the active pixel sensor array 1. The correlated double sampler 6 double samples a specific noise level and a signal level based on the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0018] An analog-to-digital converter (ADC) 7 converts the analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal and outputs it.

[0019] The input / output buffer 8 latches the digital signals and sequentially outputs the latched signals to a video signal processor (not shown) according to the decoding result of the column decoder 4 .

[0020] FIG. 2 is a circuit diagram of a unit pixel of an image sensor according to an embodiment of the present invention.

[0021] 1 and 2, an active pixel sensor array 1 includes a plurality of pixels PX, which are arranged in a matrix. Each pixel PX includes a first photoelectric conversion element PD1, a second photoelectric conversion element PD2, a first transfer transistor TX1, a second transfer transistor PX2, and logic transistors (RX, SX, DX). The logic transistors (RX, SX, DX) include a reset transistor RX, a select transistor SX, and a drive transistor DX. The first transfer transistor TX1, the second transfer transistor PX2, the reset transistor RX, and the select transistor SX each include a first transfer gate TG1, a second transfer gate TG2, a reset gate RG, and a select gate SG. Each pixel PX further includes a floating diffusion region FD.

[0022] The first and second photoelectric conversion elements (PD1, PD2) generate and accumulate photocharges in proportion to the amount of light incident from outside. The first and second photoelectric conversion elements (PD1, PD2) are photodiodes including a P-type impurity region and an N-type impurity region. The first transfer transistor TX1 transfers the charge generated in the first photoelectric conversion element PD1 to the floating diffusion region FD, and the second transfer transistor TX2 transfers the charge generated in the second photoelectric conversion element PD2 to the floating diffusion region FD.

[0023] The floating diffusion region FD receives and cumulatively stores the charges generated by the first and second photoelectric conversion elements PD1 and PD2. The drive transistor DX is controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

[0024] The reset transistor RX periodically resets the charge stored in the floating diffusion region FD. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode of the reset transistor RX is connected to the power supply voltage V. DD When the reset transistor RX is turned on, the power supply voltage V connected to the source electrode of the reset transistor RX is DD is applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged and the floating diffusion region FD is reset.

[0025] The drive transistor DX acts as a source follower buffer amplifier. DD is applied to the drain electrode, amplifying the potential change in the floating diffusion region FD and outputting it to the output line (Vout) via the selection transistor SX.

[0026] The selection transistor SX selects the pixel PX to be read out row by row. When the selection transistor SX is turned on, the potential change in the floating diffusion region FD amplified by the drive transistor DX is output to the output line (Vout).

[0027] 2 illustrates a unit pixel PX having two photoelectric conversion elements (PD1, PD2) and five transistors (TX1, TX2, RX, DX, SX), but the image sensor according to the present invention is not limited thereto. For example, the reset transistor RX, the drive transistor DX, or the selection transistor SX may be shared by adjacent pixels PX. This can improve the integration density of the image sensor.

[0028] Fig. 3 is a plan view of an image sensor according to an embodiment of the present invention, Fig. 4 is a cross-sectional view of a first example taken along line A-A' in Fig. 3, and Fig. 5 is an enlarged view of X in Fig. 4.

[0029] 3, 4, and 5, an image sensor according to an embodiment of the present invention includes a photoelectric conversion layer 10, a wiring layer 20, and a light-transmitting layer 30. The photoelectric conversion layer 10 is disposed between the wiring layer 20 and the light-transmitting layer 30.

[0030] The photoelectric conversion layer 10 includes a substrate 100, which includes a plurality of pixel regions PX. The substrate 100 is a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, a silicon-germanium substrate, a II-VI compound semiconductor substrate, or a III-V compound semiconductor substrate) or an SOI (Silicon on Insulator) substrate. The substrate 100 has a first surface 100a and a second surface 100b facing each other. The plurality of pixel regions PX are two-dimensionally arranged along a first direction D1 and a second direction D2 parallel to the first surface 100a of the substrate 100. The first direction D1 and the second direction D2 intersect with each other. The first surface 100a of the substrate 100 contacts the gate electrode TG, and light is incident on the second surface 100b of the substrate 100. That is, light is incident from the second surface 100b of the substrate 100 and transmitted to the pixel regions.

[0031] In one embodiment, a first photoelectric conversion region PD is disposed within the first pixel region PX1, and a second photoelectric conversion region PD is disposed within the second pixel region PX2. The first pixel region PX1 and the second pixel region PX2 are adjacent to each other in the first direction D1. The first photoelectric conversion region PD1 and the second photoelectric conversion region PD2 are adjacent to each other in the first direction D1. The third pixel region PX3 is disposed spaced apart from the second pixel region PX2 in the second direction D2. The fourth pixel region PX4 is disposed spaced apart from the third pixel region PX3 in the first direction D1. The third photoelectric conversion region PD3 is disposed within the third pixel region PX3, and the fourth photoelectric conversion region PD4 is disposed within the fourth pixel region PX4. Although the first to fourth photoelectric conversion regions PD are illustrated as being arranged clockwise, this is for ease of explanation only, and the present invention is not limited thereto. A deep device isolation pattern 150 is disposed between the first photoelectric conversion region PD1 and the second photoelectric conversion region PD2. Light incident from the outside is converted into an electrical signal in the photoelectric conversion region PD. The photoelectric conversion region PD is an impurity region having a second conductivity type different from the first conductivity type of the semiconductor substrate 100. The photoelectric conversion region PD has an impurity concentration difference between a first region adjacent to the first surface 100a and a second region adjacent to the second surface 100b.

[0032] The photoelectric conversion layer 10 further includes deep isolation patterns 150 disposed between the pixel regions PX. The deep isolation patterns 150 extend from the second surface 100b of the substrate 100 toward the first surface 100a of the substrate. The deep isolation patterns 150 extend from the second surface 100b of the substrate toward the interior of the substrate. The bottom surfaces of the deep isolation patterns 150 are located within the interior of the substrate. The deep isolation patterns 150 prevent crosstalk between adjacent pixel regions PX.

[0033] The deep element isolation pattern 150 surrounds each of the pixel regions PX in a plan view. The deep element isolation pattern 150 defines the pixel regions PX. The deep element isolation pattern 150 extends in the first direction D1 and the second direction D2 to surround each pixel region PX.

[0034] The deep isolation pattern 150 includes a semiconductor pattern 115 and an insulating pattern 113 interposed between the semiconductor pattern 115 and the substrate. The semiconductor pattern 115 penetrates a portion of the semiconductor substrate 100 in the third direction D3.

[0035] The deep isolation pattern 150 includes an insulating pattern 113 that conformally covers the vertical trench BTR and the second surface 100b of the substrate 100, and a semiconductor pattern 115 that is provided on the insulating pattern 113 and fills the vertical trench BTR. The insulating pattern 113 is provided between the semiconductor pattern 115 and the substrate 100.

[0036] The insulating pattern 113 includes, for example, at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0037] The semiconductor pattern 115 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or an organic transparent conductive material. The semiconductor pattern 115 may include, for example, polysilicon.

[0038] The deep isolation pattern 150 fills a vertical trench BTR that extends from the second surface 100b of the semiconductor substrate 100 toward the first surface 100a. The deep isolation pattern 150 covers the second surface 100b of the semiconductor substrate 100. Again, the deep isolation pattern 150 includes a vertical portion that fills the vertical trench BTR and a horizontal portion that covers the second surface 100b of the semiconductor substrate 100. In other words, the deep isolation pattern 150 includes a horizontal portion that is parallel to the first surface 100a of the substrate and a vertical portion that extends from the horizontal portion toward the first surface 100a of the substrate. The vertical portion of the deep isolation pattern 150 is disposed in the vertical trench BTR that extends from the horizontal portion toward the first surface 100a of the substrate 100.

[0039] The vertical portion of the deep isolation pattern 150 has a substantially constant width. The inner wall of the vertical trench BTR is perpendicular to the first surface 100a of the substrate. The sidewall of the vertical portion of the deep isolation pattern is perpendicular to the first surface 100a of the substrate.

[0040] The depth of the vertical trench BTR is smaller than the thickness of the substrate 100. The bottom surface of the vertical trench BTR is spaced apart from the first surface 100a of the substrate 100. The bottom surface of the vertical portion of the deep isolation pattern 150 is spaced apart from the first surface 100a of the substrate 100.

[0041] The deep isolation pattern 150 includes an insulating material that has a lower refractive index than the semiconductor substrate 100 (eg, silicon).

[0042] 4, an insulating pattern 113 is provided to conformally cover the inner walls of the vertical trench BTR and the second surface 100b of the substrate 100. A semiconductor pattern 115 is provided on the insulating pattern 113 to fill the vertical trench BTR, and a semiconductor pattern 115 is provided on the insulating pattern 113 on the second surface 100b. In this case, the horizontal portion of the deep device isolation pattern 150 includes a vertical portion 115V of the semiconductor pattern 115 and an insulating pattern 113 between the horizontal portion 115H of the semiconductor pattern 115 and the substrate. The vertical portion of the deep device isolation pattern 150 includes a vertical portion 115V of the semiconductor pattern 115 and an insulating pattern 113 between the vertical portion 115V of the semiconductor pattern 115 and the substrate.

[0043] The additional isolation patterns 250 are disposed adjacent to the first surface 100a of the substrate 100. The additional isolation patterns 250 define active portions on the first surface 100a of the semiconductor substrate 100 in each of the pixel regions PX. The additional isolation patterns 250 include, for example, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The active portions are spaced apart from each other in each of the pixel regions PX and have different sizes. The additional isolation patterns 250 are interposed between the active patterns.

[0044] The additional isolation pattern 250 and the vertical trench BTR overlap vertically. The additional isolation pattern 250 and the deep device isolation pattern 150 overlap vertically. The additional isolation pattern 250 is vertically spaced apart from the deep device isolation pattern 150. The sidewalls of the additional isolation pattern 250 are inclined with respect to the first surface 100a of the substrate 100. In other words, the width of the additional isolation pattern 250 is not constant depending on the distance from the first surface 100a of the substrate 100. The width of the additional isolation pattern 250 gradually decreases from the first surface 100a to the second surface 100b of the substrate 100. The additional isolation pattern 250 includes a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

[0045] A gate electrode TG and a floating diffusion region FD are disposed on each pixel region PX and adjacent to the first surface 100a of the substrate 100. The gate electrode TG and the floating diffusion region FD are disposed on corresponding active portions among the active portions. The gate electrode TG overlaps the photoelectric conversion region PD perpendicularly (for example, in the third direction D3).

[0046] The gate electrode TG extends into the substrate 100. At least a portion of the gate electrode TG is provided in a vertical trench recessed from the first surface 100a of the semiconductor substrate 100. The gate electrode TG includes a lower portion recessed into the semiconductor substrate 100 and an upper portion connected to the lower portion and protruding above the first surface 100a of the semiconductor substrate 100.

[0047] The lower portions of the gate electrodes TG penetrate at least a part of the semiconductor substrate 100. The lower portion of each of the gate electrodes TG extends into the substrate 100 toward the photoelectric conversion region PD, and the upper portion of each of the gate electrodes TG protrudes above the upper surface of the corresponding active portion (i.e., the first surface 100a of the substrate 100).

[0048] A gate insulating film GIL is interposed between the gate electrode TG and the semiconductor substrate 100.

[0049] The wiring layer 20 includes wiring (for example, MOS transistors) connected to the photoelectric conversion layer 10. The electrical signals converted by the photoelectric conversion layer 10 are processed by the wiring layer 20.

[0050] The wiring layer 20 is disposed on the first surface 100a of the substrate 100. The wiring layer 20 includes an interlayer insulating film 210 that is sequentially stacked on the first surface 100a of the substrate 100. The interlayer insulating film 210 is disposed on the first surface 100a of the substrate 100 and covers the transmission gate electrode TG. The interlayer insulating film 210 includes an insulating material. The interlayer insulating film 210 includes at least one of silicon oxide, silicon oxynitride, and silicon nitride, for example.

[0051] The wiring layer 20 further includes wiring structures 221 and 223 provided in the interlayer insulating film 210. The wiring structures 221 and 223 include metal wirings 223 and contact plugs 221 connecting the metal wirings 223. A portion of the contact plugs 221 is connected to the floating diffusion regions FD. The metal wirings 223 and the contact plugs 221 include conductive materials.

[0052] The light-transmitting layer 30 is provided on the second surface 100b of the semiconductor substrate 100. The light-transmitting layer 30 includes a light-shielding pattern 48, a low-refractive pattern 50, a color filter CF, a lens insulating film 322, and a microlens MR. The light-transmitting layer 30 collects and filters light incident from the outside and provides the light to the photoelectric conversion layer 10.

[0053] A protective film (not shown) is additionally provided between the light-transmitting layer 30 and the deep isolation pattern 150 .

[0054] A light-shielding pattern 48 is disposed on the deep device isolation pattern 150. The light-shielding pattern 48 is disposed on a horizontal portion of the deep device isolation pattern 150. A low-refraction pattern 50 is disposed on each of the light-shielding patterns 48. The light-shielding pattern 48 and the low-refraction pattern 50 have a lattice structure that defines light-transmitting regions 10 that vertically overlap a plurality of unit pixels.

[0055] The light-shielding patterns 48 and the low-refractive index patterns 50 overlap the deep device isolation patterns 150 and have a grid shape in plan view. The light-shielding patterns 48 include, for example, titanium. The low-refractive index patterns 50 each have the same thickness and include the same organic material. The low-refractive index patterns 50 have a refractive index smaller than that of the color filters CF described below. For example, the low-refractive index patterns 50 have a refractive index of approximately 1.3 or less. The light-shielding patterns 48 and the low-refractive index patterns 50 prevent crosstalk between adjacent unit pixels PX.

[0056] Color filters corresponding to the first to fourth pixel regions (PX1, PX2, PX3, PX4) are provided, respectively. For example, a color filter CF corresponding to the first pixel region PX1 is provided in the first pixel region PX1. The same applies to the second to fourth pixel regions (PX2, PX3, PX4).

[0057] Color filters CF are disposed between adjacent low refractive index patterns 50. Each color filter CF has one of blue, green, and red. As another example, the color filters CF may include other colors such as cyan, magenta, or yellow. In the image sensor according to this embodiment, the color filters CF are arranged in a Bayer pattern. As another example, the color filters CF are arranged in a 2x2 Tetra pattern, a 3x3 Nona pattern, or a 4x4 Hexadeca pattern.

[0058] A lens insulating film 322 is interposed between the color filter CF and the microlens MR. The microlens MR is disposed on the lens insulating film 322.

[0059] The microlenses MR overlap the corresponding photoelectric conversion regions PD. One microlens MR overlaps one photoelectric conversion region PD. In plan view, one microlens is disposed between two vertical portions 115V of adjacently spaced apart deep element isolation patterns 150.

[0060] 4 and 5, FIG. 5 illustrates in more detail the vertical portion of the deep isolation pattern 150. The vertical portion of the deep isolation pattern 150 fills the vertical trench BTR. In other words, the vertical portion of the deep isolation pattern 150 is defined by the deep isolation pattern 150 being located below the second surface 100b of the substrate 100. The vertical portion of the deep isolation pattern 150 includes the vertical portion 115V of the semiconductor pattern 115 and the insulating pattern 113.

[0061] The vertical portion of the deep device isolation pattern 150 has a height of 1.5 μm or more. The vertical portion of the deep device isolation pattern 150 includes a bottom portion 15 defined at the bottom surface of the vertical portion, a top portion 11 defined at the top surface of the vertical portion, a central portion 13 defined at the center of the vertical portion, a central bottom portion 14 defined between the bottom portion 15 and the central portion 13, and a central top portion 12 defined between the top portion 11 and the central portion 13. The distance between the top portion 11 and the central top portion 12, the distance between the central top portion 12 and the central portion 13, the distance between the central portion 13 and the central bottom portion 14, and the distance between the central bottom portion 14 and the bottom portion 15 are all the same.

[0062] The width W1 of the top portion 11 is 150 nm or less. The ratio of the width W1 of the top portion 11, the width W2 of the central-upper portion 12, and the width W3 of the central portion 13 is 1:1 to 1.15:0.9 to 1.1. The width W4 of the central-lower portion 13 and the width W5 of the bottom portion 15 are the same as or smaller than the width W1 of the top portion 11.

[0063] In one embodiment, the width W1 of the top portion 11, the width W2 of the central top portion 12, the width W3 of the central portion 13, the width W4 of the central bottom portion 13, and the width W5 of the bottom portion 15 are all the same.

[0064] 6 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention, and corresponds to a cross-section of a second example taken along line A-A' in FIG. 3. For simplicity of explanation, details that overlap with those described above will be omitted.

[0065] 6, the deep isolation pattern 150, i.e., the vertical portion of the deep isolation pattern 150, includes a first vertical portion 1501 and a second vertical portion 1502 adjacent to and spaced apart from the first vertical portion 1501. The first vertical portion 1501 is provided in a first vertical trench BTR1. The second vertical portion 1502 is provided in a second vertical trench BTR2. The depth of the first vertical trench BTR1 is deeper than the depth of the second vertical trench BTR2.

[0066] The level of the bottom surface 1501BS of the first vertical portion 1501 is different from the level of the bottom surface 1502BS of the second vertical portion 1502. For example, the level of the bottom surface 1501BS of the first vertical portion 1501 is higher than the level of the bottom surface 1502BS of the second vertical portion 1502. In other words, the distance from the bottom surface 1501BS of the first vertical portion 1501 to the first surface 100a of the substrate 100 is shorter than the distance from the bottom surface 1502BS of the second vertical portion 1502 to the first surface 100a of the substrate 100. For example, the ratio of the length of the first vertical portion 1501 to the length of the second vertical portion 1502 is approximately 1:0.8. In a plan view, one microlens MR is disposed between the first vertical portion 1501 and the second vertical portion 1502.

[0067] If the deep isolation pattern 150 is not vertical, bowing increases the width of the deep isolation pattern 150. In this case, voids are formed within the deep isolation pattern 150 when the semiconductor pattern 115 and the insulating pattern 113 are formed.

[0068] If the deep isolation pattern 150 is not vertical, a bow is formed, and when a doping process is performed on the sidewall of the deep isolation pattern 150, the doping concentration increases intensively in the bowed portion, thereby reducing the full well capacity (FWC).

[0069] According to the present invention, the deep isolation pattern 150 is provided in a vertical trench BTR that is perpendicular to the first surface 100a of the substrate 100. Since the deep isolation pattern 150 is perpendicular to the first surface 100a of the substrate 100, bowing and voids in the deep isolation pattern 150 are improved, and therefore, the full well capacity (FWC) is increased.

[0070] 7 to 10 are diagrams illustrating a method for manufacturing an image sensor according to an embodiment of the present invention, and are cross-sectional views of a first example taken along line AA' in FIG.

[0071] 4 and 7, a wiring layer 20 and a semiconductor substrate 100 connected to the wiring layer 20 by a gate electrode TG are provided. The semiconductor substrate 100 is doped with impurities to have a first conductivity type (e.g., p-type).

[0072] An additional isolation pattern 250 is formed on the first surface 100a of the substrate 100. Forming the additional isolation pattern 250 includes forming shallow trenches in the first surface 100a of the substrate 100 and filling the shallow trenches with an insulating film. The insulating film is formed using silicon oxide, silicon nitride, and / or silicon oxynitride.

[0073] The additional isolation patterns 250 define active patterns. Impurities are doped into each active pattern to form floating diffusion regions FD. Gate electrodes TG are formed on the active patterns. An interlayer insulating film 220, wiring 223, and contact plugs 221 are formed on the first surface 100a of the substrate 100.

[0074] Referring to FIG. 8, an etching process is performed on the second surface 100b of the substrate 100 to form trenches TR. The depth of the trenches TR is smaller than the thickness of the semiconductor substrate 100. The width of the trenches TR is constant from the second surface 100b to the first surface 100a of the semiconductor substrate 100. In a plan view, the trenches TR are formed to have a lattice structure. A plurality of unit pixels PX are defined by the trenches TR. The unit pixels PX are two-dimensionally arranged in a first direction D1 and a second direction D2 that intersect with each other.

[0075] 9, a preliminary insulating pattern p113 and a preliminary semiconductor pattern p115 are sequentially formed to fill the trench TR. The preliminary insulating pattern p113 is conformally formed to partially fill the trench TR. The trench TR is a vertical trench BTR. The preliminary insulating pattern p113 covers the second surface 100b of the substrate 100. A horizontal portion p115H of the preliminary semiconductor pattern p115 is formed on the preliminary insulating pattern p113 covering the second surface 100b of the substrate 100. A vertical portion p115V of the preliminary semiconductor pattern p115 is formed on the preliminary insulating pattern p113 conformally covering the inner wall of the vertical trench BTR. The vertical portion p115V of the preliminary semiconductor pattern p115 fills the vertical trench BTR.

[0076] 10, the top surface of the horizontal portion p115H of the preliminary semiconductor pattern p115 is planarized. The top surface of the horizontal portion p115H of the preliminary semiconductor pattern p115 becomes conformal. A deep isolation pattern 150 including the semiconductor pattern 115 and the insulating pattern 113 is formed.

[0077] 4 and 10, the light-shielding pattern 48, the low-refractive pattern 50, the color filter CF, the lens insulating film 322, and the microlens MR are formed on the horizontal portion 115H of the semiconductor pattern 115, and the light-transmitting layer 30 is formed.

[0078] 11 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention, and corresponds to a cross-section of the third example taken along line A-A' in FIG. 3. For simplicity of explanation, details that overlap with those described above will be omitted.

[0079] 11, a deep isolation pattern 150 is provided in the photoelectric conversion layer 10. The deep isolation pattern 150 includes an insulating pattern 113 and a semiconductor pattern 115. The deep isolation pattern 150 includes a horizontal portion parallel to the first surface 100a of the substrate 100 and a vertical portion disposed in a vertical trench BTR extending from the horizontal portion toward the first surface 100a of the substrate 100.

[0080] The vertical portion of the deep isolation pattern 150 is filled with the insulating pattern 113, and the horizontal portion of the deep isolation pattern 150 includes the semiconductor pattern 115 and the insulating pattern 113. In this case, the semiconductor pattern 115 does not extend into the substrate 100, but is disposed only on the second surface 100b of the substrate 100. In other words, the semiconductor pattern 115 is defined by the horizontal portion 115H of the semiconductor pattern 115.

[0081] The depth of the vertical portions of the deep isolation patterns 150 is the same. In other words, the depth of the vertical trenches BTR is the same.

[0082] 12 is a cross-sectional view illustrating an image sensor according to an embodiment of the present invention, and corresponds to a cross-section of a fourth example taken along line A-A' in FIG. 3. For simplicity of explanation, details that overlap with those described above will be omitted.

[0083] 12, a deep isolation pattern 150 is provided in the photoelectric conversion layer 10. The deep isolation pattern 150 includes a horizontal portion parallel to the first surface 100a of the substrate 100 and a vertical portion disposed in a vertical trench BTR extending from the horizontal portion toward the first surface 100a of the substrate 100.

[0084] The vertical portion of the deep isolation pattern 150 is filled with the insulating pattern 113, and the horizontal portion of the deep isolation pattern 150 includes the semiconductor pattern 115 and the insulating pattern 113. In this case, the semiconductor pattern 115 does not extend into the substrate 100, but is disposed only on the second surface 100b of the substrate 100. In other words, the semiconductor pattern 115 is defined by the horizontal portion 115H of the semiconductor pattern 115.

[0085] The depths of the vertical portions of the deep isolation pattern 150 are different, in other words, the depths of the vertical trench BTRs are different.

[0086] The depth of one vertical portion is deeper than the depth of the other vertical portions. The distances from the additional isolation pattern 250 to the deep isolation patterns 150 are different among the plurality of deep isolation patterns 150.

[0087] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0088] 1 Active Pixel Sensor Array 2-row driver 3-line decoder 4-row decoder 5 Timing Generator 6. Correlated Double Sampler (CDS) 7 Analog-to-Digital Converter (ADC) 8 Input / Output Buffers 10 Photoelectric conversion layer 11 Top 12 Upper middle 13 Central part 14 Middle and lower 15 Bottom 20 wiring layer 30 Light transmission layer 48 Blackout Pattern 50 Low Refraction Pattern 100 boards 100a Page 1 100b 2nd side 113 Insulation Pattern 115 Semiconductor Pattern 115H, p115H horizontal part 115V, p115V vertical part 150 Deep isolation pattern 210 Interlayer insulating film 221 Contact plug (wiring structure) 223 Metal wiring (wiring structure) 250 additional separation patterns 322 Lens insulating film 1501, 1502 1st, 2nd vertical section 1501BS, 1502BS bottom surface BTR Vertical Trench BTR1, BTR2 First and second vertical trenches CF color filter DX drive transistor FD Floating diffusion region GIL Gate insulating film MR Micro Lens p113 Spare insulation pattern p115 Spare semiconductor pattern PD photoelectric conversion region PD1, PD2 First and second photoelectric conversion elements PX pixel area PX1~PX4 1st to 4th pixel area RG Reset Gate RX reset transistor SG Select Gate SX select transistor TG gate electrode TG1, TG2 First and second transmission gates TR Trench TX1, TX2 First and second transmission transistors V DD Power supply voltage Vout output line

Claims

1. a substrate having a first surface and a second surface facing each other and including a plurality of pixel regions to which light is incident from the second surface; a gate electrode on the first surface; a photoelectric conversion region disposed within the pixel region; a deep isolation pattern defining the pixel area; the deep isolation pattern includes a horizontal portion parallel to a first surface of the substrate and a vertical portion extending from the horizontal portion toward the first surface of the substrate; The vertical portion of the deep element isolation pattern is a lowest portion defined on the lowest surface of the vertical portion; an uppermost portion defined on the uppermost surface of the vertical portion; a central portion defined at the center of the vertical portion; a central lower portion defined between the lowermost portion and the central portion; a central upper portion defined between the top portion and the central portion; the ratio of the width of the top portion to the width of the central portion is 1:0.9 to 1:1.1; The deep isolation pattern is spaced apart from a first surface of the substrate.

2. 2. The image sensor of claim 1, further comprising an additional isolation pattern disposed on the first surface of the substrate, spaced apart from the deep isolation pattern and vertically overlapping the deep isolation pattern.

3. The deep element isolation pattern is a semiconductor pattern; 2. The image sensor of claim 1, further comprising an insulating pattern interposed between the semiconductor pattern and the substrate.

4. The vertical portion of the deep element isolation pattern is a first vertical portion; a second vertical portion spaced adjacent to the first vertical portion, The image sensor of claim 1 , wherein the level of the bottom surface of the first vertical portion is different from the level of the bottom surface of the second vertical portion.

5. 5. The image sensor of claim 4, wherein a ratio of a length of the first vertical portion to a length of the second vertical portion of the deep isolation pattern is 1:0.

8.

6. a light-shielding pattern on a horizontal portion of the deep element isolation pattern; A low refractive index pattern on the light-shielding pattern, 2. The image sensor of claim 1, wherein the light-blocking pattern and the low-refractive pattern have a lattice structure that defines light-transmitting regions that vertically overlap a plurality of unit pixels.

7. 2. The image sensor of claim 1, wherein a ratio of the width of the top portion to the width of the middle portion is 1:1 to 1:1.

15.

8. The vertical portion of the deep element isolation pattern is A first vertical portion; a second vertical portion spaced adjacent to the first vertical portion, The image sensor according to claim 1 , wherein, in a plan view, one microlens is disposed between the first vertical portion and the second vertical portion.

9. 2. The image sensor of claim 1, further comprising a wiring provided in an interlayer insulating film on the first surface and electrically connected to the gate electrode.

10. a substrate having a first surface in contact with the gate electrode and a second surface facing the first surface and onto which light is incident, the substrate including a plurality of pixel regions; a photoelectric conversion region disposed within the pixel region; a deep isolation pattern defining the pixel area; The deep element isolation pattern is a horizontal portion parallel to the first surface of the substrate; a vertical portion disposed within a vertical trench extending from the horizontal portion toward the first surface of the substrate; a sidewall of the vertical trench is perpendicular to the first surface of the substrate; The image sensor is characterized in that the depth of the vertical trench is smaller than the thickness of the substrate.

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