Semiconductor device

Abstract

To provide a semiconductor device that generates a temperature-compensated and power supply-voltage-compensated current.SOLUTION: A semiconductor device 1 includes: a first current generating circuit 11 that generates a first current that has a positive temperature coefficient and is independent of a first power supply voltage; a second current generating circuit 12 that generates a second current that has a negative temperature coefficient and is independent of the first power supply voltage; and a third current generating circuit 13 that generates a third current that is independent of temperature and the first power supply voltage based on the first current and the second current.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to semiconductor devices that generate temperature compensated current. [Background technology]

[0002] Patent Document 1 discloses a technique for generating a temperature-compensated and power supply voltage-compensated reference voltage of 1.2 V or less. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-206633 Summary of the Invention [Problem to be solved by the invention]

[0004] The reference voltage generating circuit described in Patent Document 1 has a problem in that it is unable to generate a temperature-compensated and power supply voltage-compensated voltage of 1.2 V or higher.

[0005] The present disclosure has been made to solve such problems, and has an object to realize a semiconductor device that generates a current that is temperature compensated and power supply voltage compensated.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes a first current generating circuit that generates a first current having a positive temperature coefficient and independent of a first power supply voltage, a second current generating circuit that generates a second current having a negative temperature coefficient and independent of the first power supply voltage, and a third current generating circuit that generates a third current based on the first current and the second current, the third current being independent of temperature and the first power supply voltage. [Effects of the Invention]

[0008] According to the embodiment, it is possible to provide a semiconductor device that generates a current that is temperature compensated and power supply voltage compensated. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a graph showing the temperature dependence of current according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of the semiconductor device according to the second embodiment. [Figure 4] FIG. 4 is a graph showing the temperature dependency of the reference voltage according to the second embodiment. [Figure 5] FIG. 5 is a diagram for explaining one of the effects of the second embodiment. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of a semiconductor device according to the third embodiment. [Figure 7] FIG. 7 is a graph showing the temperature dependency of the reference voltage according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are denoted by the same reference numerals, and repeated explanations have been omitted as necessary.

[0011] Embodiment 1 1 is a circuit diagram of a semiconductor device 1 according to embodiment 1. The semiconductor device 1 includes current generating circuits 11, 12, and 13. The current generating circuits 11, 12, and 13 are also referred to as a first current generating circuit, a second current generating circuit, and a third current generating circuit, respectively.

[0012] The current generating circuit 11 includes p-channel MOS (Metal-Oxide-Semiconductor) transistors MP1 and MP2, an n-channel MOS transistor MN1, npn-type bipolar transistors Bip1 and Bip2, a resistor R1, and an amplifier Amp1.

[0013] The MOS transistor MP1 and the bipolar transistor Bip1 are connected in series between a power supply voltage VCC and a ground voltage GND. The power supply voltage VCC is also referred to as the first power supply voltage. The MOS transistor MP2, the bipolar transistor Bip2, and the resistor R1 are connected in series and in parallel with the MOS transistor MP1 and the bipolar transistor Bip1. The gates of the bipolar transistors Bip1 and Bip2 are connected to the source of the MOS transistor MN1, and the gate of the MOS transistor MN1 is connected to the connection node between the MOS transistor MP1 and the bipolar transistor Bip1. The drain of the MOS transistor MN1 is connected to the power supply voltage VCC. The negative input terminal of the amplifier Amp1 is connected to the connection node between the MOS transistor MP1 and the bipolar transistor Bip2. The positive input terminal of the amplifier Amp1 is connected to the connection node between the MOS transistor MP2 and the bipolar transistor Bip2. The output terminal of the amplifier Amp1 is connected to the gates of the MOS transistors MP1 and MP2. The amplifier Amp1 controls the MOS transistors MP1 and MP2 so that the voltage at the connection node to which the positive input terminal is connected and the voltage at the connection node to which the negative input terminal is connected become equal to each other.

[0014] When the element sizes of the MOS transistors MP1 and MP2, i.e., the gate length and gate width, are equal to each other, the current Iref1 (also referred to as the first current) flowing between the source and drain of the MOS transistor MP2 of the current generating circuit 11 is expressed by the following equation (1). The temperature coefficient ΔIref1 / ΔT of the current Iref1 is expressed by the following equation (2). Iref1=1 / R1*(kT / q)*(lnM)...Equation (1) ΔIref1 / ΔT=(1 / R1)*(k / q)*(lnM)...Equation (2) Here, M represents the ratio of the emitter area of ​​bipolar transistor Bip1 to the emitter area of ​​bipolar transistor Bip2. The elementary charge q is 1.6*10^(-19) [C], Boltzmann's constant k is 1.38*10^(-23) [J / K], and T represents absolute temperature [K]. The resistance value of resistor R1 is R1.

[0015] From equation (2), it can be seen that ΔIref1 / ΔT>0··· equation (3) holds.

[0016] The current generating circuit 12 includes p-channel MOS transistors MP3 to MP4, n-channel MOS transistors MN2 to MN3, an npn bipolar transistor Bip3, and a resistor R2.

[0017] MOS transistors MP3, MN1, and bipolar transistor Bip3 are connected in series between power supply voltage VCC and ground voltage GND. The collector and base of bipolar transistor Bip3 are connected together. MOS transistors MP4, MN3, and resistor R2 are connected in series and connected in parallel to MOS transistors MP3, MN1, and Bip3. The gates of MOS transistors MP3 and MP4 are connected to the node between MOS transistors MP4 and MN3. The gates of MOS transistors MN2 and MN3 are connected to the node between MOS transistors MP3 and MN2. MOS transistors MP3, MP4, MN2, and MN3 form a current mirror circuit. If the device sizes of MOS transistors MP3, MP4, MN1, and MN2 are equal, the currents flowing through MOS transistors MP3, MP4, MN1, and MN2 are equal. The voltage at the connection node between the MOS transistor MN2 and the bipolar transistor Bip3 is equal to the voltage at the connection node between the MOS transistor MN3 and the resistor R2.

[0018] When the element sizes of the MOS transistors MP3, MP4, MN1, and MN2 are equal to one another, the current Iref2 (also referred to as the second current) flowing through the MOS transistor MP4 of the current generating circuit 12 is expressed by the following equation (4). The temperature coefficient ΔIref2 / ΔT is expressed by the following equation (5). Iref2=(VBE_Bip3) / R2...Equation (4) ΔIref2 / ΔT=((ΔVBE_Bip3) / ΔT) / R2...(5) Here, VBE_Bip3 is the base-emitter voltage of the bipolar transistor Bip3. The resistance value of the resistor R2 is R2.

[0019] Since ΔVBE_Bip3 / ΔT<0, the following equation (6) is derived from equation (5). ΔIref2 / ΔT<0...Equation (6)

[0020] The current generating circuit 13 includes p-channel MOS transistors MP5 to MP6. The source of the MOS transistor MP5 is connected to the power supply voltage VCC, and the gate of the MOS transistor MP5 is connected to the gate of the transistor MP4. The MOS transistor MP6 is connected in parallel to the MOS transistor MP5, and the gate of the MOS transistor MP6 is connected to the gate of the transistor MP2. The MOS transistor MP5 copies the current Iref2 flowing between the source and drain of the MOS transistor MP4 at a predetermined mirror ratio. The MOS transistor MP6 copies the current Iref1 flowing between the source and drain of the MOS transistor MP2 at a predetermined mirror ratio. The current flowing between the source and drain of the MOS transistor MP5 and the current flowing between the source and drain of the MOS transistor MP6 join together to generate a current Iref3 (also referred to as a third current).

[0021] The current Iref3 is expressed by the following equation (7): The temperature coefficient ΔIref3 / ΔT is expressed by the following equation (8). Iref3=A*Iref1+B*Iref2...Equation (7) ΔIref3 / ΔT=A*ΔIref1 / ΔT+B*ΔIref2 / ΔT...Formula (8) Here, A represents the mirror ratio of the MOS transistors MP2 and MP6, and B represents the mirror ratio of the MOS transistors MP4 and MP5.

[0022] From equations (8), (3), and (6), by appropriately setting A and B, a current Iref3 that is independent of temperature can be obtained. Furthermore, equation (8) does not include a term related to the power supply voltage VCC. Therefore, the semiconductor device 1 according to the first embodiment can generate a current that is independent of the power supply voltage and temperature.

[0023] Next, a specific description will be given of the case where the following condition 1 is set. Condition (1): R1=50[KΩ], M=8, R2=900[KΩ], A=2, B=4

[0024] By substituting the numerical values ​​of condition (1) into equations (1), (2), (4), (5), (7), and (8), the following equations (1'), (2'), (4'), (5'), (7'), and (8') are obtained. Iref1=(1 / 50K)*(kT / q)*(ln8)=1[μA]...Equation (1') ΔIref1 / ΔT=(1 / 50K)*(k / q)*(ln8)=3.6[nA / ℃]...Equation (2') Iref2=(VBE_Bip3) / 900K=770[nA]...Formula (4') ΔIref2 / ΔT=(ΔVBE / ΔT) / 900K=-1.62[mV / ℃] / 900[KΩ]=-1.8[nA / ℃]...Formula (5') Iref3=2*Iref1+4*Iref2=5[μA]...Equation (7') ΔIref3 / ΔT=2*ΔIref1 / ΔT+4*ΔIref2 / ΔT=0[A / ℃]...Formula (8') Here, (ΔVBE / ΔT)=−1.62 [mV / ° C.] is set based on the simulation results of the temperature coefficient of VBE when the emitter current: IE=770 nA.

[0025] Since the temperature coefficient shown in equation (8') is 0, it is confirmed that a current independent of temperature can be generated.

[0026] Figure 2 shows the simulation results when condition (1) is set. The horizontal axis represents temperature, and the vertical axis represents current. C1 represents the temperature dependence of the current flowing between the source and drain of MOS transistor MP6, i.e., Iref1*2. C2 represents the temperature dependence of the current flowing between the source and drain of MOS transistor MP5, i.e., Iref2*4. C3 represents the temperature dependence of Iref3. The dotted line extending vertically represents 25°C. When the temperature is 25°C, Iref1*2 = 2 μA, Iref2*4 = 3 μA, and Iref3 = 5 μA. It can be seen that Iref1 has a positive temperature dependence, Iref2 has a negative temperature dependence, and Iref3 has no temperature dependence.

[0027] Embodiment 2 3 is a circuit diagram of a semiconductor device 1a according to embodiment 2. The semiconductor device 1a generates a reference voltage that is independent of temperature and power supply voltage VCC, based on the above-mentioned current Iref3.

[0028] 1 and 3, the current generating circuit 13 of the semiconductor device 1a further includes a resistor R3. One end of the resistor R3 is connected to the connection node between the MOS transistor MP5 and the MOS transistor MP6. The other end of the resistor R3 is connected to the ground voltage GND. When a current Iref3 flows through the resistor R3, a reference voltage Vref3 is generated at one end of the resistor R3.

[0029] The reference voltage Vref3 is expressed by the following equation (9): The temperature coefficient ΔVref3 / ΔT is expressed by the following equation (10). Vref3=Iref3*R3 Equation (9) ΔVref3 / ΔT=(ΔIref3 / ΔT)*R3...Equation (10)

[0030] As described above, by appropriately setting A and B in equation (8), it is possible to realize a current Iref3 that has no temperature dependency and has a temperature coefficient ΔIref3 / ΔT shown in equation (11) below. ΔIref3 / ΔT=0 Equation (11) By substituting equation (11) into equation (10), it is found that ΔVref3 / ΔT=0 can be realized.

[0031] From the above explanation, it can be seen that by appropriately selecting the resistance value of resistor R3, it is possible to generate any reference voltage Vref that is temperature compensated and power supply voltage compensated. In particular, a reference voltage Vref of 1.2 V or higher can be generated.

[0032] Next, a specific description will be given of a case where the following condition (2) is set in addition to the above-mentioned condition (1). Condition (2): R3=500[KΩ]

[0033] Substituting Iref3 calculated in equation (7') and condition (2) into equation (9) gives the following equation (9'): Then, substituting ΔIref3 / ΔT=0 shown in equation (11) into equation (10) gives the following equation (10'): Vref3=Iref3*R3=5[μA]*500[KΩ]=2.5[V]...Formula (9') ΔVref3 / ΔT=(ΔIref3 / ΔT)*R3=0*500[KΩ]=0[V / ℃]...Formula (10')

[0034] It is confirmed that the temperature coefficient shown in equation (10') is 0, and that a reference voltage Vref that is independent of temperature can be generated. Referring to equation (9'), it is confirmed that a reference voltage of 1.2 V or higher can be generated.

[0035] FIG. 4 shows the simulation results when conditions (1) and (2) are set. The horizontal axis represents temperature, and the vertical axis represents voltage. C4 represents the temperature dependence of the reference voltage Vref. The reference voltage Vref is approximately 2.5 V, which is 1.2 V or higher. This simulation result shows that embodiment 2 can generate a reference voltage of 1.2 V or higher that is not temperature dependent.

[0036] Next, referring to Figure 5, one of the effects achieved by generating an arbitrary reference voltage of 1.2V or higher that is independent of temperature and power supply voltage will be described. Negative feedback amplifier circuit 2 includes amplifier circuit 3 and feedback circuit 4. Feedback circuit 4 returns a portion of the voltage amplified by amplifier circuit 3 to the input of amplifier circuit 3 in reverse phase. The following equation (12) holds for the input voltage Vin and output voltage Vout of negative feedback amplifier circuit 2. Vout / Vin=A / (1+β F *A)...Formula (12) Here, β F represents the feedback ratio of the feedback circuit 4, and A represents the gain of the amplifier circuit 3.

[0037] A is usually sufficiently large relative to 1, and is 1000 times or more. Therefore, equation (12) can be transformed as shown in the following equation (13). Vout / Vin=A / (1+β F *A)≒1 / β F ...Equation (13)

[0038] β, which constitutes equation (13), F It is known that the larger β is, the lower the distortion and the higher the speed can be. For example, when the reference voltage Vref=2.5V according to the second embodiment is supplied as Vin to obtain Vout=2.5[V], β F On the other hand, when the reference voltage Vref=1.25V according to the conventional technology is supplied as Vin, β F =0.5.

[0039] The feedback amount β of the negative feedback amplifier circuit F Therefore, the second embodiment can achieve low distortion and high speed in the negative feedback amplifier circuit.

[0040] Embodiment 3 6 is a circuit diagram of a semiconductor device 1b according to embodiment 3. The semiconductor device 1b generates a reference voltage based on the power supply voltage Vbat, based on the above-mentioned current Iref3.

[0041] 1 and 6, semiconductor device 1b further includes a reference voltage generation circuit 14 that uses power supply voltage Vbat as a reference. Reference voltage generation circuit 14 includes an n-channel MOS transistor MN5 and a resistor R4. Current generation circuit 13 also includes an n-channel MOS transistor MN4.

[0042] MOS transistor MN4 is provided between the connection node of MOS transistors MP3 and MP4 and ground voltage GND. Resistor R4 and MOS transistor MN5 are connected in series between power supply voltage Vbat and ground voltage GND. Power supply voltage Vbat is also referred to as the second power supply voltage. The gates of MOS transistors MN4 and MN5 are connected to the drain of transistor MN4. One end of resistor R4 is connected to power supply voltage Vbat, and the other end of resistor R4 generates reference voltage Vref4.

[0043] The power supply voltage Vbat is, for example, the voltage of a battery installed in a vehicle. MOS transistors MN4 and MN5 form a current mirror circuit, and MOS transistor MN5 passes a mirror current Iref4 of current Iref3 through resistor R4. This generates a reference voltage Vref4 at the connection node between resistor R4 and MOS transistor MN5.

[0044] The reference voltage Vref4 is expressed by the following equation (14): The temperature coefficient ΔVref4 / ΔT is expressed by the following equation (15). Vref4=Vbat-(Iref4*R4)...Equation (14) ΔVref4 / ΔT=-(ΔIref4 / ΔT)*R4...Equation (15) Here, Iref4 is the mirror current of the current Iref3, as described above. Since ΔIref3 / ΔT=0 holds in equation (11), ΔIref4 / ΔT=0 also holds. Therefore, it can be seen from equation (15) that ΔVref4 / ΔT=0 can also be realized.

[0045] Therefore, in the third embodiment, by appropriately selecting the resistor R4, it is possible to obtain an arbitrary temperature-compensated reference voltage Vref4 based on a power supply voltage Vbat different from the power supply voltage VCC. Furthermore, the power supply voltage Vref4 does not depend on the power supply voltage VCC.

[0046] Next, a specific description will be given of a case where the following condition (3) is set in addition to the above-mentioned condition (1). Condition (3): R4=200[KΩ], Vbat=12.5[V]

[0047] Substituting condition (3) into equation (14) gives the following equation (14'): Substituting condition (3) into equation (15) gives the following equation (15'): Note that Iref4=5[μA] is set based on Iref3=5[μA] in equation (7'). Vref4=Vbat-(Iref4*R4)=12.5[V]-5[μA]*200[KΩ])=11.5[V]...Formula (14') ΔVref4 / ΔT=-(ΔIref4 / ΔT)*R4=0*200[KΩ]=0...Formula (15')

[0048] It is confirmed that the temperature coefficient shown in equation (15') is 0, and that the reference voltage Vref4 can be generated independent of temperature.

[0049] FIG. 7 shows the simulation results when conditions (1) and (3) are set. The horizontal axis represents temperature, and the vertical axis represents voltage. C5 represents the power supply voltage Vbat, and C6 represents the temperature dependence of the reference voltage Vref. The power supply voltage Vbat is 12.5 V, and the reference voltage Vref4 is approximately 11.5 V. This simulation result shows that embodiment 3 can generate a reference voltage Vref4 that is not temperature dependent.

[0050] In the third embodiment, a mirror current Iref4 of the current Iref3 generated with respect to the ground voltage GND is passed through a resistor R4 connected to the power supply voltage Vbat, thereby enabling the third embodiment to generate a reference voltage Vref with respect to the power supply voltage Vbat.

[0051] Normally, to generate a reference voltage based on the power supply voltage Vbat, a reference voltage source based on the power supply voltage Vbat must be prepared in addition to a reference voltage source based on the ground voltage GND. In the third embodiment, this is not necessary, and therefore the circuit area and current consumption can be reduced.

[0052] Furthermore, the reference voltage generating circuit 14 may be included in a semiconductor device separate from the semiconductor device including the current generating circuits 11, 12, and 13. For example, the semiconductor device including the reference voltage generating circuit 14 may be an intelligent power device (IPD) including a power MOSFET, and the semiconductor device including the current generating circuits 11, 12, and 13 may be an MCU that controls the IPD. The IPD may include a control circuit connected to a battery power supply (Vbat) and controlling the power MOSFET. If a reference voltage is required by the control circuit in the IPD, a reference voltage source based on the battery power supply Vbat, such as a bandgap reference circuit, must be provided in the IPD. In this case, the reference voltage source in the IPD must be composed of high-voltage elements. However, according to the third embodiment, the reference potential generating circuit in the IPD can generate a reference voltage based on the battery power supply Vbat with a circuit configuration simpler than that of a bandgap reference circuit. This makes it possible to reduce the circuit area and current consumption of the IPD.

[0053] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0054] For example, the regulators according to the above embodiments may be configured such that the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. are reversed. Therefore, if one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type. [Explanation of symbols]

[0055] 1, 1a, 1b Semiconductor device 11, 12, 13 Current generation circuit 14 Reference voltage generation circuit 2. Negative feedback amplifier circuit 3 Amplification circuit 4 Feedback circuit MP1, MP2, MP3, MP4, MP5, MP6, MN1, MN2, MN3, MN4, MN5 MOS transistors Bip1, Bip2 bipolar transistors R1, R2, R3, R4 resistance Amp1 operational amplifier Iref1, Iref3, Iref3 current Vref3, Vref4 reference voltage VCC, Vbat power supply voltage GND Ground voltage

Claims

1. a first current generating circuit that generates a first current that has a positive temperature coefficient and is independent of a first power supply voltage; a second current generating circuit that generates a second current that has a negative temperature coefficient and is independent of the first power supply voltage; a third current generating circuit that generates a third current that has no temperature dependency and is independent of the first power supply voltage, based on the first current and the second current; A semiconductor device comprising:

2. the third current is generated by combining a current obtained by copying the first current at a first mirror ratio and a current obtained by copying the second current at a second mirror ratio; The first mirror ratio and the second mirror ratio are set so that the temperature coefficient of the third current is zero. The semiconductor device according to claim 1 .

3. generating a reference voltage that has no temperature dependency and that is independent of the first power supply voltage based on the third current; The semiconductor device according to claim 1 .

4. The reference voltage is greater than 1.2V The semiconductor device according to claim 3 .

5. The power supply further includes a negative feedback amplifier circuit for amplifying the reference voltage. The semiconductor device according to claim 3 .

6. The feedback ratio in the negative feedback amplifier circuit is greater than 0.

5. The semiconductor device according to claim 5 .

7. a current mirror circuit that causes a current that is a copy of the third current to flow through a resistor having one end connected to a second power supply voltage; The reference voltage is generated at the other end of the resistor. The semiconductor device according to claim 3 .

8. The second power supply voltage is a battery voltage. The semiconductor device according to claim 7 .

9. The second current is generated based on the base-emitter voltage of the bipolar transistor. The semiconductor device according to claim 1 .

Images