Semiconductor device

Abstract

To mitigate the adhesion strength between an alloy layer formed on a semiconductor layer and a metal layer above it, while preventing deterioration of the contact resistance.SOLUTION: A semiconductor device comprises a semiconductor substrate (10), an alloy layer (20) containing the constituent elements of the semiconductor substrate (10) as its main components, and an upper metal layer (30) formed on the alloy layer (20). A plurality of micro regions (31) containing an inert gas are discretely arranged at the interface between the alloy layer (20) and the upper metal layer (30). Over 90% of the plurality of micro regions (31) have an arc shape with the widest opening.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, Patent Document 1 below discloses a technique for suppressing the generation of voids caused by the incorporation of Ar gas into a silicide film by using a metal that forms a silicide with a high metal composition in the initial silicide reaction, such as Co, as a barrier metal when forming a silicide layer on a semiconductor substrate. This technique can prevent the deterioration of contact resistance between the silicide film and the electrode formed thereon.

[0003] The phenomenon of void formation due to aggregation of inert gas elements contained in a metal film by heat treatment has been reported in, for example, Non-Patent Document 1 listed below.

[0004] Furthermore, Patent Document 2 listed below discloses a technology in which a recess that is keyhole-shaped in cross section (with an entrance narrower than the internal space) is formed on the surface of an electrode, and the bonding strength between the electrode and the upper electrode above it is improved by the anchor effect. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-223178 [Patent Document 2] International Publication No. 2021 / 246241 [Non-patent literature]

[0006] [Non-Patent Document 1] Peter Hatton, et al., "Inert gas bubble formation in magnetron sputtered thin-film CdTe solar cells", Proc. Of the royal soc. A, vol 476, issue 2239 Summary of the Invention [Problem to be solved by the invention]

[0007] The technology in Patent Document 1 forms a uniformly dense silicide film at the contact point between the semiconductor substrate and the electrode, which increases the adhesive strength between the semiconductor substrate and the electrode. However, if the adhesive strength between the semiconductor substrate and the electrode is too high, damage caused by external stress can easily extend to the active cells of the semiconductor substrate, which can cause serious accidents such as short-circuit damage.

[0008] The present disclosure has been made to solve the above-mentioned problems, and aims to reduce the adhesion strength between an alloy layer formed on a semiconductor layer and a metal film while preventing deterioration of the contact resistance between the alloy layer and the metal layer above it. [Means for solving the problem]

[0009] The semiconductor device according to the present disclosure comprises a semiconductor substrate, an alloy layer containing constituent elements of the semiconductor substrate as its main component, and an upper metal layer formed on the alloy layer, wherein a plurality of micro-regions containing an inert gas are discretely arranged at the interface between the alloy layer and the upper metal layer, and at least 90% of the plurality of micro-regions have an arc shape with the widest opening. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to prevent deterioration of the contact resistance between an alloy layer formed on a semiconductor layer and a metal layer (upper metal layer) thereon, while reducing the adhesion strength between the alloy layer and the metal film. [Brief explanation of the drawings]

[0011] [Figure 1] 2 is a diagram showing a basic structure of a contact portion of the semiconductor device according to the first embodiment. FIG. [Figure 2] 5A to 5C are diagrams for explaining a method of forming a contact portion of the semiconductor device according to the first embodiment. [Figure 3] 5A to 5C are diagrams for explaining a method of forming a contact portion of the semiconductor device according to the first embodiment. [Figure 4] 3 is a diagram showing a specific example of a contact portion of the semiconductor device according to the first embodiment. FIG. [Figure 5] 4 is a diagram showing an atomic number contrast image of a contact portion of the semiconductor device according to the first embodiment. FIG. [Figure 6] FIG. 10 is a diagram showing an atomic number contrast image of a conventional contact portion without a micro-region. [Figure 7] FIG. 6 is an enlarged view of the vicinity of a minute region in the atomic number contrast image of FIG. 5. [Figure 8] FIG. 3 is a diagram showing an elemental map image of Si in the contact portion of the semiconductor device according to the first embodiment. [Figure 9] FIG. 4 is a diagram showing an element map image of Ar at the contact portion of the semiconductor device according to the first embodiment. [Figure 10] FIG. 4 is a diagram showing an EDX spectrum of a contact portion of the semiconductor device according to the first embodiment. [Figure 11] 2 is a diagram showing the structure of a contact portion of the semiconductor device according to the first embodiment; FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] <First Embodiment> 1 is a diagram showing the basic structure of a contact portion of a semiconductor device according to embodiment 1. The "contact portion" in this embodiment refers to the portion where a semiconductor substrate 10 and an upper metal layer 30 are connected via an alloy layer 20, as shown in FIG.

[0013] The semiconductor substrate 10 has, for example, Si, SiC, or a compound containing Ga as its constituent elements. The alloy layer 20 is formed on the upper surface of the semiconductor substrate 10 and is made of an alloy containing the constituent elements of the semiconductor substrate 10 as its main component. When the semiconductor substrate 10 is a wide bandgap semiconductor such as SiC or GaN, a semiconductor device that is superior in operation at high voltages, large currents, and high temperatures can be obtained compared to when the semiconductor substrate 10 is made of silicon.

[0014] An n-type layer or a p-type layer containing a donor or an acceptor as a dopant may be selectively formed in the surface layer portion of the semiconductor substrate 10. The alloy layer 20 may be in contact with either or both of the n-type layer and the p-type layer formed in the semiconductor substrate 10. Alternatively, the alloy layer 20 may be formed by alloying the surface layer portion of either or both of the n-type layer and the p-type layer formed in the semiconductor substrate 10.

[0015] The alloy layer 20 is formed, for example, by depositing a metal film (corresponding to the "metal film 21" described below) on the semiconductor substrate 10 by sputtering or chemical vapor deposition (CVD), and then performing heat treatment to chemically react the metal film with the semiconductor substrate 10 to form an alloy. Therefore, the alloy layer 20 contains, as its main components, the constituent elements of the semiconductor substrate 10 and the constituent elements of the metal film before alloying. The metal film before alloying is expected to contain, for example, Ti, Ni, Co, or the like, as its main component. When the semiconductor substrate 10 is Si or SiC, the alloy layer 20 is preferably a silicide compound.

[0016] The upper metal layer 30 is formed on the alloy layer 20. The upper metal layer 30 is made of, for example, Ti, Ni, W, Cu, Al, or an alloy containing one or more of these (for example, TiN), and is formed by, for example, a sputtering method or a CVD method. There may be another upper metal layer on the upper metal layer 30 that is made of a different component from the upper metal layer 30. Furthermore, a stacked structure in which a metal made of a different component or the same metal as the upper metal layer 30 is stacked may be formed on the upper metal layer 30.

[0017] A plurality of minute regions 31 containing an inert gas are discretely formed at the interface between the alloy layer 20 and the upper metal layer 30. The minute regions 31 have a shape that corrodes the alloy layer 20, i.e., a shape that penetrates into the alloy layer 20 from the interface between the alloy layer 20 and the upper metal layer 30. Furthermore, in a cross-sectional view, the minute regions 31 have an arc shape with the widest opening. By discretely forming minute regions 31 of this shape between the alloy layer 20 and the upper metal layer 30, it is possible to prevent a deterioration in contact resistance between the alloy layer 20 and the upper metal layer 30 while reducing the adhesion strength between the alloy layer 20 and the upper metal layer 30. The inert gas may be Ar, N, or another rare gas element.

[0018] Here, as shown in FIG. 1, the depth of the minute region 31 is defined as t1, the width of the minute region 31 as w1, and the thickness of the alloy layer 20 as t2. The thickness t2 of the alloy layer 20 is preferably, for example, 10 nm or more and 50 nm or less. The depth t1 of the minute region 31 is preferably, for example, 5 nm or more and less than t2. The width w1 of the minute region 31 is preferably, for example, 5 nm or more and less than 100 nm. It is desirable that 90% or more of the multiple minute regions 31 have an arc shape with the widest opening in a cross-sectional view.

[0019] In the semiconductor device, the upper metal layer 30 is used as an electrode electrically connected to the semiconductor substrate 10 via the alloy layer 20. For example, if the semiconductor device is a semiconductor device for power control (a so-called power device), the adhesion strength of the electrode can be an important design parameter in stress tests such as a power cycle (P / C) test and a heat cycle (H / C) test.

[0020] If the adhesion strength of the upper metal layer 30, which serves as an electrode, is too low, the upper metal layer 30 will peel off during a stress test, shortening the lifespan of the semiconductor device. However, if the adhesion strength of the upper metal layer 30 is too high, destruction during a stress test will extend into the interior of the semiconductor substrate 10 rather than to the interface between the upper metal layer 30 and the alloy layer 20. Destruction within the semiconductor substrate 10 can short-circuit the semiconductor device. For example, if a semiconductor device that holds a voltage of several hundred to several thousand volts shorts out, it can cause serious destruction of the entire system in which the semiconductor device is installed.

[0021] The adhesion strength of the electrode can be controlled by applying the contact structure according to the first embodiment to the electrode of the semiconductor device. By keeping the adhesion strength of the electrode within a desired range, breakdown can be limited to the interface between the alloy layer 20 and the upper metal layer 30 without impairing the lifespan during stress testing, and short circuits in the semiconductor device can be suppressed.

[0022] In the past, a problem was that the contact resistance of the upper metal layer 30 deteriorated due to the formation of voids in the alloy layer 20. Because it was difficult to control the composition, shape, and size of the voids, it was thought that the voids should be completely eliminated.

[0023] Through detailed analysis of the semiconductor manufacturing process, the inventors of the technology disclosed herein have succeeded in discretely arranging minute regions 31, which are different from voids, at the interface between the alloy layer 20 and the upper metal layer 30.

[0024] More preferable parameters for controlling adhesion strength without deteriorating the contact resistance of the upper metal layer 30 are that the thickness t2 of the alloy layer 20 is 30 nm or more, the width w1 of the microregion 31 is less than 100 nm, and the depth t1 of the microregion 31 is less than t2. Also, it is desirable that the occupancy rate of the microregion 31 at the interface between the alloy layer 20 and the upper metal layer 30 is less than 50%. It is desirable that the atomic concentration of the inert gas in the microregion 31 is 0.5 wt% or more and less than 20.0 wt%, and it is desirable that the atomic density of the constituent elements of the alloy layer 20 in the microregion 31 is 80.0 wt% or more.

[0025] The atomic concentration of the micro-region 31 may be a value that is quantitatively evaluated by a general elemental analysis method such as EDX (Energy Dispersive X-ray spectroscopy). In the elemental analysis method, if the evaluation region is small, such as on the order of nanometers, it is expected that a value including regions other than the evaluation target will be output. However, this is not a problem as long as the elements in the micro-region 31 can be detected as shown in Figures 8 and 10, which will be described later.

[0026] If the width w1 of the minute region 31 is too wide, the substantial thickness of the alloy layer 20 will decrease and the contact resistance will deteriorate. Also, if the depth t1 of the minute region 31 is too large, the upper metal layer 30 and the semiconductor substrate 10 will come into contact with each other, preventing good ohmic contact, which will also deteriorate the contact resistance. Also, if the occupancy rate of the minute region 31 is too high, this will result in the substantial thickness of the alloy layer 20 decreasing and the contact resistance deteriorating, just as in the case where the width w1 of the minute region 31 is too wide.

[0027] Furthermore, if the minute regions 31 are not formed at the interface between the alloy layer 20 and the upper metal layer 30, the adhesion strength of the upper metal layer 30 increases, making it easier for the fracture to extend into the semiconductor substrate 10 during a stress test. Also, if the minute regions 31 have a keyhole shape like the recesses in Patent Document 2, the adhesion strength of the upper metal layer 30 will be excessively high due to the anchor effect, making it easier for the fracture to extend into the semiconductor substrate 10 during a stress test. Therefore, it is important to control the width, depth, density, shape, and position of the minute regions 31 within preferred ranges.

[0028] 2(a) to 2(c) show a method for manufacturing a semiconductor device according to the first embodiment, in particular a method for forming a contact portion.

[0029] First, as shown in Figure 2(a), a metal film 21, which will be the material for alloy layer 20, is formed on semiconductor substrate 10 by sputtering or CVD. Then, heat treatment is performed to chemically react semiconductor substrate 10 with metal film 21, thereby forming alloy layer 20. At this time, by using the following method, minute regions 31 can be formed on the surface of alloy layer 20, as shown in Figure 2(b).

[0030] Here, we will explain the case where the metal film 21 is formed by sputtering. Sputtering is a film formation method in which a chamber is generally filled with an inert gas at a certain ratio, the inert gas is converted into plasma, and the plasma is caused to collide with a target metal, physically breaking the bonds between the atoms of the target metal, ionizing (activating) the metal atoms, and depositing them on the semiconductor substrate 10. The metal film 21 deposited on the semiconductor substrate 10 contains not only the desired metal ions, but also trace amounts of inert gas ions converted into plasma. In conventional manufacturing methods, the content of these inert gas ions is small, and they either volatilize and disappear during heat treatment to alloy the metal film 21, or are incorporated into the alloy layer 20 without agglomerating.

[0031] In this embodiment, by increasing the concentration of the inert gas contained in the metal film 21 before alloying, minute regions 31 are formed on the surface of the alloy layer 20, as shown in FIG. 2(b). In the minute regions 31, the mass percent concentration of the atoms constituting the alloy layer 20 is low, and the content of the inert gas is high. In other words, the minute regions 31 are coarse regions where the atomic density is reduced due to the aggregation of the inert gas during heat treatment.

[0032] 2(c), a metal film is deposited on the alloy layer 20 including the minute regions 31 to form the upper metal layer 30. After the upper metal layer 30 is formed, it may be subjected to a heat treatment.

[0033] The heat treatment for alloying the metal film 21 and forming the microregions 31 may be performed after depositing the upper metal layer 30. That is, first, as shown in FIG. 3(a), a metal film 21 that will be the material for the alloy layer 20 is formed on the semiconductor substrate 10, and then, as shown in FIG. 3(b), the upper metal layer 30 is formed on the metal film 21. Then, by performing a heat treatment thereafter, as shown in FIG. 3(c), the semiconductor substrate 10 and the metal film 21 are chemically reacted to form the alloy layer 20, and the microregions 31 may be formed on the surface of the alloy layer 20.

[0034] The micro-regions 31 are similar to voids in that they are formed by the aggregation of inert gas elements contained in the metal film 21 before alloying due to heat treatment, but the width, depth, density, position, atomic density, etc. of the micro-regions 31 are controlled and are not complete voids.

[0035] The metal film 21 before alloying may be deposited using a CVD method. However, unlike the sputtering method, the metal film 21 does not incorporate an inert gas. Therefore, after depositing the metal film 21, it is necessary to introduce an inert gas into the metal film 21 by, for example, an ion implantation method. Even if an inert gas is introduced after depositing the metal film 21, the inert gas will aggregate if a heat treatment is performed, and the microdomains 31 will be formed.

[0036] Next, we will explain how to control the parameters of the minute region 31. Since the minute region 31 is formed by aggregation of inert gas atoms, in order to control the parameters of the minute region 31, it is necessary to control the amount of inert gas contained in the metal film 21 before alloying.

[0037] For example, when forming the metal film 21 by sputtering, the amount of inert gas incorporated into the metal film 21 can be controlled by adjusting the pressure in the chamber, the plasma density, the voltage for attracting active species to the semiconductor substrate 10, and the like. The pressure in the chamber can be adjusted by the flow rate of the inert gas, which can be adjusted, for example, from 1 sccm to 100 sccm. The plasma density can be adjusted by the DC bias, which is one of the adjustment parameters, which can be adjusted, for example, from 1 kW to 50 kW. The voltage for attracting active species can be adjusted by the AC bias, which can be adjusted, for example, from 1 W to 1 kW. The temperature during film formation can be adjusted, for example, from room temperature to 500°C.

[0038] Furthermore, the thicker the metal film 21 before alloying, the greater the amount of inert gas atoms that aggregate at the interface, so a thicker metal film 21 is preferred. However, if the metal film 21 is too thick, the resulting alloy layer 20 will also be thick, and the alloy layer 20 will be formed deeper than the n-type layer or p-type layer in the surface layer portion of the semiconductor substrate 10, increasing the contact resistance. Therefore, the thickness t2 of the alloy layer 20 is preferably, for example, 30 nm or more and 50 nm or less.

[0039] Furthermore, the conditions of the heat treatment after depositing the metal film 21 before alloying can also be an important parameter. For example, if the heat treatment is performed at a high temperature for a long time, the aggregation of the inert gas accelerates, causing the micro-domains 31 to become larger, which increases the width and depth of the micro-domains 31 and makes it impossible to obtain the desired shape. The heat treatment conditions are preferably a temperature in the range of 700°C to 900°C and a time in the range of 10 to 120 seconds.

[0040] By adjusting the above parameters, the parameters of the minute region 31 can be controlled.

[0041] The metal film 21 before alloying may be deposited using a CVD method. However, unlike when a sputtering method is used, an inert gas is not introduced during the deposition of the metal film 21. Therefore, after the deposition of the metal film 21, it is necessary to introduce the inert gas, for example, by an ion implantation method. Even if an inert gas is introduced after the deposition of the metal film 21, the inert gas will aggregate if a heat treatment is performed, and the microdomains 31 will be formed.

[0042] 4 is a specific example of a contact portion of a semiconductor device according to the first embodiment, and schematically illustrates a cross section of an emitter (or source) contact of a semiconductor device for power conversion. An interlayer insulating film 50 is formed on a semiconductor substrate 10. A contact hole reaching the semiconductor substrate 10 is formed in the interlayer insulating film 50, and an alloy layer 20 is formed in the surface layer of the semiconductor substrate 10 exposed at the bottom of the contact hole. An upper metal layer 30 is formed on the alloy layer 20, and a minute region 31 is formed at the interface between the alloy layer 20 and the upper metal layer 30. Furthermore, an upper metal layer 40 is formed on the upper metal layer 30 as a contact plug filling the contact hole.

[0043] The semiconductor substrate 10 is, for example, a compound containing Si, SiC, or Ga. The alloy layer 20 is, for example, a silicide compound or an alloy mainly containing the elements of the semiconductor substrate 10. The interlayer insulating film 50 is, for example, a TEOS film, a BPSG film, a thermal oxide film, or a laminated film thereof, and is provided to ensure insulation from the gate electrode (not shown).

[0044] The bottom width of the contact hole formed in the interlayer insulating film 50 (contact bottom width shown in FIG. 4) is on the submicron order of, for example, 0.2 μm or more and 1.0 μm or less, and the aspect ratio with respect to the thickness of the interlayer insulating film 50 (i.e., thickness of the interlayer insulating film / bottom width of the contact hole) is, for example, 1.5 or more. Although not shown, an n-type or p-type emitter layer is selectively formed in the surface layer portion of the semiconductor substrate 10 at the bottom of the contact hole, and the alloy layer 20 is in contact with the emitter layer.

[0045] FIG. 5 is an atomic number contrast image obtained by cross-sectional TEM of the contact portion of the semiconductor device according to embodiment 1 having the structure of FIG. 4. In the atomic number contrast image, the lower the atomic density, the darker the black color. Therefore, the minute regions 31 are shown as localized dark black regions. From FIG. 5, it can be seen that the minute regions 31 are formed discretely. As a comparative example, FIG. 6 shows an atomic number contrast image of a conventional contact portion without minute regions.

[0046] Figure 7 is an enlarged view of the vicinity of the minute region 31 in the atomic number contrast image of Figure 5, with dimensions indicated. By adjusting the inert gas elements contained in the metal film 21 before alloying and the heat treatment conditions, we have succeeded in forming a minute region 31 with a reduced atomic concentration, 35 nm wide and 10 nm deep. Note that the dimensions of the upper metal layer 30 shown in Figure 7 are merely an example.

[0047] 8 and 9 show elemental map images of the contact portion of the semiconductor device according to the first embodiment having the structure of FIG. 4. FIG. 8 is an elemental map image of Si, and FIG. 9 is an elemental map image of Ar. Si is not included in the constituent elements of the upper metal layer 30, but Si is included in the constituent elements of the alloy layer 20 and the semiconductor substrate 10. Therefore, in the elemental map image of Si shown in FIG. 8, the upper metal layer 30 is depicted with a dark contrast. At the boundary between the alloy layer 20 and the upper metal layer 30 (the area surrounded by the white dashed line), a minute region 31 with a reduced Si atomic concentration is depicted with a localized dark contrast. Note that a bright contrast appears in the portion of the upper metal layer 40 that does not contain Si, but the EDX spectrum confirms that this is due to background noise.

[0048] On the other hand, in the element map image of Ar shown in Fig. 9, a minute region 31 where the atomic concentration of Ar is increased is depicted with locally bright contrast at the boundary portion (the region surrounded by the white dashed line) between the alloy layer 20 and the upper metal layer 30. Note that, also in Fig. 9, it has been confirmed that the bright contrast in the upper metal layer 40 portion is background noise.

[0049] Figure 10 shows EDX spectra, which are the original data for the element map images in Figures 8 and 9. The dashed line is the spectrum of the alloy layer 20 in the portion not including the minute region 31, and the solid line is the spectrum of the alloy layer 20 in the portion including the minute region 31. In the portion including the minute region 31, the peak intensity of Si, which is a constituent element of the alloy layer 20, is reduced by about 3.1% compared to the portion not including the minute region 31. Furthermore, Ar, an inert gas element, is significantly detected in the portion including the minute region 31.

[0050] 8, 9 and 10, it can be seen that the minute region 31 is a region where the concentration of the constituent elements of the alloy layer 20 is low and the atomic concentration of the inert gas is high.

[0051] <Embodiment 2> In the second embodiment, the minute region 31 described in the first embodiment is applied to an electrode formed on an interlayer insulating film 50.

[0052] 11 is a diagram showing the basic structure of a contact portion of a semiconductor device according to embodiment 2. The "contact portion" in this embodiment refers to a portion where a lower metal layer 41 formed on an interlayer insulating film 50 is connected to an upper metal layer 42 thereon, as shown in FIG. 11. The interlayer insulating film 50 is, for example, an oxide film.

[0053] In the contact portion of the semiconductor device according to the second embodiment, minute regions 31 are formed at the interface between the lower metal layer 41 and the upper metal layer 42. The minute regions 31 have a shape that erodes the lower metal layer 41, that is, a shape that penetrates into the lower metal layer 41 from the interface between the lower metal layer 41 and the upper metal layer 42. It is desirable that 90% or more of the multiple minute regions 31 have an arc shape with the widest opening in a cross-sectional view.

[0054] Furthermore, in cross-sectional view, the minute region 31 has an arc-shaped opening that is widest. The width, depth, density, shape, position, etc. of the minute region 31 are the same as those in the first embodiment. However, the lower metal layer 41 in which the minute region 31 is formed is formed on the interlayer insulating film 50 and is not alloyed with the semiconductor substrate 10. Therefore, the lower metal layer 41 does not contain the constituent elements of the semiconductor substrate 10, and the minute region 31 does not contain the constituent elements of the semiconductor substrate 10 either. The atomic concentration of the constituent elements of the lower metal layer 41 in the minute region 31 is preferably 80.0 wt% or more.

[0055] The minute region 31 can be formed by subjecting the lower metal layer 41 containing an inert gas to a heat treatment. The method for forming the minute region 31 is the same as the method for forming the contact portion shown in the first embodiment (FIGS. 2 and 3), and therefore a description thereof will be omitted here. The width, depth, density, shape, position, etc. of the minute region 31 can be controlled by adjusting the inert gas element contained in the lower metal layer 41 and the conditions for the heat treatment.

[0056] In the second embodiment, it is possible to reduce the adhesive strength between lower metal layer 41 and upper metal layer 42 formed on interlayer insulating film 50 while preventing deterioration of the contact resistance therebetween. Even if peeling occurs at the electrode on interlayer insulating film 50 during a stress test, since the adhesive strength is adjusted to an appropriate level, it is possible to prevent the breakdown from spreading into semiconductor substrate 10 without impairing the lifespan during the stress test.

[0057] It should be noted that the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0058] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0059] (Appendix 1) a semiconductor substrate; an alloy layer containing the constituent elements of the semiconductor substrate as a main component; an upper metal layer formed on the alloy layer; Equipped with a plurality of micro-regions containing an inert gas are discretely arranged at the interface between the alloy layer and the upper metal layer; 90% or more of the plurality of minute regions have an arc shape with the widest opening. Semiconductor device.

[0060] (Appendix 2) The atomic concentration of the constituent elements of the alloy layer in the micro-region is 80 wt% or more. 2. The semiconductor device according to claim 1.

[0061] (Appendix 3) The thickness of the alloy layer is 30 nm or more, The width of the microdomain is less than 100 nm, The depth of the minute region is less than the thickness of the alloy layer. 10. The semiconductor device according to claim 1 or 2.

[0062] (Appendix 4) the occupancy rate of the micro-domains at the interface between the alloy layer and the upper metal layer is less than 50%; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0063] (Appendix 5) an interlayer insulating film formed on the semiconductor substrate; a contact hole formed in the interlayer insulating film and reaching the semiconductor substrate; Furthermore, the alloy layer and the upper metal layer are formed on the semiconductor substrate at the bottom of the contact hole; The bottom width of the contact hole is, for example, 0.2 μm or more and 1.0 μm or less. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0064] (Appendix 6) an aspect ratio of the bottom width of the contact hole to the thickness of the interlayer insulating film is 1.5 or more; 6. The semiconductor device according to claim 5.

[0065] (Appendix 7) The atomic concentration of the inert gas in the micro-region is 0.5 wt% or more and less than 20.0 wt%. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0066] (Appendix 8) The inert gas is Ar or N2; 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0067] (Appendix 9) The semiconductor substrate is made of Si, SiC, or a compound containing Ga. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0068] (Appendix 10) the semiconductor substrate is made of Si or SiC, the alloy layer is a silicide compound containing Ti or Ni; 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0069] (Appendix 11) The upper metal layer is made of a metal containing Ti, W, or Al as a main component, or a laminated structure of multiple metals containing Ti, W, or Al as a main component. 11. The semiconductor device according to claim 1.

[0070] (Appendix 12) a bottom metal layer; an upper metal layer formed on the lower metal layer; Equipped with a plurality of minute regions containing an inert gas are discretely arranged at an interface between the lower metal layer and the upper metal layer; 90% or more of the plurality of minute regions have an arc shape with the widest opening. Semiconductor device.

[0071] (Appendix 13) the atomic concentration of the constituent elements of the lower metal layer in the micro-region is 80 wt% or more; 13. The semiconductor device according to claim 12. [Explanation of symbols]

[0072] 10 semiconductor substrate, 20 alloy layer, 21 metal film, 30 upper metal layer, 31 microregion, 40 upper metal layer, 41 lower metal layer, 42 upper metal layer, 50 interlayer insulating film.

Claims

1. a semiconductor substrate; an alloy layer containing the constituent elements of the semiconductor substrate as a main component; an upper metal layer formed on the alloy layer; Equipped with a plurality of micro-regions containing an inert gas are discretely arranged at the interface between the alloy layer and the upper metal layer; 90% or more of the plurality of minute regions have an arc shape with the widest opening. Semiconductor device.

2. the atomic concentration of the constituent elements of the alloy layer in the micro-region is 80 wt % or more; The semiconductor device according to claim 1 .

3. The thickness of the alloy layer is 30 nm or more, The width of the microdomain is less than 100 nm, The depth of the minute region is less than the thickness of the alloy layer.

3. The semiconductor device according to claim 1.

4. the occupancy rate of the micro-domains at the interface between the alloy layer and the upper metal layer is less than 50%; 3. The semiconductor device according to claim 1.

5. an interlayer insulating film formed on the semiconductor substrate; a contact hole formed in the interlayer insulating film and reaching the semiconductor substrate; Furthermore, the alloy layer and the upper metal layer are formed on the semiconductor substrate at the bottom of the contact hole; The bottom width of the contact hole is, for example, 0.2 μm or more and 1.0 μm or less.

3. The semiconductor device according to claim 1.

6. an aspect ratio of the bottom width of the contact hole to the thickness of the interlayer insulating film is 1.5 or more; The semiconductor device according to claim 5 .

7. The atomic concentration of the inert gas in the micro-region is 0.5 wt % or more and less than 20.0 wt %.

3. The semiconductor device according to claim 1.

8. The inert gas is Ar or N ２ That is, 3. The semiconductor device according to claim 1.

9. The semiconductor substrate is made of Si, SiC, or a compound containing Ga.

3. The semiconductor device according to claim 1.

10. the semiconductor substrate is made of Si or SiC, the alloy layer is a silicide compound containing Ti or Ni; 3. The semiconductor device according to claim 1.

11. the upper metal layer is made of a metal containing Ti, W, or Al as a main component, or a laminated structure of multiple metals containing Ti, W, or Al as a main component; 3. The semiconductor device according to claim 1.

12. a bottom metal layer; an upper metal layer formed on the lower metal layer; Equipped with a plurality of minute regions containing an inert gas are discretely arranged at an interface between the lower metal layer and the upper metal layer; 90% or more of the plurality of minute regions have an arc shape with the widest opening. Semiconductor device.

13. the atomic concentration of the constituent elements of the lower metal layer in the micro-region is 80 wt % or more; The semiconductor device according to claim 12.

Images