Semiconductor device

Abstract

To apply an excellent electric characteristic to a semiconductor device.SOLUTION: In an oxide semiconductor film, a plurality of electronic diffraction patterns is observed by irradiating an electronic beam while relatively moving a position of a film and a position of the electronic beam to a formed surface of the oxide semiconductor film by using the electronic beam of which a half value width of a probe diameter is 1nm, and the plurality of electronic diffraction patterns includes fifty or more electronic diffraction patterns observed at a different place each other. A sum of a rate having a first electronic diffraction pattern and a rate having a second electronic diffraction pattern of fifty or more electronic diffraction patterns is 100%, and the rate having the first electronic diffraction pattern is 50% or more. The first electronic diffraction pattern includes an observation point without a symmetric property and a plurality of observation points arranged so as to draw a circle. The second electronic diffraction pattern includes an observation point positioned at a top of a hexagon.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The invention relates to the manufacture or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method for the above-mentioned liquid crystal display device or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "device" refers to a device in general. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. devices, storage devices, imaging devices, electro-optical devices, power generation devices (thin-film solar cells, organic thin-film solar cells) and the like), and electronic devices may include semiconductor devices. [Background technology]

[0003] The properties of oxides containing indium and zinc are interesting and have been extensively studied ( Non-patent literature 1, Non-patent literature 2). In Non-patent literature 1, 1-x Ga 1+x O3(ZnO ) m (x is a number satisfying -1≦x≦1, m is a natural number) It has also been reported that the solid solution region of the homologous phase For example, powders of In2O3, Ga2O3, and ZnO have been described. When the powders are mixed and fired at 1350°C, the solid solution region of the homologous phase when m=1 is x The solid solution region of the homologous phase when m=2 is The values ​​range from -0.68 to 0.32.

[0004] In addition, compounds with a spinel-type crystal structure include AB2O4 (A and B are metals). In addition, Non-Patent Document 1 discloses a compound represented by In x Zn y Ga z O w Examples of x, y, and z are the composition of ZnGa2O4, that is, x, y, and z are the composition of (x, y When the value of z is close to (0, 1, 2), a spinel-type crystal structure is formed. It is stated that these substances are easily mixed together.

[0005] Furthermore, technology for constructing transistors using semiconductor materials is attracting attention. A monitor is an electronic device such as an integrated circuit (IC) or an image display device (also simply written as a display device). Silicon-based semiconductors are widely used in devices. While semiconductor materials are widely known, oxide semiconductors are also attracting attention.

[0006] For example, zinc oxide or In-Ga-Zn oxide semiconductor is used as the oxide semiconductor. Techniques for fabricating transistors using this method have been disclosed (see Patent Documents 1 and 2).

[0007] In recent years, with the increasing performance, miniaturization, and weight reduction of electronic devices, Demand is increasing for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0009] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, pp.298-315 [Non-patent document 2] M. Nespolo, A. Sato, T. Osawa, and H. Ohashi, “Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.

[0011] Another object is to provide a highly reliable semiconductor device.

[0012] Another object is to provide a good transistor with little variation in characteristics. Another object is to provide a semiconductor device having a memory element with good retention characteristics. Another object is to provide a semiconductor device suitable for miniaturization. It is an object of the present invention to provide a semiconductor device having a reduced area. One of the objectives is to provide a body device.

[0013] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0014] One embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc. The element M is at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M, and zinc is indium:element M :zinc = x:y:z, where x, y, and z are the three elements indium, element M, and zinc. In the equilibrium diagram with vertices at , the first coordinate (x:y:z=8:14:7) and the second Coordinates (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), and the fourth Coordinates (x:y:z=51:149:300) and the fifth coordinate (x:y:z=46:288 :833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y:z= 0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate, The ratio of the number of atoms in the range connected by a line segment to the first coordinate to the sixth coordinate is The electron beam does not include the seventh and eighth coordinates, and the half width of the probe diameter is 1 nm. The position of the oxide semiconductor film and the position of the electron beam are compared with respect to the surface on which the oxide semiconductor film is to be formed. By irradiating the electron beam while moving the sample relative to the sample, multiple electron diffraction patterns were observed. In some cases, multiple electron diffraction patterns are obtained from 50 or more different locations. The electron diffraction pattern is a first electron diffraction pattern among 50 or more electron diffraction patterns. The sum of the proportion of the sample having the first electron diffraction pattern and the proportion of the sample having the second electron diffraction pattern is 100%. The electron diffraction pattern of the electron microscope is obtained by observing points that have no symmetry, or by observing points arranged in a circle. The second electron diffraction pattern has observation points at the vertices of a hexagon. It is a nitride semiconductor film.

[0015] Alternatively, one aspect of the present invention is to perform oxidation using an electron beam with a probe diameter of 1 nm. The position of the oxide semiconductor film and the position of the electron beam are moved relative to the surface on which the oxide semiconductor film is to be formed. By irradiating the sample with an electron beam while rotating the sample, multiple electron diffraction patterns were observed. The multiple electron diffraction patterns are composed of more than 50 electron diffraction patterns observed at different locations. It has a turn and has the first electron diffraction pattern among 50 or more electron diffraction patterns. The sum of the percentage having the second electron diffraction pattern and the percentage having the first electron diffraction pattern is 100%. The proportion of the electron diffraction patterns having a pattern is 50% or more, and the first electron diffraction pattern has no symmetry. a single observation point or a plurality of observation points arranged in a circle, and a second electron diffraction pattern The film is an oxide semiconductor film having observation points located at the vertices of a hexagon.

[0016] Alternatively, one embodiment of the present invention is In:M(Al, Ga, Y, or Sn):Zn=x:y The oxide semiconductor film is expressed by the atomic ratio of x:y:z, and the coordinates are x:y:z=1:0:0 and z=1:0:0. Equilibrium diagram with vertices at coordinates x:y:z=0:1:0 and x:y:z=0:0:1 In this example, the first coordinates (x:y:z=8:14:7) and the second coordinates (x:y:z=2: 4:3), the third coordinate (x:y:z=2:5:7), and the fourth coordinate (x:y:z=51 :149:300), the fifth coordinate (x:y:z=46:288:833), and the sixth coordinate The 7th coordinate (x:y:z=0:0:1) and the 8th coordinate (x:y:z=0:2:11) Within the range connecting the coordinates (x:y:z=1:0:0) and the first coordinates in order with a line segment The position of the oxide semiconductor film and the half width of the probe diameter are By moving the electron beam position, which is 1 nm apart, relatively, more than 50 particles were detected at different locations. Observing the above electron diffraction patterns, more than 50 electron diffraction patterns were found to be at least asymmetric. Electron diffraction patterns having a plurality of spots arranged in a circular pattern and a plurality of spots arranged in a circular pattern. and an electron diffraction pattern with spots arranged at the vertices of a hexagon. and a diffraction pattern, the range including the first coordinate to the sixth coordinate, and the seventh coordinate The oxide semiconductor film does not include the coordinates A and B.

[0017] In the above structure, the oxide semiconductor film contains indium, an element M, and zinc. , element M is at least one of aluminum, gallium, yttrium, and tin; The ratio of the number of atoms of indium, element M, and zinc is indium:element M :zinc = x:y:z, where x, y, and z are the three elements indium, element M, and zinc. In the equilibrium diagram with vertices at , the first coordinate (x:y:z=8:14:7) and the second Coordinates (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), and the fourth Coordinates (x:y:z=51:149:300) and the fifth coordinate (x:y:z=46:288 :833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y:z= 0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate, in that order. The ratio of the number of atoms in the range connected by the line segment is set to the first coordinate to the sixth coordinate, It is preferred that the seventh and eighth coordinates are not included.

[0018] Another embodiment of the present invention is an oxide semiconductor including indium, an element M, and zinc. The oxide semiconductor film has a plurality of crystal parts arranged randomly, and the plurality of crystal parts The oxide semiconductor film has an average longitudinal diameter of 1 nm to 3 nm.

[0019] Another embodiment of the present invention is an oxide semiconductor including indium, an element M, and zinc. The film, wherein the element M is at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M and zinc is In: element M: zinc = x:y:z, where x, y, and z are the ratios of indium, element M, and zinc. In an equilibrium diagram with three elements at the vertices, the first coordinate (x:y:z=8:14:7) and the second coordinates (x:y:z=2:4:3) and the third coordinates (x:y:z=2:5:7) and the fourth coordinate (x:y:z=51:149:300) and the fifth coordinate (x:y:z=4 6:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x :y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate The ratio of the number of atoms in the range connected by a line segment in order is and the seventh coordinate and the eighth coordinate are not included, and the density of the oxide semiconductor film is The oxide semiconductor film has a single crystal density of 90% or more.

[0020] Another embodiment of the present invention is an oxide semiconductor including indium, an element M, and zinc. The film, wherein the element M is at least one of aluminum, gallium, yttrium, and tin. The oxide semiconductor film has a plurality of crystal parts arranged randomly. The plurality of crystal portions do not have orientation, and the diameter of the plurality of crystal portions in the longitudinal direction is 1 nm or more to 3 nm. The density of the oxide semiconductor film is 9 times that of a single crystal having the same atomic ratio. 0% or more.

[0021] Alternatively, one embodiment of the present invention is an oxide semiconductor containing indium, gallium, and zinc. The oxide semiconductor film has a plurality of crystal parts, and the crystal parts have no orientation. First, the average longitudinal diameter of the plurality of crystal portions is 1 nm or more and 3 nm or less, and the oxide semiconductor The density of the film is 5.7 g / cm 3 More than 6.49g / cm 3 The oxide semiconductor film is as follows: In the above structure, the density of the oxide semiconductor film is the same as that of a single crystal having the same atomic ratio. It is preferable that the ratio is 90% or more.

[0022] Alternatively, one embodiment of the present invention is an oxide semiconductor containing indium, gallium, and zinc. The oxide semiconductor film has a plurality of crystal parts arranged randomly, and the plurality of crystal parts The crystal parts do not have orientation, and the average diameter A [nm] of the longitudinal direction of the multiple crystal parts is 1 nm or more and 3 nm or less. nm or less, and the electron beam energy is 1×10 7 [e - / nm2 ] or more 4 x 10 8 [ e - / nm 2 After irradiation for less than 1000 times, the average diameter B [nm] of the crystal part in the longitudinal direction is A × The oxide semiconductor film has a value larger than 0.7 and smaller than A×1.3.

[0023] In the above structure, the oxide semiconductor film is formed by a sputtering method. The target used in the targeting method contains indium, element M, and zinc. The atomic ratio of indium, element M, and zinc contained in the sintered body is indium:element M:zinc= a:b:c is satisfied, and a, b, and c are composed of three elements: indium, element M, and zinc. In the equilibrium diagram, the first coordinate (a:b:c=8:14:7) and the second coordinate (a:b:c=2:4:3), the third coordinate (a:b:c=1:2:5.1), and the fourth Coordinates (a:b:c=1:0:1.7), the fifth coordinate (a:b:c=8:0:1), and the The coordinates of the six points (a:b:c=6:2:1) and the first coordinate are connected in order by line segments. Preferably, the ratio of the number of atoms is within a range, and the range includes the first coordinate to the sixth coordinate.

[0024] Another embodiment of the present invention is a semiconductor device including any of the above oxide semiconductor films. In the above structure, the first conductive layer and the first insulating layer contacting the upper surface and side surfaces of the first conductive layer are provided. a first insulating film and a pair of electrodes in contact with the top surface of the oxide semiconductor film; In the above structure, it is preferable that the first conductive layer has a region in contact with the upper surface of the insulating film. a first insulating film in contact with the top surface and side surfaces of the first conductive layer; and a second insulating film in contact with the top surface of the oxide semiconductor film. and a second insulating film in contact with the top surface of the oxide semiconductor film and the top and side surfaces of the second insulating film. a pair of electrodes, and the oxide semiconductor film has a region in contact with an upper surface of the first insulating film; In the above structure, it is preferable that a second oxide film be in contact with the top surface of the oxide semiconductor film. In the above structure, it is preferable that the electron affinity of the oxide of the oxide semiconductor film is The electron affinity of the oxide film is preferably greater than the electron affinity of the oxide film of the second oxide film. In the above structure, the second oxide film contains indium, the element M, and zinc, and the element M is selected from at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M, and zinc contained in the second oxide film is It is expressed as x2:y2:z2, where (x2:y2:z2) is the indium:element M:zinc ratio. In the equilibrium diagram with the three elements of Zn, element M and zinc as vertices, the first coordinate (8:1 4:7), the second coordinate (2:4:3), the third coordinate (2:5:7), and the fourth coordinate ( 51:149:300), the fifth coordinate (1:4:10), and the sixth coordinate (1:1:4) The seventh coordinate (2:2:1) and the first coordinate are connected by a line segment in order. It is preferable that the range includes the first coordinate to the seventh coordinate, and the ratio of the number of atoms is the same.

[0025] Another embodiment of the present invention is a display device including the above semiconductor device and a display element. It is a location.

[0026] Another embodiment of the present invention is the semiconductor device or the display device described above. and an FPC.

[0027] Another embodiment of the present invention is any one of the above semiconductor devices, the above display devices, and The above-described module and a microphone, a speaker, or an operation key are included. It is an electronic device. [Effects of the Invention]

[0028] According to one embodiment of the present invention, a semiconductor device can have good electrical characteristics. A highly reliable semiconductor device can be provided.

[0029] Furthermore, it is possible to provide a transistor with little variation. In addition, it is possible to provide a semiconductor device having a memory element suitable for miniaturization. It is also possible to provide a semiconductor device with a reduced circuit area. Furthermore, it is possible to provide a semiconductor device with a novel configuration. However, this does not necessarily preclude the existence of other effects. It is not necessary for the invention to have all of the above effects. Effects other than these may be included in the specification, drawings, claims, etc. It becomes clear from the description, drawings, claims, etc. It is possible to extract other effects besides these. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 10 illustrates the atomic ratio of an oxide film according to one embodiment of the present invention. [Figure 2] FIG. 10 illustrates the atomic ratio of an oxide film according to one embodiment of the present invention. [Figure 3] FIG. [Figure 4] FIG. 10 illustrates the atomic ratio of an oxide film according to one embodiment of the present invention. [Figure 5] FIG. 10 is a graph illustrating the atomic ratio of a target according to one embodiment of the present invention. [Figure 6] FIG. [Figure 7] 1A and 1B are diagrams showing nanobeam electron diffraction patterns of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; [Figure 8] Figure showing the analysis results of nc-OS using an X-ray diffraction device. [Figure 9] Electron diffraction pattern of nc-OS. [Figure 10] A diagram explaining the InGaZnO4 crystal. [Figure 11] FIG. 10 is a diagram showing a band structure of a part of a transistor according to one embodiment of the present invention. [Figure 12] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 13] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 14] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 15] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 16] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 17] Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS. [Figure 18] Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. [Figure 19] Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. [Figure 20] Cs-corrected high-resolution cross-sectional TEM image of nc-OS. [Figure 21] Cs-corrected high-resolution cross-sectional TEM image of nc-OS. [Figure 22] Figure 1 shows the pellet sizes and their frequencies observed in Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS. [Figure 23] 10A and 10B are graphs showing the relationship between the atomic ratio of a target and the atomic ratio of an oxide semiconductor film. [Figure 24] Schematic diagram explaining the film formation model of nc-OS and a diagram showing the pellet. [Figure 25]FIG. 1 is a schematic diagram illustrating a film forming apparatus. [Figure 26] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 27] 1 is a diagram of a display module according to an embodiment. [Figure 28] 1 shows an example of the configuration of an RF tag according to an embodiment. [Figure 29] 1A and 1B illustrate examples of transistors. [Figure 30] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 31] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 32] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 33] 1A and 1B illustrate examples of transistors according to one embodiment of the present invention. [Figure 34] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 35] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 36] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 37] FIG. 1 is a circuit diagram according to an embodiment. [Figure 38] 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention. [Figure 39] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 40] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 41] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 42] 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 43] 1 shows XRD evaluation results of an oxide semiconductor film according to one embodiment of the present invention. [Figure 44] Electron diffraction pattern of an oxide semiconductor film. [Figure 45] Electron diffraction pattern of an oxide semiconductor film. [Figure 46] Electron diffraction pattern of an oxide semiconductor film. [Figure 47] Electron diffraction pattern of an oxide semiconductor film. [Figure 48] Electron diffraction pattern of an oxide semiconductor film. [Figure 49] Electron diffraction pattern of an oxide semiconductor film. [Figure 50] Electron diffraction pattern of an oxide semiconductor film. [Figure 51] Electron diffraction pattern of an oxide semiconductor film. [Figure 52] Electron diffraction pattern of an oxide semiconductor film. [Figure 53] Electron diffraction pattern of an oxide semiconductor film. [Figure 54] TDS analysis results of oxide semiconductor film. [Figure 55] FIG. 1 shows changes in crystals due to electron beam irradiation. [Figure 56] 10 shows an example of how an RF tag is used according to an embodiment. [Figure 57] 1. An electronic device according to an embodiment. [Figure 58] 10A and 10B are graphs showing film densities of oxide semiconductor films; [Figure 59] 10A and 10B are graphs showing etching rates of oxide semiconductor films. [Figure 60] 10A and 10B are graphs showing the amounts of released gases from oxide semiconductor films. [Figure 61] 10A and 10B show hydrogen concentrations in oxide semiconductor films. [Figure 62] 10A and 10B are diagrams showing crystal sizes of oxide semiconductor films; [Figure 63] 10A and 10B are diagrams showing crystal sizes of oxide semiconductor films; [Figure 64] 10A and 10B show CPM measurement results of an oxide semiconductor film. [Figure 65] 10A and 10B show CPM measurement results of an oxide semiconductor film. [Figure 66] 10A and 10B show CPM measurement results of an oxide semiconductor film. [Figure 67] Cs-corrected high-resolution cross-sectional TEM image of a-like OS. [Figure 68] 10A and 10B show hydrogen concentrations in oxide semiconductor films. DETAILED DESCRIPTION OF THE INVENTION

[0031] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiments, and various changes and modifications may be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0032] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and repeated explanations thereof will be omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be assigned.

[0033] In each figure described in this specification, the size, layer thickness, or area of ​​each component is The figures may be exaggerated for clarity and are not necessarily limited to that scale. stomach.

[0034] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a numerical limitation.

[0035] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0036] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0037] A transistor is a type of semiconductor device that controls the amplification of current and voltage, and conduction or non-conduction. In this specification, the transistor can be , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT) ) is included.

[0038] (Embodiment 1) In this embodiment, an example of an oxide semiconductor film according to one embodiment of the present invention will be described.

[0039] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0040] Single crystals can be formed by firing at high temperatures, for example, above 1000°C. Therefore, from an industrial viewpoint, a non-single-crystal oxide semiconductor film that can be formed at a lower temperature is desired. The use of the above is preferable because it allows semiconductor devices to be manufactured more inexpensively.

[0041] The fewer grain boundaries in the oxide semiconductor film, the better. The carrier mobility can be increased. By fabricating a transistor with high field-effect mobility, for example, it is possible to realize As will be described in detail later, examples of non-single-crystal oxide semiconductor films with few grain boundaries include For example, an nc-OS film or a CAAC-OS film can be mentioned.

[0042] On the other hand, an oxide semiconductor film may have crystals with a spinel structure. The presence of crystals in the CAAC-OS and nc-OS films results in clear boundaries (or grain boundaries). ) may be formed. For example, carrier scattering increases at the boundary, and the carrier mobility In addition, the boundary area is likely to become a path for impurities to move and also to capture impurities. Since it is thought that the impurity concentration in the oxide semiconductor film is likely to increase, there is a concern that the impurity concentration in the oxide semiconductor film may increase. When a conductive film is formed over an oxide semiconductor film, an element contained in the conductive film, such as a metal, may have a spin Therefore, the oxide semiconductor film is It is more preferable that the material does not contain or contains only a small amount of a Spinel type crystal structure.

[0043] Here, the oxide semiconductor is, for example, an oxide semiconductor containing indium. When oxide contains indium, for example, carrier mobility (electron mobility) increases. The semiconductor preferably contains an element M. The element M is preferably aluminum, gallium, Yttrium or tin, etc. Other elements that can be used for element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum Lithium, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. However, there are cases where the element M may be a combination of multiple elements. The element M is, for example, an element that has a high bond energy with oxygen. The element M is an element having a higher energy than indium. Alternatively, the element M is, for example, an element of an oxide semiconductor. It is an element that has the function of widening the energy gap. In addition, oxide semiconductors contain zinc When the oxide semiconductor contains zinc, it may be easily crystallized. An oxide containing indium, element M, and zinc is represented as In-M-Zn oxide.

[0044] [Atomic ratio] The atomic ratio of the In-M-Zn oxide film, which is the oxide semiconductor film of one embodiment of the present invention, is In: The formula is M:Zn=x:y:z. The preferred ranges of x, y, and z are shown in Figs. 1 and 2. and explain.

[0045] Here, the ratio of the number of atoms of each element will be explained using FIG. 3. FIG. 3 shows the ratio of the number of atoms of each element in XYZ acid. In the oxide film, when the ratio of the number of atoms of elements X, Y, and Z is x:y:z, The atomic ratio of oxygen is not shown in FIG. Also, Figure 3 is sometimes called an equilibrium phase diagram. Figure 3(A) and Figure 3(B) show X, Y and An equilateral triangle with Z as its vertex and coordinates R (4:2:1) are shown below. represent the elements X, Y, and Z, respectively. The value of each term in the atomic ratio is The closer to the vertex, the higher the value, and the further away from the vertex, the lower the value. The value of each term is expressed as the length of the perpendicular line from the coordinate to the opposite side of the vertex of the triangle. For example, for element X, the coordinate of the perpendicular line 21 from the coordinate to the opposite side of vertex X, that is, side YZ, Therefore, the coordinate R shown in FIG. 3 is expressed as the atomic ratio of element X, element Y, and element Z. The ratio of the lengths of the perpendicular lines 21, 22 and 23, i.e. x:y:z=4:2:1. Also, the point where the line passing through the vertex X and the coordinate R intersects with the side YZ is γ. If the ratio of the length of the segment Yγ to the length of the segment γZ is Yγ:γZ, then Yγ:γZ = (atoms of element Z) number): (number of atoms of element Y).

[0046] Also, as shown in Figure 3(B), there are three points that pass through the coordinate R and are parallel to the three sides of the triangle. Draw a straight line. At this time, use the intersections of the three straight lines and the three sides to determine x, y, and z as shown in Figure 3(B). It can be expressed as shown.

[0047] Figure 6 shows the In-M-Zn oxide film when x:y:z satisfies the following formula: The range is indicated by a dashed line.

[0048] x:y:z=(1-α):(1+α):m(-1≦α≦1)

[0049] Here, FIG. 6 shows the cases where m=1, 2, 3, 4, and 5.

[0050] As described in Non-Patent Document 1, in In-M-Zn oxide, InMO3(Zn O) m (m is a natural number) It is known that the element M is Ga. The region is made by mixing powders of In2O3, Ga2O3, and ZnO and heating them at 1350°C. It is known that when fired, it can form a single-phase solid solution region. It is known that the width increases as the value of m increases, i.e., as the ratio of zinc increases. do.

[0051] The coordinates indicated by square symbols in FIG. 6 are, for example, For example, when powders of In2O3, Ga2O3, and ZnO are mixed and fired at 1350°C, This is a composition known to be prone to the coexistence of spinel-type crystal structures. The composition near ZnGa2O4, that is, x, y, and z are (x, y, z) = (0, 2, 1). When the values ​​are close to each other, it is very likely that a spinel-type crystal structure will be formed or that a mixture will be formed. It is described in Patent Document 1.

[0052] The In-M-Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, has a ratio of indium In the In-M-Zn oxide film, the s orbital of the metal atom is mainly carried By increasing the indium content, more s orbitals are Since the indium content is high, the carrier mobility is higher. By using the film in the channel region to fabricate a transistor, for example, high field effect mobility can be achieved. For example, x / y>0.5 is preferable, x / y≧0.75 is more preferable, and x / y≧1 is even more preferable. is preferred.

[0053] Therefore, it is preferable that x, y, and z have the ratio of the number of atoms in the region 11 shown in FIG. It is more preferable that the atomic ratio of the region 12 is as shown in FIG. 2(A). The first coordinate K (x:y:z=8:14:7) and the second coordinate R (x:y:z=2:4:3 ), the third coordinate L (x:y:z=2:5:7), and the fourth coordinate M (x:y:z=51: 149:300), the fifth coordinate N(x:y:z=46:288:833), and the sixth coordinate The seventh coordinate P(x:y:z=0:0:1) and the seventh coordinate O(x:y:z=0:2:11) The coordinate Q (x:y:z=1:0:0) of the eighth point and the first coordinate K are connected by a line segment in order. It is within the area 11. The area 11 includes the line segment connecting the eight points. Except for the coordinate P and the coordinate Q, the other coordinates are included in the area 11. The area 12 includes the first coordinate K. (x:y:z=8:14:7), the second coordinate R(x:y:z=2:4:3), and the third The coordinates L (x:y:z=2:5:7), the fourth coordinate S (x:y:z=1:0:1), and the The coordinates Q (x:y:z=1:0:0) of the fifth point and the first coordinate K are connected by line segments in order. It is within the area. Note that area 12 includes the line segment connecting the five points. Also, from area 12 Except for coordinate Q, the other coordinates are included in region 12.

[0054] [Structure of oxide semiconductor film] Next, the structure of the oxide semiconductor film will be described.

[0055] First, the CAAC-OS film will be described.

[0056] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0057] Transmission Electron Microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of the CAAC-OS film was obtained using a microscope. (also called high-resolution TEM images) On the other hand, high-resolution TEM images also clearly show the boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur.

[0058] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. The CAAC-OS film is formed on a surface (also called a surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the upper surface thereof.

[0059] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction almost perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0060] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, a thickness of 1 nm or more is observed on the surface on which the CAAC-OS film is to be formed or on the upper surface. When electron diffraction is performed using an electron beam of 30 nm or less (also called nanobeam electron diffraction), A pot is observed (see Figure 7(B)).

[0061] The high-resolution TEM images of the cross section and the plane reveal the crystal structure of the CAAC-OS film. It can be seen that the part has orientation.

[0062] Most of the crystals in the CAAC-OS film are cubic crystals with sides of less than 100 nm. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This also includes cases where the size fits within a cube of less than 5 nm, or less than 3 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a high-resolution TEM image of a plane, a region at 2500 nm 2 Below Top, 5μm 2 or more than 1000μm 2 Crystal regions with more than this size may be observed.

[0063] X-ray diffraction (XRD) of the CAAC-OS film When structural analysis is performed using this device, for example, CAAC-OS with InGaZnO4 crystals can be seen. In the out-of-plane analysis of the film, the diffraction angle (2θ) peaks around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0064] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction almost perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0065] From the above, it can be concluded that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, it can be seen that the orientation of the crystals is in the same direction as that confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in a layered fashion is parallel to the ab plane of the crystal.

[0066] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization treatment such as a heat treatment. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is to be formed. Therefore, for example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0067] Furthermore, the distribution of c-axis oriented crystals in the CAAC-OS film does not need to be uniform. For example, the crystalline part of the CAAC-OS film is grown from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has a crystal orientation that is more c-axis oriented than the region near the surface on which the crystal is formed. In addition, the CAAC-OS film containing impurities may have a high percentage of impurities. The region where the ZnO was added was transformed, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0068] In addition, the out-of-plane structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have crystalline structure. It is preferable that the peak is exhibited at 2θ of about 36° and that the peak is not exhibited at 2θ of about 36°.

[0069] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is made of an element other than the main component, such as silicon or a transition metal element. The elements such as ZnO, which have stronger bonding strength with oxygen than the metal elements constituting the oxide semiconductor film, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Because the diameter (or molecular radius) is large, when the molecule is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement of the oxide semiconductor film, which may result in a decrease in crystallinity. The pure material may act as a carrier trap or a carrier generation source.

[0070] For example, oxygen vacancies in the oxide semiconductor film can become carrier traps or trap hydrogen. The CAAC-OS film can trap defects and become a carrier generation source. Specifically, the oxide semiconductor film has a low level density of 8×10 11 / cm 3 Less than, preferably is 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1× 10 -9 / cm 3 An oxide semiconductor having a carrier density of 1000 or more can be obtained.

[0071] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. There is little gender variation.

[0072] Next, the polycrystalline oxide semiconductor film will be described.

[0073] In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in a high-resolution TEM image. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, 2 nm or more in size and 3 nm or less in size in a high-resolution TEM image. The particle size is 00 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the polycrystalline oxide semiconductor film, the grain boundaries can be confirmed in a high-resolution TEM image. There are cases where this happens.

[0074] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation between the plurality of crystal grains is In addition, when an XRD device is used for a polycrystalline oxide semiconductor film, When structural analysis is performed, for example, the out of polycrystalline oxide semiconductor film having InGaZnO4 crystals In the t-of-plane analysis, there is a peak at 2θ around 31° and a peak at 2θ around 36°. peak or other peaks may appear.

[0075] A polycrystalline oxide semiconductor film has high crystallinity and therefore may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, in a polycrystalline oxide semiconductor film, impurities may segregate at the grain boundaries. The grain boundaries of the polycrystalline oxide semiconductor film become defect states. Since the oxide semiconductor film may become a carrier trap or a carrier generation source, The electrical characteristics of such transistors may fluctuate significantly, resulting in low reliability. be.

[0076] Next, a microcrystalline oxide semiconductor film will be described.

[0077] The microcrystalline oxide semiconductor film has crystalline parts that can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal parts contained in the film are large, with sizes of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are microcrystals is called n c-OS(nanocrystalline oxide semiconductor ) film. In addition, the nc-OS film clearly shows the grain boundaries in high-resolution TEM images, for example. It may not be possible to confirm.

[0078] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. The peak around 31°, which indicates the crystallinity, is not detected (see Figure 8). Electron diffraction (selected area) using an electron beam with a probe diameter larger than the target area (e.g., 50 nm or more) When electron diffraction is performed, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films, the electron beam with a probe diameter close to or smaller than the size of the crystalline part is used. When nanobeam electron diffraction is performed using a diffractometer, spots are observed. However, when nanobeam electron diffraction is performed, a circular (ring-shaped) area of ​​high brightness is observed. In addition, nanobeam electron diffraction of the nc-OS film reveals a ring-shaped region. In some cases, multiple spots are observed within a region. For example, as shown in Figure 9(A), For nc-OS with a diameter of about 50 nm, the probe diameter was set to 30 nm, 20 nm, 10 nm, or When nanobeam electron diffraction is performed with a diameter of 1 nm, a bright circular (ring-shaped) pattern is observed. Furthermore, as the probe diameter is reduced, the ring-shaped region is split into multiple spots. It can be seen that it is formed from pits.

[0079] For more detailed structural analysis, the nc-OS film was sliced ​​to a thickness of several nanometers (approximately 5 nm). A transmission electron diffraction pattern was obtained using an electron beam with a probe diameter of 1 nm. A transmission electron diffraction pattern was obtained with spots indicating crystallinity as shown in Figure 9(B).

[0080] Furthermore, when nanobeam electron diffraction was performed on the nc-OS film, two ring-shaped regions were observed. It may be measured.

[0081] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film.

[0082] In addition, the nc-OS film does not exhibit regularity in the crystal orientation between different crystal parts. The nc-OS film has a higher defect density than the CAAC-OS film. The S film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high conductivity may have high electron mobility. The resulting transistor may have high field-effect mobility.

[0083] The nc-OS film can be formed at a lower temperature than the CAAC-OS film. In some cases, films can be formed even if they contain relatively large amounts of impurities. The formation of c-OS films may be easier than that of CAAC-OS films. A semiconductor device including a transistor using an OS film can be manufactured with high productivity in some cases. There is a match.

[0084] In addition, the nc-OS membrane may have a moderate oxygen permeability. In this case, for example, oxygen released from the film containing excess oxygen diffuses throughout the nc-OS film. Therefore, in the nc-OS film, oxygen vacancies may be easily reduced.

[0085] The low impurity concentration and low defect level density (low oxygen vacancies) are called high-purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) such that the threshold voltage is negative. It is also called "marine.") It is rare for it to become pure or substantially pure. An intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it is fixed. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may be the case.

[0086] Next, the amorphous oxide semiconductor film will be described.

[0087] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state like quartz.

[0088] In amorphous oxide semiconductor films, no crystalline parts can be identified in high-resolution TEM images. .

[0089] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of- In the analysis by the plane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on a semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on a semiconductor film, no spots are observed, and a halo pattern is observed. is observed.

[0090] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. In addition, the amorphous oxide semiconductor film has a high density of defect states.

[0091] An oxide semiconductor film with a high impurity concentration and a high density of defect states has carrier traps and The oxide semiconductor film is a common source of CO2.

[0092] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film may not be able to Therefore, it is difficult to obtain normally-on electrical characteristics from transistors that require normally-on electrical characteristics. The amorphous oxide semiconductor film may be preferably used as a photoresist. Therefore, when an amorphous oxide semiconductor film is used, the carrier traps may increase. The transistors using the CAAC-OS film and the nc-OS film have the following characteristics: The electrical characteristics vary greatly, resulting in a transistor with low reliability.

[0093] Next, a single crystal oxide semiconductor film will be described.

[0094] The single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. Furthermore, since the single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single-crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0095] Note that the oxide semiconductor film has a high density when it has few defects. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of a single-crystal oxide semiconductor film is higher than that of a CAAC-OS film. The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. The conductor film has a higher density than the microcrystalline oxide semiconductor film. The density is higher than that of an crystalline oxide semiconductor film.

[0096] Note that the oxide semiconductor film has a structure that exhibits physical properties intermediate between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be formed, particularly, by using an amorphous oxide. amorphous-like oxide semiconductor :a-like OS) membrane.

[0097] In the a-like OS film, voids are observed in high-resolution TEM images. In addition, crystals may not be clearly visible in high-resolution TEM images. The a-like OS film has regions where crystals are visible and regions where no crystals are visible. Crystallization occurs when a small amount of electrons is irradiated, similar to the amount observed with a TEM, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the amount of precipitation is so small that it can be observed by TEM. Almost no crystallization due to electron irradiation is observed.

[0098] The size of the crystalline parts of the a-like OS film and the nc-OS film was measured using a high-resolution This can be done using TEM images. For example, InGaZnO4 crystals have a layered structure. There are two Ga-Zn-O layers between the In-O layers. The device has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned along the c-axis. It has a layered structure. Therefore, the distance between adjacent layers is (009) The lattice spacing (also called the d value) is approximately the same as that of the Therefore, focusing on the lattice fringes in the high-resolution TEM image, In the area where the spacing is 0.28 nm or more and 0.30 nm or less, each lattice fringe is In It is considered to correspond to the ab plane of the GaZnO4 crystal. The maximum length in the crystal structure is the size of the crystalline part of the a-like OS film and the nc-OS film. The size of the crystal portion is selected to be 0.8 nm or larger.

[0099] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density is between 78.6% and 92.3% of the original density.

[0100] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0101] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline silicon film. The film may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film. .

[0102] [Nanobeam electron diffraction] Next, nanobeam electron diffraction will be described.

[0103] When an oxide semiconductor film has multiple structures, the structure can be resolved by using nanobeam electron diffraction. analysis may be possible.

[0104] FIG. 7C shows an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, and an optical system 611 below the electron gun chamber 610. 2, a sample chamber 614 under the sample chamber 614, an optical system 616 under the sample chamber 614, and an observation under the optical system 616. room 620, a camera 618 installed in the observation room 620, and a film room below the observation room 620. The transmission electron diffraction measurement device shown in FIG. 6 has a camera 618 inside an observation chamber 620. The film chamber 622 does not necessarily have to be provided.

[0105] FIG. 7(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. Inside the electron diffraction measurement device, electrons emitted from the electron gun installed in the electron gun chamber 610 The light is irradiated onto a substance 628 placed in a sample chamber 614 via an optical system 612. The electrons passing through the optical system 616 are projected onto a fluorescent screen 632 installed inside the observation chamber 620. On the fluorescent screen 632, a pattern appears according to the intensity of the incident electrons. Electron diffraction patterns can be measured.

[0106] The camera 618 is set facing the fluorescent screen 632 and captures the pattern that appears on the fluorescent screen 632. The center of the lens of the camera 618 and the center of the fluorescent screen 632 can be photographed. The angle between the line passing through the center and the upper surface of the fluorescent screen 632 is, for example, 15° or more and 80° or less. , 30° to 75° or 45° to 70°. The smaller the angle, the The transmission electron diffraction pattern taken by MERA 618 is highly distorted. If this angle is known, it is possible to correct distortions in the obtained transmission electron diffraction pattern. There are cases where the camera 618 may be installed in the film chamber 622. For example, The camera 618 is installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with little distortion is captured from the rear surface of the fluorescent screen 632. It is possible.

[0107] In the sample chamber 614, a holder for fixing a substance 628 as a sample is installed. The holder is constructed to be transparent to electrons passing through the material 628. For example, the holder may have a function to move the substance 628 in the X-axis, Y-axis, Z-axis, etc. The movement function can be, for example, 1 nm to 10 nm, 5 nm to 50 nm, or 10 nm or more. Ranges such as 100nm or less, 50nm to 500nm, and 100nm to 1μm. These ranges are optimal depending on the structure of the substance 628. Just set it as follows.

[0108] Next, the transmission electron diffraction pattern of the substance is measured using the above-mentioned transmission electron diffraction measurement device. This article explains how to do this.

[0109] For example, as shown in FIG. 7(D), the irradiation position of the electron 624, which is a nanobeam, in the material By changing (scanning) the In this case, if the substance 628 is a CAAC-OS film, the Alternatively, if the material 628 is an nc-OS film, the diffraction pattern shown in Figure 7(A) is The diffraction pattern shown, for example, a diffraction pattern having multiple bright spots arranged in a circle, Turns (ring-shaped diffraction patterns with bright spots) are observed. The diffraction pattern has bright spots that are not symmetrically arranged (have no symmetry).

[0110] As shown in Figure 7(B), the diffraction pattern of the CAAC-OS film shows that the vertices of the hexagons, for example, In the CAAC-OS film, the spot located at the center of the irradiated area can be confirmed by scanning the irradiation position. As a result, the orientation of the hexagons is not uniform, but appears to rotate slightly. , the angle of rotation has a certain range.

[0111] Alternatively, in the diffraction pattern of the CAAC-OS film, by scanning the irradiation position, It can be seen that the structure rotates little by little around the c-axis. This is because, for example, the a-axis and b-axis form It can also be said that the surface is rotating.

[0112] By the way, the material 628 is in the region where the same diffraction pattern as that of the CAAC-OS film is observed (hereafter, The region with the CAAC structure (shown below) and the nc-OS film show similar diffraction patterns. In this case, there may be a region where the nc structure is formed (hereinafter referred to as a region having an nc structure). The ratio of the area where the diffraction pattern of the CAAC-OS film is observed in the range is defined as the CAAC ratio ( Similarly, the diffraction pattern of the nc-OS film can be expressed as The proportion of the area where the line is observed can be expressed as the nc ratio (also called the nc rate).

[0113] The method for evaluating the CAAC ratio of the CAAC-OS film is described below. The diffraction patterns of the CAAC-OS films were obtained by selecting the measurement points. The ratio of the number of measurement points where the fold pattern is observed is calculated. Here, the number of measurement points is 50 or more. is preferable, and 100 points or more is more preferable.

[0114] As a method for randomly selecting measurement points, for example, the irradiation position is scanned linearly and the measurement points are selected at regular intervals. The diffraction pattern can be acquired at each time. This is preferable because it allows you to see the boundaries between the structured region and other regions. Similarly, the rate of conversion was calculated by randomly selecting measurement points and obtaining a transmission electron diffraction pattern. It is possible.

[0115] This measurement method makes it possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0116] In the oxide semiconductor film of one embodiment of the present invention, for example, the sum of the nc ratio and the CAAC ratio is 80%. It is preferable that the ratio is 90% or more and 100% or less, and it is preferable that the ratio is 95% or more. It is preferably 100% or less, more preferably 98% or more and 100% or less, and 9 It is more preferable that the ratio is between 9% and 100%. Increase the sum of the nc ratio and CAAC ratio. This makes it possible to realize, for example, an oxide semiconductor film with few clear grain boundaries. By reducing the number of grain boundaries, it is possible to increase the carrier mobility of the oxide semiconductor film, for example. Cut.

[0117] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0118] (Embodiment 2) In this embodiment, an example of an oxide semiconductor film according to one embodiment of the present invention will be described.

[0119] The nc-OS film can be formed at a relatively low deposition temperature compared to the CAAC-OS film. For example, it may be possible to form the nc-OS film without heating the substrate. A semiconductor device including a transistor using the above-mentioned method can be manufactured with high productivity in some cases. .

[0120] In addition, the nc-OS membrane has moderate oxygen permeability, which allows oxygen to easily diffuse throughout the membrane. Therefore, when an oxide semiconductor film with a low defect density is formed, oxygen vacancies can be reduced more easily. Therefore, the present invention provides a semiconductor device having a transistor using an nc-OS film. It may be possible to improve the characteristics and reliability. do.

[0121] Here, both the nc-OS film and the CAAC-OS film have layered atomic arrangements. Such layered atomic arrangement can be observed using, for example, a TEM. do.

[0122] Here, the spherical aberration correction (Spherical Aberration Correction) for the nc-OS film and CAAC film is Transmission electron microscopy (TEM) with the Aberration Corrector function Transmission Electron Microscopy The bright-field image and diffraction pattern obtained by TEM observation are also observed. The composite analysis image of the turn is called a high-resolution TEM image. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. The images were acquired using, for example, an atomic resolution analytical electron microscope JEM-ARM20 manufactured by JEOL Ltd. This can be done by using 0F etc.

[0123] For CAAC-OS and nc-OS, Cs-corrected high-resolution cross-sectional TEM images were obtained in more detail. The size and orientation of the crystals are investigated by analyzing the crystal structure. The crystal part is sometimes called a pellet. The size and orientation of the crystals can be seen in cross-sectional TEM images. For example, extract pellets in an area of ​​20 nm square or more and investigate their size and orientation. .

[0124] FIG. 17(A) is a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. , and Figure 17(B) is a Cs-corrected high-resolution cross-sectional TEM image of nc-OS. The image on the right shows the same area, with an auxiliary line indicating the pellet.

[0125] FIG. 18(A) is a cross-sectional TEM image of a CAAC-OS film formed by DC sputtering. Also, Figure 18(B) is a Cs-corrected high-resolution cross-sectional TEM image of a part of the sample enlarged. In Figure 18(B), the number of pellets was counted and their size and orientation were plotted on a frequency distribution. (See FIG. 22(A)). Here, the arrows shown in FIG. 18(A) indicate the direction perpendicular to the sample surface. The direction of the white line in Figure 18(B) indicates the direction of the pellet, and the length of the white line indicates the length of the pellet. Indicates the size of the let.

[0126] FIG. 19(A) is a cross-sectional TEM image of a CAAC-OS film formed by RF sputtering. Also, Figure 19(B) is a Cs-corrected high-resolution cross-sectional TEM image of a part of the sample enlarged. In Figure 19(B), the number of pellets was counted and their size and orientation were plotted on a frequency distribution. (See Figure 22(B)).

[0127] FIG. 20(A) is a cross-sectional TEM image of the nc-OS film formed by DC sputtering. Figure 20(B) is a Cs-corrected high-resolution cross-sectional TEM image of a portion of the sample enlarged. 0(B), the number of pellets is counted and their size and orientation are frequency-distributed. (See Figure 22(C)).

[0128] FIG. 21(A) is a cross-sectional TEM image of the nc-OS film formed by RF sputtering. Figure 21(B) is a Cs-corrected high-resolution cross-sectional TEM image of a portion of the sample enlarged. In 1(B), the number of pellets is counted and their size and orientation are frequency-distributed. (See Figure 22(D)).

[0129] The table below summarizes the results of Figure 22. The orientation of the pellet is the angle relative to the sample surface. Indicates the absolute value of .

[0130] [Table 1]

[0131] The nc-OS has a thickness of, for example, preferably 0.5 nm or more and 3 nm or less, more preferably 1 nm or less. It is preferable that the nc-OS has pellets with a size of 3 nm or less. The pellet orientation was more perpendicular to the sample surface in RF sputtering than in DC sputtering. Here, the orientation of the nc-OS pellets is The ratio of 0° or more and less than 30° is preferably, for example, 0% or more and 70% or less, and 30° or more and The ratio of angles less than 60° is preferably, for example, 10% or more and 60% or less, and more preferably 60° or more and less than 90°. The percentage of the CAAC-OS is preferably, for example, 0% or more and 60% or less. It can be seen that the orientation of the pellets is more random than in the previous example.

[0132] An oxide semiconductor film having such pellets can be explained by the following film formation model, for example. It is possible.

[0133] [Film formation model] The following describes the film formation model of nc-OS.

[0134] Figure 24 shows a schematic diagram of the deposition chamber, showing how the nc-OS film is deposited by sputtering. This is a formula diagram.

[0135] The target 5130 is glued onto the backing plate. A plurality of magnets are disposed under the backing plate. A magnetic field is generated on the target 5130 by the magnet. A sputtering method that increases the film deposition rate is called magnetron sputtering.

[0136] The target 5130 has a polycrystalline structure, and each grain contains a cleavage plane. The cleavage plane will be described in detail later.

[0137] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (also called the TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is 0.02m or more and 0.5m or less. Oxygen, argon, or a gas mixture containing 50% or more by volume of oxygen) and 0. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 5130, a discharge starts and a plasma It is confirmed that a high density plasma region is formed by the magnetic field on the target 5130. In the high density plasma region, the deposition gas is ionized, generating ions 5101. The ions 5101 are, for example, oxygen cations (O + ) and argon cations (Ar + ) etc.

[0138] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. The pellet 5100a and the pellet 5100b are formed by the impact of the collision of the ion 5101. distortion may occur.

[0139] The pellet 5100a is a flat plate or pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles in the form of plates or pellets. Sputter particles in the form of flat or pellets, such as pellets 5100b, are collectively called pellets. The planar shape of the pellet is not limited to a triangle or a hexagon. For example, For example, two equilateral triangles can form a quadrilateral. It may also be angular.

[0140] The thickness of the pellet is determined depending on the type of deposition gas. It is also preferable that the sputtered particles are in the form of thin pellets, since they are thicker than the sputtered particles. This is preferable to the cube shape.

[0141] The pellet picks up an electric charge as it passes through the plasma, causing the sides to become negatively or positively charged. The pellets have oxygen atoms on the sides, and these oxygen atoms may be negatively charged. There is a gender.

[0142] As shown in Figure 24, for example, the pellet flies like a kite through the plasma and flutters. The pellets are electrically charged and fly up onto the substrate 5120. When an area where dots are already deposited approaches, a repulsive force is generated. In this case, a magnetic field is generated parallel to the upper surface of the substrate 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet is located on the upper surface of the substrate 5120. The pellet is subjected to a force (Lorentz force) due to the action of the magnetic field and current. In order to increase the force exerted, the upper surface of the substrate 5120 is The magnetic field in the desired direction is 10 G or more, preferably 20 G or more, more preferably 30 G or more, Preferably, a region where the voltage is 50 G or more is provided. , the magnetic field parallel to the top surface of the substrate 5120 is perpendicular to the top surface of the substrate 5120. 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more It is a good idea to set up an upper area.

[0143] According to the above model, it is believed that pellets are deposited on the substrate 5120. Therefore, unlike epitaxial growth, when the surface on which the film is formed does not have a crystalline structure, For example, it is possible to form an nc-OS film on the upper surface (the surface to be formed) of the substrate 5120. Even if the structure of the deposited surface is amorphous, it is possible to deposit an nc-OS film.

[0144] Since the nc-OS film is formed by this model, the sputtered particles are thin and It is preferable that the sputtered particles are in a cubic shape. The surface of the sputtered particles facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. It may not be possible.

[0145] In addition, when the substrate 5120 is heated, friction between the pellet and the substrate 5120 increases. As a result, the pellets are in a state where the resistance of the substrate 5120 is smaller than that of the upper surface of the substrate 5120. The pellet moves in a gliding manner with the flat surface of the pellet facing the substrate 5120. Then, it reaches the side of the other pellets 5100 that have already accumulated. Then, the sides bond together to obtain a CAAC-OS film.

[0146] When the substrate 5120 is not heated, friction between the pellet and the substrate 5120 occurs. As a result, the pellet slides over the top surface of the substrate 5120. It is difficult to move like an air mass, and the irregular accumulation of snow results in nc-OS. It is possible.

[0147] CAAC-OS is formed by heating the substrate 5120, whereas nc-OS is formed by heating the substrate 51 Film formation is possible without the heating step 20.

[0148] Also, as shown in FIG. 25, the atmosphere in the chamber is preferably maintained at a temperature of 500°C above room temperature. The heating temperature may be 200°C or less, more preferably 200°C or more and 400°C or less. For example, a lamp 5140 such as a halogen lamp may be used. If this is done, the pellets flying in the chamber will be heated, which may reduce the number of defects. The size of the chips may increase. Also, heating the atmosphere can cause problems, e.g., in the chamber. This allows the moisture in the container to evaporate more easily, thereby increasing the degree of vacuum.

[0149] [cleavage plane] Below, we will explain the cleavage plane of the target described in the nc-OS film formation model. do.

[0150] First, the cleavage plane of the target will be explained using Figure 10. Figure 10 shows the cleavage plane of InGaZ The crystal structure of nO4 is shown in Fig. 10(A). The c-axis is oriented upward and parallel to the b-axis. The structure of the InGaZnO4 crystal is shown when observed from the direction of the crystal. This shows the structure of an InGaZnO4 crystal when observed from a direction parallel to the axis.

[0151] The energy required for cleavage on each crystal plane of InGaZnO4 crystal was calculated using first-principles calculations. The calculation is performed using a pseudopotential and a density functional function using a plane wave basis. The pseudopotential used is an ultra-soft pseudopotential. The potential is used. The functional is GGA PBE. The cutoff The energy is set to 400 eV.

[0152] The energy of the structure in the initial state was derived after structural optimization including the cell size. In addition, the energy of the structure after cleavage on each plane is calculated by the atomic ratio with the cell size fixed. It is derived after structural optimization of the arrangement.

[0153] Based on the crystal structure of InGaZnO4 shown in Figure 10, the first, second and third planes A structure cleaved at either the first or fourth plane was fabricated, and structural optimization calculations were performed with the cell size fixed. Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, and ( The second plane is a crystal plane parallel to the (001) plane (or ab plane) (see Figure 10(A)). , the crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, and the (001) plane (or a The third plane is a crystal plane parallel to the (110) plane (see Figure 10(A)). The fourth plane is the (100) plane (or bc plane) (see Figure 10(B)). The crystal planes are parallel (see Figure 10(B)).

[0154] Under the above conditions, the energy of the structure after cleavage on each plane is calculated. Divide the difference between the energy of the structure and the energy of the structure in its initial state by the area of ​​the cleavage plane. The cleavage energy, which is a measure of the ease of cleavage on each plane, is calculated. The energy is the kinetic energy of the electrons and the interatomic and atomic energy for the atoms and electrons contained in the structure. This is the energy that takes into account interactions between electrons and between electrons.

[0155] As a result of calculations, the cleavage energy of the first facet is 2.60 J / m 2 , the cleavage energy of the second face -0.68J / m 2 , the cleavage energy of the third face is 2.18 J / m 2 , cleavage of the fourth plane Energy is 2.12J / m 2 It was found that (see table below).

[0156] [Table 2]

[0157] From this calculation, in the crystal structure of InGaZnO4 shown in Figure 10, The cleavage energy is lowest at the Ga-Zn-O layer and the Ga-Zn-O layer. It can be seen that the plane between the two is the plane (cleavage plane) that is easiest to cleave. When the term "cleavage plane" is used, it refers to the second plane, which is the plane that is easiest to cleave.

[0158] Since the cleavage plane is on the second plane between the Ga-Zn-O layers, The InGaZnO4 crystal shown in 10(A) is separated by a plane equivalent to the two second planes. Therefore, when ions or the like are bombarded with the target, the highest cleavage energy is obtained. The wafer-like units (we call them pellets) cleaved from the lower surface of the ghee are the best. In this case, the InGaZnO4 pellets The resulting layer is a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

[0159] The first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer, which is the (001) plane) (or ab plane)), the third plane (crystal plane parallel to the (110) plane), the The cleavage energy of the 4th plane (a crystal plane parallel to the (100) plane (or bc plane)) is low. This suggests that the planar shape of the pellets is often triangular or hexagonal.

[0160] [Membrane density] Next, the density of the In-M-Zn oxide film was evaluated. =1:1:1 polycrystalline In-Ga-Zn oxide was used, and nc- The pressure was 0.4 Pa, the film formation temperature was room temperature, the power supply was 100 W, and the film formation gas Argon and oxygen were used as gases, with the flow rates of argon at 98 sccm and oxygen at 2 The density of the obtained In-Ga-Zn oxide was 6.1 g / cm 3 was Here, according to Non-Patent Document 2, the density of single crystal InGaZnO4 is 6.357 g / cm 3 Also, as stated on the JCPDS card, No. 00-038-1097, The density of single crystal In2Ga2ZnO7 is 6.494 g / cm 3 It is known to be Therefore, the obtained nc-OS film is an excellent film with high density.

[0161] The density of the In-M-Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, is, for example, approximately The density is preferably 85% or more, more preferably 90% or more, of the density of a single crystal having the same atomic ratio. , and 95% or more is more preferable.

[0162] Alternatively, when the element M is gallium, the density of the oxide semiconductor film of one embodiment of the present invention is For example, 5.7g / cm 3 More than 6.49g / cm 3 Preferably less than 5.75 g / cm 3 Below Upper 6.49g / cm 3 Less than 5.8 g / cm is preferred 3 More than 6.33g / cm 3 The following is More preferably, 5.85 g / cm 3 More than 6.33g / cm 3 The following is even more preferred:

[0163] Here, the term "approximately the same atomic ratio" means that the difference between the atomic ratios is within 10%, for example. This refers to the following:

[0164] Here, for example, the density of a single crystal is determined by the ratio of the number of atoms of two or more In-M-Zn It can also be estimated from the density of the oxide film. Here, the atomic ratio is In:M:Zn=1:1:1. Let D1 be the density of a single crystal, and let D2 be the density of a single crystal with an atomic ratio of In:M:Zn=2:2:1. D2. In-M-, indium, element M and zinc in an atomic ratio of 1:1:0.8. The density of the Zn oxide film is expected to be between D1 and D2. For example, the average value of D1 and D2 may be calculated and used as the degree of You can also refer to the value of D1, for example, the value closer to the atomic ratio. Calculate the average value using D1 and D2. When doing so, for example, 0.6×D1+0.4×D2 may be used. The density of a single crystal where n = A:B:C is D α The atomic ratio is In:M:Zn=D:E:F. The density of the single crystal is D β The density of a single crystal with the atomic ratio In:M:Zn=X:Y:Z is The degree may be calculated, for example, as follows:

[0165] First, select α so that (αA+βD):(αB+βE):(αC+βF)=X:Y:Z. Next, using the calculated α and β, the density of the single crystal is calculated as {α / (α+β)}D α +{β / (α+β)}D β It can be calculated as follows.

[0166] Next, an example of a method for forming an nc-OS film will be described.

[0167] Common methods for forming an oxide semiconductor film include sputtering, chemical vapor deposition, and the like. Chemical vapor deposition (CVD) method (metal organic chemical deposition (MOCVD) method, atomic layer deposition (ALD) method or plasma-enhanced chemical vapor deposition (PECVD), vacuum deposition or pulsed laser deposition Examples include photolithography (PLD) and photolithography.

[0168] The nc-OS film is preferably formed by sputtering. As a target used in this method, an In-M-Zn oxide can be used.

[0169] The target preferably has a polycrystalline In-M-Zn oxide. When a target having a crystalline In-M-Zn oxide is used, the target is cleavable. and thus, it is more preferable because it may be easy to form an nc-OS film.

[0170] The target is a mixture of indium oxide, an oxide containing element M, and zinc oxide. In-M-Zn oxide can be produced using this method, but polycrystalline In-M-Zn oxide It is preferable to use a target having

[0171] In addition, the nc-OS film can be preferably formed at room temperature. In some cases, it can be formed without heating, which is preferable. The gas is heated preferably at room temperature or higher and 500°C or lower, more preferably at 200°C or higher and 400°C or lower. You may do so.

[0172] [Atomic ratio] Here, as an oxide semiconductor film according to one embodiment of the present invention, for example, an In-M-Zn oxide film It is preferable to use In-M-Zn oxide in such a manner that the atomic ratio of In, M, and Zn is I Let n:M:Zn=x:y:z.

[0173] The In-M-Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, can be formed by, for example, using indium It is preferable to increase the ratio of

[0174] Furthermore, it is preferable that the oxide semiconductor film have fewer grain boundaries. Examples of conductive films include nc-OS films and CAAC-OS films. The body membrane may have both an nc-OS membrane and a CAAC-OS membrane.

[0175] In addition, when nanobeam electron diffraction was performed on the oxide semiconductor film of one embodiment of the present invention, It is preferable that the nc-OS film has a region (nc structure) where the diffraction pattern can be observed. In addition, the oxide semiconductor film according to one embodiment of the present invention has a diffraction pattern of an nc-OS film. and a region where the diffraction pattern of the CAAC-OS film is observed (CAAC structure). That's fine.

[0176] The oxide semiconductor film of one embodiment of the present invention preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, more preferably 50% or more, and even more preferably 80% or more. In addition, the oxide semiconductor film of one embodiment of the present invention preferably has a ratio of nc to CAAC. is preferably 80% or more, more preferably 90% or more and 100% or less, It is preferably 5% or more and 100% or less, and more preferably 98% or more and 100% or less. It is preferable that the content is 99% or more and 100% or less.

[0177] The oxide semiconductor film of one embodiment of the present invention may have a stack of multiple films. The nc ratio and CAAC ratio of each membrane may be different. That is, it is preferable that at least one layer of the film has a high nc ratio. For example, the nc ratio is It is preferably 30% or more, more preferably 50% or more, and even more preferably 80% or more. Among the multiple films, at least one film has a sum of the nc ratio and CAAC ratio of 80% or more. It is preferable that the ratio is 90% or more and 100% or less, and it is preferable that the ratio is 95% or more and 100% or less. It is preferable that the ratio is 98% or more and 100% or less, and it is preferable that the ratio is 99% or more and 100% or less. % or more and 100% or less is more preferable.

[0178] As shown in Figure 6, In2O3, Ga2O3, and ZnO powders were mixed and heated to 1350 When firing at ℃, it is notable that the solid solution range is widened by increasing the zinc ratio. Here, the atomic ratio of In-Ga-Zn oxide is set to the solid solution range. By setting the content of the CAAC in the oxide semiconductor film to a range where the content of the CAAC can be obtained, the content of the CAAC in the oxide semiconductor film of one embodiment of the present invention can be further increased. Therefore, by reducing the ratio of zinc, the oxide semiconductor of one embodiment of the present invention can be obtained. The nc ratio of the conductive film can be increased in some cases. The atomic ratio of element M and zinc is indium:element M:z = x:y:z. For example, By increasing the ratio of x+y to z, that is, (x+y) / z, the nc ratio can be increased. Specifically, for example, (x+y)>z is preferable, and (x+ Preferably, (x+y)≧1.5z, and more preferably, (x+y)≧2z.

[0179] In addition, the presence of spinel crystals in the CAAC-OS and nc-OS films Clear grain boundaries or boundaries may be formed. This allows the crystals of the spinel structure to be more clearly formed. It is preferable to keep away from the atomic ratio that is easily achieved.

[0180] Therefore, the In-M-Zn oxide film, which is the oxide semiconductor film of one embodiment of the present invention, The atomic ratios x, y, and z of the element M and zinc are the atomic ratios in the region 13 shown in FIG. 4(A). It is preferable that the atomic ratio of the region 14 is the same as that shown in FIG. 4(B). Here, the area 13 is defined by the first coordinate K (x:y:z=8:14:7) and the second coordinate R (x:y:z=2:4:3), the third coordinate V(x:y:z=1:2:3), and the fourth coordinate The marker S (x:y:z=1:0:1), the fifth coordinate T (x:y:z=8:0:1), and the sixth coordinate The area where the coordinates U (x:y:z=6:2:1) and the first coordinate K are connected by a line segment in order. The area 13 includes the line segments connecting the six points. The area 14 also includes a first coordinate K (x:y:z=8:14:7) and a second coordinate R(x:y:z=2:4:3), the third coordinate V(x:y:z=1:2:3), and the fourth The coordinate W (x:y:z=7:1:8), the fifth coordinate X (x:y:z=7:1:1), and the The area connecting the coordinates U (x:y:z=6:2:1) of the sixth coordinate and the first coordinate K with a line segment in order. The area 14 includes the line segments connecting the six points. Includes.

[0181] In addition, when an oxide semiconductor film is formed by a sputtering method, the atomic ratio of the resulting film is The ratio of the number of atoms in the target may deviate from that of the target. The zinc ratio of the resulting film may be smaller than that of the target. The ratio is, for example, 40 atomic % to 90 atomic % of the zinc ratio of the target. The following may occur:

[0182] Here, when forming an In-Ga-Zn oxide film by sputtering, the target used is The relationship between the atomic ratio of the dots and the atomic ratio of the resulting film was investigated.

[0183] The film formation conditions were argon and oxygen as the film formation gas, with the oxygen flow rate ratio set to 33%. Here, the oxygen flow rate ratio is expressed as oxygen flow rate ÷ (oxygen flow rate + argon flow rate) × 100 [%] The pressure is set to a range of 0.4 Pa to 0.7 Pa, and the substrate temperature is set to 200° C. The temperature was set to 300°C and the power supply power was set to 0.5 kW (DC).

[0184] Figure 23 shows the ratio of the atomic number of the two elements in the target and the residual rate of zinc. The numbers in the figure represent the atomic ratio of In:Ga:Zn in the target. The zinc residual ratio is explained below. The zinc term in the atomic ratio of the obtained film is calculated as follows: The value obtained by dividing the value by the sum of the values ​​of indium, gallium and zinc is Zn(Film). In addition, the value of the zinc term in the atomic ratio of the target is calculated based on the indium and gallium content of the target. The value obtained by dividing the value of the Zn and Zn terms by the sum of the values ​​of the Zn and Zn terms is Zn(Target). The ratio is defined as the value expressed as A = Zn(Film) ÷ Zn(Target) × 100[%]. do.

[0185] In addition, the elements of indium, gallium and zinc of the In-Ga-Zn oxide target used The ratio of the number of children is expressed as a:b:c.

[0186] In Figure 23(A), the horizontal axis shows the ratio of zinc to gallium in the target (c / b), and the horizontal axis shows the ratio of zinc to gallium in the target (c / b). 3(B) shows the ratio of gallium to indium atoms in the target on the horizontal axis (b / a ) on the horizontal axis, and Figure 23(C) shows the ratio of zinc to indium in the target (c / a). The vertical axis of each graph shows the zinc retention rate A.

[0187] From Figure 23, it can be seen that the zinc residual rate of the film obtained by sputtering is approximately 5 It can be seen that the ratio is between 0% and 90%. In addition, indium and gallium are It can be said that the atomic ratio of the target does not change significantly compared to the target. For example, if the ratio of zinc to zinc (c / b) is 1, the zinc retention rate A is about 66%, In the case of 2, it is about 74% and in the case of 3, it is about 83%.

[0188] Also, from Figure 23(A), the ratio of zinc to gallium in the target (c / b) and the It can be seen that there is a good correlation between the residual rate of zinc and gallium. The lower the value, the lower the retention rate.

[0189] In view of the above, the oxide semiconductor film in the region 13 shown in FIG. 4(A) is formed by sputtering. To obtain this, for example, the zinc ratio of the target is preferably adjusted to the zinc ratio of the target film. Preferably, it is 1.7 times or more, and more preferably, 1.5 times or more. It is preferable that indium, gallium, and zinc have an atomic ratio in the region 15 shown in FIG. Here, the area 15 is defined by the first coordinates K (a:b:c=8:14:7) and the second coordinates R (a :b:c=2:4:3), the third coordinate Y(a:b:c=1:2:5.1), and the fourth coordinate Marker Z (a:b:c=1:0:1.7), fifth coordinate T (a:b:c=8:0:1), The sixth coordinate U (a:b:c=6:2:1) and the first coordinate K are connected in order by line segments. The area 15 includes the line segment connecting the six points. Includes coordinates.

[0190] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0191] (Embodiment 3) In this embodiment, an example of a transistor including an oxide semiconductor film according to one embodiment of the present invention will be described. This article explains:

[0192] [Transistor example 1] An example of a transistor including an oxide semiconductor film will be described with reference to FIGS.

[0193] FIG. 12A is a top view of the transistor 100. FIG. 12B is a top view of the transistor 100. ) is a cross section taken along the dashed line X-X', and FIG. 12(C) is a cross section taken along the dashed line Y-Y'. The transistor 100 shown in FIG. 12 is made up of a substrate 50 and an insulating layer in contact with the upper surface of the substrate 50. The insulating film 51, the insulating film 114 in contact with the upper surface of the insulating film 51, and the semiconductor film 114 in contact with the upper surface of the insulating film 114. A conductor layer 101, a conductive layer 104a and a conductive layer 104b, and a gate insulating layer on the semiconductor layer 101. a gate electrode 103 overlapping the semiconductor layer 101 via the gate insulating film 102; In addition, an insulating film 112 and an insulating film 113 are provided to cover the transistor 100. The transistor 100 may also include a conductive layer 105. An insulating film does not necessarily have to be provided between the insulating films 114 .

[0194] The semiconductor layer 101 may be formed as a single layer or as a stacked structure of first to third layers. More preferably, the second layer is provided on and in contact with the first layer, and the third layer is provided on the second layer. In the transistor of one embodiment of the present invention, the first layer and the second layer are provided in contact with each other. The third layer has an area where the current is less likely to flow than the second layer. The layer 3 is sometimes called an insulating layer. Therefore, as shown in the example of FIG. The insulating layer 101a is formed of a laminated structure of an insulating layer 101a, a semiconductor layer 101b, and an insulating layer 101c. It is preferable that the insulating layer 101a or the insulating layer 101c is not included. In the example shown in FIG. 12, the semiconductor layer 101b is formed by the insulating layer 101. The conductive layer 104a and the conductive layer 104b are in contact with the upper surface of the semiconductor layer 101b. The insulating layer 101c is in contact with the semiconductor layer 101b and is separated from the semiconductor layer 101b in the overlapping region. The gate insulating film 102 is in contact with the upper surface of the insulating layer 101b. The gate electrode 103 is in contact with the gate insulating film 102 and the insulating layer 101c. It overlaps with the semiconductor layer 101b.

[0195] In addition, an insulating film 112 and an insulating film 113 are provided to cover the transistor 100 . The insulating film 112 and the insulating film 113 will be described in detail in the embodiment described later.

[0196] The conductive layer 104a and the conductive layer 104b function as a source electrode and a drain electrode. In addition, a voltage lower or higher than that of the source electrode is applied to the conductive layer 105, The threshold voltage of the transistor may be shifted in the positive or negative direction. By shifting the threshold voltage of the transistor in the positive direction, the transistor In some cases, a normally-off transistor can be realized, in which the transistor is in a non-conducting state (off state). The voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to the conductive layer 105 is variable, a circuit for controlling the voltage is connected to the conductive layer 105. The conductive layer 105 may be connected to the gate electrode 103.

[0197] The upper surface of the insulating film 114 is etched by CMP (Chemical Mechanical Polishing). It is preferable that the surface is planarized by a planarization process using a fining method or the like.

[0198] The insulating film 114 preferably contains an oxide. It is preferred that the oxide material contains more oxygen than the stoichiometric composition. It is preferable to use an oxide containing oxygen. The oxide film containing oxygen is partially desorbed by heating. is supplied to the semiconductor layer 101, which is an oxide semiconductor, and reduces oxygen vacancies in the oxide semiconductor. As a result, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability is improved. It is possible.

[0199] The oxide film containing more oxygen than the oxygen that satisfies the stoichiometric composition is, for example, In TDS analysis, the amount of oxygen released was 1.0 x 10 1 8 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 That's all The surface temperature of the film during the TDS analysis was 100°C or higher. The temperature is preferably in the range of 00°C or lower, or 100°C or higher and 500°C or lower.

[0200] For example, such a material may include silicon oxide or silicon oxynitride. Alternatively, a metal oxide can be used. Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttria Usable are yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, etc. In this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen as its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. Indicates the material with the highest content.

[0201] In order to make the insulating film 114 contain excess oxygen, oxygen is introduced into the insulating film 114. For example, a region containing excess oxygen (a small amount of oxygen) may be formed in the insulating film 114 after deposition. At least one of oxygen radicals, oxygen atoms, and oxygen ions is introduced to create an excess of oxygen. The oxygen-containing region is formed. The oxygen-introducing method is ion implantation or ion doping. , plasma immersion ion implantation, plasma treatment, etc. can be used.

[0202] The semiconductor layer 101 is composed of an oxide semiconductor. If a semiconductor material with a wide band gap and low carrier density is used, In addition, the semiconductor layer 101 is preferably an oxide semiconductor. The inclusion of a conductor suppresses fluctuations in electrical characteristics, resulting in highly reliable transistors. This can be achieved.

[0203] Here, as the semiconductor layer 101, for example, the oxide semiconductor shown in the first embodiment or the second embodiment may be used. You can use your body.

[0204] In this specification and the like, when the term "substantially intrinsic" is used, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 x 10 13 / cm 3 By making the oxide semiconductor layer highly purified and intrinsic, the transistor has stable electrical characteristics. Sex can be given.

[0205] Here, the semiconductor layer 101 includes an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101b. The case where the laminated film of the semiconductor layer 101b and the semiconductor layer 101c is used will be described in detail. It is preferable to use an oxide having a larger electron affinity than the layer 101a and the insulating layer 101c. For example, the semiconductor layer 101b may have a higher electrical conductivity than the insulator layers 101a and 101c. Electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less More preferably, an oxide having a larger electron energy than the ... The affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0206] The semiconductor layer 101b has a higher electron affinity than the insulator layers 101a and 101c. By using a large oxide, when an electric field is applied to the gate electrode, the insulating layer 101a, Of the semiconductor layer 101b and the insulator layer 101c, the semiconductor layer 101b has a larger electron affinity. Here, by forming a channel in the semiconductor layer 101b, For example, since the channel forming region is separated from the interface with the gate insulating film 102, Therefore, the influence of scattering at the interface of the transistor can be reduced. Here, the semiconductor layer 101b and the insulating layer 101c are formed as described below. Since the constituent elements are common, there is almost no interfacial scattering.

[0207] In addition, the gate insulating film may be a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or When a silicon nitride film or the like is used, the silicon contained in the gate insulating film is When silicon is contained in the oxide semiconductor film, the crystal structure of the oxide semiconductor film may be contaminated. Therefore, the channel formation may cause a decrease in the conductivity and carrier mobility. In order to reduce the impurity concentration, for example, the silicon concentration, of the semiconductor layer 101b, It is preferable to provide an insulating layer 101c between the gate insulating film and the insulating layer 101b. In order to reduce the influence of impurity diffusion from the insulating film 114, the semiconductor layer 101b and the insulating film It is preferable to provide an insulating layer 101a between the layers 114.

[0208] The semiconductor layer 101b is, for example, an oxide semiconductor containing indium, the element M, and zinc. For example, the oxide semiconductor film described in Embodiment 1 or 2 may be used. It is preferable.

[0209] The semiconductor layer 101b is made of, for example, an oxide with a large energy gap. The energy gap of 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.7 eV or less, more preferably 2.8 eV or more and 3.3 eV or less .

[0210] Next, the insulating layer 101a and the insulating layer 101c will be described. The O1a and the insulator layer 101c contain at least one element other than oxygen that constitutes the semiconductor layer 101b, Alternatively, the semiconductor layer 101b may be an oxide composed of two or more elements other than oxygen. Since the insulating layer 101a and the insulating layer 101c are made of one or more kinds of elements, Therefore, the interface between the insulator layer 101a and the semiconductor layer 101b, and the interface between the semiconductor layer 101b and the insulator layer 101a Interface states are unlikely to form at the interface with O1c.

[0211] The band structure is shown in Figure 11. vel), the energy of the bottom of the conduction band of each layer (Ec) and the top of the valence band Indicates energy (denoted as Ev).

[0212] Here, between the insulating layer 101a and the semiconductor layer 101b, there is a In some cases, the semiconductor layer 101b and the insulating layer 101b are mixed together. Between the semiconductor layer 101b and the insulating layer 101c, there may be a mixed region of the semiconductor layer 101b and the insulating layer 101c. The interfacial state density is low in the mixed region. The laminate of the insulating layer 101c and the insulating layer 101d has a structure in which energy is continuously distributed near the interfaces of the insulating layer 101c and the insulating layer 101d. This results in a band structure that changes (also called a continuous junction).

[0213] At this time, the electrons are not in the insulator layer 101a and the insulator layer 101c but in the semiconductor layer 1 As described above, the electrons move mainly through the insulating layer 101a and the semiconductor layer 101b. the interface state density at the interface between the semiconductor layer 101b and the insulator layer 101c, The lowering of the surface state density inhibits the movement of electrons in the semiconductor layer 101b. Therefore, the on-state current of the transistor can be increased.

[0214] In FIG. 11, the insulating layer 101a and the insulating layer 101c have the same Ec. However, they may be different. For example, The Ec of the layer 101c may have a high energy.

[0215] As shown in FIG. 12B, the side surface of the semiconductor layer 101b is covered with the conductive layer 104a and the conductive layer 104b. 12(C), the electric field of the gate electrode 103 causes The semiconductor layer 101b can be electrically surrounded (the electric field of the conductor can electrically surround the semiconductor). The structure of the transistor that is electrically surrounded is called the surrounded channel (sc The gate electrode 103 is formed on the top and side surfaces of the semiconductor layer 101b. By providing the semiconductor layer 101b facing each other, the semiconductor layer 101b is not only provided near the upper surface thereof but is also provided over the entire surface (bulk). In the s-channel structure, the source-drain A large current can be passed between the drains, and the current (on-state current) can be increased when the transistor is conducting. .

[0216] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. Preferably, the transistor has a channel width of 20 nm or less. or 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. In particular, the smaller the channel width, the more the channel is formed inside the semiconductor layer 101b. Since the area covered by the gate electrode is wider, the contribution to the on-current increases as the gate electrode becomes smaller.

[0217] The insulating layer 101a and the insulating layer 101c are made of, for example, In-M-Zn oxide. It is possible.

[0218] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, for example, the insulating layer 101c may contain indium gallium oxide. The ratio of the sodium atoms [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it is 90% or more.

[0219] More preferably, the insulating layer 101c contains gallium oxide. If gallium oxide is included in c, a lower off-state current may be achieved.

[0220] The insulating layer 101a and the insulating layer 101c are formed using an nc-OS film or a CAAC-OS film. Here, it is preferable that the nc ratio of the insulating layer 101a and the insulating layer 101c and the CA By increasing the AC ratio, for example, it is possible to reduce defects. For example, the region having spinel crystals can be reduced. In addition, for example, by using a film with high blocking ability against impurities, In addition, it is possible to suppress the incorporation of impurities into the semiconductor layer 101b. The impurity concentration of 101b can be reduced.

[0221] The nc ratio of the insulator layer 101a and the insulator layer 101c is preferably, for example, 10% or more. 30% or more is preferable, 50% or more is preferable, 80% or more is preferable, and 90% or more is preferable. Preferably, it is 95% or more.

[0222] Here, the insulating layer 101a, the semiconductor layer 101b, and the insulating layer 101c are made of In-M-Zn Consider the case of an oxide. The atomic ratio of In, element M, and Zn in the insulator layer 101a is x a , y a and z a Similarly, the In, element M, and Zn contained in the semiconductor layer 101b are The atomic ratio of x b , y b and z b Similarly, the insulator layer 101c contains In, The atomic ratio of M and Zn is x c , y c and z c The following describes the preferred values ​​for each. I will explain.

[0223] x b , y b and z b 1, 2(A) and 4. It is preferable that the range is one of the ranges 11 and 14.

[0224] The insulating layer 101a and the insulating layer 101c do not contain a spinel type crystal structure, or It is preferable that the number is small. Therefore, x a :y a :z a and x c :y c :z c For example, Figure 1 The value is set to be within the range of the region 11 and to have a smaller electron affinity than the semiconductor layer 101b. It is preferable that

[0225] Here, the electron affinity of the semiconductor layer 101b is increased by more than that of the insulator layers 101a and 101c. To increase the indium content, for example, the indium content of the semiconductor layer 101b is increased by It is preferable that the thickness is higher than that of the insulating layer 101c.

[0226] For example, x b / (x b +y b +z b )>x a / (x a +y a +z a ), and x b / (x b +y b +z b )>x c / (x c +y c +z c ) is preferably satisfied.

[0227] For example, preferably x a / (x a +y a )<0.5, and more preferably x a / (x a +y a )<0.33, and more preferably x a / (x a +y a )<0.25 Also, preferably x b / (x b +y b ) ≧0.25, and more preferably x b / ( x b +y b )≧0.34. c / (x c +y c )<0.5 , more preferably x c / (x c +y c )<0.33, and more preferably x c / (x c +y c )<0.25.

[0228] or x a , y a , z a , and x c , y c , z c is the element in the region 16 shown in FIG. Here, the region 16 has a first coordinate K (x:y:z=8: 14:7), the second coordinate R (x:y:z=2:4:3), and the third coordinate L (x:y:z =2:5:7), the fourth coordinate M(x:y:z=51:149:300), and the fifth coordinate B(x:y:z=1:4:10), the sixth coordinate C(x:y:z=1:1:4), and the seventh The area where the coordinates A (x:y:z=2:2:1) and the first coordinate K are connected by a line segment in order. Note that the area 16 includes all coordinates.

[0229] When the transistor has an s-channel structure, the entire semiconductor layer 101b Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor. For example, it is possible to set the thickness to 20 nm or more, preferably 40 nm or more, and more preferably 60 nm or more. More preferably, the semiconductor layer 101b may have a region with a thickness of 100 nm or more. However, since the productivity of semiconductor devices may decrease, for example, 300 nm or less, A semiconductor having a region with a thickness of preferably 200 nm or less, more preferably 150 nm or less This may be called layer 101b.

[0230] In order to increase the on-current of the transistor, the thickness of the insulating layer 101c is small. For example, it is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm. The insulating layer 101c may have the following regions: The semiconductor layer 101b on which the hole is formed is doped with elements other than oxygen (hydrogen, The insulating layer 10 has a function of blocking the intrusion of silicon and other inorganic materials. It is preferable that 1c has a certain thickness, for example, 0.3 nm or more, preferably When the insulating layer 101c has a region with a thickness of 1 nm or more, more preferably 2 nm or more, The insulating layer 101c also functions to absorb oxygen released from the gate insulating film 102 and other components. To suppress diffusion, it is preferable that the material has oxygen blocking properties.

[0231] In order to increase reliability, the insulating layer 101a is thick and the insulating layer 101c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 4 100 nm or more, more preferably 60 nm or more. By increasing the thickness of the insulating layer 101a, the insulating layer 101a can be easily formed between the adjacent insulating layers. The distance from the interface with a to the semiconductor layer 101b where the channel is formed can be increased. However, since the productivity of the semiconductor device may decrease, for example, 200 nm or less is preferred. or an insulating layer 1 having a region with a thickness of 120 nm or less, more preferably 80 nm or less. Just use 01a.

[0232] When a large amount of hydrogen or moisture is contained in an oxide semiconductor film, a donor level due to hydrogen is formed. The formation of donor levels can cause the threshold voltage of the transistor to shift in the negative direction. Therefore, after the oxide semiconductor film is formed, dehydration treatment (dehydrogenation treatment) is performed. It is preferable to highly purify the material by removing hydrogen or moisture so that it contains as few impurities as possible. stomach.

[0233] Note that oxygen is also reduced by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, after the dehydration treatment, oxygen is supplied to the oxide semiconductor film to eliminate oxygen vacancies. In this specification and the like, supplying oxygen to the oxide semiconductor film is Alternatively, the proportion of oxygen contained in the oxide semiconductor film may be chemically adjusted. Increasing the composition to a level higher than the stoichiometric composition is sometimes referred to as hyperoxygenation treatment.

[0234] In this way, hydrogen or water is removed by the dehydration treatment, and then oxygen is added by the oxygenation treatment. By compensating for the element deficiency, it becomes type i (true), or as close as possible to type i, essentially i It is to be noted that the term "substantially intrinsic" means that the oxide semiconductor film is an oxide semiconductor film. The number of carriers originating from donors in the compound semiconductor film is extremely small (close to zero), and the carrier density is Degrees are 1 x 10 17 / cm 3 Below, 1×10 16 / cm 3 Below, 1×10 15 / cm 3 below , 1×10 14 / cm 3 Below, 1×10 13 / cm 3 This means that:

[0235] A transistor including an i-type or substantially i-type oxide semiconductor film has excellent properties. For example, the off-state current of a transistor including an oxide semiconductor film can be The flow rate was 1 × 10 -18 A or less, preferably 1×10 -21 Below A , and more preferably 1 × 10 -24 A or less, or 1 x 10 at 85°C -15 A or below, good Preferably 1 x 10 -18 A or less, more preferably 1 × 10 -21 A or less Here, the off-state current refers to the drain current when the transistor is in the off state. In addition, when a transistor is in the off state, in the case of an n-channel transistor, the gate voltage is Specifically, when the gate voltage is 1 V or more higher than the threshold, , 2V or more or 3V or more less, the transistor is in an off state.

[0236] One of the conductive layers 104a and 104b functions as a source electrode and the other functions as a drain electrode. It functions as an electrode.

[0237] The conductive layer 104a and the conductive layer 104b are made of aluminum, titanium, chromium, nickel, copper, or the like. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten Metals or alloys containing metals as the main component are used in a single layer structure or a multilayer structure. For example, Single layer structure of aluminum film containing silicon, two layer structure of aluminum film laminated on titanium film Two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, Two-layer structure in which a copper film is laminated on a titanium film or titanium nitride film and the titanium An aluminum film or a copper film is laminated on the titanium nitride film or the titanium nitride film, and then a titanium film or a copper film is laminated on the aluminum film or the copper film. A three-layer structure in which a titanium film or titanium nitride film is formed, a molybdenum film or molybdenum nitride film, and Then, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There is also a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed on top of the above. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0238] The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminated layer or a single layer.

[0239] The gate insulating film 102 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium Luminate (HfAl x O y N z ), using high-k materials such as yttrium oxide Good too.

[0240] The gate insulating film 102 may be made of aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, silicon oxide oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide Insulating films, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film can be formed using any of nitride insulating films or a mixture of these materials.

[0241] The gate insulating film 102 is made of an acid having a stoichiometric composition, similar to the insulating film 114. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0242] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide can be used to shift the threshold voltage in the positive direction. For example, a laminated film of aluminum and hafnium oxide is used as a gate insulating film. Materials with many electron capture levels, such as aluminum and tantalum oxide, are used, and the temperature is higher (semiconductor Temperatures higher than the operating or storage temperature of the device, or between 125°C and 450°C Typically, the gate electrode is biased to the source electrode or drain electrode at a temperature of 150°C or higher and 300°C or lower. By maintaining a state where the potential is higher than that of the lead electrode for at least one second, typically at least one minute, the semiconductor Electrons move from the layer to the gate electrode, and some of them are captured in the electron trap level. will be done.

[0243] The gate electrode 103 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide The gate electrode 103 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a silicon film on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride Two-layer structure with tungsten film stacked on top of film, tantalum nitride film or tungsten nitride film A two-layer structure with a tungsten film laminated on top of the titanium film, and an aluminum film on top of the titanium film. There are three-layer structures, such as a laminated aluminum film and a titanium film on top of that. Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium An alloy film made of one or more of the above metals or a nitride film may also be used.

[0244] The gate electrode 103 is made of indium tin oxide or indium containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide may also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0245] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode 103 and the gate insulating film 102. Conductor film, In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Zn Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I These films may have a resistivity of 5 eV or more, preferably 5.5 eV or more. Since the work function is higher than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using this material can be shifted in the positive direction, For example, an In-Ga-Zn oxynitride film can be used as a switching element with a turn-off characteristic. When a compound semiconductor film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 101, specifically, An In-Ga-Zn-based oxynitride semiconductor film having a thickness of 100 nm or more is used.

[0246] This concludes the description of transistor 100.

[0247] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on state). The source (source region or source electrode) in the region where the channel is formed. The distance between the transistor and the drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0248] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The area where the gate electrode overlaps with the gate electrode (the area where current flows) or the area where the channel is formed. The length of the part where the source and drain face each other is called the length of one transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one of the values, maximum and minimum, in the region where the channel is formed. The value is the average value.

[0249] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in a transistor with a fine, three-dimensional structure, the upper surface of the semiconductor The ratio of the channel region formed on the side of the semiconductor to the ratio of the channel region formed on the inside of the semiconductor In this case, the apparent channel width shown in the top view may be The effective channel width where the channel is actually formed is larger than the actual channel width.

[0250] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0251] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent thickness is the length of the part where the source and drain face each other in the region where the The channel width is referred to as "Surrounded Channel Width (SCW)". In this specification, when simply referred to as the channel width, This may refer to the enclosed channel width or apparent channel width. In the detailed description, when simply referred to as a channel width, it may refer to an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, and enclosure The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. , values ​​can be determined.

[0252] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0253] [Transistor example 2] A structure of a transistor including an oxide semiconductor film according to one embodiment of the present invention, which is different from that shown in FIG. An example of the semiconductor device of one embodiment of the present invention will be described with reference to FIG. 13(B) is a top view of a transistor 100, which is a device, and FIG. 13(C) is a top view of a transistor 100 shown in FIG. FIG. 13(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2. 1 corresponds to a cross-sectional view taken along the dashed dotted line Y1-Y2 shown in FIG.

[0254] The transistor 100 includes a gate electrode 203a that functions as a gate electrode on the substrate 50. , the gate insulating film 202 on the substrate 50 and the gate electrode 203a, and a semiconductor layer 201, and a source electrode and a drain electrode electrically connected to the semiconductor layer 201; The transistor 100 also includes a conductive layer 204a and a conductive layer 204b. More specifically, an insulating film 21 is formed on the conductive layer 204a, the conductive layer 204b, and the semiconductor layer 201. 4. An insulating film 216 and an insulating film 218 are laminated in this order.

[0255] Next, components included in the transistor of this embodiment will be described.

[0256] The gate electrode 203a functioning as the gate electrode of the transistor 100 is Please refer to the description of the electrode 103.

[0257] The gate insulating film 202 that functions as the gate insulating film of the transistor 100 is The description of the gate insulating film 102 can be referred to. For example, as shown in FIG. 13, a gate insulating film 202a and a gate insulating film 202b may be used. In this case, for example, the lower layer, here the gate insulating film 20 A film having a function as a blocking film that suppresses oxygen permeation may be used for 2a. As a film having a function as a locking film, for example, see the barrier film 111 described later. Just do that.

[0258] The semiconductor layer 201 is formed using the oxide semiconductor film described in Embodiment 1 or 2. For the semiconductor layer 201, the description of the semiconductor layer 101 may be referred to. The semiconductor layer 201 may be a laminated film of two or more layers.

[0259] The insulating films 214, 216, and 218 serve as protective insulating films for the transistor 100. The insulating film 214 functions as a protective layer for the semiconductor layer 201 when the insulating film 216 is formed. It also functions as a damage mitigation membrane.

[0260] The insulating films 214 and 216 have a stoichiometric composition, for example, as in the insulating film 114 described above. It is more preferable that the oxygen-excess region has a region containing oxygen in excess of the oxygen-excess region.

[0261] Furthermore, it is preferable that the insulating film 214 has a small number of defects. , the spin density of the signal appearing at g=2.001 due to the silicon dangling bond is 3×10 17 spins / cm 3 The insulating film 214 preferably has a defect density of 0.01 to 0.01 mm. If the defect density is high, oxygen will bond to the defects, and the amount of oxygen permeating through the insulating film 214 will decrease. It will decrease.

[0262] In the insulating film 214, all of the oxygen that has entered the insulating film 214 from the outside is Some oxygen does not move to the outside of the insulating film 214 and remains in the insulating film 214. At the same time, oxygen contained in the insulating film 214 moves to the outside of the insulating film 214, Oxygen migration may occur in the film 214. When the oxide insulating film capable of forming the insulating film 216 is formed, the insulating film 216 is formed on the insulating film 214. The desorbed oxygen can be transferred to the semiconductor layer 201 via the insulating film 214 .

[0263] The insulating film 214 has an upper energy (E v_os ) and the energy at the bottom of the conduction band (E c_os ) between the oxide insulators with low density of nitrogen oxide levels It can be formed using a velum. v_os and E c_os The density of nitrogen oxides between As an oxide insulating film with a low degree of conductivity, a silicon oxynitride film which emits a small amount of nitrogen oxide, or An aluminum oxynitride film or the like that emits a small amount of nitrogen oxides can be used.

[0264] In addition, a silicon oxynitride film that emits a small amount of nitrogen oxides can be analyzed by thermal desorption spectroscopy. It is a membrane that releases more ammonia molecules than nitrogen oxides, and a typical example is ammonia. The amount of released near molecules is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is the The amount of ammonia molecules released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 5 The amount released by heat treatment at 0°C to 550°C.

[0265] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO or NO forms a level in the insulating film 214. Therefore, the nitrogen oxide is located within the energy gap of the insulating film 214 and the semiconductor. When the electrons diffuse to the interface of the insulating film 214, the level traps electrons on the insulating film 214 side. As a result, the trapped electrons may move near the interface between the insulating film 214 and the semiconductor layer 201. The electrons remain nearby, shifting the threshold voltage of the transistor in the positive direction.

[0266] Nitrogen oxide reacts with ammonia and oxygen during the heat treatment. The nitrogen oxide contained in the insulating film 216 reacts with the ammonia contained in the insulating film 216 during the heat treatment. Therefore, the nitrogen oxide contained in the insulating film 214 is reduced. Electrons are less likely to be trapped at the interface between the silicon layer and the semiconductor layer 201.

[0267] The insulating film 214 is formed on the opposite side of the semiconductor layer 201 from the region where the channel is formed. (hereinafter referred to as the back channel region) contacts the semiconductor layer 201. It serves to protect the back channel region of layer 201 .

[0268] The insulating film 214 is made of E v_os and E c_os The nitrogen oxide level density is low during oxidation. By using a dielectric insulating film, it is possible to reduce the shift in the threshold voltage of the transistor. As a result, fluctuations in the electrical characteristics of the transistor can be reduced.

[0269] Also, E v_os and E c_os The oxide insulating film with low density of nitrogen oxide levels between the The nitrogen concentration measured by IMS is 6×10 20 atoms / cm 3 The following is the result.

[0270] Furthermore, it is preferable that the insulating film 216 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating film 216 has a thickness of 100 nm or less than that of the semiconductor layer 2. Since it is far from O1, it may have a higher defect density than the insulating film 214.

[0271] The transistor 100 may also have the structure shown in Figures 14 and 15. The transistor 100 shown is a channel-etched transistor, but the transistors shown in FIGS. The transistor 100 shown in FIG. 15 is a channel protection transistor.

[0272] FIG. 14A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 14(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 14(A). 14(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 14(A). The transistor 100 shown in FIG. an electrode 203a, a gate insulating film 202 formed on the substrate 50 and the gate electrode 203a; , a semiconductor layer 201 overlapping with a gate electrode 203a via a gate insulating film 202, and a gate The insulating film 214 on the insulating film 202 and the semiconductor layer 201, and the insulating film 216 on the insulating film 214 , the semiconductor layer 20 in the openings 141 a and 141 b of the insulating film 214 and the insulating film 216 . The transistor 1 has a pair of conductive layers 204a and 204b in contact with the transistor 1. 00, more specifically, on the conductive layer 204a, the conductive layer 204b, and the insulating film 216, an insulating film 218 may be provided.

[0273] FIG. 15A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 15(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 15(A). 15(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 15(A). The transistor 100 shown in FIG. 15 corresponds to the transistor 10 shown in FIG. 15. The shape of the insulating films 214 and 216 differs from that of the transistor 1 shown in FIG. The insulating films 214 and 216 of 00 are provided in an island shape on the channel region of the semiconductor layer 101. The other configurations are similar to those of the transistor 100 shown in FIG. 14, and similar effects are achieved.

[0274] The transistor 100 shown in FIGS. 14 and 15 includes a pair of conductive layers 204a and 204b. When forming the insulating layer 204b, the semiconductor layer 201 is covered with the insulating film 214 and the insulating film 216. Therefore, the semiconductor layer 204 is formed by etching to form the pair of conductive layers 204a and 204b. The conductor layer 201 is not damaged. By using an oxide insulating film with a low defect content, fluctuations in electrical characteristics are suppressed, and reliability is improved. Therefore, a transistor with improved performance can be fabricated.

[0275] As shown in FIG. 16, the transistor 100 has an electrode 203b on the insulating film 218. FIG. 16A illustrates a transistor 100, which is a semiconductor device of one embodiment of the present invention. 16(B) is a top view, and FIG. 16(B) is a cross section taken along the dashed line X1-X2 shown in FIG. 16(A). 16(C) corresponds to a cross-sectional view of the plane, and FIG. 16(C) is a cross-sectional view of the plane between the dashed line Y1-Y2 shown in FIG. 16(A). 16 corresponds to a cross-sectional view of the cut surface of the electrode 203b. 16, and is connected to the gate electrode 203a through the openings 142c and 142d. However, the electrode 203b and the gate electrode 203a may not be connected to each other. When the electrode 203b and the gate electrode 203a are not connected, the electrodes are provided with different potentials. can be given.

[0276] As shown in FIG. 16, in the channel width direction, the side surface of the semiconductor layer 201 and the electrode 203b and are opposed to each other, the gate electrode 203a and the electrode 203b is formed by interposing the gate insulating film 202, the insulating film 214, the insulating film 216 and the insulating film 218. By surrounding the semiconductor layer 201 with the gate electrode, the region in which carriers flow in the semiconductor layer 201 is The insulating film 202 and the insulating film 214 are not only at the interface between the semiconductor layer 201 and the semiconductor layer 201, but also at the interface between the semiconductor layer 20 Since carriers also flow inside the transistor 100, the movement of carriers in the transistor 100 As a result, the on-state current of the transistor 100 increases and the field effect In addition, the electric field of the electrode 203b is applied to the side surface of the semiconductor layer 201, or the side surface and Since the edge including its vicinity is affected, parasitic charges at the side or edge of the semiconductor layer 201 The occurrence of filaments can be suppressed.

[0277] 16, as an example of the semiconductor layer 201, a semiconductor layer 201b is formed on a semiconductor layer 201a. Here, for example, the semiconductor layer 201b is more conductive than the semiconductor layer 201a. The energy of the bottom of the band is close to the vacuum level, and typically, the bottom of the conduction band of the semiconductor layer 201b and the energy of the bottom of the conduction band of the semiconductor layer 201a is 0.05 eV. or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, The value is 1 eV or less, 0.5 eV or less, or 0.4 eV or less. The difference between the electron affinity of the semiconductor layer 201a and the electron affinity of the semiconductor layer 201a is 0.05 eV or more, and 0.07 e V or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0. It is 5 eV or less, or 0.4 eV or less.

[0278] The semiconductor layer 101b described in Embodiment 3 may be referred to as the semiconductor layer 201a. For example, the atomic ratio of indium, element M, and zinc contained in the semiconductor layer 101b is within a preferred range. The semiconductor layer 201b may be formed by the insulating layer 1 shown in the third embodiment. For example, the insulator layer 101c may contain indium, element M, and zinc. Reference may be made to the preferred range of the atomic ratio of lead.

[0279] [Transistor Modification] Modifications of the transistor 100 are shown in Figures 30 to 33. For example, the transistor 100 30. FIG. 30 shows a structure in which the shapes of the conductive layer 104a and the conductive layer 104b are different from each other. 30(B) is different from FIG. 30(A) passing through the dashed line AB shown in FIG. A cross section perpendicular to 0(A) is shown.

[0280] The transistor 100 may also have a structure shown in Figure 31. In Figure 12, the insulator layer 101 31, the conductive layer 104a and the conductive layer 104b are in contact with each other. 31(A) and 31(B) are in contact with the bottom surfaces of the conductive layer 104a and the conductive layer 104b. The cross section is shown along the dashed line AB and perpendicular to FIG. 31(A). As a result, the insulating layer 101a, the semiconductor layer 101b, and the insulating layer 101c are During film formation, the film can be formed continuously without being exposed to the atmosphere. This can reduce various interface defects.

[0281] The transistor 100 may have a structure shown in FIG. 32(A) shows a cross section of a plane passing through the dashed line AB shown in FIG. 32(A) and perpendicular to FIG. 32(A). 12 in that it does not have the conductive layer 104a and the conductive layer 104b. As shown in (C), the transistor 100 has a low resistance layer 171a and a low resistance layer 171b. The low resistance layer 171a and the low resistance layer 171b may be formed as a source region or a drain region. It is preferable that the low resistance layer 171a and the low resistance layer 171b have impurities. The resistance of the semiconductor layer 101 can be reduced by adding impurities. The impurities to be added include, for example, argon, boron, carbon, magnesium, and argon. Aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium , manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium, Zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium It is preferable to add one or more selected from the group consisting of hafnium, tantalum, and tungsten. The low resistance layers 171a and 171b are formed by, for example, removing the above-mentioned impurities from the semiconductor layer 101. 5×10 physical elements 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / c m 3 More preferably, 2 × 10 20 atoms / cm 3 More preferably, 5x 10 20 atoms / cm 3 This is the area including the above. This is an enlarged view of 324.

[0282] In addition, impurities, such as unnecessary hydrogen, may be trapped in such a low-resistance region. By trapping unnecessary hydrogen in the low resistance layer, the hydrogen concentration in the channel region can be reduced. As a result, the transistor 100 can have good characteristics.

[0283] The transistor 100 may also have a structure shown in FIG. 33. FIG. 33 shows a structure in which the insulator layer 101 The shape of the gate insulating film 102 is different from that of FIG. 32. 33(A) and passes through the dashed line AB shown in FIG.

[0284] 30 to 33, the insulating layer 101 is in contact with the semiconductor layer 101b. The configuration in which the insulating layer 101a and the insulating layer 101c are provided has been described. One or both of the 01c may be omitted.

[0285] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0286] (Fourth embodiment) In this embodiment, a display device including the transistor described in the previous embodiment will be described. An example will be described below with reference to FIGS.

[0287] 34 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 provided on a substrate 701 and a source driver 703 provided on the first substrate 701 are connected to the pixel portion 702. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, a sealant 712 arranged to surround the gate driver circuit section 704 and the gate driver circuit section 706; and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 are sealed. Although not shown in FIG. 34, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0288] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel section 702, a source driver circuit section 704, a gate driver circuit section a path portion 706 and an FPC terminal portion 708 electrically connected to the gate driver circuit portion 706; (FPC: Flexible printed circuit) is provided. An FPC 716 is connected to the FPC terminal section 708, and the pixel section 702 is Various signals are supplied to the source driver circuit section 704 and the gate driver circuit section 706. In addition, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 A signal line 710 is connected to the FPC terminal portion 708. Various signals are supplied to the pixel section 702, the source driver circuit 704, and the like via signal lines 710. 704 and a gate driver circuit section 706.

[0289] Furthermore, the display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit etc. is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead of COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0290] The display device 700 also includes a pixel section 702, a source driver circuit section 704, and a gate The driver circuit section 706 has a wiring section or a plurality of transistors. The semiconductor device according to the embodiment can be applied.

[0291] The display device 700 can also include various elements, such as liquid crystal Elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) transistors (transistors that emit light according to the current), electron emitters, electron insulators Electrophoretic element, Grating light valve (GLV), Plasma display (P Display elements using DP, MEMS (microelectromechanical systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter) ), MIRASOL (registered trademark), IMOD (Interference Modulation ) element, shutter type MEMS display element, optical interference type MEMS display element, elect Low-wetting element, piezoelectric ceramic display, display using carbon nanotubes In addition to these, it has at least one of an electric or magnetic function. The display medium may have a contrast, brightness, reflectance, transmittance, etc. that change depending on the display device. An example of a display device using an EL element is an EL display. An example of a display device using electrons is a field emission display (FED) or is a SED (Surface-conduction E) flat panel display. LCD displays include liquid crystal displays. An example of the device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display). LCD, reflective LCD, direct view LCD, projection LCD) An example of a display device using electronic ink or electrophoretic elements is electronic paper. In addition, when realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, In this case, a part or all of the pixel electrodes may function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM can be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0292] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying colors include R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a B pixel, and a W (white) pixel. Like the column, two colors of RGB make up one color element, and two different colors are created by the color element. Alternatively, you can select one or more colors such as yellow, cyan, magenta, etc. for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. The present invention can also be applied to display devices such as those shown in the accompanying drawings.

[0293] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) uses white light ( In order to display full color on the display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) Yellow (Y) and other colors can be used in combination as appropriate. The color reproducibility can be improved compared to when no color layer is used. By arranging a region having a colored layer and a region not having a colored layer, the region not having a colored layer can be The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30%. When using a device to display full color, R, G, B, Y, and white (W) are It is also possible to emit light from an element having a luminescent color. In some cases, power consumption can be reduced even further than when the

[0294] In this embodiment, a liquid crystal element and an EL element are used as display elements. 35 and 36. Note that FIG. 35 shows the area indicated by the dashed line QR in FIG. 36 is a cross-sectional view of the display device, which uses a liquid crystal element as the display element. 34 is a cross-sectional view taken along the dashed line QR, and shows a configuration in which an EL element is used as a display element. is.

[0295] First, the common parts shown in Figures 35 and 36 will be explained, and then the different parts will be explained. This will be explained below.

[0296] [Explanation of common parts of display devices] The display device 700 shown in FIGS. 35 and 36 includes a wiring portion 711, a pixel portion 702, and a , a source driver circuit section 704, and an FPC terminal section 708. The line portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and The capacitor 790 (the capacitor 790a or the capacitor 790b) is included. The driver circuit portion 704 includes a transistor 752 .

[0297] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752 source electrode and drain electrode, a conductive film formed in a different process, such as a gate The signal line 710 may be formed of a conductive film containing, for example, copper. When this material is used, there is little signal delay caused by wiring resistance, making it possible to display on a large screen. do.

[0298] The transistors 750 and 752 may be the transistors shown above. Here, transistor 750 and transistor 752 are the transistors shown in FIG. Although an example using the structure of transistor 100 is shown, other transistors shown above may also be used.

[0299] In addition, the transistors 750 and 752 may be, for example, transistors shown in FIG. In this case, the electrode 203b may be formed by, for example, the conductive layer 772 or The conductive layer 784 can be formed by the same process as that for forming the conductive layer 784. By using the structure of transistor 100, for example, transistors 750 and 75 2, the on-current can be increased, and the circuit operating speed can be increased. The channel width of the transistor 750 or the transistor 752 can be reduced in some cases, which improves circuit integration. It becomes possible.

[0300] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The transistor has a low current value in an off state (off-state current value). Therefore, the retention time of the electric signals such as the image signals can be extended, and the power supply When it is on, the write interval can be set longer. Therefore, the frequency of refresh operations can be reduced. This has the effect of reducing power consumption.

[0301] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section can be In other words, the driver transistor can be formed on the same substrate as a separate driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, high quality images can be provided.

[0302] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive layer 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminals of the PC 716 are electrically connected via the anisotropic conductive layer 780 .

[0303] The first substrate 701 and the second substrate 705 may be made of, for example, glass. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0304] By using a flexible substrate, a flexible display device can be manufactured. The display device is flexible, so it can be attached to curved or irregularly shaped surfaces. This makes it possible to realize a wide variety of uses.

[0305] For example, by using a flexible substrate such as a plastic substrate, the display device can be made thin. It is possible to make the substrate thin and lightweight. A display device using this material is less likely to break, and can improve durability against shocks when dropped, for example. Cut.

[0306] On the second substrate 705 side, there is a light-shielding film 738 that functions as a black matrix, A colored film 736 that functions as a color filter, a light-shielding film 738, and a film that contacts the colored film 736 An insulating film 734 is provided.

[0307] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled. It should be noted that a spherical spacer may be used as the structure 778. In the above, the structure 778 is provided on the second substrate 705 side. For example, as shown in FIG. 36, a structure 778 is provided on the first substrate 701 side. or a structure in which the structures 778 are provided on both the first substrate 701 and the second substrate 705. It may also be possible to use the following.

[0308] 35 and 36, on the transistor 750 and the transistor 752, Insulating films 764, 766, and 768 are provided.

[0309] The insulating films 764, 766, and 768 are the same as the insulating film 214 shown in the previous embodiment. , 216, 218 can be formed using the same materials and manufacturing methods.

[0310] [Configuration example of a display device using a liquid crystal element as a display element] The display device 700 shown in FIG. 35 includes a capacitor 790a. This structure has a dielectric between a pair of electrodes. The oxide semiconductor film serving as the semiconductor layer of the transistor 750 is formed by the same process as that of the oxide semiconductor film. The other electrode of the capacitor 790a is formed using an oxide semiconductor film having high conductivity. A conductive layer 772 electrically connected to the transistor 750 is used. An insulating film 768 is used as the dielectric sandwiched between the electrodes.

[0311] Here, a highly conductive oxide semiconductor serving as one of a pair of electrodes of the capacitor 790a The body membrane will be explained below.

[0312] [Highly conductive oxide semiconductor films] When hydrogen is added to an oxide semiconductor with oxygen vacancies, hydrogen enters the oxygen vacancy sites. A donor level is formed near the conduction band. As a result, the oxide semiconductor has high conductivity. The oxide semiconductor that has become a conductor can be called an oxide conductor. Oxide semiconductors have a large energy gap and therefore transmit visible light. On the other hand, an oxide conductor is an oxide semiconductor that has a donor level near the conduction band. Therefore, the influence of absorption due to the donor level is small, and the transparency to visible light is the same as that of an oxide semiconductor. It has photosensitivity.

[0313] Here, a film formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and In each of the films formed by oxide conductors (hereinafter referred to as oxide conductor films (OC)), The temperature dependence of resistivity will be explained.

[0314] The temperature dependence of resistivity in an oxide conductor film (OC) is The temperature dependence of resistivity is smaller than that of the oxide film at temperatures between 80K and 290K. The resistivity of the OC film changes by less than ±20%. The rate of change in resistivity at 50K or less is less than ±10%. It is a thin semiconductor, and it is assumed that the conduction band edge and the Fermi level coincide or nearly coincide. Therefore, the oxide conductor film can be used for one electrode of the capacitor 790a. Here, the oxide conductor film can be formed by forming silicon nitride on an In-M-Zn oxide, for example. It can be formed by the above.

[0315] 35 includes a liquid crystal element 775. The liquid crystal element 775 includes: The liquid crystal display device includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776. The conductive layer 774 is 35 is provided on the side of the electrode 705 and functions as a counter electrode. The orientation state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive layer 772 and the conductive layer 774. By doing so, the transmittance or non-transmittance of light is controlled, and an image can be displayed.

[0316] The conductive layer 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive layer 772 is connected to a conductive film that functions as a pixel electrode, a That is, it functions as one electrode of the display element.

[0317] The conductive layer 772 may be formed of, for example, indium tin oxide or indium containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium titanium oxide oxide, indium tin oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as doped indium tin oxide can be used.

[0318] Although not shown in FIG. 35, the conductive layers 772 and 774 are in contact with the liquid crystal layer 776. Although not shown in FIG. Optical members (optical substrates) such as optical members, phase difference members, and anti-reflection members may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Critters, sidelights, etc. may also be used.

[0319] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0320] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in a liquid crystal layer. It has a short response time, is optically isotropic so alignment treatment is not required, and has little viewing angle dependency. In addition, since there is no need to provide an alignment film, rubbing treatment is also unnecessary. Therefore, it is possible to prevent electrostatic breakdown caused by the electrostatic discharge, and to prevent defects in the liquid crystal display device during the manufacturing process. Damage can be reduced.

[0321] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero) lectric Liquid Crystal) mode, AFLC (AntiFerr It can be used in dielectric liquid crystal mode. .

[0322] Furthermore, normally black type liquid crystal display devices, such as those employing vertical alignment (VA) mode, The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode Mode, ASV mode, etc. can be used.

[0323] [Display device using light-emitting elements as display elements] The display device 700 shown in FIG. 36 includes a capacitor 790b. This structure has a dielectric between a pair of electrodes. The conductive film is formed in the same process as the conductive film that functions as the gate electrode of the transistor 750. The other electrode of the capacitor 790b is a conductive film formed of a A conductive film is used to function as a drain electrode or a gate electrode. As the dielectric, an insulating film that functions as a gate insulating film of the transistor 750 is used.

[0324] In addition, in FIG. 36, a planarization insulating film 770 is provided on the insulating film 768 .

[0325] The planarization insulating film 770 may be made of a polyimide resin, an acrylic resin, or a polyimide amide resin. Heat-resistant organic materials such as benzocyclobutene resin, polyamide resin, and epoxy resin It should be noted that by stacking multiple insulating films made of these materials, 35, a planarization insulating film 770 may be formed. A configuration without setting 0 is also possible.

[0326] 36 also includes a light-emitting element 782. The light-emitting element 782 includes: The display device 700 shown in FIG. 36 includes a conductive layer 784, an EL layer 786, and a conductive layer 788. The EL layer 786 of the light emitting element 782 emits light, thereby displaying an image. can be done.

[0327] The conductive layer 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive layer 784 is connected to a conductive film that functions as a pixel electrode. The conductive layer 784 functions as an electrode, that is, one electrode of the display element. In this case, a conductive film that is light-transmitting or a conductive film that is reflective to visible light can be used. Examples of conductive films that are transparent to visible light include indium (In) and zinc (Zn). It is recommended to use a material containing one of the following elements: (Zn) and tin (Sn). As the reflective conductive film, for example, a material containing aluminum or silver is preferably used. stomach.

[0328] 36, an insulating film is formed on the planarization insulating film 770 and the conductive layer 784. An insulating film 730 is provided. The insulating film 730 covers part of the conductive layer 784. 782 is a top-emission structure. Therefore, the conductive layer 788 is transparent, and E It transmits light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified below, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive layer 784 and the conductive layer 788; It can also be applied to al-emission structures.

[0329] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position where the light-shielding film 738 is to be drawn, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is exemplified. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0330] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0331] (Embodiment 5) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0332] The display device shown in FIG. 26(A) has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504), and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided in the configuration. That's fine.

[0333] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0334] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0335] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a may also provide other signals.

[0336] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0337] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0338] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0339] The protection circuit 506 shown in FIG. 26(A) is, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be formed by wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to a power supply and a line from an external circuit to the display device. This refers to the part where terminals for inputting control signals and image signals are provided.

[0340] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 This is a circuit that brings one wire into electrical continuity with another wire.

[0341] As shown in FIG. 26A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 50. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrents caused by electrostatic discharges and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a configuration in which the protection circuit 506 is connected to the source driver 504b Alternatively, a configuration in which a protection circuit 506 is connected to the terminal portion 507 may be used. It can also be done as follows.

[0342] In FIG. 26(A), the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a separately prepared source driver circuit is formed. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is implemented. It may also be configured to be equipped with

[0343] Furthermore, the plurality of pixel circuits 501 shown in FIG. 26(A) may be, for example, a configuration shown in FIG. 26(B). It can be said that:

[0344] The pixel circuit 501 shown in FIG. 26B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. can be applied.

[0345] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0346] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mode) Micro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal id Crystal) mode, AFLC (AntiFerroelectric Li Quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carrier Board) or the like. Ally Controlled Birefringence mode, PDLC (P Polymer Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of materials can be used.

[0347] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is connected to a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the electrodes of the scan line G. L_m. The transistor 550 can be turned on or off. This provides a function of controlling the writing of data signals.

[0348] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0349] For example, in a display device having the pixel circuit 501 of FIG. 26(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 550 is turned on and data of the data signal is written.

[0350] The pixel circuit 501 in which data has been written is turned off by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0351] Furthermore, the plurality of pixel circuits 501 shown in FIG. 26(A) may be, for example, a configuration shown in FIG. 26(C). It can be said that:

[0352] The pixel circuit 501 shown in FIG. 26C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either one or both of the above. .

[0353] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 55 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0354] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0355] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0356] The capacitor 562 functions as a storage capacitor for holding written data.

[0357] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0358] One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0359] The light emitting element 572 may be, for example, an organic electroluminescence element (also known as an organic EL element). However, the light emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0360] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0361] In a display device having the pixel circuit 501 of FIG. 26(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0362] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0363] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0364] (Sixth embodiment) An example of a semiconductor device including an oxide semiconductor according to one embodiment of the present invention will be described below.

[0365] [Example of semiconductor device] FIG. 37A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device includes a transistor 100, a transistor 130, a capacitor element 150, and an array. The wiring WBL, the wiring RBL, the wiring WL, the wiring CL, the wiring BG, and the wiring SL. do.

[0366] One of the source and the drain of the transistor 130 is electrically connected to the wiring RBL. The other end is electrically connected to the wiring SL, and the gate is the source or drain of the transistor 100. One electrode of the transistor 100 is electrically connected to one electrode of the capacitor 150. The other of the source and drain is electrically connected to the wiring WBL, and the first gate is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. The line BG is electrically connected to the second gate of the transistor 100. 30, one of the source and drain of the transistor 100, and the capacitance element 150 The node between the electrodes on one side is called node FN.

[0367] In the semiconductor device shown in FIG. 37A, when the transistor 100 is in a conductive state (on state), A potential corresponding to the potential of the wiring WBL is applied to the node FN. When in a conductive state (off state), the potential of the node FN is maintained. The semiconductor device shown in Figure 37A functions as a memory cell of a memory device. By arranging the semiconductor devices shown in (A) in a matrix, a memory device (memory cell array) ) can be constructed.

[0368] In addition, the liquid crystal element and organic EL (Electroluminescent) element electrically connected to the node FN When a display element such as a luminescence element is included, the semiconductor device of FIG. It can also function as a pixel in the image sensor.

[0369] The conductive state or non-conductive state of the transistor 100 is selected by applying a signal to the wiring WL or the wiring BG. It can be controlled by the potential applied to the wiring WL or the wiring BG. The threshold voltage of the transistor 100 can be controlled by the By using a transistor with a small current, the potential of the node FN in the non-conducting state Therefore, the refresh frequency of the semiconductor device can be reduced. This allows for a reduction in the power consumption of the semiconductor device. For example, a transistor including an oxide semiconductor film is used as the transistor 100. A transistor with a small current can be realized.

[0370] The wiring CL is supplied with a constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential. At this time, the apparent threshold voltage of the transistor 100 is The apparent threshold voltage fluctuation causes the conduction state of transistor 130 to change. By utilizing the change in the non-conducting state, the potential information held in the node FN is used as data. can be read out.

[0371] The potential held at node FN is 3.15×10 for 10 years at 85°C. 8 seconds) To maintain the capacitance, the off-state current per 1 fF and the channel width of the transistor per 1 μm must be The current value is 4.3 yA (1 yA is 10 -24 A) is preferably less than At this time, it is preferable that the allowable fluctuation in the potential of the node FN is within 0.5 V. Alternatively, the off-state current at 95°C is preferably less than 1.5 yA.

[0372] In addition, by increasing the capacitance, the potential at the node FN can be maintained for a longer period of time. In other words, the retention time can be extended.

[0373] In the semiconductor device shown in FIG. 37A, the potential of the gate electrode of the transistor 130 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0374] The writing and holding of data will be described. First, the potential of the wiring WL is set to the value of 0.001V. 00 is set to a potential at which the transistor 100 is turned on, thereby turning on the transistor 100. The potential of the wiring WBL is applied to the gate electrode of the transistor 130 and the capacitor 150. That is, a predetermined charge is applied to the gate electrode of the transistor 130 (write Here, we consider charges that give two different potential levels (hereinafter, low-level charge and high-level charge). Then, the potential of the wiring WL is set to The transistor 100 is turned off by applying a potential that turns the transistor 100 off. As a result, the charge applied to the gate electrode of the transistor 130 is retained (retained).

[0375] Since the off-state current of the transistor 100 is extremely small, the gate electrode of the transistor 130 The charge is retained for a long time.

[0376] Next, the reading of information will be explained. When a predetermined potential (constant potential) is applied to the wiring RBL, In this state, when an appropriate potential (read potential) is applied to the wiring CL, the gate of the transistor 130 The wiring SL takes on different potentials depending on the amount of charge held in the electrode. If 130 is an n-channel type, a high level charge is applied to the gate electrode of the transistor 130. The apparent threshold V given th_H is the gate voltage of transistor 130. Apparent threshold voltage V when a low-level charge is applied to the pole th_L become lower Here, the apparent threshold voltage is the voltage at which the transistor 130 is in the "on state." Therefore, the potential of the wiring CL is V t h_H and V th_L By setting the potential V0 between For example, when writing, if a high level charge is applied, If the potential of the wiring CL is V0 (> V th_H ), then transistor 1 When a low level charge is applied, the voltage of the wiring CL The digit is V0( <V th_L ), transistor 130 remains in the "off state" Therefore, by determining the potential of the wiring SL, the stored data can be read out. In order to reduce the number of wirings, for example, the WBL and RBL shown in Figure 37(A) can be connected It is also acceptable to do so.

[0377] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 130 is in the "off state" regardless of V th_H Alternatively, a smaller potential may be applied to the wiring CL. The potential at which the transistor 130 is in the "ON state," i.e., V th_L A larger potential It is sufficient to provide it to the wiring CL.

[0378] The semiconductor device shown in FIG. 37B differs from the semiconductor device shown in FIG. 37 mainly in that the transistor 130 is not provided. This is different from (A). In this case, the same operations as above are performed to write and store information. is possible.

[0379] Next, the reading of information will be described. When the transistor 100 is turned on, The wiring BL in the free state and the capacitance element 150 are electrically connected, and a current flows between the wiring BL and the capacitance element 150. The charge is redistributed. As a result, the potential of the wiring BL changes. The amount of change in the potential of the wiring BL is The potential of one electrode of the capacitor 150 (or the charge stored in the capacitor 150) and take different values.

[0380] For example, the potential of one electrode of the capacitor 150 is V, the capacitance of the capacitor 150 is C, and the potential of the wiring B is If the capacitance component of L is CB and the potential of the wiring BL before the charge is redistributed is VB0, then The potential of the wiring BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C) Therefore, the state of the memory cell is such that the potential of one electrode of the capacitance element 150 is V1 If there are two states, V0 and V1 (V1>V0), the wiring BL when the potential V1 is maintained is The potential (=(CB×VB0+C×V1) / (CB+C)) is When the potential of the wiring BL is higher than the potential of the wiring BL (=(CB×VB0+C×V0) / (CB+C)), It can be seen that...

[0381] Then, by comparing the potential of the wiring BL with a predetermined potential, data can be read out. .

[0382] The semiconductor device shown in FIG. 37(A) and FIG. 37(B) is used as a memory device for a CPU, for example. It is also possible to do so.

[0383] FIG. 38 shows an example of a cross-sectional structure of a semiconductor device that can realize the circuit shown in FIG. 37(A). In addition, in Figure 38, an example is shown in which WBL and RBL are made conductive to reduce the number of wirings. 38(B) is a plane that passes through the dashed line AB shown in FIG. 38(A) and is perpendicular to FIG. 38(A). 38(C) shows a cross section of the semiconductor device shown in FIG. 38(A) passing through the dashed line CD. 8(A) and a cross section perpendicular to the plane.

[0384] Preferably, transistor 100 is located above transistor 130. By stacking the transistor 100 and the transistor 130, for example, the circuit area can be reduced. The transistor 100 can be, for example, the transistor described in Embodiment 3. FIG. 38 shows an example in which the transistor 100 shown in FIG. .

[0385] The transistor 130 is made of a first semiconductor material. 00 is composed of a first semiconductor material or a second semiconductor material Examples of semiconductors that can be used as materials include silicon, germanium, and gallium. semiconductor materials such as silicon, germanium, gallium, arsenic, and aluminum; Examples of the semiconductor material include a compound semiconductor material, an organic semiconductor material, and an oxide semiconductor material having the following formula: .

[0386] The first and second semiconductor materials may be the same material, but may also be different semiconductors. It is more preferable to use single crystal silicon as the first semiconductor material. The case where an oxide semiconductor is used as the second semiconductor material will be described.

[0387] [First Transistor] The transistor 130 is provided on a semiconductor substrate 131 and is made up of a part of the semiconductor substrate 131. The semiconductor layer 132, the gate insulating film 134, the gate electrode 135, and the source region or drain region are The insulating film 133 includes a low resistance layer 133a and a low resistance layer 133b which function as an in-region.

[0388] The transistor 130 may be either a p-channel type or an n-channel type, depending on the circuit configuration and An appropriate transistor may be used depending on the driving method.

[0389] The region where the channel of the semiconductor layer 132 is formed and the region nearby, the source region or the drain region In the low resistance layer 133a and the low resistance layer 133b which become the drain region, a silicon-based semiconductor It is preferable that the semiconductor material contains a semiconductor such as silicon dioxide, and it is preferable that the semiconductor material contains single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). The structure may be made of strained silicon, or GaAs and GaAlAs, etc. By using the above, the transistor 130 is a HEMT (High Electron Mob It may also be called a "ability transistor."

[0390] The transistor 130 has an LDD (Lightly Doped Drain) region. The area may have two regions, region 176a and region 176b.

[0391] The low resistance layer 133a and the low resistance layer 133b are made of a semiconductor material applied to the semiconductor layer 132. In addition, elements that impart n-type conductivity, such as phosphorus, or p-type conductivity, such as boron, are added. Contains elements that

[0392] The gate electrode 135 is made of an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron. Semiconductor materials such as silicon containing elements that impart electrical conductivity, metal materials, alloy materials, or A conductive material such as a metal oxide material can be used.

[0393] Here, instead of the transistor 130, a transistor as shown in FIG. 29(A) and FIG. 29(B) is used. 29(A) is a circuit diagram showing a circuit diagram of a semiconductor device according to the present invention. 29(A) shows a cross section of a plane perpendicular to that of FIG. 29(A). The semiconductor layer 132 (part of the semiconductor substrate) has a convex shape, and the gate is formed along the side and top surfaces of the convex shape. A gate insulating film 134 and a gate electrode 135 are provided between the transistors. An isolation layer 181 is provided. Such a transistor 190 utilizes the protruding portion of the semiconductor substrate. It is also called a FIN type transistor because it uses a The insulating film may function as a mask for forming the semiconductor portion. Although the case where a protrusion is formed by processing a part of the conductor substrate has been shown, the case of SOI (Silicon on Insulator) A semiconductor layer having a convex shape may be formed by processing a n-insulator substrate.

[0394] The transistor 130 is covered with an insulating film 136, an insulating film 137, and an insulating film 138 in this order. They are provided in a stacked manner.

[0395] The insulating film 136 is formed by insulating the low resistance layer 133a and the low resistance layer 133b during the manufacturing process of the semiconductor device. The insulating film 13 functions as a protective film when activating the conductive element added to b. 6 may not be provided if not required.

[0396] When the semiconductor layer 132 is made of a silicon-based semiconductor material, the insulating film 137 is made of an insulating material containing hydrogen. By performing heat treatment, hydrogen in the insulating film 137 is oxidized to the semiconductor layer 132, thereby terminating the dangling bonds in the transistor 130 and improving the reliability of the transistor 130. This can be done.

[0397] The insulating film 138 smooths out any steps caused by the transistor 130 and other components disposed below it. The upper surface of the insulating film 138 can be planarized by a CMP method or the like. good.

[0398] In addition, the insulating film 136, the insulating film 137, and the insulating film 138 are formed with the low resistance layer 133a and the low resistance layer 133b. 33b, etc., and a plug 140 electrically connecting the gate electrode 135 of the transistor 130 and A plug 139 or the like may be embedded to provide an electrical connection.

[0399] A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film 111 prevents water and hydrogen from diffusing from the lower layer to the upper layer. It is a layer having a function. In addition, it is preferable that the barrier film 111 has low oxygen permeability. The term "diffusiveness of water and hydrogen" refers to the silicon oxide film, which is generally used as an insulating film. This indicates that the permeability of water and hydrogen is low compared to other materials. Also, low oxygen permeability means For example, compared to silicon oxide, which is generally used as an insulating film, it has low oxygen permeability. This indicates that

[0400] Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, and the like. Titanium, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), steel titanate The so-called h, such as rontium (SrTiO3) or (Ba,Sr)TiO3 (BST) Insulating films containing igh-k materials can be used as a single layer or a laminate. The coating may be made of, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, or the like. Silicon, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, gas oxide Alternatively, these insulating films may be nitrided to form oxynitride films. The insulating film is laminated with silicon oxide, silicon oxynitride, or silicon nitride. In particular, aluminum oxide is more preferable because it has excellent barrier properties against water and hydrogen. I wish.

[0401] Furthermore, the above-mentioned materials are excellent barriers to oxygen as well as hydrogen and water. When the insulating film 114 is heated, oxygen is released and diffuses to a layer below the barrier film 111. As a result, the electrons emitted from the insulating film 114 and This increases the amount of oxygen that can be supplied to the semiconductor layer.

[0402] Here, in the layer below the barrier film 111, hydrogen, water, etc. are reduced by, for example, heat treatment. The heat treatment conditions are, for example, in an inert gas atmosphere or a reduced pressure atmosphere. The minimum temperature is 170°C or higher.

[0403] In addition, when single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment The principle is to terminate the unpaired bonds (also called dangling bonds) of silicon with hydrogen. This process can also serve as a treatment (also called hydrogenation treatment).

[0404] A conductive layer 151, a conductive layer 152a, and a conductive layer 152b are provided so as to sandwich the barrier film 111. The conductive layer 151 is a conductive layer of the transistor 100. It is electrically connected to 104a.

[0405] An insulating film is formed by covering the barrier film 111, the conductive layer 152a, the conductive layer 152b, the conductive layer 105, etc. The insulating film 114 is provided as shown in FIG. Refer to.

[0406] [Second Transistor] The transistor 100 is provided on the insulating film 114. In the example shown in FIG. The transistor 100 is the transistor shown in FIG.

[0407] 38. The transistor 100 shown in FIG. 38 has a conductive layer 1 functioning as a second gate electrode. The conductive layer 105 includes a conductive layer 152a and a conductive layer 152b that form a part of the capacitive element 150. By forming these conductive layers simultaneously, e.g. For example, the process can be simplified.

[0408] The transistor 100 is covered with insulating films 112, 113, and 116. It is provided.

[0409] As with the barrier film 111, the insulating film 112 is preferably made of a material that is difficult for water and hydrogen to diffuse into. It is particularly preferable to use a material that is difficult for oxygen to permeate.

[0410] The insulating film 112 may have a stacked structure of two or more layers. It is preferable that the upper layer of the 112 is made of a material that is difficult for water and hydrogen to diffuse into. The lower layer may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride The insulating film provided in the lower layer may be formed by heating, similar to the insulating film 114. The gate insulating film 102 acts as an insulating film from which oxygen is released, and the semiconductor layer 101 is also exposed from above. Oxygen may also be supplied.

[0411] By covering the semiconductor layer 101 with the insulating film 112, the semiconductor layer 101 is Furthermore, oxygen can be prevented from being released upward from the insulating film 114 and the like. The oxygen supplied to the semiconductor layer 101 can be trapped below the insulating film 112. The amount of oxygen that can be supplied can be increased.

[0412] In addition, the insulating film 112 prevents water and hydrogen from entering the oxide semiconductor from the outside. This makes it possible to suppress the fluctuation of electrical characteristics and realize a highly reliable transistor. It can be realized.

[0413] The insulating film 113 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, nitride Aluminum or the like may be used, and the layer may be a laminated layer or a single layer.

[0414] The insulating film 116 covering the transistor 100 serves as a planarizing layer that covers the uneven shape of the underlying layer. The insulating film 113 also functions as a protective film when the insulating film 116 is formed. The insulating film 113 may not be provided if it is not necessary. Examples include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide. Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. may be used. It is provided as a laminated or single layer.

[0415] The insulating film 112, the insulating film 113, and the insulating film 116 are provided with a conductive layer 104b. Plugs 321, 322, and 123 are embedded.

[0416] On the insulating film 116, wiring 124 and the like are provided to electrically connect to the plug 322. There are.

[0417] 38, a material similar to that of the barrier film 111 is formed on the insulating film 136 containing hydrogen. In this case, the insulating film 137 containing hydrogen may be provided. Therefore, the water and hydrogen remaining in the insulating film 136 can be effectively prevented from diffusing upward. Cut.

[0418] Wirings such as wiring 124 and wiring 166, conductive layer 143, conductive layer 151, conductive layer 152a, The conductive layers, such as the conductive layer 152b and the conductive layer 251, and the plugs 123, 139, and 139 are The plugs such as 40, plug 164, and plug 165 are made of metal materials, alloy materials, or In particular, conductive materials such as metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. It is preferable to use stainless steel. In addition, materials such as titanium nitride and titanium can be stacked with other materials. It may also be used in layers.

[0419] [Example of manufacturing method] Next, an example of a manufacturing method of the semiconductor device in FIG. 38 will be described with reference to FIGS. 39 to 42. do.

[0420] First, a semiconductor substrate 131 is prepared. The semiconductor substrate 131 is, for example, single crystal silicon. Substrates (including p-type semiconductor substrates or n-type semiconductor substrates), silicon carbide and gallium nitride A compound semiconductor substrate made of a silicon dioxide film or the like can be used as the semiconductor substrate 131. In the following, single crystal silicon is used as the semiconductor substrate 131. This section explains what happens when:

[0421] Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer is formed by LOC. OS (Local Oxidation of Silicon) method or STI (Sh If the trench isolation method or mesa isolation method is used, good.

[0422] When forming p-type and n-type transistors on the same substrate, the semiconductor substrate 1 An n-well or p-well may be formed in a part of the n-type semiconductor substrate 13. 1 is doped with impurity elements such as boron to give it p-type conductivity, forming a p-well. An n-type transistor and a p-type transistor may be formed on the substrate.

[0423] Next, an insulating film that will become the gate insulating film 134 is formed on the semiconductor substrate 131. For example, The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, the surface of the semiconductor substrate 131 is oxidized by a thermal oxidation method. After forming the silicon oxide film, a nitriding treatment is performed to nitride the surface of the silicon oxide film. By this, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed. Alternatively, silicon oxide, silicon oxynitride, or high-dielectric-constant materials (also known as high-k materials) Tantalum oxide, hafnium oxide, hafnium silicate, zirconium oxide, Metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide Other materials may also be used.

[0424] The insulating film is formed by sputtering, CVD (Chemical Vapor Deposition), sition) method (thermal CVD method, MOCVD (Metal Organic CVD) method , PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo lecular beam epitaxy) method, ALD (Atomic Layer Deposition) method, or PLD (Pulsed Laser Deposit) Alternatively, the film may be formed by a film formation method such as an ion method.

[0425] Subsequently, a conductive film is formed to become the gate electrode 135. The conductive film is made of tantalum, tantalum, or the like. a metal selected from the group consisting of tin, titanium, molybdenum, chromium, niobium, etc., or It is preferable to use an alloy material or a compound material whose main component is a metal. In addition, the metal nitride film and the above-mentioned polycrystalline silicon film can be used. A laminated structure of metal films may be used. Examples of metal nitrides include tungsten nitride and molybdenum nitride. By providing a metal nitride film, the density of the metal film can be improved. This can improve adhesion and prevent peeling.

[0426] Conductive films are formed by sputtering, evaporation, CVD (thermal CVD, MOCVD, PEC It is possible to form films by methods such as VD (including VD method). It also reduces damage caused by plasma. For this purpose, thermal CVD, MOCVD or ALD is preferred.

[0427] Subsequently, a resist mask is formed on the conductive film by lithography or the like. The unnecessary part of the film is removed. Then, the resist mask is removed to reveal the gate electrode. 135 can be formed.

[0428] Here, we will explain the processing method of the film to be processed. For example, a resist mask formed by photolithography or the like can be used. Alternatively, a method of forming a dummy electrode by photolithography or the like may be used. A pattern is formed, a sidewall is formed on the dummy pattern, and then the dummy pattern The remaining sidewall is used as a resist mask to etch the film to be processed. In addition, in order to achieve a high aspect ratio when etching the film to be processed, It is preferable to use anisotropic dry etching. A hard mask may also be used.

[0429] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6nm), H-line (wavelength 405nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Alternatively, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultraviolet) or X-rays may also be used. Instead of light used for exposure, electron beams can also be used. The use of an electron beam is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0430] In addition, before forming the resist film that will become the resist mask, the film to be processed and the resist film are closely An organic resin film having a function of improving adhesion may be formed. By using a pin coating method or the like, the step of the lower layer is covered and the surface is flattened. This makes it possible to reduce variations in the thickness of the resist mask provided on the organic resin film. In particular, when fine processing is performed, the organic resin film is required to have a high resistance to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0431] Hereafter, the description of processing using a resist mask will be given for the gate electrode 135, for example. In addition, in this specification, the etching of the film to be processed is performed. The description of the subsequent removal of the resist may be omitted.

[0432] After the gate electrode 135 is formed, a sidewall is formed to cover the side surface of the gate electrode 135. The sidewall may be formed by depositing an insulating film thicker than the gate electrode 135, and then Anisotropic etching is performed to leave the insulating film only on the side of the gate electrode 135. It can be formed by:

[0433] FIG. 39 shows an example in which the gate insulating film is not etched when the sidewall is formed. However, when the sidewall is formed, the insulating film that will become the gate insulating film 134 is also etched at the same time. In this case, the gate insulating film 134 is formed on the lower part of the gate electrode 135 and the sidewall. is formed.

[0434] Next, the gate electrode 135 (and sidewalls) of the semiconductor substrate 131 is provided. In the region where there is no conductivity, elements such as phosphorus that give n-type conductivity or boron that give p-type conductivity are added. The element to be added is added. The cross-sectional view at this stage is shown in Figure 39(A).

[0435] Subsequently, after forming the insulating film 136, for example, the activation of the element that gives the conductivity is performed. The heat treatment is carried out in an inert gas atmosphere such as a rare gas or nitrogen gas, or The heating can be carried out in a reduced pressure atmosphere at a temperature of, for example, 400° C. or higher and lower than the strain point of the substrate.

[0436] The insulating film 136 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon nitride. Silicon, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride The insulating film 136 may be formed by a sputtering method. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, the insulating film can be formed by a PLD method or the like. In particular, the insulating film can be formed by a CVD method, preferably a Alternatively, it is preferable to form the film by plasma CVD, since this can improve the coating property. In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or A The LD method is preferred.

[0437] At this stage, the transistor 130 is formed. The third transistor 160 may be formed in a similar manner.

[0438] Subsequently, an insulating film 137 and an insulating film 138 are formed.

[0439] The insulating film 137 may be made of a material that can be used for the insulating film 136, as well as a nitrogen containing oxygen and hydrogen. Silicon nitride (SiNOH) may be used. In addition to materials that can be used, TEOS (Tetra-Ethyl-Ortho-Silicon A step formed by reacting silane or silane with oxygen or nitrous oxide. It is preferable to use silicon oxide, which has good coating properties.

[0440] The insulating film 137 and the insulating film 138 are formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD, PECVD, etc.), MBE, ALD, or PLD methods are used. In particular, the insulating film can be formed by a CVD method, preferably a plasma CVD method. Therefore, forming a film is preferable because it can improve the coverage. To reduce damage, thermal CVD, MOCVD, or ALD is preferred.

[0441] Next, the upper surface of the insulating film 138 is planarized by using a CMP method or the like. In this case, it is not necessary to perform planarization by CMP or the like. The planarization film can be formed by, for example, atmospheric pressure CVD or coating. Examples of films that can be formed using the VD method include BPSG (Boron Phosphorus Glycol), Also, it can be formed using a coating method. Examples of films that can be used include HSQ (hydrogen silsesquioxane). In order to terminate the dangling bonds in the insulating layer 132 with hydrogen desorbed from the insulating film 137, For this purpose, a heat treatment may be carried out.

[0442] Subsequently, the low resistance layer 133a and the low resistance layer 133b are formed on the insulating film 136, the insulating film 137, and the insulating film 138. An opening is formed that reaches the layer 133b and the gate electrode 135 (see FIG. 39(B)). After that, a conductive film is formed to fill the opening (see FIG. 39(C)). The conductive film is planarized so that the upper surfaces of the plugs 139 and plugs 140 are exposed. The conductive film is formed by, for example, sputtering. , CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method Alternatively, it can be formed by using a PLD method or the like.

[0443] Subsequently, an insulating film 215 is formed on the insulating film 138. The insulating film 215 is formed on the insulating film 136, etc. After the insulating film 215 is formed, the insulating film 215 is subjected to a heat treatment. The theory may also be carried out.

[0444] The third heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. The conditions described for the heat treatment in 1 can be used.

[0445] Next, an opening is formed in the insulating film 215. After that, a conductive film is formed so as to fill the opening. The conductive film is subjected to a planarization treatment so that the upper surface of the insulating film 215 is exposed. The conductive layer 251, the conductive layer 143, the conductive layer 151, and the like are formed (see FIG. 39(E)). When forming a conductive film, for example, a material such as titanium nitride or titanium is formed in the opening. After that, other conductive materials may be laminated. For example, titanium nitride or titanium may be used as the lower layer of the laminated film. This can improve adhesion to the opening.

[0446] Next, a barrier film 111 is formed and an opening is formed (see FIG. 40(A)). 111 is, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, PECVD method) The layer can be formed by using a method such as MBE, ALD, or PLD. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, the coating property is improved. In addition, to reduce damage caused by plasma, The CVD method, the MOCVD method or the ALD method is preferred.

[0447] Subsequently, a conductive film to be the conductive layer 105, the conductive layer 152a, and the conductive layer 152b is formed. Thereafter, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like. (See Figure 40(B)).

[0448] Next, the insulating film 114 is formed. The insulating film 114 is formed by, for example, a sputtering method or a CVD method. (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PL In particular, the insulating film can be formed by a CVD method, preferably a Plasma method. The deposition by the Zuma CVD method is preferable because it can improve the coating properties. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD are preferred. I wish.

[0449] In order to make the insulating film 114 contain excess oxygen, for example, the insulating film 11 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to make it contain excess oxygen. Alternatively, a region having the above structure may be formed, or both methods may be combined.

[0450] For example, the insulating film 114 after deposition may contain oxygen (at least oxygen radicals, oxygen atoms, and oxygen ions). The oxygen-introducing method includes introducing oxygen into the silicon dioxide gas to form a region containing excess oxygen. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0451] The oxygen introduction treatment can be performed using a gas containing oxygen. For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, when a mixed gas of carbon dioxide, hydrogen, and argon is used, good.

[0452] After forming the insulating film 114, the CMP method or the like is used to improve the flatness of the upper surface. A flattening process may also be performed.

[0453] Next, a semiconductor film that will become the insulator layer 101a and a semiconductor film that will become the semiconductor layer 101b are formed in this order. The semiconductor film is continuously formed without being exposed to the atmosphere (see FIG. 40(C)). It is preferable that the semiconductor that will become the insulator layer 101a and the semiconductor that will become the semiconductor layer 101b are The body is formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Just film it.

[0454] The semiconductors to be used for the insulator layer 101a and the semiconductor layer 101b are I When forming an n-Ga-Zn oxide layer by MOCVD, trimethylsilane is used as the source gas. Indium, trimethylgallium, dimethylzinc, etc. may be used. The combination of the gases is not limited to the above, and triethylindium may be used instead of trimethylindium. Alternatively, triethylgallium may be used instead of trimethylgallium. Dimethyl zinc may be replaced by diethyl zinc or the like.

[0455] Here, after the insulating layer 101a is formed, oxygen may be introduced into the insulating layer 101a. For example, the insulating layer 101a after deposition contains oxygen (at least oxygen radicals, oxygen atoms, oxygen ions) to form a region containing excess oxygen. The methods include ion implantation, ion doping, and plasma immersion ion implantation. , plasma treatment, etc. can be used.

[0456] The oxygen introduction treatment can be performed using a gas containing oxygen. For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, when a mixed gas of carbon dioxide, hydrogen, and argon is used, good.

[0457] After the insulating layer 101a and the semiconductor layer 101b are formed, heat treatment may be performed. is inactive at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The treatment may be carried out in a gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. In addition, the heat treatment was carried out in an inert gas atmosphere, and then the desorbed oxygen was replaced with oxygen. For this purpose, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more. This may be done immediately after the semiconductor film is formed, or by processing the semiconductor film to form island-shaped insulating layers 101a and 101b. The heat treatment may be performed after the insulating film 114 or the oxide film is formed. Oxygen is supplied, and oxygen vacancies in the semiconductor film can be reduced.

[0458] Then, using a resist mask, the island-shaped insulating layer 101a and the island-shaped semiconductor layer 101b are (See FIG. 40(D)). A part of the film 114 is etched and covered with the insulating layer 101a and the semiconductor layer 101b. Therefore, the insulating film 114 may become thinner in the area where the insulating film 114 is not present. It is preferable to form the insulating film 114 thick in advance so that it does not disappear.

[0459] Depending on the etching conditions of the semiconductor film, the resist may disappear during the etching process. Therefore, it is recommended to use a material that is highly resistant to etching, such as an inorganic or metal film. Here, a conductive film is used as the hard mask 281. FIG. 41(A) shows an example in which a semiconductor film is processed using a hard mask 281, and an insulating film is formed. Here, an example of forming a layer 101a and a semiconductor layer 101b is shown. If a material that can be used for the conductive layer 104a and the conductive layer 104b is used, a hard The mask 281 can be processed to form the conductive layer 104a and the conductive layer 104b. By using such a method, for example, a transistor 100 shown in FIG. can be done.

[0460] After forming the structure shown in FIG. 40(D), the conductive layer 151, the conductive layer 251, etc. are formed on the insulating film 114. Then, an opening is formed in the insulating film 114 so as to reach the insulating film 114 (see FIG. 41(B)). Conductive films that will become the conductive layers 104a, 104b, etc. are formed so as to fill the conductive layers 104a, 104b, etc. The conductive film that becomes the conductive layer 104a, the conductive layer 104b, etc. can be formed by, for example, a sputtering method, a CVD method ( Thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PLD In particular, the insulating film can be formed by a CVD method, preferably a plasma Forming the film by the micro-CVD method is preferable because it can improve the coating properties. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD are preferred. It's nice.

[0461] Next, a resist mask is used to remove impurities from the conductive film that will become the conductive layers 104a, 104b, and the like. Necessary portions are removed by etching to form conductive layers 104a and 104b etc. 41(C). Here, when the conductive film is etched, the semiconductor layer 101b and the insulating film 1 A part of the upper part of 14 is etched away, and the part that does not overlap with the conductive layer 104a and the conductive layer 104b is left. Therefore, the thickness of the semiconductor film or the like that becomes the semiconductor layer 101b may be reduced. It is preferable to form the film thick in advance in consideration of the depth to be etched.

[0462] Next, the insulating layer 101c and the gate insulating film 102 are formed. Then, the gate electrode 103 is formed by etching (see FIG. 42(A)). A conductive film is formed on the gate electrode 103 by processing the conductive film using a resist mask. (See Figure 42(B)).

[0463] Regarding the method for forming the insulating layer 101c, for example, see the method for forming the insulating layer 101a. good.

[0464] Alternatively, oxygen may be introduced into the insulating layer 101c after the insulating layer 101c is formed. For example, the insulating layer 101c after deposition may contain oxygen (at least oxygen radicals, oxygen atoms, and oxygen ions). The oxygen-introducing method includes introducing oxygen into the silicon dioxide gas to form a region containing excess oxygen. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0465] The oxygen introduction treatment can be performed using a gas containing oxygen. For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen introduction process, a rare gas may be contained in the oxygen-containing gas. For example, when a mixed gas of carbon dioxide, hydrogen, and argon is used, good.

[0466] At this stage, transistor 100 is formed.

[0467] Next, the insulating film 112 is formed. The insulating film 112 is formed by, for example, a sputtering method or a CVD method. (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PL In particular, the insulating film can be formed by a CVD method, preferably a Plasma method. The deposition by the Zuma CVD method is preferable because it can improve the coating properties. To reduce damage caused by plasma, thermal CVD, MOCVD, or ALD are preferred. I wish.

[0468] After the insulating film 112 is formed, heat treatment may be performed. Therefore, oxygen is supplied to the semiconductor layer 101, and oxygen vacancies in the semiconductor layer 101 can be reduced. can.

[0469] The insulating film 112 may have a stacked structure of two or more layers.

[0470] Subsequently, the insulating film 113 is formed. The insulating film 113 is formed by, for example, a sputtering method or a CVD method. method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or P It can be formed by using the LD method, etc. In particular, the CVD method, preferably the plasma CVD method. It is preferable to form the film by this method because it is possible to obtain good coating properties. To reduce damage caused by smears, thermal CVD, MOCVD, or ALD methods are preferred. stomach.

[0471] Next, the insulating film 113, the insulating film 112, the gate insulating film 102, and the insulating layer 101c are An opening is provided that reaches the conductive layer 104a, etc. Next, a conductive film is formed so as to fill the opening. After the formation, unnecessary portions are removed using a resist mask, and plugs 321 and 322 are formed. Form.

[0472] Subsequently, the insulating film 116 is formed. The insulating film 116 is formed by, for example, a sputtering method or a CVD method. method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method or P The insulating film 116 can be formed by using an LD method or the like. When an insulating material is used, the insulating material may be formed by a coating method such as spin coating. After the insulating film 116 is formed, it is preferable to perform planarization treatment on the upper surface thereof. The insulating film 116 may be formed using the material and method shown for the insulating film 138.

[0473] Subsequently, in the same manner as above, a plug 12 reaching the plug 322 is formed in the insulating film 116. Forms 3rd class.

[0474] Subsequently, a conductive film is formed on the insulating film 116. After that, a resist is formed by the same method as above. Using a mask, unnecessary portions of the conductive film are removed by etching to form wiring 124 and the like. It is possible.

[0475] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0476] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0477] (Embodiment 7) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be explained with reference to the following.

[0478] [Circuit configuration example] In the configuration shown in the semiconductor device to which the first embodiment is applied, transistors and wiring By changing the electrode connection configuration, various circuits can be configured. 1 will explain an example of a circuit configuration that can be realized by using a semiconductor device of one embodiment of the present invention. .

[0479] [CMOS Circuit] The circuit diagram shown in FIG. 37C is a circuit diagram of a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. The figure shows the configuration of an OS circuit. In the figure, the transistors to which the second semiconductor material is applied are The CMOS circuit shown in this embodiment is N AND circuit, NOR circuit, encoder, decoder, MUX (multiplied amplifier) As a basic element of logic circuits such as DEMUX (demultiplexer) It can be used.

[0480] [Analog Switch] The circuit diagram shown in FIG. 37(D) shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called analog switch.

[0481] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0482] (Embodiment 8) In this embodiment, a display module including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. 27 will be used for explanation.

[0483] The display module 8000 shown in FIG. 27 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003 and Display panel 8006, backlight 8007, frame 8009, printed circuit board 801 0, has battery 8011.

[0484] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0485] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as needed to fit the size of the 8006.

[0486] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of 006 to make it an optical touch panel.

[0487] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is disposed on the base 8007 has been illustrated, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 may not be provided.

[0488] The frame 8009 has a function of protecting the display panel 8006 and also a function of preventing the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the The frame 8009 may also function as a heat sink.

[0489] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. This can be omitted if a commercial power source is used.

[0490] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0491] The display module 8000 described in this embodiment may be flexible. This makes it possible to bond to curved or irregularly shaped surfaces, enabling a wide variety of uses. do.

[0492] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0493] (Embodiment 9) In this embodiment, the R The F tag will be explained with reference to FIG.

[0494] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It stores information and transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems, etc. Extremely high reliability is required.

[0495] The structure of an RF tag will be described with reference to Fig. 28. Fig. 28 shows an example of the structure of an RF tag. FIG.

[0496] As shown in FIG. 28, an RF tag 800 includes a communicator 801 (such as an interrogator, reader / writer, etc.). 803 is transmitted from an antenna 802 connected to The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 804, and a 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectifying action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of controlling the temperature, such as an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linearity. The data transmission format is a pair of coils arranged facing each other and communicating by mutual induction. electromagnetic coupling method, which communicates by induced electromagnetic fields; electromagnetic induction method, which communicates by using radio waves; The RF tag 800 shown in this embodiment is compatible with any of these methods. It can also be used in formulas.

[0497] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 adjusts the input AC signal generated by receiving a radio signal with the antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is averaged by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by smoothing the input voltage. A limiter circuit may be provided on the output side. When the internally generated voltage is large, power above a certain level is not input to the subsequent circuit. This is a circuit for controlling the

[0498] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0499] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0500] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for doing this.

[0501] The above-mentioned circuits can be selected or removed as needed.

[0502] Here, the memory circuit described in the above embodiment can be used as the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance between when reading and writing data. and suppressing malfunctions or erroneous writing caused by a power shortage when writing data. This can be done.

[0503] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to all the RF tags produced, we will assign a unique number to only the good products that are shipped. This means that the unique numbers of products will be discontinuous after shipment. This makes it easier to manage customers' needs after products are shipped.

[0504] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0505] (Embodiment 10) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, and the like. Image playback device (typically DVD: Digital Versatile Disk) c) a device having a display that can play back a recording medium such as a In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used As mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) navigation systems, audio playback devices (car audio, digital audio players) Layers, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 57. .

[0506] FIG. 57A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 57(A) has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. stomach.

[0507] FIG. 57(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit The first display unit 91 has a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The display may be switched according to the angle between the first display unit 913 and the second display unit 912. and a display device to which a function as a position input device is added to at least one of the first display unit 911 and the second display unit 912. The function as a position input device may be realized by using a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel part of the display device. can be done.

[0508] FIG. 57(C) shows a notebook personal computer, which includes a housing 921, a display unit 922, It has a keyboard 923, a pointing device 924, and the like.

[0509] FIG. 57(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and a It has 33 etc.

[0510] FIG. 57(E) shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. , an operation key 944, a lens 945, a connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0511] FIG. 57(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, It has Light 954 etc.

[0512] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0513] (Embodiment 11) In this embodiment, an example of use of an RF tag according to one embodiment of the present invention will be described with reference to FIG. RF tags are used in a wide range of applications, including banknotes, coins, securities, and unregistered Bonds, certificates (driver's licenses, resident cards, etc., see Figure 56(A)), packaging containers (wrapping paper (See Figure 56(C)), recording media (See Figure 56(B)), (See Figure 56(D)), vehicles (bicycles, etc.), personal belongings (bags, glasses, etc.), food, Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices ( LCD displays, EL displays, televisions, or mobile phones) or other items It can be attached to tags (see Figure 56(E) and Figure 56(F)) to be used for each item. can.

[0514] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. It is fixed to the object. For example, if it is a book, it is embedded in the paper and the packaging is made of organic resin. If so, the RF tag according to one aspect of the present invention is embedded in the organic resin and fixed to each article. The GU4000 is small, thin, and lightweight, so even after it is fixed to an object, it does not lose its shape. It does not impair the design of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one embodiment of the present invention to a document or the like, an authentication function is provided. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention can be applied to vessels, recording media, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching an RF tag according to one aspect, the efficiency of a system such as an inspection system can be improved. Furthermore, even in the case of vehicles, the RF tag according to one aspect of the present invention can be attached. This can improve security against theft and the like.

[0515] As described above, the RF tag according to one aspect of the present invention can be used for the applications listed in this embodiment. This reduces the operating power consumption, including that for writing and reading information, thereby extending the maximum communication distance. It is also possible to keep the information for a very long time even when the power is cut off. Since it can be retained for a long period of time, it can be used suitably for applications where writing and reading are not performed frequently. can.

[0516] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0517] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. , another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part thereof) described in other embodiments of the present invention, This allows for even more diagrams to be constructed.

[0518] In addition, regarding the contents not specified in the drawings or text in the specification, Alternatively, it is possible to define an upper limit for a certain value. When a numerical range is stated, such as a lower limit and a value, the range may be arbitrarily narrowed. By excluding one point in the scope, it is possible to define an embodiment of the invention that excludes a part of the scope. By these, for example, it is possible to determine whether the prior art falls within the technical scope of one aspect of the present invention. It may be stipulated that the

[0519] As a specific example, a circuit diagram using first to fifth transistors in a circuit is shown below. In this case, the circuit does not have a sixth transistor. Or, the circuit does not have a capacitance element. Furthermore, it is possible to specify that the circuit has a specific connection structure. The invention can be stipulated as not having a sixth transistor as described above. Or, the circuit is defined as not having a capacitance element with a specific connection structure. For example, the gate of the first transistor may be connected to the gate of the second transistor. It is possible to provide the invention as not having a sixth transistor connected to it. Alternatively, for example, a capacitor element having a first electrode connected to the gate of the third transistor may be It is possible to define an invention as not having

[0520] Another specific example is when describing the properties of a substance, for example, "a certain film is an insulating film." In this case, for example, except when the insulating film is an organic insulating film, Alternatively, for example, the insulating film may be made of an inorganic material. It is possible to define one aspect of the invention as excluding the case where the insulating film is an insulating film. It is possible to define one aspect of the invention as excluding cases where the film is a conductive film. Alternatively, for example, one aspect of the invention may be defined as excluding cases where the film is a semiconductor film. It is possible.

[0521] As another specific example, regarding a certain laminated structure, for example, "between film A and film B, there is a film In that case, for example, if the film has four or more layers, It is possible to define the invention as excluding the case of a laminated film. It is possible to define the invention as excluding cases where a conductive film is provided between the film and the conductive film. do.

[0522] In this specification, etc., in a drawing or text described in a certain embodiment, Therefore, it is possible to extract a part of it and use it to constitute an aspect of the invention. If a drawing or text describing a certain part is included, the drawing or text of that part may be omitted. The content of the invention is also disclosed as one aspect of the invention and constitutes one aspect of the invention. It is assumed that this is possible. And one aspect of the invention can be said to be clear. Therefore, for example, in drawings or texts that describe one or more active elements (such as transistors and diodes), wirings, passive elements (such as capacitor elements , resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc., it is assumed that one or more parts can be extracted to form one aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors and capacitor elements), M (M is an integer and M < N) circuit elements (such as transistors and capacitor elements) are extracted to form one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, M (M is an integer and M < N) layers are extracted to form one aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, M (M is an integer and M < N) elements are extracted to form one aspect of the invention. As yet another example, from a text stating that "A has B, C, D, E, or F", some elements are arbitrarily extracted to form inventions such as "A has , B and E", "A has E and F", "A has C, E, and F", , or "A has B, C, D, and E", etc. This is possible.

[0523] In addition, in this specification, etc., when at least one specific example is described in the drawings or texts described in a certain embodiment, deriving the upper concept of that specific example is easily understood by those skilled in the art. Therefore, as described in a certain embodiment, If at least one specific example is described in the drawings or text, The concept is also disclosed as an aspect of the invention and may constitute an aspect of the invention. It is possible, and one aspect of the invention can be said to be clear.

[0524] In this specification, at least the contents shown in the drawings (or even a part of the drawings) is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if a certain content is shown in a diagram, it can be explained in writing. Even if there is no such content, the content is disclosed as one aspect of the invention, and one aspect of the invention Similarly, even if a part of the drawings is taken out, it is possible to construct it as one aspect of the invention. and can constitute one embodiment of the invention. One aspect of the invention is clear. [Example]

[0525] In this example, evaluation results of an oxide semiconductor film according to one embodiment of the present invention will be described.

[0526] [Production method] A silicon wafer was subjected to thermal oxidation to form a silicon oxide film of 100 nm. As a semiconductor film, a 100 nm thick In-Ga-Zn oxide was formed by sputtering. The sputtering conditions were as follows: the target was In:Ga:Zn=1:1:1 (atomic ratio). The power supply was 0.5 kW (DC), and the substrate The distance between the target and the source was 60 mm. Argon and oxygen were used as the deposition gas. The flow rates of argon and oxygen were 30 sccm and 15 sccm, respectively. The substrate temperature was set to 170°C for sample E1-1 and 300°C for sample F1-1. did.

[0527] Next, heat treatment was carried out at 450°C in a nitrogen atmosphere. After this was done for 1 hour, the sample was heat treated in an oxygen atmosphere at 450°C in the same treatment chamber. This was done for an hour.

[0528] [XRD evaluation] Next, we will explain the results of the evaluation using an XRD device. Evaluation X-ray diffractometer D8 DISCOVER Hybrid (manufactured by Bruker AXS) Each sample was evaluated using the method shown in Figure 43. The results for sample E1-1 are shown in Figure 43(A), and those for sample F1-1 are shown in Figure 43(B). A peak was observed around 2θ=31° in the sample. The peak tends to be sharper when the film is formed at 300°C. This is attributed to the (009) plane of the InGaZnO4 crystal, so by increasing the film formation temperature, This suggests that the amount of crystals in the oxide semiconductor film having c-axis orientation increases.

[0529] [Film density evaluation] Next, the film density was measured. The film density was evaluated using XRR (X-ray reflectometry). The obtained film density was 6.18 g for sample E1-1. / cm 3 ], and sample F1-1 was 6.36 [g / cm 3 ]. Under all conditions, A dense and good film was obtained.

[0530] [Nanobeam electron diffraction] Next, specimens E1-1 and F1-1 were analyzed by nanobeam electron diffraction. The electron diffraction data was obtained using the Hitachi High-Technologies HF-2000. The voltage was set to 200 kV.

[0531] The sample stage was moved little by little to the top surface of each sample having an oxide semiconductor film. Transmission electron diffraction patterns were obtained while scanning. The nano-beam electron beam was used. The same measurements were carried out at three points on each sample. A total of three scans, scan 1 to scan 3, were performed on the specimen.

[0532] The diffraction pattern was observed while scanning at a speed of 5 nm / sec, and a video was acquired. The diffraction patterns observed in the obtained movie were converted into still images every 0.5 seconds. The still images were analyzed to identify the patterns of the nc-OS film, the CAAC-OS film, and the spinel The crystal structure patterns of the samples were classified into three types. The number of images classified into each pattern in Scan 1 to Scan 3 is shown in Table 3. The results of scan 1 of the electron diffraction pattern of sample E1-1 are shown in FIGS. 44 to 48, and those of sample F1 The results of scan 1 of -1 are shown in Figs. 49 to 53. Among the diffraction results, the patterns determined to be those of the CAAC-OS film are shown enclosed by dashed lines. 49 to 53, the patterns of the nc-OS film were determined to be the same as those of the nc-OS film. The items that have been removed are shown surrounded by dashed lines.

[0533] [Table 3]

[0534] In sample E1-1, the nc ratio was as high as 90% or more. It was found that the nc ratio was further increased by this. The sum of the c ratio and the CAAC ratio was 100%. [Example]

[0535] In this example, the film density evaluation results and TDS (Thermal Data Set) of In-Ga-Zn oxide were obtained. Desorption Spectroscopy (Temperature Programmed Desorption Spectroscopy) Analysis Results show.

[0536] In-Ga-Zn oxide was deposited on a pre-cleaned quartz substrate using the sputtering method. The target was a polycrystalline In-Ga:Zn film with an atomic ratio of 1:1:1. The film was formed using Ga-Zn oxide under the conditions of a power supply of 100 W and Al as the film-forming gas. The flow rate of oxygen gas is 2 times the total flow rate of argon gas and oxygen gas. The flow rate was adjusted to 0.4 Pa or 1.0 Pa. The substrate temperature The film deposition conditions and film density are shown in Table 4. D is a film of In-Ga-Zn oxide formed by sputtering and then heat-treated at 450°C. The film density was evaluated using XRR. As shown in Table 4, the density of sample C was The degree is 6 [g / cm 3 ] and showed high values.

[0537] [Table 4]

[0538] Next, TDS analysis was performed on sample A to sample D. The amount of outgassing of 8 is shown in Figure 54 (A) and (B). The amount of outgassing of 18 molecular weight is H2O. The amount of release was large in sample A, and the amount of release was small in sample B, which was heat-treated. In sample C, which has a high film density, the amount of gas released was small even without heat treatment. is small, and it is thought that the amount of water contained in the film is small.

[0539] Next, for sample A to sample D, the size of the crystals ( The change in crystal size was evaluated. The crystal size was calculated by observing the cross section using a TEM. Electron beam irradiation was performed using a TEM, and the relationship between cumulative irradiation dose and crystal size was evaluated. 55. In sample A, the crystals tended to grow larger with each electron beam irradiation. Here, the crystal size before electron beam irradiation is, for example, the cumulative approximation line shown in FIG. The irradiation dose is 0 [e - / nm 2 In the heat-treated sample B, The change in crystal size was small. In D, the cumulative dose of electron beam is 4.2 × 10 8 [e - / nm 2 ] in the range No significant change was observed in the size of [Example]

[0540] In this example, the stability of the oxide semiconductor films was evaluated. The method for producing the above is described below.

[0541] First, a 100 nm thick In-Ga-Z film was deposited on a quartz substrate by RF sputtering. The target is polycrystalline In-Ga-Zn oxide (In:Ga:Z The deposition gas was oxygen gas at 2 sccm and aluminum. The gas flow rate was 98 sccm. The power was 100 W. The substrate temperature during film formation was The film deposition pressure for sample 1 was 0.4 Pa. The film deposition pressure for sample 2 was 0.4 Pa. was set to 1.0 Pa.

[0542] For sample 3, a 100 nm thick In-Ga was deposited on a quartz substrate by DC sputtering. The target is In-Ga-Zn oxide (In:Ga:Zn= The deposition gas was oxygen gas at 10 sccm and argon gas at 10 sccm. The gas flow rate was 20 sccm. The power was 200 W. The substrate temperature during film formation was The temperature was set to 300° C. The film formation pressure was set to 0.4 Pa.

[0543] Next, the sample was subjected to a heat treatment for 1 hour in an atmosphere containing oxygen and nitrogen. The five conditions were 0°C, 300°C, 350°C, 400°C, and 450°C. The film densities of Samples 1, 2, and 3 were measured, including the condition where no treatment was performed. The measurement was performed using XRR with a Bruker AXS X-ray diffractometer D8 ADVANCE. The results for sample 1 are shown in Figure 58(A), the results for sample 2 in Figure 58(B), and the results for sample 3 in Figure 58(C). The results are shown in Figure 58(C). The horizontal axis is the temperature of the heat treatment. The film density of sample 1 was 5.9 g / cm². m 3 to 6.1 g / cm 3 The film density of sample 2 was 5.6 g / cm 3 From 5.8g / cm 3 The film density of sample 3 was 6.2 g / cm 3 to 6.4 g / cm 3 Range It was.

[0544] Next, samples 1, 2, and 3 were analyzed using an aqueous solution of phosphoric acid diluted 100 times with pure water. Then, by measuring the thickness before and after etching, the etching rate The results for sample 1 are shown in Figure 59(A), the results for sample 2 in Figure 59(B), and the results for sample 3 in Figure 59(C). The results are shown in Figure 59(C). For Samples 1 and 2, the higher the temperature of the heat treatment, the more the etching It was found that the difference in the heat treatment temperature was small for sample 3. In addition, sample 1, which was not heat-treated, showed a higher It was found that the etching rate was lower than that of sample 1, which had been subjected to heat treatment. It was found that the etching rate of the untreated sample 3 was lower.

[0545] Next, Sample 1, Sample 2, and Sample 3 were analyzed by TDS, and the mass-to-charge ratio of the degassed water was 18. The amount of released gas was measured. The TDS analysis was performed using a thermal desorption analyzer TDS-12 manufactured by Denshi Kagaku Co., Ltd. The results for sample 1 are shown in Figure 60(A), the results for sample 2 are shown in Figure 60(B), and the results for sample 3 are shown in Figure 60(C). The results are shown in Figure 60(C). It was found that the amount of outgassing with a mass-to-charge ratio of 18 was reduced. The mass-to-charge ratio of sample 1, which was not heat-treated, was 18, and the mass-to-charge ratio of sample 2, which was heat-treated, was 18. It was also found that the amount of released carbon dioxide was less than that of sample 1 that had been heat-treated. It was found that the amount of outgassing with a mass-to-charge ratio of 18 was smaller in sample 3, which had no It was.

[0546] Next, the hydrogen concentrations of Sample 1 and Sample 2 were measured. The hydrogen concentrations were measured by SIMS. SIMS was performed using an IMS 7fR manufactured by CAMECA. The results for sample 1 are shown in Figure 61(A) and The results for Sample 1 are shown in Fig. 61(B) and Fig. 68(B), and the results for Sample 2 are shown in Fig. 61(A) and Fig. 68(B). In Figure 68(A) and Figure 68(B), the horizontal axis represents the depth from the film surface and the vertical axis represents the hydrogen concentration. In addition, Figure 61(A) and Figure 61(B) show hydrogen deposition from a depth of 10 nm to 60 nm. In addition, in Figures 68(A) and 68(B), the average concentration is After the region where the hydrogen concentration changes rapidly, the In-Ga-Zn oxide film does not remain. It is possible that the quartz substrate is being measured. In addition, the influence of the surface condition is being considered in the region of less than 10 nm. Therefore, the hydrogen concentration in the In-Ga-Zn oxide film is It is preferable to express the average value from 100 nm to 60 nm. It was found that the higher the temperature, the lower the hydrogen concentration. It was found that the hydrogen concentration was lower in Sample 1, which had not been heat-treated.

[0547] Next, the change in crystal size due to heat treatment of Samples 1, 2, and 3 was measured by TEM. The crystal size is shown as the average value of 20 to 45 points. TEM is a Hitachi transmission electron microscope. The microscope used was H-9000NAR. The results for sample 1 are shown in Figure 62(A), and the results for sample 2 are shown in Figure 6 The results for Sample 2(B) and Sample 3 are shown in Figure 62(C). Sample 1 showed crystalline structure regardless of the heat treatment temperature. The size was found to be about 1.4 nm. Sample 2 was not subjected to heat treatment. (See Figure 67) The crystal size was about 1.2 nm, but after heat treatment at 250°C, Therefore, it grows to about 1.3 nm, and then heat treatment at 300°C reduces it to about 1.6 nm. In addition, no change in crystal size was observed between 300 and 450°C. In addition, in sample 3, the crystal size was 1.5 to 1.6 nm regardless of the heat treatment temperature. It was.

[0548] Next, the change in crystal size due to electron beam irradiation in Sample 1, Sample 2, and Sample 3 was measured using TEM. The results for sample 1 are shown in Figure 63(A), the results for sample 2 in Figure 63(B), and the results for sample 3 in Figure 63(C). 63(C). Samples 1 and 3 were not affected by the temperature of the heat treatment or the electron beam irradiation. The crystal size of sample 2 was almost unchanged by electron beam irradiation. The crystal size increased, and this tendency became more pronounced as the heat treatment temperature decreased.

[0549] The changes in crystal size due to heat treatment and electron beam irradiation are as follows: It can be seen that Sample 1 and Sample 3 have higher stability than Sample 2. When comparing sample 1 and sample 3 with the above-mentioned structural classification, sample 1 is an nc-OS film, and sample 3 is an nc-OS film. Sample 2 is an a-like OS film, and sample 3 is a CAAC-OS film.

[0550] Thus, the nc-OS film has a higher film density than the a-like OS film, and the etching level is The difference is due to the heating after film formation. It cannot be filled by processing. That is, the transistor has an nc-OS film at the time of deposition. It is important to use an oxide semiconductor film. [Example]

[0551] In this example, the localized states of the nc-OS film were evaluated. Measurements were performed using the static photocurrent method.

[0552] For the CPM measurement, a gate electrode (tungsten) on a glass substrate and nc- The OS film, the gate insulator (silicon oxynitride) between the gate electrode and the nc-OS film, and the n A pair of electrodes (tungsten, aluminum, and titanium formed in this order) in contact with the c-OS film. The insulators (silicon oxynitride and silicon oxynitride) on the nc-OS film and on the pair of electrodes were A sample was prepared having a silicon nitride layer (a laminate of silicon nitride and silicon dioxide) and an nc-OS layer. The film was deposited to a thickness of 35 nm by AC sputtering. The film was made of Ga-Zn oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]). The gas was 10% by volume of oxygen gas and 90% by volume of argon gas. The substrate temperature during film formation was room temperature. The film formation pressure was 0.6 Pa. did.

[0553] Next, the prepared sample was subjected to a heat treatment. The heat treatment was carried out for 1 hour in a nitrogen atmosphere. After that, the reaction was continued for another hour under an atmosphere containing oxygen and nitrogen.

[0554] CPM measurement was performed by applying a voltage between a pair of electrodes placed in contact with the nc-OS film. The amount of light irradiated onto the sample surface between the terminals is adjusted so that the current value is constant, and the absorption coefficient is calculated from the amount of irradiated light. Here, the absorption coefficient was derived for each wavelength. The absorption coefficient increases at energy (converted from wavelength) according to the potential density. By multiplying the increase by a constant, the localized level density of the sample can be derived.

[0555] In addition, the optical absorption spectrum curve indicates the optical absorption due to the band tail (Urbach tail). ) can be removed, the absorption coefficient α due to the localized level can be calculated from the following equation: do.

[0556] α=∫[(α(E)-α u ) / E]dE

[0557] Here, E is the energy, α(E) is the absorption coefficient at each energy, and α u Ah Represents the absorption coefficient due to the bucktail.

[0558] The slope of the Urbach tail is called the Urbach energy. The lower the value, the fewer defects there are and the steeper the slope of the tail of the level at the edge of the valence band. It can be said that this is a highly ordered semiconductor film.

[0559] Figure 64 shows the absorption coefficient measured by a spectrophotometer (dotted line) and the absorption coefficient measured by CPM. The energy gap of the oxide semiconductor film is larger than the energy gap of the oxide semiconductor film. The fitting results are shown in Figure 64(A). Fig. 64(B) shows the results for the sample that was heat-treated at 400°C after film formation, and Fig. 64(C) shows the results for the sample that was heat-treated at 400°C after film formation. C) shows the results for a sample that was heat treated at 450°C after film formation. The Urbach energies obtained from the measured absorption coefficients were 72.65 meV and 69 0.45meV and 70.32meV.

[0560] In addition, in Figure 64, the background (thin dotted line) is calculated from the absorption coefficient derived from the CPM measurement. The integrated value of the absorption coefficient was calculated by subtracting the absorption coefficient. The results are shown in Figure 65. Absorption coefficient due to localized levels are 6.27×10-1 cm -1 , 4.19 × 10 -1 cm -1 and 2.29 x10 -1 cm -1 The relationship between the heat treatment temperature and the absorption coefficient is shown in Figure 66. Therefore, the higher the temperature of the heat treatment, the smaller the absorption coefficient becomes, and the smaller the localized level density becomes. We can see that. [Explanation of symbols]

[0561] 11 areas 12 areas 13 areas 14 areas 15 areas 16 areas 21 Perpendicular 22 Perpendicular 23 Perpendicular 50 boards 51 insulating film 100 transistors 101 Semiconductor layer 101a Insulator layer 101b Semiconductor layer 101c Insulator layer 102 Gate insulating film 103 gate electrode 104a conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier Film 112 insulating film 113 Insulating film 114 insulating film 116 Insulating film 123 Plug 124 Wiring 130 transistors 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 gate electrode 136 Insulating Film 137 Insulating Film 138 insulating film 139 Plug 140 plug 143 Conductive Layer 150 Capacitive element 151 Conductive layer 152a Conductive layer 152b Conductive layer 160 transistors 164 plug 165 plug 166 Wiring 171a Low resistance layer 171b Low resistance layer 176a area 176b area 181 Element isolation layer 190 transistors 191 transistors 201 Semiconductor layer 201a Semiconductor layer 201b Semiconductor layer 202 Gate insulating film 202a Gate insulating film 202b Gate insulating film 203a Gate electrode 203b Electrode 204a Conductive layer 204b Conductive layer 214 insulating film 215 insulating film 216 Insulating film 218 Insulating film 251 Conductive Layer 281 Hard Mask 321 Plug 322 Plug 324 areas 501 pixel circuit 502 pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistor 554 Transistor 560 Capacitor 562 Capacitor 570 Liquid Crystal Devices 572 Light-emitting element 610 Electron Gun Room 612 Optical system 614 Sample Room 616 Optical system 618 Camera 620 Observation Room 622 Film Room 624 electronic 632 Fluorescent screen 700 Display device 701 PCB 702 pixel section 704 Source driver circuit section 705 PCB 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 insulating film 732 Sealing film 734 Insulating Film 736 Colored film 738 Light-shielding film 750 transistors 752 transistors 760 connecting electrode 764 insulating film 766 Insulating Film 768 insulating film 770 Planarization insulating film 772 Conductive layer 774 Conductive Layer 775 Liquid Crystal Elements 776 Liquid Crystal Layer 778 Structure 780 Anisotropic Conductive Layer 782 Light-emitting element 784 Conductive Layer 786 EL layer 788 Conductive Layer 790 Capacitor 790a Capacitive element 790b Capacitive element 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 2100 transistors 2200 transistors 4000 RF tags 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5120 board 5130 Target 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

[Claim 1] An oxide semiconductor film containing indium, an element M, and zinc, The element M is at least one element selected from aluminum, gallium, yttrium, and tin, The ratio of the number of atoms of the indium, the element M, and the zinc is: : the zinc satisfies the ratio x:y:z, The x, y, and z represent the following in an equilibrium diagram with the indium, the element M, and the zinc at the vertices: First coordinates (x:y:z=8:14:7); second coordinates (x:y:z=2:4:3); a third coordinate (x:y:z=2:5:7); A fourth coordinate (x:y:z=51:149:300); A fifth coordinate (x:y:z=46:288:833), A sixth coordinate (x:y:z=0:2:11), The seventh coordinate (x:y:z=0:0:1), eighth coordinates (x:y:z=1:0:0); a ratio of the number of atoms in a range connected in order by a line segment to the first coordinate, the range includes the first coordinate to the sixth coordinate, but does not include the seventh coordinate and the eighth coordinate; Using an electron beam with a probe diameter half width of 1 nm, a plurality of electron diffraction patterns are observed by irradiating an electron beam onto a surface on which the oxide semiconductor film is to be formed while moving a position of the oxide semiconductor film and a position of the electron beam relative to each other; the plurality of electron diffraction patterns include 50 or more electron diffraction patterns observed at different locations; the sum of the proportion of the 50 or more electron diffraction patterns having the first electron diffraction pattern and the proportion of the 50 or more electron diffraction patterns having the second electron diffraction pattern is 100%; the first electron diffraction pattern has an observation point having no symmetry or a plurality of observation points arranged in a circle; The oxide semiconductor film, wherein the second electron diffraction pattern has observation points located at vertices of a hexagon.

Images