Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A memory circuit includes an unipolar circuit using an OS transistor. Therefore, a connection with a different layer in the memory circuit becomes unnecessary. Thus, the number of connection parts can be reduced, and the degree of freedom of a circuit layout and the reliability of the OS transistor can be improved. In particular, since a large number of memory cells is provided, the number of connection parts can be significantly reduced by forming the memory cells by the unipolar circuit. By providing a driver circuit in the same layer as a cell array, a large number of wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, so that the number of connection parts can be further reduced. A plurality of integrated circuits can be provided in an interposer to function as one electronic component.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, etc. , storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and their driving The method, or the method for producing the same, can be mentioned as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general. Transistors, semiconductor circuits, arithmetic units, memory devices, etc. are types of semiconductor devices. In addition, they are used in display devices, imaging devices, electro-optical devices, power generation devices (thin film solar cells, organic thin films) Semiconductor devices may be included in the devices (including thin-film solar cells, etc.) and electronic devices. [Background technology]

[0004] Patent Document 1 describes a transistor using an oxide semiconductor and a transistor using single crystal silicon. The document also describes a memory device configured with a transistor using an oxide semiconductor. It is described that the transistor has an extremely small off-state current.

[0005] Examples of oxide semiconductors include oxides of single-component metals such as indium oxide and zinc oxide. In addition, oxides of multi-component metals are also known. Among the multi-component metal oxides, in particular, Research into In-Ga-Zn oxide (hereinafter referred to as IGZO) is being actively conducted. do.

[0006] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous, AAC (c-axis aligned crystalline) structure and nc(n A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. Furthermore, a technique for fabricating a transistor using a CAAC structure and an nc structure has also been disclosed. Even oxide semiconductors with lower crystallinity than those described above have minute crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0007] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non- See Patent Document 6.) LSIs and displays that utilize these properties have been reported ( See Non-Patent Document 7 and Non-Patent Document 8. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-256400 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-patent document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-patent document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device having a high degree of freedom in layout. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device. Another object of one embodiment of the present invention is to provide a novel electronic device.

[0011] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but It is sufficient if the invention can solve at least one of the problems. Other issues than these are not covered by the description, claims, drawings, etc. It becomes clear from the description, claims, drawings, etc. It is possible to extract other issues besides these. [Means for solving the problem]

[0012] A semiconductor device according to one aspect of the present invention includes a cell array, a first driver circuit, and a second driver circuit. a memory cell array including a first memory cell and a second memory cell; The driving circuit has a function of supplying a selection signal, and the second driving circuit has a function of writing or reading data. The first memory cell has a function of reading out the data, and the first memory cell includes a first transistor and a first capacitor. the second memory cell includes a second transistor and a second capacitor; One of the source and the drain of the first transistor is electrically connected to the first capacitor. One of the source and the drain of the second transistor is electrically connected to the second capacitor element. The first driving circuit has a third transistor, and the second driving circuit has a fourth transistor. a first transistor, a second transistor, a third transistor, and a fourth transistor; The transistor has a metal oxide in a channel formation region, and The polarities of the first transistor, the third transistor, and the fourth transistor are the same, The channel formation region of the first transistor and the channel formation region of the second transistor are the same. The semiconductor device is formed in the semiconductor layer.

[0013] Furthermore, a semiconductor device according to one embodiment of the present invention includes a control circuit. a control circuit for controlling the operation of the fifth transistor and the second driving circuit; the fifth transistor has a metal oxide in a channel formation region; The polarity of the transistor is the first transistor, the second transistor, the third transistor, and The polarity of the transistors may be the same as that of the transistors in 4.

[0014] In the semiconductor device according to one embodiment of the present invention, the first transistor has a first gate the first transistor has a second gate electrode and a first insulating layer, and the second transistor has a second gate electrode and a second insulating layer. the first insulating layer has a region in contact with a side surface of the first gate electrode; The second insulating layer has a region in contact with a side surface of the second gate electrode, and the semiconductor layer has a region in contact with the first insulating layer. Alternatively, the second insulating layer may be electrically connected to a conductive layer having a region in contact with the side surface of the second insulating layer. .

[0015] In the semiconductor device according to one embodiment of the present invention, the first transistor and the second transistor The transistor has a back gate, and the back gate of the first transistor and the back gate of the second transistor The back gates of the transistors may be formed from the same conductive layer.

[0016] In the semiconductor device according to one embodiment of the present invention, the semiconductor layer has a metal-containing layer on the surface thereof. The metal-containing layer includes a first gate electrode, a second gate electrode, a first insulating layer, and a second The metal may be different from the main component of the semiconductor layer. stomach.

[0017] In the semiconductor device according to one embodiment of the present invention, the metal may be aluminum, ruthenium, or the like. , titanium, tantalum, tungsten, or chromium.

[0018] One aspect of the present invention is a package substrate, an interposer, an integrated circuit, and the above semiconductor and a device, wherein the integrated circuit and the semiconductor device are provided on the interposer, and the integrated circuit The interposer is electrically connected to the semiconductor device through wiring provided thereon, and is used as an integrated circuit or At least one of the semiconductor devices is electrically connected to the package substrate via the interposer. It is an electronic component that continues to

[0019] An electronic device according to one embodiment of the present invention includes the electronic component, a microphone, a speaker, and the like. It is an electronic device having a camera. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In this manner, a highly reliable semiconductor device can be provided. Therefore, a semiconductor device with a high degree of freedom in layout can be provided. In this way, it is possible to provide a semiconductor device that can be miniaturized or highly integrated. According to one embodiment of the present invention, a novel electronic component can be provided. This makes it possible to provide novel electronic devices.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be clearly It is clear from the description, claims, drawings, etc. Other effects can be extracted from the claims, drawings, etc. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 illustrates an example of the configuration of a memory circuit. [Figure 2] 1A and 1B illustrate structural examples of a semiconductor device. [Figure 3] 1A and 1B illustrate structural examples of a semiconductor device. [Figure 4] 1A and 1B illustrate structural examples of a semiconductor device. [Figure 5] 1A and 1B illustrate a configuration example of a semiconductor device. [Figure 6] 1A and 1B illustrate a configuration example of a semiconductor device. [Figure 7] FIG. 2 illustrates an example of the configuration of a memory circuit. [Figure 8] FIG. 2 illustrates an example of the configuration of a memory circuit. [Figure 9] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 10] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 11] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 13] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 14] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 15] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 17] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 18] 1A and 1B are top views illustrating configuration examples of a semiconductor device. [Figure 19] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 20] 1A and 1B are top views illustrating configuration examples of a semiconductor device. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 25] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 26] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 27] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 28] 1A and 1B are a perspective view and a top view illustrating a configuration example of a semiconductor device. [Figure 29] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] 1 is a cross-sectional view showing a configuration example of a semiconductor device. [Figure 31] FIG. 1 is a perspective view showing a configuration example of a semiconductor device. [Figure 32] 1A and 1B are diagrams illustrating examples of the configuration of electronic devices. [Figure 33] 1A and 1B are diagrams illustrating examples of the configuration of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the following embodiments, and does not deviate from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications can be made to the form and details of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] In this specification, the term "metal oxide" is used in a broad sense. Metal oxides are oxide insulators, oxide conductors (transparent oxide conductors, Oxide Semiconductor (also known as Oxide Semiconductor or simply OS) For example, metal oxide is used in the channel formation region of a transistor. In other words, when the metal oxide is increased, the metal oxide is sometimes called an oxide semiconductor. When the metal oxide has at least one of a width function, a rectifying function, and a switching function, The substance is called a metal oxide semiconductor, abbreviated Hereinafter, we will refer to transistors that contain metal oxide in the channel formation region as OS. is also referred to as an OS transistor.

[0025] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). Metal oxides may also be called metal oxynitrides. Details of metal oxides will be discussed later. do.

[0026] Furthermore, in this specification and the like, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also considered to be described in the drawings or text. Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0027] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, and elements (e.g., switches, transistors, capacitors) that allow electrical connection between X and Y. without using any capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. In this case, X and Y are connected.

[0028] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch has the function of being in an on or off state, controlling whether or not current flows. Alternatively, the switch has the function of selecting and switching a path through which a current flows. In addition, when X and Y are electrically connected, X and Y are directly connected. This includes cases where:

[0029] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0030] If it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., when there is another element or another circuit between X and Y), X and Y are functionally connected (i.e., X and Y are (When X and Y are functionally connected with another circuit between them) and (When X and Y are directly connected) (i.e., when X and Y are connected without any other element or circuit between them) In other words, it is assumed that the above is disclosed in the present specification. If it is explicitly stated that it is connected, The same contents as those in the above case are deemed to be disclosed in the present specification.

[0031] In addition, although the drawings show independent components as if they are electrically connected to each other, Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0032] Also, in the drawings, the size, thickness of layers, or areas are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The figures are merely schematic illustrations, and are not limited to the shapes or values ​​shown in the drawings. During the manufacturing process, layers and resist masks may become unintentionally damaged by etching or other processes. However, in order to make it easier to understand, they may be omitted. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, when referring to the same function, In some cases, the pitch patterns are the same and no particular reference numerals are attached.

[0033] In addition, the invention can be easily understood, especially in top views (also called "plan views") and perspective views. In order to simplify the description, some components may be omitted. The information may be omitted.

[0034] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" "the" or "third" can be used as appropriate for explanation. The ordinal numbers listed in the specification do not match the ordinal numbers used to identify an aspect of the present invention. There are cases where this happens.

[0035] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0036] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value, the maximum value, in the region where the channel is formed. , the minimum or average value.

[0037] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, the maximum value in the region where the channel is formed. , the minimum or average value.

[0038] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter also referred to as the "effective channel width") of the transistor in a top view is The channel width indicated by the For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes The effect of this may become larger than the channel width of the In a transistor in which the gate electrode covers the side surface of the semiconductor, In this case, the ratio of the channel formation region may be larger than the apparent channel width. , the effective channel width becomes larger.

[0039] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. For example, the oxygen content is preferably 55 atomic % or more and 65 atomic % or less. , nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The concentration range of 0.1 atomic % to 10 atomic % is also referred to as nitride oxide. The silicon film has a composition in which the nitrogen content is higher than the oxygen content. Preferably, nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, Silicon concentration is 25 atomic % or more and 35 atomic % or less, and hydrogen concentration is 0.1 atomic % or more and 10 atomic % or less It refers to what is included in the range.

[0040] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0041] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0042] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to the present invention includes a memory circuit formed using an OS transistor.

[0043] <Example of memory circuit configuration> First, a configuration example of a memory circuit included in a semiconductor device according to one embodiment of the present invention will be described. FIG. 1A-1 shows a configuration example of a memory circuit MEM.

[0044] The memory circuit MEM has a cell array CA, a drive circuit WD, and a drive circuit BD. The memory array CA is composed of multiple memory cells MC arranged in a matrix. do.

[0045] The memory cell MC has a function of storing data. It may have a function to store data (high and low level), or it may have a function to store multi-level data of four or more values. The memory cell MC may have a function of storing analog data. It may have a function to

[0046] The memory cell MC is connected to the wiring WL and the wiring BL. belong to the same row, and two adjacent memory cells MC share one wiring BL. This shows an example configuration.

[0047] The drive circuit WD has a function of selecting the memory cell MC. Specifically, the drive circuit WD is a signal for selecting a memory cell MC for writing or reading data (hereinafter, The signal line WL has a function of supplying a signal (also referred to as a selection signal) to the wiring WL.

[0048] The drive circuit BD has a function of writing data to the memory cells MC and a function of storing data in the memory cells MC. Specifically, the drive circuit BD has a function of writing data. The wiring BL connected to the memory cell MC to read data is connected to the wiring BL. The driver circuit has a function of supplying a corresponding potential (hereinafter also referred to as a write potential). BD is a potential corresponding to the data stored in the memory cell MC (hereinafter also referred to as a read potential). It has the function of reading out the data (c) and outputting it externally.

[0049] The memory cells MC, the drive circuits WD, and the drive circuits BD are configured using OS transistors. Since the band gap of oxide semiconductors is 3.0 eV or more, The off-state current is extremely small. The term "current flow" refers to the current that flows between the source and drain when the transistor is in the off state. The oxide semiconductor used in the channel formation region of the transistor is made of indium (In) and It is preferable that the oxide semiconductor contains at least one of zinc (Zn). Examples of the compound semiconductor include In-M-Zn oxide (wherein the element M is, for example, Al, Ga, Y, or S). n) is a typical example. It reduces impurities such as water and hydrogen, which act as electron donors, and Furthermore, by reducing oxygen vacancies, the oxide semiconductor can be made i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be called a highly purified oxide semiconductor. Note that the OS transistor will be described in detail in Embodiment 3.

[0050] Since the off-state current of OS transistors is extremely small, they are particularly suitable for use in memory cells MC. For example, the OS transistor has an off-state current per 1 μm of channel width. The current is set to 100 zA / μm or less, or 10 zA / μm or less, or 1 zA / μm or less, or 1 The OS transistor can be used in the memory cell MC to achieve a current density of 0 yA / μm or less. This allows the data stored in the memory cell MC to be retained for an extremely long period of time. do.

[0051] FIG. 1A-2 shows a configuration example of a memory cell MC using an OS transistor. indicates two adjacent memory cells MC, one of which is referred to as memory cell MCa. The other memory cell MC is also called memory cell MCb. One wiring BL is shared by Cb.

[0052] Each of the memory cells MC includes a transistor T and a capacitance element C. The transistor T and the capacitance element C of a are also referred to as the transistor Ta and the capacitance element Ca, respectively. The transistor T and the capacitance element C of the memory cell MCb are referred to as transistors T b, and capacitance element Cb. The wiring WL connected to the memory cells MCa and MCb is These are also called wiring WLa and WLb. The transistor T is an n-channel OS transistor. It is a pedestrian.

[0053] The gate of the transistor T is connected to the wiring WL, and one of the source and drain is connected to the capacitance element The other of the source and drain is connected to the wiring BL. The other electrode of the capacitance element C is connected to a wiring VL to which a constant potential (for example, ground potential) is supplied. In addition, one of the source or drain of the transistor T and one of the capacitance elements C The node connected to the electrode is called node N.

[0054] When writing data to the memory cell MC, a write potential is supplied to the wiring BL. By supplying a selection signal (high level potential) to the wiring WL, the transistor T is turned on. This causes the write potential to be supplied to the node N. After that, By supplying a low level potential, the transistor T is turned off. , the node N is in a floating state and the write potential is maintained.

[0055] When reading data stored in the memory cell MC, the potential of the wiring BL is set to a read potential. By supplying a selection signal (high level potential) to the wiring WL, the transistor T As a result, the potential of the wiring BL is determined according to the potential of the node N, and The data stored in the memory cell MC is read out.

[0056] Since an OS transistor is used for the transistor T, when the transistor T is in the off state, During this period, the potential of the node N is maintained for an extremely long period. This makes it possible to extremely reduce the frequency of data refresh, thereby reducing power consumption. It is possible.

[0057] In addition, since the memory cell MC rewrites data by charging and discharging the capacitance element C, In principle, there is no limit to the number of times that memory cells MC can be rewritten, and data can be written using low energy. The memory cell MC has a simple circuit configuration. Therefore, it is easy to increase the capacity of the memory circuit MEM.

[0058] FIG. 1(B) shows an example of the configuration of the memory cell MC. In particular, in FIG. 1(A-2), 1 shows a cross-sectional view of memory cells MCa and MCb.

[0059] The memory cell MCa has a transistor Ta and a capacitance element Ca, and the memory cell MCb has a It has a transistor Tb and a capacitance element Cb. It functions as the gate of the transistor Ta. The conductive layer is connected to the wiring WLa and functions as the gate of the transistor Tb. The conductive layer is connected to the wiring WLb. The conductive layer having the function as an electrode of the capacitance element Ca is The conductive layer having the function as an electrode of the capacitance element Cb is connected to the wiring VL. It is connected to VL.

[0060] Furthermore, the transistor Ta and the transistor Tb may have a pair of gates. When a transistor has a pair of gates, one of the gates is referred to as a first gate and the other as a second gate. The other gate is sometimes called the second gate or back gate. It is sometimes called a gate.

[0061] In FIG. 1(A-2), the transistor Ta and the transistor Tb are back gate The back gates of the transistors Ta and Tb are , and the wiring BGL. The wiring BGL is connected to the transistor Ta and the transistor Tb By supplying a predetermined potential to the back gate of the transistor Ta and the transistor For example, the threshold voltage of the transistor Ta and the transistor T The threshold voltage of b can be made higher than 0 V. This reduces the off-current. The back gates of the transistors Ta and Tb are connected to the same conductive It may be composed of layers.

[0062] In addition, the transistors Ta and Tb are formed using a common oxide OX. The oxide OX acts as a semiconductor layer for the transistor Ta and the transistor Tb. and functions as electrodes of the capacitance element Ca and the capacitance element Cb. The channel forming region of the transistor Ta and the channel forming region of the transistor Tb are formed on the same semiconductor. The oxide OX is formed on the conductive layer. The oxide OX is connected to the conductive layer connected to the wiring BL. The conductive layer connected to the wiring BL is used as the source or drain of the transistor Ta. and a function as the source or drain of the transistor Tb.

[0063] As shown in FIG. 1B, the transistors Ta and Tb share the wiring BL. By having the memory cell array CA, the area of ​​the memory cell array CA can be reduced. The specific configuration of the memory cells MCa and MCb will be described in the third embodiment. and explain.

[0064] Furthermore, by configuring the memory cells MC included in the cell array CA as described above, The array CA can be configured using n-channel OS transistors. A circuit composed of transistors of the same polarity is hereinafter referred to as a unipolar circuit. cormorant.

[0065] The drive circuits WD and BD also use OS transistors, similar to the cell array CA. This allows the cell array CA, the drive circuit W The polarities of the transistors included in the memory circuit M The EM can be configured as a unipolar circuit using OS transistors. The transistors included in the cell array CA, the driver circuit WD, and the driver circuit BD are formed in the same process. This allows for simultaneous production.

[0066] Note that a unipolar circuit using OS transistors can also be stacked on a semiconductor substrate. Therefore, a recording layer made up of a unipolar circuit is formed above the circuit formed on the semiconductor substrate. This makes it possible to stack memory circuits MEM, thereby reducing the area of ​​the semiconductor device. do.

[0067] <Configuration Example 1 of Semiconductor Device> FIG. 2 shows a configuration example of the semiconductor device 10. The semiconductor device 10 uses an OS transistor. The layer 20 has a unipolar circuit configured as shown in FIG. A memory circuit MEM may be provided.

[0068] Data to be written in the cell array CA is input from the outside to the drive circuit BD. The data read from the cell array CA is output to the outside from the drive circuit BD.

[0069] The cell array CA, the drive circuit WD, and the drive circuit BD included in the memory circuit MEM are This is composed of a unipolar circuit using S transistors. M can be formed in the same layer 20.

[0070] Here, for example, the memory circuit MEM is an n-channel OS transistor formed in the layer 20. and transistors formed on other layers (such as transistors formed on a semiconductor substrate). When the transistors are configured using the same, a connection portion (contact) for connecting these transistors is provided. In particular, multiple memory cells MC are connected to OS transistors. When the memory cell MC is configured using transistors formed in other layers, The increase in the number of connections becomes more significant. The increase reduces the degree of freedom in circuit layout.

[0071] In addition, impurities (such as hydrogen) are mixed into the oxide semiconductor in the OS transistor. This causes the deterioration of the S transistor. Impurities can penetrate layer 20 through oxidation, so that the interface between the two layers increases. The amount of impurities mixed into the compound semiconductor increases, causing deterioration of the OS transistor formed in layer 20. .

[0072] In one embodiment of the present invention, the memory circuit MEM is a unipolar circuit using an OS transistor. Therefore, there is no need to connect different layers inside the memory circuit MEM. This reduces the number of connections and improves the flexibility of the circuit layout. Furthermore, the reliability of the OS transistor can be improved.

[0073] In particular, since a large number of memory cells MC are provided, the memory cells MC are configured with a single-polarity circuit. By configuring the drive circuit WD and By providing the drive circuit BD on the same layer as the cell array CA, the drive circuit WD and the cell array CA, and a large number of wirings WL and wirings BL that connect the drive circuit BD and the cell array CA are layered. This can avoid the need for a connection between the wiring and the wiring, thereby further reducing the number of connections.

[0074] The memory circuit MEM may be, for example, a cache memory or a main memory device in a computer. It can also be used as an auxiliary storage device.

[0075] Layer 20 may also include a control circuit CC, which includes a drive circuit WD and Specifically, the control circuit CC receives an external input signal. Based on the input control signals (such as address signals, clock signals, or chip enable signals), A function to generate various signals to control the operation of the drive circuits WD and BD based on the It has.

[0076] The drive circuit WD receives a signal (such as an address signal or a control signal) from the control circuit CC. ) and supplies the selection signal to the cell array CA. Based on the signal (address signal, control signal, etc.) supplied from CC, the external input The write potential corresponding to the received data is generated and output to the cell array CA. The circuit BD operates based on a signal (address signal, control signal, etc.) supplied from the control circuit CC. Based on this, the data read from the cell array CA is output to the outside.

[0077] The control circuit CC is composed of a unipolar circuit using OS transistors. Therefore, the control circuit CC can be provided on the layer 20, and the operation of the memory circuit MEM can be controlled by setting it on the same layer. This allows the control circuit CC and the drive The connection between the drive circuit WD and the drive circuit BD can be omitted.

[0078] Layer 20 may also include other circuits. For example, layer 20 may include a processor and peripherals. In this case, the processor and peripheral circuits may use OS transistors. It is composed of a unipolar circuit.

[0079] The processors are CPU (Central Processor Unit), M PU (Micro Processor Unit), GPU (Graphics Pro The peripheral circuits include memory circuits, Input / output circuits, power management unit, timers, counters, conversion circuits (AD conversion A plurality of peripheral circuits can be provided. It may be possible.

[0080] The control circuit CC may also be connected to the processor and peripheral circuits via a bus. This allows data or signals to be transmitted and received between the control circuit CC, the processor, and the peripheral circuits. For example, the signal output from the cell array CA to the control circuit CC is The data can be processed, such as for processing by a processor or peripheral circuitry. .

[0081] The layer 20 is laminated on a semiconductor substrate, and a signal input to the layer 20 is formed on the semiconductor substrate. FIG. 3 shows an example of a configuration in which layer 20 is stacked on top of layer 30. Layer 30 contains circuits made up of transistors formed in a semiconductor substrate. The circuit has a function of outputting a control signal to the control circuit CC or a function of outputting a data signal to the drive circuit BD. The data output from the driving circuit BD may be It may be input to the circuitry that layer 30 has.

[0082] When data or signals are transmitted and received between layer 20 and layer 30, layer 20 and layer 30 are referred to as interlayer are connected by wiring provided in

[0083] As described above, in one embodiment of the present invention, the memory circuit MEM is formed using an OS transistor. By configuring the circuit with a single polarity, the number of connections between layers 20 and 30 is reduced. The semiconductor device 10 can be used as a memory device, an arithmetic device, etc. Cut.

[0084] In the above description, OS transistors are used in the circuits provided in layer 20. As described above, in the case where a channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor, A transistor can also be used. Such a transistor can be, for example, an amorphous silicon Silicon film, microcrystalline silicon film, polycrystalline silicon film, single crystal silicon film, amorphous germanium The semiconductor is a germanium film, a microcrystalline germanium film, a polycrystalline germanium film, or a single-crystal germanium film. Examples of such transistors include those using a semiconductor layer.

[0085] In the above description, the control circuit CC is provided on the layer 20. The control circuit CC may be provided in layer 30 shown in Figure 3. In this case, the control circuit CC is formed on the semiconductor substrate The control circuit CC is composed of a drive circuit WD and a transistor formed in the and the driver circuit BD via a connection formed between the layer 20 and the layer 30 .

[0086] In addition, although the above description has been given of a configuration in which a processor and peripheral circuits are provided, The processor and peripheral circuits may be located on layer 30. In this case, the processor and peripheral circuits is composed of transistors formed on a semiconductor substrate.

[0087] <Configuration Example 2 of Semiconductor Device> FIG. 2 shows an example of the configuration of a semiconductor device 10 having one layer 20 having a memory circuit MEM. Although shown, two or more layers 20 can be stacked. The layer 20 (layers 20_1 to 20_N) is a stack of layers 20 (integer). Each of the memory circuits ME_1 to MEM_N includes a memory circuit ME_2. The configurations and functions of the memory circuits M_1 to MEM_N are the same as those of the memory circuit MEM in FIG.

[0088] In this way, by stacking the memory circuits MEM, the data stored in the semiconductor device 10 The amount of data can be increased.

[0089] <Configuration Example 3 of Semiconductor Device> FIG. 2 shows a configuration example in which the memory circuit MEM is provided in the layer 20. The circuit to be implemented is not limited to the memory circuit MEM. In addition, the layer 20 may include a plurality of circuits with different functions. 5, the layer 20 may include a memory circuit MEM, an FPGA, and an analog processor. 1 shows an example of a configuration having a calculation circuit.

[0090] FPGA is a device that allows users to freely change the circuit configuration. The circuit configuration of the GA is changed by the logic elements of the FPGA and the switches between the wiring. Data stored in the configuration memory (configuration data) The configuration memory is implemented by changing the OS transistors. It can be constructed using a unipolar circuit.

[0091] The analog arithmetic circuit has the function of performing arithmetic operations using analog data. The data is stored in an analog memory provided in the analog calculation circuit. The path is used for AI (Artificial Intelligence) calculations, for example. Specifically, the product-sum operation of the neural network can be performed by the This can be done by an analog arithmetic circuit. This allows for a reduction in circuit scale and an improvement in power consumption. The analog memory provided in the memory is configured by a unipolar circuit using OS transistors. This can be done.

[0092] In FIG. 5, the memory circuit MEM, the FPGA, and the analog arithmetic circuit are all on the same layer 20. Although the circuit shown in FIG. 1 is provided on a separate layer 20, these circuits are provided on separate layers 20. It's fine.

[0093] <Configuration Example 4 of Semiconductor Device> The semiconductor device 10 may have a function as an imaging device. The semiconductor device 10 shown in FIG. 6 has a memory circuit. The structure has a layer 40 stacked on top of a layer 20 (see FIG. 2) having a path MEM.

[0094] The layer 40 has a light receiving section 41 that is composed of a plurality of light receiving elements. It has the function of converting the incident light 42 into an electrical signal and outputting it as imaging data.

[0095] The light receiving element is, for example, a pn junction photodiode with a photoelectric conversion layer made of a selenium-based material. Photoelectric conversion elements using selenium-based materials have a high sensitivity to visible light. A highly sensitive optical sensor with high external quantum efficiency can be realized.

[0096] Selenium-based materials can be used as p-type semiconductors. Selenium, crystalline selenium such as polycrystalline selenium, amorphous selenium, copper, indium, selenium oxide Compounds of copper, indium, gallium, and selenium (CIS) or compounds of copper, indium, gallium, and selenium (CIGS) can be used.

[0097] The n-type semiconductor of the pn junction photodiode has a wide band gap and is resistant to visible light. It is preferable to form the insulating film from a material having light-transmitting properties. For example, zinc oxide, gallium oxide, etc. The oxides that can be used include oxides of indium, tin, and mixtures thereof. Cut.

[0098] The light receiving element in the layer 40 uses a p-type silicon semiconductor and an n-type silicon semiconductor. A pn junction photodiode with a p-type silicon semiconductor and an n-type silicon semiconductor may also be used. A pin junction photodiode in which an i-type silicon semiconductor layer is provided between the semiconductors. Good too.

[0099] The photodiodes using the above silicon are available in single crystal silicon, amorphous silicon, and microcrystalline silicon. It can also be formed using silicon, polycrystalline silicon, or the like.

[0100] The layer 40 may also include a driving circuit 43 connected to the light receiving section 41. The imaging data acquired by the image sensor 1 is read out by the driving circuit 43 and output to the outside. The driving circuit 43 is configured by a unipolar circuit using an OS transistor. can be done.

[0101] The semiconductor device 10 shown in FIG. 6 can be used as a sensor built into a camera or the like. can.

[0102] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0103] (Embodiment 2) In this embodiment, a specific configuration example of the memory circuit described in the above embodiment will be described. do.

[0104] 7 shows a specific example of the configuration of the memory circuit MEM. The memory circuit MEM shown in FIG. The memory cell arrays CA have a plurality of cell arrays CA and the same number of amplifier circuits ACa as the cell arrays CA. The memory circuit MEM includes an amplifier circuit ACb having a plurality of sense amplifiers SA, a driver circuit SAD, and The driver circuit BD in FIG. It includes ACb, a drive circuit SAD, and an input / output circuit IO.

[0105] The amplifier circuit ACa has a function of amplifying the potential of the wiring BL. The potential (read potential) supplied from CA to the wiring BL is amplified by the amplifier circuit ACa. The amplifier circuit ACa outputs the potential of the wiring BL to the wiring GBL. The electric current output to the wiring GBL may have a function of selecting whether to output the electric current or not. The output signal is input to an amplifier circuit ACb.

[0106] The amplifier circuit ACb has a function of amplifying the potential of the wiring GBL. ACb amplifies the read potential output from the cell array CA via the amplifier circuit ACa. The amplifier circuit ACb has a function of outputting the signal to the input / output circuit IO. The amplifier circuit has a function of amplifying the write potential input from the amplifier circuit and outputting it to the wiring GBL. A plurality of sense amplifiers SA are used to amplify the potential by ACb.

[0107] The sense amplifier SA has a function of amplifying the potential difference between the two wirings GBL. In this case, the sense amplifier SA is connected to two wires GBL, and the potential of one of the wires GBL is used as the reference potential. The potential difference between the reference potential and the potential of the other wiring GBL is amplified. The sense amplifier SA has a function of maintaining the potential difference between the two wirings GBL.

[0108] The operation of the sense amplifier SA can be controlled by a drive circuit SAD. The operation circuit SAD receives control signals for controlling the operation of the sense amplifier SA, address signals, etc. The driver circuit SAD receives the data and controls the sense amplifier SA. The sense amplifier SA that outputs a signal to the input / output circuit IO is selected, and the The driver circuit SAD selects the sense amplifier SA that receives the input signal. may be connected to the control circuit 21 in FIG.

[0109] The input / output circuit IO receives data read from the cell array CA via the sense amplifier SA. The input / output circuit IO has the function of outputting data input from the outside. to the cell array CA via the sense amplifier SA.

[0110] In addition, an additional amplifier circuit is provided between the amplifier circuit ACb and the input / output circuit IO. The amplifier circuit may have a function of amplifying the output of the amplifier circuit ACb and supplying the amplified output to the input / output circuit IO. and a function of amplifying the output of the input / output circuit IO and supplying it to the amplifier circuit ACb.

[0111] The amplifier circuit ACa, the amplifier circuit ACb, the driver circuit SAD, and the input / output circuit IO are connected to the OS transistor. This allows the driver circuit BD The drive circuit BD can be formed by a unipolar circuit, and the drive circuit BD can be provided on the layer 20 shown in FIG. This can be done.

[0112] The circuits included in the memory circuit MEM can also be arranged as shown in FIG. In FIG. 8, a plurality of cell arrays CA and amplifier circuits ACa are arranged with an amplifier circuit ACb in between. The sense amplifier SA is arranged to face each other in the vertical direction of the drawing. The wiring GBL connected to the array CA and the wiring GBL connected to the lower cell array CA The potential difference between these wirings GBL is amplified.

[0113] The layouts of the memory circuits MEM shown in FIGS. 7 and 8 are respectively a folded type and an open type. It can be called.

[0114] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0115] (Embodiment 3) In this embodiment mode, specific structural examples of the semiconductor device described in the above embodiment modes will be described. This will be explained using FIG. 9 to FIG.

[0116] <Configuration example of semiconductor device> 9 to 14 show a transistor 700, a memory cell 600a, and a semiconductor memory device according to one embodiment of the present invention. 6A and 6B are a top view and a cross-sectional view of a semiconductor device having a memory cell 600b. Below, memory cell 600a and memory cell 600b are collectively referred to as memory cell 600. There are cases where this happens.

[0117] FIG. 9 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention, and shows the structure of layer 2 shown in the above embodiment. 10 corresponds to 0. FIG. 10 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, which is different from FIG. FIG. 11 shows the channel length of transistor 700 shown in FIG. 12A is a cross-sectional view of the memory cell 600a and the memory cell 600b in the width direction. 12(B), 13(A), and 13(B) are top views of the memory cell. 12(B) is a cross-sectional view of the memory cell 600a and the memory cell 600b. 1A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, and shows the transistor 200a and 13A is also a cross-sectional view of the transistor 200b in the channel length direction. 2(A) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 2(A), 1 is a cross-sectional view of the transistor 200b in the channel width direction. 13A is the same as the cross-sectional view of the transistor 200a in the channel width direction shown in FIG. FIG. 13B is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 12A. FIG. 14 is a cross-sectional view of the portion indicated by the dashed line A7-A8 in FIG. 12(A). In the top view of FIG. 12(A), some elements are omitted for clarity.

[0118] Here, the transistor 700 is connected to the driver circuit WD, the driver circuit BD, or the control circuit CC. The memory cell 600a corresponds to the memory cell MCa. The transistor 200a corresponds to the transistor Ta, and the capacitance element 100a corresponds to the capacitance element Ca. Also, the memory cell 600b corresponds to the memory cell MCb, and the transistor 200 b corresponds to the transistor Tb, and the capacitance element 100b corresponds to the capacitance element Cb. Below, transistor 200a and transistor 200b are collectively referred to as transistor 20 0. In the following, the capacitance elements 100a and 100b are collectively referred to as It may also be referred to as a capacitance element 100 .

[0119] The layer corresponding to the layer 20 of the semiconductor device shown in this embodiment is a transistor 200a and a transistor The transistor 200b, the capacitor 100a, the capacitor 100b, and the transistor 700 and an insulator 210, an insulator 212, an insulator 273, an insulator 274, which function as an interlayer film. The transistor 200a includes an insulator 280, an insulator 282, and an insulator 284. The conductor 203a, which functions as a wiring and is electrically connected to the transistor 200b, Conductor 203b functions as a wiring and conductor 240a functions as a plug. , conductor 240b, and conductor 240c. Conductor 703 functions as a wiring by connecting the two electrodes, and conductor 74 functions as a plug. conductor 740a and conductor 740b. The conductor 112, which functions as a wiring layer by connecting to the conductor 740, and the insulator 150 are provided. Good too.

[0120] In the following description, the conductor 203a and the conductor 203b are collectively referred to as the conductor 203. In the following, the conductors 240a, 240b, and 240 In the following, the conductors 740a and 740c will be referred to as the conductors 240. The conductor 740b may be collectively referred to as the conductor 740. The conductor 203 and the conductor 740 are formed in the same layer as the conductor 240 and have the same configuration. Therefore, the conductor 703 is the conductor 203, and the conductor 740 is the conductor 240. It is possible.

[0121] The conductor 203 is in contact with the inner wall of the opening of the insulator 212. A second conductor of the conductor 203 is formed on the inner side. The height of the top surface of the conductive body 203 and the height of the top surface of the insulator 212 can be made to be approximately the same. In this embodiment, the first conductor of the conductor 203 and the second conductor of the conductor 203 are stacked. However, the present invention is not limited to this. 3 may be provided as a single layer or a laminated structure of three or more layers. When a layer structure is used, an ordinal number may be assigned to indicate the order of formation. The conductor 703 has the same structure as the conductor 203 .

[0122] The insulator 273 is connected to the transistors 200a, 200b, and 700. , and the capacitor element 100. The insulator 274 is disposed on the insulator 273. Insulator 280 is disposed on insulator 274. Insulator 282 is disposed on insulator 280. Insulator 284 is disposed on insulator 282.

[0123] The conductor 240 includes an insulator 273, an insulator 274, an insulator 280, an insulator 282, and is formed in contact with the inner wall of the opening of the insulator 284. Here, the upper surface of the conductor 240 The height of the conductive material 284 can be made to be approximately the same as the height of the upper surface of the insulator 284. Although the structure of the body 240 is shown as a two-layer laminate structure, the present invention is not limited to this. For example, the conductor 240 may have a single layer structure or a laminated structure of three or more layers. The conductor 740 has a similar configuration to the conductor 240 .

[0124] As shown in FIGS. 12 and 13A, the transistor 200a and the transistor 200 b is an insulator 214 and an insulator 216 disposed on a substrate (not shown), and 214 and the conductor 205a and the conductor 205b disposed so as to be embedded in the insulator 216. 205b, an insulator 216, an insulator disposed on the conductor 205a and the conductor 205b a body 220, an insulator 222 disposed on the insulator 220, and a an insulator 224, an oxide 230a disposed on the insulator 224, and an oxide 230a and an oxide 230ca disposed on the oxide 230b. and oxide 230cb, an insulator 250a disposed on oxide 230ca, and oxide Insulator 250b is disposed on object 230cb, and metal is disposed on insulator 250a. The metal oxide 252a and the metal oxide 252b disposed on the insulator 250b are Conductor 260a (conductor 260aa and conductor 260ab) disposed on conductor 252a ) and a conductor 260b (conductor 260ba, and conductor 260bb), an insulator 270a disposed on the conductor 260a, and an insulator 270b disposed on the conductor 260b. Insulator 270b is disposed on insulator 270b, and insulator 271a is disposed on insulator 270a. and an insulator 271b disposed on the insulator 270b, and at least an oxide 230ca, an insulator Insulators arranged in contact with the sides of the insulator 250a, the metal oxide 252a, and the conductor 260a an insulator 275a, at least an oxide 230cb, an insulator 250b, a metal oxide 252b, and an insulator 275b disposed in contact with the side surface of the conductor 260b, an oxide 230a, and and a layer 242 formed on the oxide 230b. The portion located between conductor 260a and conductor 260b is called layer 242b. The portion located opposite to the layer 242b is called the layer 242a, and the conductive material 260b is sandwiched between the layer 242a and the conductive material 260b. The portion located on the opposite side of layer 242b may be referred to as layer 242c. 240b is placed.

[0125] In the transistor 200a, the layer 242a functions as one of the source and drain. The layer 242b functions as the other of the source and drain, and the conductor 260a serves as the front gate. the insulator 250a acts as a gate insulating layer for the front gate; The conductor 205a functions as a back gate, and the insulators 220, 222, and The body 224 functions as a gate insulating layer for the back gate. In FIG. 0b, layer 242b functions as one of the source and drain, and layer 242c functions as the source. The other of the source and drain is the conductor 260b, which acts as a front gate and is an insulator. The insulator 250b acts as a gate insulating layer for the front gate, and the conductor 205b acts as a barrier. The insulators 220, 222, and 224 function as a backgate. The conductor 240b functions as a gate insulating layer for the gate. The conductor 260a is electrically connected to the conductor 260b. The conductor 260a functions as the wiring WLa. Alternatively, the conductor 260b is electrically connected to a conductor corresponding to the wiring WLa. It is electrically connected to a conductor that functions as the line WLb or corresponds to the wiring WLb. In addition, the conductor 203a and the conductor 203b function as the wiring BGL.

[0126] In the following, oxide 230a, oxide 230b, oxide 230ca, and oxide The oxide 230cb may be collectively referred to as oxide 230. 230ca and oxide 230cb are sometimes collectively referred to as oxide 230c. In the following, the conductor 205a and the conductor 205b may be collectively referred to as the conductor 205. In the following description, the insulator 250a and the insulator 250b are collectively referred to as the insulator 250. In the following, the metal oxide 252a and the metal oxide 252b are In the following, the conductors 260a and The conductors 260aa and 260b may be collectively referred to as the conductors 260. The conductor 260a and the conductor 260ab may be collectively referred to as the conductor 260a. a and the conductor 260bb may be collectively referred to as the conductor 260b. In this case, the insulator 270a and the insulator 270b may be collectively referred to as the insulator 270. In addition, in the following, the insulator 271a and the insulator 271b will be collectively referred to as the insulator 271. In addition, in the following, the insulator 275a and the insulator 275b are collectively referred to as the insulator 275b. 75. Also, the transistor 200b is made of the same layer as the transistor 200a. Therefore, unless otherwise specified, The configuration of the transistor 200b can be understood from the description of the configuration of the transistor 200a. .

[0127] As shown in FIGS. 9 and 11, the transistor 700 is formed on a substrate (not shown). The insulators 214 and 216 disposed thereon and the insulators 214 and 216 embedded therein A conductor 705 is disposed so as to be embedded in the insulator 216 and the conductor 705. an insulator 220 disposed on the insulator 220; an insulator 222 disposed on the insulator 220; An insulator 724 is disposed on the insulating layer 724, and an oxide 730 (oxide 730 a, oxide 730b, and oxide 730c) and an insulator disposed on oxide 730. 750, a metal oxide 752 disposed on the insulator 750, and a metal oxide 752 disposed on the metal oxide 752. The conductor 760 (conductor 760a and conductor 760b) placed on the conductor 760 an insulator 770 disposed on the insulating layer 771; and The oxide 730c is in contact with the sides of the insulator 750, the metal oxide 752, and the conductor 760. and a layer 742 formed on the oxide 730. A conductor 740a is disposed on one side of the layer 742, and a conductor 74b is disposed on the other side of the layer 742. 0b is placed.

[0128] In transistor 700, one of layers 742 functions as one of the source and drain. The other of the layers 742 functions as the other of the source and drain, and the conductor 760 is the front The conductor 705 functions as a gate and the conductor 706 functions as a back gate.

[0129] Here, the transistor 700 is formed in the same layer as the transistor 200 and has a similar configuration. Therefore, the oxide 730 has the same structure as the oxide 230. The conductor 705 has the same structure as the conductor 205. The description of the insulator 205 can be referred to. The insulator 724 has the same structure as the insulator 224. The insulator 750 has the same structure as the insulator 250. The metal oxide 752 has a similar structure, and the description of the insulator 250 can be referred to. The metal oxide 252 has a similar structure to that of the metal oxide 252, and the description of the metal oxide 252 can be referred to. The conductor 760 has the same configuration as the conductor 260, and the description of the conductor 260 should be taken into consideration. The insulator 770 has the same configuration as the insulator 270, and the description of the insulator 270 is referred to. The insulator 771 has a similar structure to the insulator 271. The insulator 775 has the same structure as the insulator 275, and In the following, unless otherwise specified, The structure of the transistor 700 can be understood by referring to the description of the structure of the transistor 200. can be done.

[0130] In the transistor 200, the oxide 230a, the oxide 230b, and the oxide 23 Although the present invention is not limited to a structure in which three layers of 0c are stacked, For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, The structure may be a two-layer structure of 230b and oxide 230c, or a laminated structure of four or more layers. The same is true for the oxide 730 of the transistor 700. In the example 200, a configuration in which conductors 260a and 260b are stacked is shown. However, the present invention is not limited to this. The same is true for .

[0131] The capacitor element 100a is formed by a layer 242a (oxide 230) that covers the source and and a region that functions as one of the drain and the insulator 130a on the layer 242a. The conductor 120a is connected to the insulator 130a via the insulator 130a. It is preferable that the conductive layer is disposed so that at least a portion of the conductive layer overlaps the layer 242a. A conductor 240a is disposed on and in contact with the layer 240a. 2c (oxide 230 serves as one of the source and drain of transistor 200b) the region where the insulator 130b is located on the layer 242c, the conductor 120b on the insulator 130b, The conductor 120b is at least partially connected to the layer 242b via the insulator 130b. It is preferable that the conductor 2 is disposed so as to overlap with the conductor 120b. In the following, the insulators 130a and 130b are collectively referred to as insulators 130a and 130b. In the following description, the conductor 120a and the conductor 120b may be collectively referred to as the conductor 120.

[0132] In the capacitor 100a, the layer 242a functions as one of the electrodes, and the conductor 120a The insulator 130a functions as the dielectric of the capacitor element 100a. Here, layer 242a serves as one of the source and drain of transistor 200a. and one of the electrodes of the capacitor 100a and functions as a node N. The conductor 240a is electrically connected to a conductor corresponding to the wiring VL.

[0133] In the capacitor 100b, the layer 242c functions as one of the electrodes, and the conductor 120b The insulator 130b functions as the other electrode. Here, layer 242c is one of the source and drain of transistor 200b. and one of the electrodes of the capacitor 100b, and functions as a node N. The conductor 240c is electrically connected to a conductor corresponding to the wiring VL.

[0134] In FIG. 9 and other figures, the insulators 130a and 130b have a multilayer structure. However, it may have a single layer structure as shown in FIG. In the configuration shown in FIG. 9, the conductors 740a and 740b are arranged close to each other. As shown in FIG. 10, the electrodes may be provided at a distance from each other. Alternatively, the electrodes may be embedded in an insulator 280 or the like. The conductors 240a and 240c electrically connected to the embedded wiring VL form a capacitance element. 10, one electrode of the capacitor element 100a and one electrode of the capacitor element 100b serve as the capacitor element 100a. In addition, in FIG. 10, the wiring BL is connected to the wirings WLa and W The diagram shows a configuration in which the electrodes are arranged perpendicular to Lb.

[0135] In FIG. 12 and other figures, the conductors 240a, 240b, and 240c are directly connected. Although the semiconductor device shown in this embodiment is arranged on a line, the semiconductor device is not limited to this. The conductive layer may be appropriately arranged in accordance with the circuit layout and driving method of the memory cell array. 240a and the conductor 240c are not necessarily provided. For example, as shown in FIG. In addition, when the conductors 120a and 120b are extended to function as wiring, The conductors 240a and 240c may not be provided. As with conductor 120b, conductor 260a, conductor 260b, conductor 203a, and conductor The conductive body 203b may also function as a wiring. In this case, the conductive body 203b may function as a wiring. 16, the wiring may be provided by extending in the channel width direction of the transistor 200b. The conductors 120a, 120b, 203a, and 203b functioning as a The conductors 260a and 260b extend in the same direction. The semiconductor device is not limited to this, and the circuit arrangement and driving method of the memory cell array may be changed. They should be arranged appropriately.

[0136] The memory cell 600a and the memory cell 600b shown in FIG. 16 are configured as shown in FIG. In addition, the wiring WLa and wiring WLb are orthogonal to the wiring BL (x direction and y direction in the figure). The wiring VL can be configured to be provided in the area where the wiring WLa and the wiring WLb extend. The structure can be such that the electrode is provided in the direction of extension (x direction in the drawing).

[0137] The memory cells 600a and 600b shown in FIG. 16 are arranged in a matrix of 3 rows and 3 columns. When the conductors 260 are arranged in a shape similar to that shown in the top view of FIG. The line WL_1 becomes the wiring WL_6, and the wiring obtained by extending the conductor 120 becomes the wiring VL. Furthermore, wirings BL_1 to BL_3 are provided in contact with the upper surface of the conductor 240b. The extension direction of the wiring WL_6 from the line WL_1 and the extension direction of the wiring BL_3 from the wiring BL_1 are , are approximately perpendicular to the direction in which the wiring BL_1 to the wiring BL_3 extend. As shown in FIG. 18, the memory cell 600a and the memory cell 600b may be arranged so that their extending directions are substantially perpendicular to each other. The memory cells 600b and 600c are arranged in a matrix to form the cell array shown in FIG. In FIG. 18, the memory cell 600a and the memory cell 600b However, the present embodiment is not limited to this, and the cell array The number and arrangement of memory cells or wirings included in the array may be set appropriately. 18, for clarity, some elements shown in FIG. 16 are omitted. There are.

[0138] 19 is a cross-sectional view corresponding to the portion indicated by the dashed line X1-X2 in FIG. As shown in FIG. 19, the wiring BL_1 and the wirings WL_1 to WL_4 are perpendicular to each other. As shown in FIG. 19, the wiring BL_1 and the wiring VL are perpendicular to each other. In addition, the wiring VL is provided so as to be shared between adjacent memory cells.

[0139] 18, the oxide 230 is formed so that its long side is substantially perpendicular to the direction in which the wiring WL extends. Although the oxide 230 and the wiring WL are provided, the present invention is not limited to this. For example, in FIG. As shown in FIG. 1, the long side of the oxide 230 is not perpendicular to the extending direction of the wiring WL, and the length of the oxide 230 is The layout may be such that the sides are inclined with respect to the extension direction of the wiring WL. The angle between the long side of the oxide 230 and the extending direction of the wiring WL is 20° or more and 70° or less, preferably The oxide 230 and the wiring WL may be provided so that the angle is between 30° and 60°.

[0140] In this way, by arranging the oxide 230 at an angle with respect to the extension direction of the wiring WL, In some cases, the memory cells can be densely arranged. In some cases, it may be possible to reduce the area and achieve a higher integration of the semiconductor device.

[0141] As shown in FIG. 12A, a part of the capacitor 100a overlaps with the transistor 200a. The capacitor 100b is formed so as to partially overlap the transistor 200b. As a result, the transistor 200a, the transistor 200b, and the capacitance element 1 The total projected area of ​​the memory cell 600a and the capacitor element 100b is reduced. The area occupied by the memory cell 600b and the memory cell 600c can be reduced. This facilitates miniaturization and high integration. , the capacitor element 100a, and the capacitor element 100b can be formed in the same process. This allows the process to be shortened and productivity to be improved.

[0142] One of the source and drain of the transistor 200a and the source of the transistor 200b One of the source and drain is electrically connected to the conductor 240b through the layer 242b. As a result, the contact between the wiring BL of the transistor 200a and the transistor 200b is The connector portion is shared, and the transistor 200a and the transistor 200b are connected to the wiring BL. The number of plugs and contact holes for the source can be reduced. By sharing the wiring electrically connecting either the source or the drain, The occupied area can be further reduced.

[0143] In the memory cell 600a and the memory cell 600b, the transistor 200a The channel length direction of the transistor 200b is parallel to the channel length direction of the transistor 200a. The transistor 200a, the transistor 200b, the capacitance element 100a, and the capacitance element 100b are However, the semiconductor device shown in this embodiment is not limited to this. The memory cell 600a and the memory cell 600b shown are examples of the configuration of a semiconductor device. Transistors with appropriate structures may be arranged as appropriate depending on the circuit configuration and driving method.

[0144] Next, an oxide film serving as a semiconductor layer of the transistor 200a and the transistor 200b is formed. The following is a detailed description of the compound 230. Unless otherwise specified, The description of the oxide 230 shall be taken into consideration for the oxide 730 of the transistor 700. The transistor 200a and the transistor 200b are formed in a region where a channel is formed (hereinafter, referred to as a channel The oxide 230 (oxide 230a, oxide 230b, oxide 230c) containing the oxide 230 is also called a channel forming region. oxide 230ca, and oxide 230cb), and metal oxides that function as oxide semiconductors. It is preferable to use a semiconductor (hereinafter also referred to as an oxide semiconductor) as the insulating layer.

[0145] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Conductors can be deposited using methods such as sputtering, making them ideal for constructing highly integrated semiconductor devices. The transistor 200 can be used.

[0146] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Tantalum, tungsten, magnesium, etc.) The oxide 230 may be an In-Ga oxide, an In-Z oxide, or the like. n-oxides may also be used.

[0147] Here, the oxide semiconductor contains aluminum, ruthenium, and the like in addition to the elements constituting the oxide semiconductor. By adding metal elements such as tungsten, titanium, tantalum, chromium, and tungsten, A metal compound is formed to reduce the resistance. Preferably, aluminum, titanium, or tantalum is used. It is preferable to use titanium, tungsten, or the like.

[0148] To add a metal element to an oxide semiconductor, for example, the metal element is deposited on the oxide semiconductor. a metal film containing a metal element, a nitride film containing a metal element, or an oxide film containing a metal element may be provided. In addition, by providing the film, a metal oxide film can be formed at the interface between the film and the oxide semiconductor or in the vicinity of the interface. A part of the oxygen in the oxide semiconductor located at the boundary is absorbed into the film, etc., forming oxygen vacancies. The resistance near the surface may become low.

[0149] Further, a metal film, a nitride film containing a metal element, or a nitride film containing a metal element may be formed over an oxide semiconductor. After the oxide film is formed, heat treatment may be performed in an atmosphere containing nitrogen. By the heat treatment of the above, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is formed. , a metal element that is a component of the film is converted into an oxide semiconductor, or a metal that is a component of an oxide semiconductor is converted into an oxide semiconductor. The element diffuses into the film, and the oxide semiconductor and the film form a metal compound, resulting in a low resistance. The metal element added to the oxide semiconductor can be a mixture of the oxide semiconductor and the metal element. By forming a metal compound, a relatively stable state is created, making it possible to create highly reliable semiconductor devices. can be provided.

[0150] In addition, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element and an oxide semiconductor A compound layer (hereinafter also referred to as a different layer) may be formed at the interface with the conductor. The compound layer (heterogeneous layer) is a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. and a metal compound containing an oxide semiconductor component. For example, As a result, a layer in which the metal element of the oxide semiconductor and the added metal element are alloyed is formed. The alloyed layer is in a relatively stable state, and a highly reliable semiconductor device can be obtained. can be provided.

[0151] Furthermore, hydrogen present in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor, When the oxygen enters the oxygen vacancy in the resistive region, it becomes relatively stable. The hydrogen in the oxygen vacancies in the oxide semiconductor is converted into oxygen vacancies by heat treatment at 250°C or higher. The oxide semiconductor is then released from the low-resistance region, diffuses into the low-resistance region, and exists in the low-resistance region. It is known that the oxygen vacancies are contained in the crystals and become relatively stable. Therefore, the region of the oxide semiconductor where the resistance is reduced or the region where the metal compound is formed has a lower resistance. Oxide semiconductors that have become resistive and have not become low-resistive are highly purified (reduced impurities such as water and hydrogen) ) and tends to have a higher resistance.

[0152] In addition, when an impurity element such as hydrogen or nitrogen is present in an oxide semiconductor, the carrier density decreases. The hydrogen in the oxide semiconductor reacts with the oxygen that bonds with the metal atoms to form water, Oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, the carrier density increases. In addition, some of the hydrogen bonds with oxygen, which bonds with metal atoms, to generate electrons, which act as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

[0153] Therefore, a metal element and impurity elements such as hydrogen and nitrogen are added to an oxide semiconductor. By selectively adding the element, it is possible to form a high-resistance region and a low-resistance region in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the oxide 2 processed into an island shape can be 30, a region that functions as a semiconductor with a low carrier density and a source region or a drain region A low resistance region that functions as a gate electrode region can be provided.

[0154] Here, an enlarged view of the area 239 enclosed by the dashed line in FIG. 12(B) is shown in FIG. 15. As shown in FIG. 5, region 239 includes selectively low-resistivity oxide 230b.

[0155] As shown in FIG. 15, the oxide 230 is divided into regions 234a, 234b, 231a, Region 231b, region 231c, region 232a, region 232b, region 232c, and region Here, the region 234a is the channel forming region of the transistor 200a. The region 234b functions as a channel forming region of the transistor 200b. The region 231a serves as one of the source and drain regions of the transistor 200a. region 231b functions as the other of the source and drain regions of transistor 200a; , and serves as one of the source and drain regions of transistor 200b, Region 231c functions as the other of the source and drain regions of transistor 200b. In addition, the region 232a is located between the region 234a and the region 231a, and the region 232b is located between the region 234a and the region 231a. The region 232c is located between the region 234a and the region 231b. The region 232d is located between the region 234b and the region 231c. In the following, the area 234a and the area 234b may be collectively referred to as the area 234. In the following, the area 231a, the area 231b, and the area 231c are collectively referred to as The area 231 may be referred to as an area 232a, an area 232b, an area 232c, and an area 232d may be collectively referred to as area 232.

[0156] The insulator 130a and the conductor 120a are provided on the region 231a. The region 31a functions as one of the electrodes of the capacitor element 100a. The region 231c is provided with the electrode 130b and the conductor 120b of the capacitance element 100b. The region 231 of the oxide 230 is made to have a low resistance, and functions as one of the conductive oxides. Therefore, it can function as one of the electrodes of the capacitor 100.

[0157] The region 231 that functions as a source region or a drain region has a low oxygen concentration and a low resistance. The region 234 that functions as a channel forming region is a region that is formed by The oxygen concentration is higher and the carrier density is lower than that of the region 231 that functions as a drain region. Region 232 is a high resistance region that functions as a source region or a drain region. The oxygen concentration is higher and the carrier density is lower than that of the region 231 where the channel is formed. The region has a lower oxygen concentration and a higher carrier density than the region 234 that functions as a gate electrode.

[0158] The region 231 contains at least metal elements and impurity elements such as hydrogen and nitrogen. Preferably, both concentrations are higher than those in regions 232 and 234 .

[0159] For example, region 231 may contain aluminum, ruthenium, titanium, tantalum, or the like in addition to oxide 230. One or more metal elements selected from the group consisting of tantalum, tungsten, chromium, etc. It is preferable that the metal element is:

[0160] To form the region 231, for example, a metal element is added to the region 231 of the oxide 230. The film containing the metal element may be etched after the formation of the region 231. The film containing the metal element may be a metal film, a metal element, or the like. An oxide film containing a metal element or a nitride film containing a metal element can be used. Preferably, a layer 242 is formed between the film having the metal element and the oxide 230 . For example, layer 242 may be formed on the top and sides of oxide 230. 42 has a metal compound containing a component of the film having the metal element and a component of the oxide 230. For example, the layer 242 may be a layer containing a compound of the oxide 230. A layer may be formed in which the metal element and the added metal element are alloyed.

[0161] By adding a metal element to the oxide 230, a metal compound is formed in the oxide 230. This can reduce the resistance of the region 231. Note that the metal compound is not necessarily an oxide. For example, the layer 242 may not be formed in the oxide 230. Alternatively, a layer 242 may be formed between the oxide 230 and the insulator 130.

[0162] Therefore, region 231 may also include a low resistance region of layer 242. At least a portion of the source region or Here, layer 242 includes regions 231a, 231b, and and region 231c, respectively, and are formed as layers 242a, 242b, and 242c. This becomes:

[0163] Region 232 has an area overlapping with insulator 275. Region 232 is made of aluminum, Metal elements such as ruthenium, titanium, tantalum, tungsten, and chromium, as well as hydrogen and and impurity elements such as nitrogen, the concentration of which is preferably higher than that of region 234. For example, a film containing the above metal element may be provided in contact with the region 231 of the oxide 230. The component in the film containing the metal element and the component of the oxide semiconductor form a metal compound. The metal compound may attract hydrogen contained in the oxide 230. Therefore, the concentration of hydrogen in the region 232 adjacent to the region 231 may become high.

[0164] Note that either or both of the region 232a and the region 232b are electrically connected to the conductor 260. By adopting such a configuration, the conductor 260a and the Therefore, the area 232a and the area 232b can be overlapped. Similarly, either or both of the region 232c and the region 232d are electrically connected to the conductor 26. 0b. By adopting such a configuration, the conductor 260b It is possible to make the area 232c and the area 232d overlap.

[0165] Also, in FIG. 15, regions 234, 231, and 232 are oxide 230b. For example, but not limited to, these regions may be formed by layer 242, oxide 230, In addition, in FIG. 15, the oxide 230a and the oxide 230c may be formed on the boundary between the respective regions. Although the field is shown as being approximately perpendicular to the top surface of the oxide 230, this embodiment is not limited to this. For example, the region 232 is not formed on the conductor 260 side near the surface of the oxide 230b. In the vicinity of the lower surface of the oxide 230b, the conductor 240a side or the conductor 240b side The shape may recede.

[0166] Also, in the oxide 230, it may be difficult to clearly detect the boundaries between the regions. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are as follows: Not only is there a gradual change in each area, but there is also a continuous change within each area (also known as gradation) In other words, the closer to the channel forming region, the more the metal elements and It is sufficient that the concentrations of impurity elements such as hydrogen and nitrogen are reduced.

[0167] To selectively reduce the resistance of the oxide 230, for example, aluminum, ruthenium, or titanium may be used. Metal elements that increase conductivity, such as tantalum, tungsten, and chromium, as well as impurities At least one of the impurities may be added to a desired region. For example, the element may be an element that can be captured by oxygen vacancies. Examples of suitable elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gases. Representative examples of rare gas elements include helium, neon, argon, krypton, and krypton. Senon et al.

[0168] The region 231 contains the above-mentioned metal element for increasing conductivity, an element for forming oxygen vacancies, or oxygen By increasing the content of elements captured by defects, the carrier density is increased, resulting in lower resistance. It is possible.

[0169] In order to reduce the resistance of the region 231, for example, the oxide 230 is in contact with the region 231, and the above It is preferable to form a film containing a metal element. An oxide film containing an element, a nitride film containing a metal element, or the like can be used. The film containing metal elements includes at least an insulator 250, a metal oxide 252, a conductor 260, an insulating material 262, and a metal oxide 252. The insulating layer 270, the insulating layer 271, and the insulating layer 275 are disposed on the oxide 230. is preferred.

[0170] The oxide 230 comes into contact with the film containing the metal element, and the film containing the metal element is formed. The components of the film and the components of the oxide 230 form a metal compound, forming a region 231, which has a low resistance. In addition, at the interface between the oxide 230 and the film containing the metal element, or in the vicinity of the interface, A portion of the oxygen in the oxide 230 located therein is absorbed into the layer 242, creating oxygen vacancies in the oxide 230. In some cases, a region 231 is formed by forming a thin film and reducing the resistance.

[0171] In addition, the oxide 230 and the film containing the metal element are in contact with each other in a nitrogen-containing atmosphere. The heat treatment is preferably performed under atmospheric pressure. The metal element that is a component of the film containing the metal element is converted into an oxide 230 or the oxide 230 is converted into an oxide 230. The metal element diffuses into the film containing the metal element, and the oxide 230 and the metal element are separated. The oxide 230 and the film containing the element form a metal compound, which reduces the resistance. A layer 242 is formed between the film having the metal element. The film is made up of an insulator 250, a metal oxide 252, a conductor 260, an insulator 270, an insulator 271, and is provided on oxide 230 via insulator 275, so that layer 242 is Conductor 260a, conductor 260b, insulator 275a, and insulator 275b of object 230 At this time, the metal element of the oxide 230 and the metal element The metallic elements of the film may be alloyed. Thus, layer 242 may include an alloy. The alloy is in a relatively stable state, and a highly reliable semiconductor device can be provided. Cut.

[0172] The heat treatment is carried out at a temperature of, for example, 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower. The heat treatment is preferably carried out at a temperature of 320° C. or higher and 450° C. or lower. Alternatively, the heat treatment may be carried out in an inert gas atmosphere. or heat treatment in an inert gas atmosphere, and then heat treatment in an atmosphere containing an oxidizing gas. Good too.

[0173] In addition, hydrogen in the oxide 230 diffuses into the region 231, and oxygen vacancies present in the region 231 are eliminated. In addition, when the oxygen vacancy in the region 234 is By heat treatment at 250°C or higher, hydrogen escapes from the oxygen vacancies and diffuses into the region 231. The oxygen enters the oxygen vacancies in the region 231 and becomes relatively stable. Therefore, the region 231 has a lower resistance, and the region 234 has a higher purity (water, hydrogen, etc.) (reduction of materials) and higher resistance.

[0174] On the other hand, the region of the oxide 230 overlapping with the conductor 260 and the insulator 275 (region 234 , and region 232) are connected via conductor 260 and insulator 275, so that the metal element In addition, in the region 234 and the region 232 of the oxide 230, The oxygen atoms in the oxide 230 are prevented from being absorbed into the film containing the metal element described above. will be done.

[0175] In addition, the film containing the metal element is provided with a region 231 of an oxide 230 and a region adjacent to the region 231. The oxygen in the adjacent region 232 is absorbed, and oxygen vacancies are formed in the region 231 and the region 232. Hydrogen in the oxide 230 enters the oxygen vacancy, and the region 231 The carrier density in regions 231 and 232 of oxide 230 increases. The region 232 is made to have a low resistance.

[0176] Here, when the film containing the metal element has the property of absorbing hydrogen, the oxide 230 The hydrogen in the oxide 230 is absorbed into the film, thus reducing the hydrogen impurities in the oxide 230. The film containing the metal element can be formed by removing the metal element absorbed from the oxide 230 in a later process. It may be removed together with hydrogen.

[0177] It is not necessary to remove the film containing the metal element. If the film containing the element is made insulating and has high resistance, it may remain. The film containing the metal element is oxidized by the oxygen absorbed from the oxide 230, becomes an insulator, and In this case, the film containing the metal element may function as an interlayer film. There is a match.

[0178] Furthermore, for example, when a conductive region remains in the film containing the metal element, By performing heat treatment, the material is oxidized and becomes an insulator, resulting in high resistance. It is preferable to carry out the treatment in an oxidizing atmosphere, for example. When there is a structure containing oxygen nearby, by performing heat treatment, the film containing the metal element can be It may react with the oxygen contained in the structure and be oxidized.

[0179] The film containing the metal element is left as an insulator, so that the interlayer film and the capacitor element 1 When the structure is formed, the metal element having the above-mentioned The film is provided to a thickness that allows it to be insulated in a later process. The film containing the element has a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. When the heat treatment is performed in the oxidizing atmosphere, the oxide 230 and the upper The film containing the metal element is heat-treated once in a nitrogen-containing atmosphere while in contact with the film. It is preferable to carry out the heat treatment once in a nitrogen-containing atmosphere. Oxygen in the oxide 230 is more likely to diffuse into the film containing the metal element.

[0180] Furthermore, after the layer 242 is formed, the film containing the metal element has sufficient conductivity. In this case, a part of the film having the metal element is removed to form the source electrode or Alternatively, a conductor that functions as a drain electrode may be formed. By making the thickness of the layer sufficiently thick, for example, between 10 nm and 200 nm, the source electrode or The source electrode can provide sufficient conductivity to act as a drain electrode. Alternatively, the conductor functioning as the drain electrode may be an oxide film containing a metal element, or a metal element. Alternatively, the nitride film may have the following structure.

[0181] In the above, as a method for forming the region 231 and the region 232, the region of the oxide 230 A method of forming the layer 242 by providing a film containing a metal element in contact with the region 231 has been described. The embodiment is not limited to this. For example, the carrier density of the oxide 230 can be increased. By adding an element as a dopant that can make the layer 2 thin and low in resistance, 42 may be formed.

[0182] The dopant may be an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative examples of such elements include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. may also be used. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon. Also, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Nesium, zirconium, beryllium, indium, ruthenium, iridium, strontium One or more metal elements selected from metal elements such as thium, lanthanum, etc. Among the above, boron and phosphorus are preferred as dopants. When iodine or phosphorus is used as a dopant, amorphous silicon or low-temperature polysilicon Equipment from the manufacturing line can be used, reducing capital investment. The concentrations of the above elements were measured using secondary ion mass spectrometry (SIMS). Measurement can be performed using mass spectrometry or the like.

[0183] In particular, it is preferable to use an element that easily forms an oxide as the element to be added to the layer 242. Representative examples of such elements include boron, phosphorus, aluminum, and magnesium. The element added to the layer 242 takes oxygen from the oxide 230 to form an oxide. As a result, many oxygen vacancies are formed in the layer 242. When the hydrogen in 30 bonds with the silicon dioxide, carriers are generated, resulting in an extremely low resistance region. The elements added to the layer 242 exist in the form of stable oxides in the layer 242, and therefore, in the subsequent processes, Even if a process requiring a high temperature is performed, the ions are unlikely to be desorbed from the layer 242. By using an element that easily forms an oxide as an element added to the layer 242, the oxide 23 It is possible to form a region in the 0 that is resistant to high resistance even when subjected to high-temperature processes.

[0184] When the layer 242 is formed by adding a dopant, for example, the insulator 271, the insulator 2 70, conductor 260, metal oxide 252, insulator 250, oxide 230c, and insulator The dopant is added using the oxide 230 as a mask. The layer 242 containing the above elements can be formed in the region where the mask does not overlap. , insulator 271, insulator 270, conductor 260, metal oxide 252, insulator 250, oxide Instead of using the insulating material 230c and the insulating material 275 as a mask, a dummy gate is formed to mask the In this case, after doping, the insulator 271, the insulator 270, the conductor 260, metal oxide 252, insulator 250, oxide 230c, and insulator 275. Just do that.

[0185] As a method for adding dopants, ionization is performed by mass separating ionized source gases and adding them. ion doping, which adds ionized source gas without mass separation; Mass separation can be performed using methods such as ion implantation. When this is done, the ion species to be added and their concentrations can be strictly controlled. If separation is not performed, high concentration ions can be added in a short time. Alternatively, an ion doping method may be used, in which molecular clusters are generated and ionized. A dopant may also be referred to as an ion, a donor, an acceptor, an impurity, or an element. stomach.

[0186] In addition, an element that forms oxygen vacancies is added to the layer 242, and then heat treatment is performed to form a channel. The hydrogen contained in the region 234 that functions as a formation region is captured by the oxygen vacancies contained in the layer 242. This may provide the transistor 200 with stable electrical characteristics and improve reliability. It is possible to improve the

[0187] Here, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate and reliability will decrease. In addition, there are cases where oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in region 234 be reduced as much as possible.

[0188] Therefore, as shown in FIG. 15, the insulator 250, the region 232 of oxide 230b, and the oxide In contact with the oxide 230c, more oxygen than the oxygen required for the stoichiometric composition (also called excess oxygen) is It is preferable to provide the insulator 275 containing the excess Oxygen diffuses into the region 234 of the oxide 230, causing the oxide 230 to This can reduce oxygen deficiency in the

[0189] In order to provide an excess oxygen region in the insulator 275, the insulator 273 in contact with the insulator 275 is As a result, it is preferable to form an oxide film by sputtering. By using the coating method, it is possible to form an insulator film with few impurities such as water or hydrogen. When using a sputtering method, for example, facing target sputtering It is preferable to form a film using a facing target type sputtering device. Since the surface to be coated is not exposed to the high electric field region between the targets, the surface to be coated can be Since the film can be formed with less damage from plasma, the insulating film 273 can be formed. This is preferable because it can reduce film formation damage to the oxide 230 during film formation. The film formation method using a facing target sputtering device is called VDSP (Vapor Deposition Sputtering). It can be referred to as Position SP (registered trademark).

[0190] When forming a film by sputtering, ions and sputtering gases are generated between the target and the substrate. For example, the target is connected to a power source and is given a potential E0. In addition, the substrate is given a potential E1 such as a ground potential. In addition, there is a region between the target and the substrate that has a potential E2. The magnitude relationship between the potentials is E2>E1>E0.

[0191] Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target. This causes the sputtered particles to be ejected from the target. The film is formed by the deposition of ions on the surface. The ions bounce off the target, pass through the formed film, and reach the insulating layer in contact with the surface to be coated. In addition, ions in the plasma may be trapped in the insulator 275. The ions are accelerated by the electrons and bombard the surface of the film. The ions are trapped in the insulator 275, and the area where the ions are trapped A region is formed in the insulator 275. That is, when the ions are oxygen-containing ions, This creates an excess oxygen region in the insulator 275.

[0192] By introducing excess oxygen into the insulator 275, an excess oxygen region is formed in the insulator 275. The excess oxygen in the insulator 275 is provided to the region 234 of the oxide 230, The oxygen vacancies in the oxide 230 can be compensated for.

[0193] The insulator 275 may be silicon oxide, silicon oxynitride, silicon nitride oxide, or a void-containing material. It is preferable to use silicon oxide, which has an excess of oxygen. On the other hand, compared to materials such as silicon oxynitride mentioned above, The oxide 230 is formed by forming an oxide film on the oxide 230 using a sputtering method. Therefore, even if the insulator 2 has an excess oxygen region, the excess oxygen region tends to be difficult to form. 75 is provided around the region 234 of the oxide 230, , the excess oxygen in the insulator 275 can be effectively supplied.

[0194] Furthermore, it is preferable to use aluminum oxide for the insulator 273. Aluminum oxide The hydrogen in the oxide 230 is removed by heat treatment in the state where the oxide 230 is in close proximity. In addition, a layer 242 is provided between the oxide 230 and the aluminum oxide. When the aluminum oxide layer 242 is heated, the aluminum oxide absorbs the hydrogen in the layer 242, and the hydrogen in the layer 242 is reduced. In the configuration shown in FIG. 15, the conductor 240 The aluminum oxide can absorb hydrogen from layer 242b before forming layer 242b. This reduces the hydrogen concentration in the oxide 230. By performing heat treatment in a state where the insulating material 273 is in close proximity to the oxide 230, the insulating material 273 is converted into the oxide 230. Oxygen may be supplied to the body 224 or the insulator 222 .

[0195] By combining the above configurations or the above processes, the resistance of the oxide 230 can be selectively reduced. It can be done.

[0196] That is, when forming a low resistance region in the oxide 230, a conductor that functions as a gate electrode is 260 and the insulator 275 are used as a mask, and the oxide 230 is self-aligned to have low resistance. Therefore, when multiple transistors 200 are formed at the same time, the distance between the transistors is The variation in electrical characteristics can be reduced. , determined by the width of the conductor 260 or the thickness of the insulator 275. By making this the minimum processing dimension, the transistor 200 can be miniaturized.

[0197] From the above, by selecting the range of each area appropriately, it is possible to match the requirements according to the circuit design. Therefore, a transistor having the above electrical characteristics can be easily provided.

[0198] In addition, oxide semiconductors can be deposited by sputtering or other methods, making them suitable for highly integrated semiconductors. It can be used in transistors that constitute semiconductor devices. Transistors using semiconductors have extremely low leakage current (off-state current) when they are off. Since the transistor 200 is small, a semiconductor device with low power consumption can be provided. Because the current is small, using this in semiconductor devices allows memory contents to be retained for a long period of time. That is, it is possible to perform a refresh operation without requiring a refresh operation. Since the frequency of the operation is extremely low, the power consumption of the semiconductor device can be reduced sufficiently. .

[0199] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, the fluctuation of the electrical characteristics is suppressed, the electrical characteristics are stable, and the reliability is improved. It is possible to provide a semiconductor device.

[0200] The detailed structure of the layer corresponding to layer 20 of the semiconductor device shown in this embodiment will be described below. In the following, unless otherwise specified, the detailed configuration of the transistor 700 will be described. For this, please refer to the detailed description of the configuration of the transistor 200.

[0201] As shown in FIG. 12(A) and FIG. 13(A), the conductor 203 is The conductive material 205 is extended and functions as a wiring for applying a potential to the conductive material 205. 3 is preferably embedded in the insulator 212.

[0202] Conductor 205a is oxide 230 and conductor 260a, and conductor 205b is oxide The conductor 205a is arranged so as to overlap with the conductor 230 and the conductor 260b. It is preferable that the conductor 205b is provided on the conductor 203a and in contact with the conductor 203b. The conductor 205 is preferably embedded in the insulators 214 and 216. .

[0203] Here, the conductor 260 functions as a first gate (also called a front gate) electrode. The conductor 205 may also function as a second gate (also called a back gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. By changing the threshold voltage of the transistor 200 independently of the applied potential, In particular, by applying a negative potential to the conductor 205, the transistor The threshold voltage of the transistor 200 can be made higher than 0 V, thereby reducing the off-current. Therefore, applying a negative potential to the conductor 205 increases the The drain current when the potential applied to 260 is 0V can be reduced.

[0204] Furthermore, by providing a conductor 205 on the conductor 203, a first gate electrode and a wiring The distance between the conductor 260, which functions as a In other words, the insulators 214 and 216 are disposed between the conductor 203 and the conductor 260. By providing the above, the parasitic capacitance between the conductor 203 and the conductor 260 is reduced, and the conductor 2 The dielectric strength between the conductor 260 and the insulating film 03 can be increased.

[0205] In addition, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the transistor 2 00's switching speed and make it a transistor with high frequency characteristics. In addition, by increasing the dielectric strength between the conductor 203 and the conductor 260, the transistor Therefore, the reliability of the capacitor 200 can be improved. It is preferable to make the film thickness of the conductor 203 thicker. For example, it may be extended in the channel length direction of the transistor 200 .

[0206] As shown in FIG. 12(A), the conductor 205 is made of an oxide 230 and a conductor 26. 0. The conductor 205 is arranged so as to overlap with the region 234 in the oxide 230. In particular, as shown in FIG. 13(A), the conductor 205a is oxidized. The region 234a of the object 230 extends to an area outside the end portion in the channel width direction. That is, the conductor 205 is preferably formed on the side surface of the oxide 230 in the channel width direction. It is preferable that the conductive material 260a and the conductive material 260b are overlapped with each other via an insulator. (A) shows the transistor 200a, but the same applies to the transistor 200b. be.

[0207] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and the oxide 2 The channel forming region formed in 30 can be covered.

[0208] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as an electrode, causes the channel forming region 234 In this specification, the first gate electrode and the second gate electrode can be electrically surrounded by the first gate electrode. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region This is called the surrounded channel (S-channel) structure.

[0209] The conductor 205 is in contact with the inner walls of the openings of the insulators 214 and 216. A conductor is formed, and a second conductor is further formed inside. The height of the upper surface of the second conductor and the height of the upper surface of the insulator 216 can be made to be approximately the same. In the transistor 200, the first conductor of the conductor 205 and the second conductor of the conductor 205 Although the present invention is not limited to a stacked structure of dielectric bodies, For example, the conductor 205 may be configured as a single layer or a laminated structure of three or more layers.

[0210] Here, the first conductor of the conductor 205 or the conductor 203 is a hydrogen atom, a hydrogen molecule, Water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. The conductive material has the function of suppressing the diffusion of impurities (the impurities are difficult to penetrate). Alternatively, oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.) It is possible to use a conductive material that has a function of suppressing the diffusion of oxygen (i.e., the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen is The function is to suppress the diffusion of either or both of the impurities and the oxygen.

[0211] The first conductor of the conductor 205 or the conductor 203 has a function of suppressing the diffusion of oxygen. As a result, the second conductor of the conductor 205 or the conductor 203 is oxidized, and the conductivity decreases. As a conductive material having a function of suppressing oxygen diffusion, For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide may be used. Therefore, the first conductor of the conductor 205 or the conductor 203 is preferably The conductive material may be a single layer or a multilayer. , conductor 203, and conductor 205 to prevent diffusion to the transistor 200 side. It can be controlled.

[0212] The second conductor of the conductor 205 is mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material having a single layer of the second conductor of the conductor 205. However, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. The above may be laminated.

[0213] In addition, the second conductor of the conductor 203 functions as a wiring, so that the second conductor of the conductor 205 It is preferable to use a conductor having a higher conductivity than the conductor of the present invention. For example, copper or aluminum A conductive material containing silicon as a main component can be used. The body may have a laminated structure, for example, a laminate of titanium, titanium nitride and the above conductive material. That's fine.

[0214] In particular, it is preferable to use copper for the conductor 203. Copper has low resistance, so it is suitable for wiring etc. On the other hand, copper is easily diffused, so by diffusing into the oxide 230, This may degrade the electrical characteristics of the transistor 200. For this purpose, materials such as aluminum oxide or hafnium oxide, which have low copper permeability, should be used. This can suppress the diffusion of copper.

[0215] In addition, in FIG. 12 and the like, the transistor 200a and the transistor 200b each have a buffer. Conductors 205a and 205b functioning as gates are provided. The semiconductor device is not limited to this. When it is not necessary to control the back gates independently in 0b, the transistors can be connected in the same conductive layer. The back gate of the transistor 200a can be used as the back gate of the transistor 200b. For example, as shown in FIG. 21, instead of the conductor 205a and the conductor 205b, The conductor 205c may be provided as a buffer for the transistor 200a. It functions as a gate for the gate of transistor 200b and a back gate for transistor 200c. When the back gates of the transistors 200a and 200b are provided separately, To pattern the back gates, it is necessary to provide a gap between the back gates. By providing the back gates of the transistors 200a and 200b in the same conductive layer, Therefore, there is no need to provide such a gap. This reduces the area occupied by the semiconductor device according to this embodiment, thereby enabling a higher integration density. In addition, a conductor 203c that functions as the wiring BGL may be provided below the conductor 205c. The conductor 205c has the same configuration as the conductor 205, and the description of the conductor 205 is referred to. The conductor 203c has the same structure as the conductor 203, and The description of the body 203 can be taken into consideration.

[0216] In the semiconductor device shown in FIG. 21, one of the side surfaces of the conductor 205c is on the side of the insulator 275a. One of the sides of the conductor 205c roughly overlaps one of the sides of the insulator 275b. However, the semiconductor device according to this embodiment is not limited to this arrangement. For example, as shown in FIG. 22, one of the side surfaces of the conductor 205c is adjacent to the side surface of the conductor 260a. One side of the conductor 205c roughly overlaps one side of the conductor 260b. In other words, in FIG. 22, the transistor 20 The length of the conductor 205 in the channel length direction is shorter than that of the conductor 205c shown in FIG. 2, the provision of the conductor 205c makes it possible to reduce the a and transistor 200b, the distance between one side of conductor 205c and region 231a, The distance between one side of the conductor 205c and the region 231c is increased, and This can reduce the parasitic capacitance and leakage current.

[0217] The conductor 205, the insulator 214, and the insulator 216 do not necessarily have to be provided. In this case, a part of the conductor 203 can function as a second gate electrode.

[0218] Insulators 210, 214, and 282 are insulated from impurities such as water or hydrogen. Barrier insulation that prevents contamination from the substrate side or the insulator 284 side from entering the transistor 200 Therefore, the insulator 210, the insulator 214, and the insulator The inductor 282 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (N2 O, NO, NO2, etc.), and copper atoms. It is preferable to use an insulating material that is difficult for substances to permeate. The film has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the film has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use an insulating material.

[0219] For example, aluminum oxide or the like is used as the insulators 210 and 282. It is preferable to use silicon nitride or the like as the body 214. This allows hydrogen, water, etc. Impurities diffuse from the substrate side to the transistor 200 side through the insulators 210 and 214. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from Diffusion toward the substrate side beyond 210 and insulator 214 can be suppressed. impurities such as hydrogen and water are introduced into the transistor 20 from the insulator 284 side rather than the insulator 282 side. It is possible to suppress diffusion to the 0 side.

[0220] In addition, by forming a structure in which the conductor 205 is laminated on the conductor 203, the conductor An insulator 214 may be provided between the body 203 and the conductor 205. Even if a metal that easily diffuses, such as copper, is used for the second conductor 3, the insulator 214 may be made of silicon nitride. By providing a barrier layer or the like, the metal is prevented from diffusing into layers above the insulator 214. It is possible.

[0221] In addition, the insulating layer 212, the insulating layer 216, the insulating layer 280, and the insulating layer 281 function as an interlayer film. Preferably, insulator 284 has a lower dielectric constant than insulator 210 or insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wiring can be reduced. .

[0222] For example, the insulators 212, 216, 280, and 284 may be made of an acid. silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide , tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate A single layer of insulator such as Ba,SrTiO3 or (Ba,Sr)TiO3 (BST) Alternatively, these insulators may be formed of, for example, aluminum oxide. , bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide Alternatively, these insulating materials may be added. The insulator may be silicon oxide, silicon oxynitride or silicon nitride. Silicon may also be used in a laminated form.

[0223] The insulators 220, 222, and 224 function as gate insulators. In addition, the insulator 724 provided in the transistor 700 is also a gate insulator, similar to the insulator 224. In this embodiment, the insulator 224 and the insulator 72 4 are separated, but the insulator 224 and the insulator 724 may be connected.

[0224] Here, the insulator 224 in contact with the oxide 230 has more oxygen than the stoichiometric composition. It is preferable to use an insulator that contains a large amount of oxygen. It is preferable that the insulator containing such excess oxygen is formed in the oxide 230. By providing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced, and the signal quality of the transistor 200 is improved. The reliability can be improved.

[0225] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use oxide materials. Oxides that release oxygen when heated are called TDS (Th Thermal Desorption Spectroscopy (DSS) analysis revealed that the oxygen atoms The converted amount of oxygen desorption is 1.0 x 10 18 atoms / cm 3 or more, preferably 1.0 x10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / c m 3 , or 3.0 × 10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film during the TDS analysis is 100°C or higher and 700°C or lower. The temperature range is preferably from 0°C to 400°C.

[0226] Also, if the insulator 224 has an excess oxygen region, the insulator 222 may be oxygen-rich (e.g., It has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the oxygen is permeable It is preferable that

[0227] The insulator 222 has a function of suppressing the diffusion of oxygen, and therefore the excess oxygen contained in the insulator 224 is prevented. The oxygen in the excess oxygen region is efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. In addition, the conductor 205 can be made to react with the oxygen in the excess oxygen region of the insulator 224. It is possible to suppress the reaction.

[0228] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or zinc oxide. lead zirconate titanate (PZT), strontium titanate (SrTiO3 ) or (Ba,Sr)TiO3 (BST), which are so-called high-k materials It is preferable to use the body in a single layer or a multilayer structure. As this progresses, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material as an insulator that functions as a thermal insulator, This makes it possible to reduce the gate potential during transistor operation.

[0229] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is less likely to permeate). ) Insulating materials containing oxides of one or both of aluminum and hafnium It is recommended to use an insulator containing oxides of either or both aluminum and hafnium. The insulators include aluminum oxide, hafnium oxide, aluminum and hafnium. It is preferable to use hafnium oxide (hafnium aluminate) or the like. When the insulator 222 is formed using the oxide 230, the insulator 222 can prevent oxygen from being released from the oxide 230 and A layer that suppresses the intrusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. It functions as such.

[0230] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. tungsten oxide, yttrium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0231] Furthermore, the insulator 220 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are thermally stable and therefore suitable as high-k materials for dielectric and dielectric 2. By combining with 20, it is possible to obtain a thermally stable laminated structure with a high relative dielectric constant. do.

[0232] The insulators 220, 222, and 224 each have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, but may be made of different materials. It may have a laminated structure.

[0233] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0234] The oxide 230 has a layered structure made of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. Things can be used.

[0235] The energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the conduction band minimum of 0b is higher than that of the oxide. The electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. It is preferable that

[0236] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and the The conduction band edge at the junction of the oxide 230c and the silicon dioxide 230c changes continuously or is called a continuous junction. In order to achieve this, the interface between the oxide 230a and the oxide 230b , and the defect levels of the mixed layer formed at the interface between oxide 230b and oxide 230c. It is better to lower the density.

[0237] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen (as the main component), a mixed layer with low defect level density can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide The oxide 230a and the oxide 230c include In-Ga-Zn oxide, Ga-Zn oxide, Gallium oxide or the like may be used.

[0238] At this time, the main path of the carriers is the oxide 230b. By configuring 30c as described above, the interface between oxide 230a and oxide 230b and the oxide This can reduce the defect state density at the interface between the oxide 230b and the nitride 230c. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 has high A large on-current can be obtained.

[0239] The oxide 230 has a region 231, a region 232, and a region 234. At least a part of the region 231 has an area adjacent to the insulator 273. 2 has at least an area that overlaps with the insulator 275.

[0240] When the transistor 200 is turned on, the region 231a or the region 231b becomes a solid state. On the other hand, at least a portion of region 234 functions as a source region or a drain region. The region 232 functions as a channel forming region. This increases the on-state current of the transistor 200 and reduces the leakage current when the transistor 200 is not conducting. The current (off-state current) can be reduced.

[0241] In the transistor 200, the region 232 is provided to define the source region and the drain region. A high resistance region is formed between the region 231 that functions as a channel region and the region 234 where the channel is formed. is not formed, the on-state current and mobility of the transistor can be increased. In addition, by providing the region 232, the source region and the drain region are separated in the channel length direction. Since the gate electrode region and the first gate electrode (conductor 260) do not overlap, unnecessary capacitance is eliminated between them. Furthermore, by providing the region 232, it is possible to prevent leakage when the device is not electrically conductive. The current can be reduced.

[0242] In other words, by selecting the range of each area appropriately, you can create a circuit that meets your requirements. It is possible to easily provide a transistor having the electrical characteristics. For example, transistor 2 00 has a small off-state current, and the transistor 700 has a large on-state current. It can be made into.

[0243] The oxide 230 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). For example, the metal oxide that forms the region 234 is a band oxide. It is preferable to use a material with a gap of 2 eV or more, preferably 2.5 eV or more. As shown in Fig. 1, by using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. can be reduced.

[0244] A transistor using an oxide semiconductor has extremely low leakage current in the off state. Therefore, a semiconductor device with low power consumption can be provided. Since the film can be formed using the above, it can be used for transistors that constitute highly integrated semiconductor devices. This can be done.

[0245] The insulator 250 functions as a gate insulator. The insulator 250a is the oxide 230ca. Preferably, the insulator 250b is disposed on the top surface of the oxide 230cb. The insulator 250 is preferably formed using an insulator that releases oxygen when heated. For example, in thermal desorption spectroscopy (TDS), the amount of oxygen converted to oxygen molecules is The amount of desorption is 1.0×10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 at oms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 , or 3 .0×10 20 atoms / cm 3 It is an oxide film that is The surface temperature of the film is preferably in the range of 100°C or higher and 700°C or lower.

[0246] Specific examples of the insulator 250 include silicon oxide having excess oxygen, silicon oxynitride, Silicon oxynitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon Silicon, carbon and nitrogen doped silicon oxide, and silicon oxide with vacancies are used In particular, silicon oxide and silicon oxynitride are stable to heat. preferable.

[0247] An insulator 250 that releases oxygen when heated is attached to the top surface of the oxide 230c. By providing the insulating layer 250, oxygen can be effectively transferred from the insulating layer 250 to the region 234 of the oxide 230b. In addition, like the insulator 224, water or hydrogen in the insulator 250 can be supplied. It is preferable that the concentration of impurities such as Zn, Ni, and Al is reduced. It is preferable to set it to 20 nm or less.

[0248] In addition, in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230, The metal oxide 252 may then be provided. The metal oxide 252 may then be provided to remove oxygen from the insulator 250. It is preferable to suppress the diffusion of oxygen. , the diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. In addition, the amount of excess oxygen supplied to the conductor 2 can be prevented from decreasing. It can suppress the oxidation of 60.

[0249] The metal oxide 252 may function as a part of the first gate. The oxide semiconductor that can be used as the oxide 230 is used as the metal oxide 252. In this case, the conductor 260 is formed by sputtering, and the metal oxide The electrical resistance of the oxide 252 can be reduced to make it a conductor. e Conductor) electrode.

[0250] The metal oxide 252 may also function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide The material 252 is preferably a metal oxide, which is a high-k material having a high dielectric constant. This laminated structure is stable against heat and has a high dielectric constant. Therefore, the gate voltage applied during transistor operation can be adjusted while maintaining the physical film thickness. In addition, the equivalent oxide thickness ( It is possible to reduce the thickness of the EOT.

[0251] Although the metal oxide 252 in the transistor 200 is shown as a single layer, it may have a stacked structure of two or more layers. For example, a metal oxide that functions as part of the gate electrode and a gate insulator Alternatively, a metal oxide that functions as a part of the insulating layer may be laminated.

[0252] When the metal oxide 252 functions as a gate electrode, the conductor 260 Therefore, the on-state current of the transistor 200 can be improved without weakening the influence of these electric fields. Alternatively, if it functions as a gate insulator, it can be made of an insulator 250 and a metal oxide 252. The physical thickness of the oxide 230 keeps the distance between the conductor 260 and the oxide 230. Therefore, the leakage current between the insulator 260 and the oxide 230 can be suppressed. 250 and the metal oxide 252 are laminated to form a conductor 260 and an oxide 2 30, and the electric field strength from the conductor 260 to the oxide 230. It can be easily adjusted as needed.

[0253] Specifically, by reducing the resistance of an oxide semiconductor that can be used for the oxide 230, Metal oxide 252 can be used. Alternatively, hafnium, aluminum, gallium Sm, yttrium, zirconium, tungsten, titanium, tantalum, nickel, gel Metals containing one or more of the following: ammonium, magnesium, etc. An oxide can be used.

[0254] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. It is preferable because it is difficult to crystallize. Note that the metal oxide 252 is not an essential component. It may be designed appropriately depending on the transistor characteristics.

[0255] The conductor 260a functioning as the first gate electrode is made up of the conductor 260aa and the conductor The conductive layer 260aa has a conductive layer 260ab on the top surface of the conductive layer 260aa. The conductive layer 260aa functions as a first gate electrode. The body 260b has a conductor 260ba and a conductor 260bb on the conductor 260ba. The conductor 260a is composed of hydrogen atoms, hydrogen molecules, water, and the like, similar to the first conductor of the conductor 205. molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities. Conductive material that has the function of suppressing the diffusion of (for example, at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a non-reactive material.

[0256] The conductor 260a has a function of suppressing the diffusion of oxygen, and thus the insulator 250 and The excess oxygen in the metal oxide 252 oxidizes the conductor 260b, reducing its conductivity. The conductive material having the function of suppressing oxygen diffusion is: For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide can be used. preferable.

[0257] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material. It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b has a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0258] As shown in FIG. 13A, the conductor 205 is formed in the oxide 230 in the channel width direction. When the conductor 260 extends to a region outside the end, the conductor 260 is insulated from the insulator in that region. It is preferable that the oxide 230 overlaps with the conductor 205 via the oxide 250. On the outer side of the side surface, the conductor 205, the insulator 250, and the conductor 260 form a laminated structure. It is preferable to form

[0259] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and the oxide 2 The channel forming region formed in 30 can be covered.

[0260] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as an electrode, causes the channel forming region 234 can be electrically surrounded.

[0261] In addition, an insulator 270a functioning as a barrier film is formed on the conductor 260ab. An insulator 270b may be disposed on the insulating layer 270bb to function as a barrier film. is an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. This prevents the conductor 260 from being oxidized by oxygen diffusing from above the insulator 270. In addition, it is possible to suppress the diffusion of water or hydrogen from above the insulator 270. The impurities are mixed into the oxide 230 through the conductor 260 and the insulator 250. can be suppressed.

[0262] In addition, an insulator 271a, which functions as a hard mask, is formed on the insulator 270a. Preferably, an insulator 271b is placed on 70b to function as a hard mask. By providing the insulator 271, the side surface of the conductor 260 is approximately vertical when the conductor 260 is processed. Specifically, the angle between the side surface of the conductor 260 and the surface of the substrate is preferably set to 75 degrees or more and 100 degrees or less. Preferably, the angle can be set to 80 degrees or more and 95 degrees or less. By this process, the insulator 275 to be formed next can be formed into a desired shape.

[0263] The insulator 271 has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. By using an insulating material having the above structure, the insulating material may also function as a barrier film. In this case, the insulator 270 may not be provided.

[0264] The insulator 275a, which functions as a buffer layer, is formed on the side of the oxide 230ca, the insulator 250 a side of the metal oxide 252a, a side of the conductor 260a, and a side of the insulator 270a. The insulator 275b, which functions as a buffer layer, is provided in contact with the side surface of the oxide 230. a side of the insulator 250b; a side of the metal oxide 252b; and a side of the conductor 260b. , and is provided in contact with the side surface of the insulator 270b.

[0265] The insulator 275a is made of an oxide 230ca, an insulator 250a, a metal oxide 252a, and a conductor. An insulating film is formed to cover the insulating film 260a, the insulating film 270a, and the insulating film 271a. It can be formed by anisotropically etching the film (for example, dry etching process). The insulator 275b can be formed at the same time as the insulator 275a.

[0266] For example, the insulator 275 may be silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and and silicon oxide with nitrogen added, silicon oxide or resin with pores. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, silicon oxide and silicon oxide with vacancies can be easily oxidized with excess oxygen in later processes. This is preferable because it allows the formation of a region.

[0267] The insulator 275 preferably has an excess oxygen region. The insulator 275 is set in contact with the oxide 230c and the insulator 250. By doing so, oxygen is effectively supplied from the insulator 250 to the region 234 of the oxide 230b. In addition, the concentration of impurities such as water or hydrogen in the insulator 275 is reduced. It is preferable.

[0268] It is preferable to use an insulator with a large relative dielectric constant for the insulator 130, such as the insulator 222. For example, one of aluminum and hafnium may be used. Insulators containing oxides of either or both of aluminum and hafnium can be used. Examples of insulators containing oxides of one or both of these include aluminum oxide, hafnium oxide, and aluminum. Use oxides containing aluminum and hafnium (hafnium aluminate) The insulator 130 may have a single layer structure or a multilayer structure. The insulator 130 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon oxide, aluminum oxide, hafnium oxide, aluminum and hafnium It is also possible to select two or more layers from oxides (hafnium aluminate) and create a laminated structure. For example, hafnium oxide, aluminum oxide, and hafnium oxide can be sequentially deposited by the ALD method. It is preferable to form a layer structure by depositing a hafnium oxide and aluminum oxide film on the surface of the substrate. The thickness of each layer is set to 0.5 nm or more and 5 nm or less. The capacitance element 100 can have a large capacitance value and a small leakage current.

[0269] As shown in FIGS. 12(A) and 12(B), in a top view, the side surface of the insulator 130 is For example, the insulator 130 may be aligned with the side of the insulating material 20, but is not limited to this. Without forming a turn, the insulator 130 is connected to the transistors 200a, 200b, and The transistor 700 may be covered.

[0270] The conductor 120 is made of a conductive material mainly composed of tungsten, copper, or aluminum. Although not shown, the conductor 120 may have a laminated structure, for example. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0271] 14, the insulator 130a and the conductor 120a are formed by the oxide 230. It is preferable that the oxide 230 is provided so as to cover the side surface. Since the capacitor element 100a can be formed in the side direction of the capacitor element 100a, The capacitance per unit area can be increased. The insulator 130b and the conductor 120b of the capacitor element 100a are also and preferably provided in the same manner as the conductor 120a.

[0272] In addition, the insulator 130 and the conductor 120 are provided so that a part of them overlaps with the insulator 271. As a result, the insulating layer 275 of the region 231a (region 231c) The insulator 275 can be formed on the edge of the insulating film 275. Therefore, the parasitic capacitance of the conductors 120 and 260 can be reduced.

[0273] The insulator 273 is made up of the insulators 275a, 275b, 271a, and 271b. , layer 742, insulator 775, insulator 771, conductor 120a, and conductor 120b. It is preferable that the insulator 273 be formed by a sputtering method. 275 and insulator 775. Oxygen can be supplied from the excess oxygen region into oxide 230 and oxide 730 . Also, an insulator 273 is formed on the layer 242c of the oxide 230 and the layer 742 of the oxide 730. By providing the insulating layer 273, hydrogen in the oxide 230 and the oxide 730 is extracted to the insulator 273. It can be done.

[0274] For example, the insulator 273 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or ma It is possible to use a metal oxide containing one or more metals selected from magnesium, etc. can.

[0275] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the thickness is increased, the diffusion of hydrogen and nitrogen can be suppressed.

[0276] Further, an insulator 274 is provided on the insulator 273. The insulator 274 has a barrier property. For example, the insulator 274 may be a film with a reduced hydrogen concentration. Silicon oxide oxynitride, silicon nitride, silicon oxide doped with fluorine, etc. By providing an insulator 273 having a barrier property and an insulator 274 having a barrier property, It is possible to suppress the diffusion of impurities from other structures into the transistor 200. do.

[0277] It is also preferable to provide an insulator 280 that functions as an interlayer film on the insulator 274. The insulator 280, like the insulator 224, has a low impurity concentration such as water or hydrogen in the film. It is preferable that the insulator 280 has a similar insulating layer as the insulator 210. The insulator 282 may be formed by sputtering. In addition, when the insulator 282 is provided, the impurities of the insulator 273 can be reduced. Alternatively, either or both of the insulating material 274 may be omitted. An insulator 284 similar to insulator 280 may be provided on body 282 .

[0278] Also, the insulators 284, 282, 280, 274, and 27 3, the conductors 240a, 240b, 240c, and conductor 74 are inserted into the openings formed in the The conductor 240a and the conductor 240b are arranged. The conductors 240b and 240c are disposed opposite each other with the conductor 260a in between. The conductor 740a and the conductor 740b are disposed opposite each other with the conductor 760 in between. The conductors 240a, 240b, 240c, and 240d are disposed opposite each other. The upper surfaces of the body 740a and the conductor 740b are flush with the upper surface of the insulator 284. Good too.

[0279] In addition, the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and The conductor 240b is formed in contact with the inner wall of the opening of the insulator 275. A region 231b of the oxide 230 is located in at least a portion of the region, and a conductor 240b is located in the region 231b. The conductor 740a and the conductor 740b are in contact with the region 231b. In addition, the conductor 240a contacts the conductor 120a, and the conductor 240c contacts the conductor 120b. do.

[0280] As shown in FIG. 12(B) and FIG. 15, the conductor 240b is connected to the conductor 260a and the conductor 260b. 0b. Here, the conductor 240b is disposed between the insulator 275a and the insulator 275b. It is preferable that the conductive layer has a region in contact with one or both of the side surfaces of b. In the opening where the insulator 240b is embedded, the insulator 273 is sandwiched between the insulator 275a and the insulator 240b. It is preferable to have an area that contacts one or both of the sides of 75b.

[0281] To form an opening for embedding the conductor 240b, the insulator 280, the insulator 274, the insulator When forming the opening 273, the etching rate of the insulator 275 is higher than the etching rate of the insulator 273. It is preferable to set the opening condition to be significantly smaller than the etching rate of the insulator 275. is set to 1, the etching rate of the insulator 273 is preferably 5 or more, more preferably 10 The insulating material used for the insulator 275 has the above etching rate. The etching conditions and the insulating material used as the insulator 273 are adjusted to satisfy the above requirements. For example, the insulating material used for the insulator 275 may be selected from the above-mentioned materials. In addition to the insulating material described above, any insulating material that can be used for the insulator 270 may be used. .

[0282] In addition, in the case where the insulators 273 and 274 are not provided, the shape of the openings During the formation, the etching rate of the insulator 275 is significantly higher than the etching rate of the insulator 280. It is preferable to set the opening condition to be very small. If the etching rate of the insulator 275 is 1, The etching rate of the insulator 280 is preferably 5 or more, and more preferably 10 or more.

[0283] By forming an opening in which the conductor 240b is embedded in this way, insulation is prevented when the opening is formed. The body 275a and the insulator 275b function as an etching stopper, so that the opening It is possible to prevent the electric current from reaching the conductor 260a and the conductor 260b. 240b and the opening into which it is embedded can be formed in a self-aligned manner. As shown in FIG. 23, the conductive body 240a, the conductive body 240b, and the conductive body 240c are formed. Even if the opening is formed shifted toward the transistor 200b, the conductor 240b and the conductor 260 b is not contacted. Also, the channel of the transistor 200 in the opening forming the conductor 240b By making the width in the longitudinal direction larger than the distance between the insulators 275a and 275b, the As shown, even if the opening is misaligned, the conductor 240b is sufficiently connected to the layer 242b. Here, the insulators 271a and 271b can be contacted. The insulators 271a and 271b are also made of the same insulating material as the insulator 275. It may also function as an etching stopper.

[0284] Therefore, the contact portions (conductors 200a and 200b) of the transistors 200a and 200b 40b), the gate of transistor 200a, and the gate of transistor 200b. The alignment margin can be widened, and the spacing between these components can be designed to be small. In this way, miniaturization and high integration of the semiconductor device can be achieved. .

[0285] As shown in FIG. 13B, the conductor 240b is connected to the oxide 2 through the layer 242b. In particular, the conductor 240b overlaps the side of the oxide 230. On the side that intersects with the width direction of the sheet, the side on the A5 side and / or the side on the A6 side In this way, the conductor 240b overlaps the source region or the drain region. In the region 231b, which is the conductive region, the side surface of the oxide 230 is overlapped. The contact area between the body 240b and the transistor 200 is not increased. The contact area of ​​the conductor 240b is increased, thereby reducing the contact resistance between the conductor 240b and the transistor 200. This allows for miniaturization of the source and drain electrodes of the transistor. In FIG. 13B, the conductor 240b The length of the oxide 230 in the channel width direction is larger than the length of the oxide 230 in the channel width direction. The semiconductor device shown in this embodiment is not limited to this. For example, Even if the length in the channel width direction is approximately the same as the length of the oxide 230 in the channel width direction, good.

[0286] The conductor 740a and the conductor 740b have the same configuration as the conductor 240b. It is possible.

[0287] The conductor 240 and the conductor 740 are mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material that has a high conductivity. may have a laminated structure.

[0288] Here, for example, insulator 284, insulator 282, insulator 280, insulator 274, and When forming the opening in the insulator 273, the oxide 230 is formed in the low-resistance region 231. In some cases, regions are removed, exposing unthinned oxide 230. The conductor 240 in contact with the oxide 230 (hereinafter also referred to as the first conductor of the conductor 240) The conductor used in the above method is a metal film, a nitride film containing a metal element, or a nitride film containing a metal element. It is preferable to use an oxide film. That is, the first oxide 230 and the conductor 240 are not made to have a low resistance. When the metal compound or oxide 230 comes into contact with the conductor, oxygen vacancies are formed in the metal compound or oxide 230, and the oxide Therefore, the region 231 of the conductor 240 in contact with the first conductor becomes low in resistance. By reducing the resistance of the oxide 230, the contact resistance between the oxide 230 and the conductor 240 can be reduced. Therefore, the first conductor of the conductor 240 can be, for example, aluminum. It is preferable that the alloy contains a metal element such as aluminum, ruthenium, titanium, tantalum, or tungsten. The conductor 740 may have a similar structure.

[0289] In addition, when the conductor 240 and the conductor 740 are formed into a layered structure, the insulator 284 and the insulating The conductors in contact with the body 282, the insulator 280, the insulator 274, and the insulator 273 are provided with conductive Similar to the first conductor of the body 205, the function of suppressing the permeation of impurities such as water or hydrogen. It is preferable to use a conductive material having the following properties. For example, tantalum, tantalum nitride, titanium It is preferable to use titanium nitride, ruthenium, or ruthenium oxide. Conductive materials that have the function of suppressing the permeation of impurities such as hydrogen can be used in single or multilayer configurations. By using such a conductive material, hydrogen, water, etc. can be easily transported from the upper layer above the insulator 284. The impurities penetrate the oxide 230 and the oxide 73 through the conductor 240 and the conductor 740. It is possible to prevent mixing with 0.

[0290] In the openings where the conductors 240 and 740 are provided, the inner walls of the openings are The insulating material may be coated with an insulating material that has a barrier property against oxygen and hydrogen. As an insulator having a barrier property against hydrogen and silicon dioxide, an insulator similar to the insulator 214 may be used. It is preferable to use, for example, aluminum oxide. Impurities such as hydrogen and water are transferred from the conductor 240 and the conductor 740 to the oxide 2 30 and the oxide 730. For example, by using the ALD method or CVD method, a film with good coverage can be formed. Cut.

[0291] Although not shown, a metal layer is provided in contact with the upper surfaces of the conductor 240 and the conductor 740 and functions as a wiring. Conductors that function as wiring may be arranged. Conductors that function as wiring may be made of tungsten, copper, or It is preferable to use a conductive material containing aluminum as the main component. Alternatively, it may have a laminated structure, for example, a laminate of titanium, titanium nitride and the above conductive material. The conductor may be embedded in an opening provided in an insulator, similar to the conductor 203. It may be formed so as to be fitted in place.

[0292] The insulator 150 may be provided on the insulator 284. The insulator 150 can be provided using the same material as the insulator 150. It may also function as a planarizing film that covers the shape.

[0293] It is also preferable to provide the conductor 112 in an opening formed in the insulator 150. 112 functions as wiring for the transistor 200, the transistor 700, the capacitor element 100, etc. It works.

[0294] The conductor 112 may be made of molybdenum, titanium, tantalum, tungsten, aluminum, or copper. a metal film containing an element selected from the group consisting of chromium, neodymium, and scandium, or Metal nitride films containing tantalum nitride (tantalum nitride film, titanium nitride film, molybdenum nitride film, titanium nitride film) Alternatively, indium tin oxide, tungsten oxide, etc. may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide, titanium oxide, indium tin oxide, indium zinc oxide, Conductive materials such as indium tin oxide doped with silicon oxide can also be applied.

[0295] 9, the conductor 112 may have a laminated structure of two or more layers. A conductor having barrier properties and a conductor having high conductivity are placed between the conductor having barrier properties and the conductor having high conductivity. A conductor having high adhesiveness may be formed on a conductor having high adhesiveness. However, the present invention is not limited to this, and may be, for example, a single-layer structure.

[0296] By forming the semiconductor device described in the above embodiment mode with the above structure, it is possible to It is possible to achieve miniaturization and high integration of semiconductor devices, while also complying with process rules for the next generation and beyond. Cut.

[0297] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices. Unless otherwise specified, the materials that can be used for the transistor 200 are It can be used for the transistor 700.

[0298] The following materials are deposited by sputtering, chemical vapor deposition (CVD), Vapor Deposition (Vapor Deposition), Molecular Beam Epitaxy (MBE) Microbeam Epitaxy (Pulse Laser Deposition (PLD) d Laser Deposition) method or Atomic Layer Deposition (ALD) method This can be done using a method such as Layer Deposition.

[0299] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0300] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can suppress plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage does not occur. In addition, the thermal CVD method does not require the use of a metal oxide film, which increases the yield of semiconductor devices. Since no plasma damage occurs inside the film, a film with few defects can be obtained.

[0301] The ALD method is also a film formation method that can suppress plasma damage to the workpiece. Therefore, a film with few defects can be obtained. For this reason, films formed by ALD are more susceptible to impurities than those formed by other film formation methods. In some cases, the film contains more impurities such as carbon than the film formed by the method described above. The quantitative determination of This can be done using endoscopic imaging.

[0302] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0303] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0304] The constituent material may be processed using a lithography method. Dry etching or wet etching can be used. This method is suitable for microfabrication.

[0305] In the lithography method, first, the resist is exposed to light through a mask. The areas are removed or left behind using a developer to form a resist mask. By etching through a resist mask, conductors, semiconductors, insulators, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the pattern is written directly on the resist, so the above-mentioned resist exposure mask is not required. The resist mask is used for dry etching such as ashing, and is also used for wet etching. Etching is performed, dry etching is performed followed by wet etching, or can be removed by wet etching followed by dry etching, etc. Cut.

[0306] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film that will be the hard mask material is formed on the constituent material. Then, a resist mask is formed on the hard mask, and the hard mask material is etched. A hard mask of the desired shape can be formed. The etching of the constituent material is performed in a resist pattern. This may be done after removing the resist mask, or may be done with the resist mask left in place. In the latter case, the resist mask may disappear during etching. After etching, the hard mask may be removed by etching. If there is no effect on the subsequent process or if it can be used in the subsequent process, it is not necessary to remove the hard mask. There's no need to.

[0307] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0308] <<Substrate>> The substrate on which the transistor 200 and the transistor 700 are formed may be, for example, an insulating substrate. An insulating substrate may be, for example, a glass substrate. Glass substrate, quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia Semiconductor substrates include, for example, silicon, Semiconductor substrates such as germanium, silicon carbide, silicon germanium, or gallium arsenide Compound semiconductor substrates made of gallium oxide, indium phosphide, zinc oxide, and gallium oxide are also available. Furthermore, the semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (S Silicon-on-insulator (Si-on-insulator) substrates are available. Conductive substrates include graphite. Substrates include metal substrates, alloy substrates, conductive resin substrates, etc. Or, metal nitride substrates There are also substrates with conductive or semiconducting layers on insulating substrates. a substrate having a semiconductor substrate with a conductor or insulator provided thereon; a substrate having a semiconductor substrate with a conductor or insulator provided thereon; There are substrates on which semiconductors or insulators are provided, or elements are provided on these substrates. The elements provided on the substrate may include a capacitor element, a resistor element, a switch element, and the like. These include transistors, light-emitting elements, and memory elements.

[0309] A flexible substrate may be used as the substrate. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is peeled off. There is also a method of separating the substrate and transferring it to a flexible substrate. It is preferable to provide a release layer between the substrate and the transistor. The substrate may also have flexibility. The plate may have the property of returning to its original shape when the bending or stretching is stopped, or The substrate may have a property of not returning to its original shape. Preferably, 10 μm or more and 500 μm or less, and more preferably, 15 μm or more and 300 μm or less By thinning the substrate, the semiconductor device having the transistor can be manufactured lighter. Furthermore, by making the substrate thinner, it is possible to achieve stretchability even when glass or other materials are used. Some have the property of returning to their original shape when bending or pulling is stopped. Therefore, it is necessary to reduce the impact that is applied to the semiconductor device on the board when it is dropped. That is, a robust semiconductor device can be provided.

[0310] The flexible substrate may be made of, for example, a metal, an alloy, a resin, or glass, or any of these. These fibers can be used as the substrate. A flexible substrate with a lower linear expansion coefficient is more environmentally friendly. The substrate that is flexible is preferably a substrate having a linear expansion coefficient of 0.05 to 0.15. 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less As the resin, for example, polyester, polyolefin, polyamide ( Nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid has a low coefficient of linear expansion and is therefore suitable for use as a flexible substrate.

[0311] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0312] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0313] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples of suitable oxides include oxynitrides with hafnium or nitrides with silicon and hafnium.

[0314] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Examples include silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resin. do.

[0315] In particular, silicon oxide and silicon oxynitride are thermally stable. For example, by combining it with resin, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon), Polyimide, polycarbonate, acrylic, etc. For example, silicon oxide and silicon oxynitride can be combined with insulators with high dielectric constants. By doing so, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant.

[0316] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the This can be done.

[0317] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon nitride oxide, silicon nitride, etc. can be used. .

[0318] For example, the insulator 273 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or ma It is possible to use a metal oxide containing one or more metals selected from magnesium, etc. can.

[0319] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the hafnium oxide is used, it is possible to suppress the diffusion of hydrogen and nitrogen. Although the barrier properties are lower than those of aluminum oxide, the barrier properties can be improved by increasing the film thickness. Therefore, by adjusting the thickness of the hafnium oxide film, it is possible to The amount of addition can be adjusted appropriately.

[0320] For example, the insulator 224 and the insulator 250, which function as part of the gate insulator, may be formed by excess It is preferable to use an insulator having an oxygen region. For example, silicon oxide having an excess oxygen region. By making the silicon or silicon oxynitride contact with the oxide 230, the oxide 230 The oxygen deficiency can be compensated for.

[0321] Also, for example, in the insulator 222 that functions as part of the gate insulator, aluminum The insulator may include one or more oxides of aluminum, hafnium, and gallium. In particular, insulators containing oxides of either or both aluminum and hafnium Examples include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use a material such as hafnium aluminate.

[0322] For example, the insulator 220 may be made of silicon oxide or silicon oxynitride, which is stable against heat. It is preferable to use a film that is stable against heat and has a high dielectric constant as the gate insulator. By using a laminated structure with a thin film, the equivalent oxide thickness of the gate insulator can be reduced while maintaining the physical film thickness. It is possible to reduce the EOT.

[0323] By using the above stacked structure, the on-current can be reduced without weakening the influence of the electric field from the gate electrode. In addition, the physical thickness of the gate insulator allows the gate electrode and By keeping the distance between the gate electrode and the region where the channel is formed, The leakage current between the two electrodes can be suppressed.

[0324] Insulator 212, insulator 216, insulator 271, insulator 275, insulator 280, and insulator The insulator 284 preferably comprises an insulator with a low dielectric constant. For example, the insulator may be Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added Silicon oxide, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, It is preferable that the insulating material has silicon oxide or resin having pores. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen It is preferable that the film has a laminated structure of silicon oxide having pores and a resin. Silicon nitride and silicon oxynitride are thermally stable and can be combined with resin. As a result, it is possible to obtain a laminated structure that is thermally stable and has a low relative dielectric constant. , polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide , polycarbonate or acrylic.

[0325] The insulators 210, 214, 270, 273, and 282 are For this purpose, an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. The insulators 270 and 273 may be, for example, aluminum oxide or hafnium oxide. Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide metal oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, or tantalum oxide; Silicon or silicon nitride may be used.

[0326] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Metal elements selected from sodium, zirconium, beryllium, indium, ruthenium, etc. In addition, a polycrystalline material containing impurity elements such as phosphorus can be used. Semiconductors with high electrical conductivity, such as crystalline silicon, and silicides such as nickel silicide A code may also be used.

[0327] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0328] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0329] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0330] The conductors 260, 203, 205, and 240 are made of aluminum. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten Iron, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Use a material containing one or more metal elements selected from the group consisting of sodium, indium, and ruthenium. In addition, it is possible to use polycrystalline silicon containing impurity elements such as phosphorus. Semiconductors with high electrical conductivity, silicides such as nickel silicide, etc. may also be used.

[0331] <<Metal oxides>> The oxide 230 is a metal oxide that functions as an oxide semiconductor (hereinafter referred to as an oxide semiconductor). It is preferable to use the oxide 230 according to the present invention. The metal oxide will now be described.

[0332] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, titanium, iron, etc. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0333] Any one or more of the above metals can be used as the main component of the metal oxide. The metal contained in the layer 242 is a metal used as a main component of a metal oxide. A metal different from

[0334] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0335] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0336] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0337] In this specification, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. An example is shown below.

[0338] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconducting properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0339] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0340] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0341] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0342] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0343] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non crystalline oxide semiconductors.

[0344] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0345] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the lattice distortion. This is because the CAAC-OS crystals are grown in the ab-plane direction. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0346] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0347] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v Therefore, CAAC- Metal oxides with OS have stable physical properties. Metal oxides are heat resistant and highly reliable.

[0348] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0349] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0350] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0351] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0352] Note that by using the above metal oxide for the channel formation region of a transistor, a high field efficiency can be achieved. It is possible to realize a transistor with high mobility. It can be realized.

[0353] Here, an example of a hypothesis regarding electrical conduction in metal oxides will be described.

[0354] Electrical conduction in solids is hindered by scattering sources called scattering centers. For example, in single crystals, In the case of silicon, lattice scattering and ionized impurity scattering are known to be the main scattering centers. In other words, when there are few lattice defects or impurities, the electrical conduction in the solid There are no blocking factors and carrier mobility is high.

[0355] The above is also assumed to be true for metal oxides. In metal oxides containing less oxygen than the oxygen that fills the composition, oxygen vacancies V O There are many It is thought that the atoms around this oxygen vacancy are in a distorted position rather than in their essential state. It is possible that the distortion caused by this oxygen vacancy is the scattering center.

[0356] For example, in a metal compound containing more oxygen than the stoichiometric composition, Excess oxygen is present. Excess oxygen, which exists in a free state in the metal compound, accepts electrons. By doing so, O - Ya O 2- It becomes. - Ya O 2- The excess oxygen may become a scattering center. There is.

[0357] From the above, it is clear that metal oxides have an essential state in which oxygen is contained in a stoichiometric composition. In this case, the carrier mobility is considered to be high.

[0358] Indium-, a type of metal oxide containing indium, gallium, and zinc, Gallium zinc oxide (IGZO) tends to have difficulty growing crystals in the atmosphere. Therefore, smaller crystals are more likely to be formed than larger crystals (here, crystals of several mm or several cm). In some cases, crystals (such as the nanocrystals mentioned above) are structurally more stable. The strain energy is relieved more easily when small crystals are connected to each other than when large crystals are formed. This is thought to be because

[0359] In addition, in the region where small crystals are connected to each other, the strain energy of the region is relaxed. Therefore, defects may be formed in the region. By relaxing the strain energy, the mobility of carriers can be increased.

[0360] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides , the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. stomach.

[0361] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0362] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0363] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0364] In addition, a thin film with high crystallinity is used as the metal oxide semiconductor for the transistor. The use of the thin film improves the stability or reliability of the transistor. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, thin films of single crystal metal oxides or thin films of polycrystalline metal oxides are also available. To form a thin film on a substrate, a high temperature or laser heating process is required. This increases the cost of the manufacturing process and also reduces throughput.

[0365] In 2009, we developed an In-Ga-Zn oxide (CAAC-IGZO) with a CAAC structure. The discovery of the compound α-hydroxybenzoic acid (α-hydroxybenzoic acid) is reported in Non-Patent Document 1 and Non-Patent Document 2. In this case, CAAC-IGZO has a c-axis orientation, the grain boundaries are not clearly visible, and the It has been reported that it can be formed on a substrate at low temperatures. The transistors made using this method have been reported to have excellent electrical properties and reliability.

[0366] In 2013, we also developed an In-Ga-Zn oxide (nc-IGZO) with an nc structure. nc-IGZO is a material that can be grown in a small area. The atomic arrangement has periodicity in the region (for example, the region of 1 nm or more and 3 nm or less), and different It has been reported that there is no regularity in the crystal orientation between the regions.

[0367] In Non-Patent Documents 4 and 5, the above-mentioned CAAC-IGZO, nc-IGZO, The average crystal size of IGZO thin films and low-crystalline IGZO thin films was measured by electron beam irradiation. The change in the thickness is shown in Fig. 1. In a thin film of IGZO with low crystallinity, before the electron beam irradiation, Even in thin films, crystalline IGZO of about 1 nm has been observed. In this case, completely amorphous structure Furthermore, it has been reported that the presence of IGZO with low crystallinity could not be confirmed. Compared with the thin films of CAAC-IGZO and nc-IGZO, the thin films of CAAC-IGZO and nc-IGZO are more resistant to electron beam irradiation. Therefore, CAA is a promising semiconductor for transistors. It is preferable to use a thin film of C-IGZO or a thin film of nc-IGZO.

[0368] Transistors using metal oxides have extremely low leakage current when they are off. Specifically, the off-state current per 1 μm of the transistor channel width is yA / μm (10 -2 4 A / μm) order is shown in Non-Patent Document 6. For example, Low-power CPUs that utilize the low leakage current characteristics of the transistors used It has been disclosed (see Non-Patent Document 7).

[0369] In addition, the leakage current of a transistor using a metal oxide is low. The application of transistors to display devices has been reported (see Non-Patent Document 8). The displayed image changes several tens of times per second. The number is called the refresh rate. The refresh rate is also called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, can cause eye fatigue. Therefore, the refresh rate of the display device is reduced to improve image quality. It has been proposed to reduce the number of times the screen is rewritten. By driving the display device, it is possible to reduce the power consumption of the display device. This is called Idling Stop (IDS) drive.

[0370] The discovery of the CAAC and nc structures was based on the discovery of metal oxides with the CAAC or nc structures. The electrical characteristics and reliability of the transistor using the material are improved, and the manufacturing process cost is reduced. This contributes to improving throughput and reducing power consumption. Taking advantage of this property, research into the application of this transistor to display devices and LSIs is underway. are.

[0371] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0372] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. and the concentration of silicon and carbon near the interface with the metal oxide (concentration obtained by SIMS). , 2 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0373] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Do the following:

[0374] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the metal-doped region tend to be normally-on. In the oxide, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxides is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following .

[0375] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, metal oxides containing hydrogen can be used The transistor tends to be normally on. Therefore, hydrogen in the metal oxide is not formed. Specifically, in the case of metal oxides, the The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than.

[0376] Use of metal oxide with sufficiently reduced impurities in the channel formation region of a transistor This allows stable electrical properties to be imparted.

[0377] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 24 to 27. I will explain.

[0378] The semiconductor devices shown in FIGS. 24, 25, and 26 have an insulating layer in the transistor 200. 12 to 15 in that an insulator 272 is provided instead of an edge 275. The other configurations are different from those of the semiconductor device shown in FIGS. The description of the semiconductor device can be referred to. Similarly, an insulator equivalent to the insulator 272 is provided instead of the insulator 775.

[0379] FIG. 24A is a top view of a semiconductor device having a memory cell 600. 24(B) and 25 are cross-sectional views of the semiconductor device. 2 is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 24(A) and 24(B) are cross-sectional views of the transistor 200b in the channel length direction. 3 is a cross-sectional view of the portion indicated by the dashed line A3-A4, showing the channel width direction of the transistor 200a. It is also a cross-sectional view in the direction of the arrow. In the top view of FIG. 24(A), some elements are omitted for clarity. The cross section of the portion indicated by the dashed line A5-A6 in FIG. 13(B). In addition, in FIG. 24(B), the region 2 surrounded by the dashed line An enlarged view of 39 is shown in FIG.

[0380] The insulator 272 is formed on the side of the oxide 230c, the side of the insulator 250, and the side of the metal oxide 252. The insulator 270 is provided in contact with the surface of the conductive body 260, the side surface of the conductive body 260, and the side surface of the insulator 270. The insulator 272 functions as a buffer layer. An insulating material having a function of suppressing the permeation of impurities and oxygen may be used. The insulator 272 also functions as a barrier layer.

[0381] For example, it is preferable to form the insulator 272 by the ALD method. By using this, a dense thin film can be formed. It is preferable to use aluminum or hafnium oxide as the insulator 272. When aluminum oxide is formed using the LD method, the thickness of the insulator 272 is 0.5 nm or more. It is preferable to set it to 3.0 nm or less.

[0382] By providing the insulator 272, it is possible to suppress the permeation of impurities such as water or hydrogen, and oxygen. The insulator 250, the metal oxide 252, and the conductor 260 are insulated from each other. Therefore, the oxide film 250 can be covered with the metal oxide film 252. Therefore, it is possible to prevent impurities such as hydrogen and water from being mixed into the oxide 230. The formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the transistor In other words, the insulator 272 can improve the reliability of the gate electrode and It functions as a side barrier to protect the side surfaces of the gate insulator.

[0383] Furthermore, by using the above-mentioned material for the insulator 272, the conductor 240 can be relatively easily b, conductor 740a, or conductor 740b. 00b, or the gate of transistor 700, and is formed in a self-aligned manner without shorting. This allows the transistor 200a, the transistor 200b, or the transistor Since the area occupied by the register 700 can be reduced, further miniaturization of the memory cell array is possible. Furthermore, high integration can be achieved.

[0384] In the above embodiment, as shown in FIG. 4, the layer 20 including the memory cell array is When a plurality of transistors are stacked, as shown in FIG. 27, layer 610 including memory cells 600a and 600b may be stacked. As shown in FIG. 27, multiple cell arrays are stacked. By layering the cells, it is possible to integrate and arrange them without increasing the area occupied by the cell array. In other words, a 3D cell array can be configured.

[0385] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. can.

[0386] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0387] (Fourth embodiment) In this embodiment, an example in which the semiconductor device 10 of one embodiment of the present invention is applied to an electronic component will be described. The electronic components are also called semiconductor packages or IC packages. Multiple semiconductor chips (integrated circuits) are mounted in one package. MCM (Multi Chip Module) is known.

[0388] 28(A) shows a perspective view of the semiconductor device 300. FIG. 28(B) shows a perspective view of the semiconductor device 300. The semiconductor device 300 is an electronic component and also an MCM. 0, an interposer 301 is provided on a package substrate 302 (printed circuit board), and A CPU 303, a GPU 304, and a plurality of semiconductor devices 10 are installed on an interposer 301. In this embodiment, as an example of the semiconductor device 10, a semiconductor device in which a plurality of cell arrays are stacked is used. Layered High Bandwidth Memory (HBM) This shows:

[0389] In this embodiment, the integrated circuit (semiconductor chip) provided on the interposer 301 Although the CPU, GPU, and memory (storage device) are given as examples, other clusters are also possible. An integrated circuit may also be used.

[0390] The package substrate 302 is a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 301 may be a silicon interposer, a resin interposer, or the like. An oil interposer or the like can be used.

[0391] The interposer 301 has a plurality of wirings and connects a plurality of integrated circuits with different terminal pitches. The wiring has a function of electrically connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 301 supports the integrated circuit provided on the interposer 301 to the package substrate 3. 02. The interposer is sometimes called a "rewiring substrate" or an "intermediate substrate." 1, a through electrode is provided, and the integrated circuit and the package substrate 302 are electrically connected by the through electrode. In addition, in silicon interposers, TSV ( Through Silicon Via can also be used.

[0392] It is preferable to use a silicon interposer as the interposer 301. Since there is no need to provide active elements in the interposer, the cost is lower than that of fabricating an integrated circuit. On the other hand, the wiring formation of the silicon interposer is performed at a low cost. This process makes it easy to form fine wiring that is difficult to do with resin interposers. is.

[0393] In HBM, many wires must be connected to achieve a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is recommended to use a silicon interposer for implementing HBM. It is preferable that:

[0394] In addition, in MCMs using silicon interposers, the expansion between the integrated circuit and the interposer The silicon interposer is also less susceptible to deterioration in reliability due to differences in the thermal expansion coefficient. Because of its high flatness, it is possible to mount the integrated circuit on the silicon interposer and the silicon interposer. In particular, when multiple integrated circuits are arranged side by side on an interposer, poor connection between the devices is unlikely to occur. In the 2.5D package (2.5-dimensional mounting) where It is preferable that:

[0395] 29(A) to 29(C) correspond to the area between A1 and A2 indicated by the dashed line in FIG. 28(B). 29A and 29B are cross-sectional views of a semiconductor device 10 according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device 300.

[0396] First, a conventional semiconductor device 300p will be described. 1 is a cross-sectional view illustrating a semiconductor device 300p. 29(C).), a GPU 304, and a semiconductor device 10p. The device 10p corresponds to the semiconductor device 10.

[0397] In FIG. 29(C), the interface is formed on the package substrate 302 via a plurality of bumps 311. A CPU 303 (not shown in FIG. 29(C)) is provided. The GPU 304 and the semiconductor device 10p are connected to each other via different bumps 312. The bump 312 is provided on the turboser 301. The bump 312 is smaller than the bump 311. The bumps 311 and 312 are made of gold (Au), nickel (Ni), indium (I For example, the bumps are made of solder. may be used.

[0398] The semiconductor device 10p includes a semiconductor device 25a, a semiconductor device 25b, a semiconductor device 25c, and and semiconductor device 35. 5c each have a cell array, and the semiconductor device 35 has the semiconductor device 25a, the semiconductor device 2 5b, and a logic circuit for controlling the semiconductor device 25c. a, semiconductor device 25b, semiconductor device 25c, and semiconductor device 35 are each made of silicon. The substrate is used.

[0399] The semiconductor device 25a is provided on top of the semiconductor device 35 via a plurality of bumps. The semiconductor device 25b is provided on top of the semiconductor device 25a via a plurality of bumps. The semiconductor device 25c is provided on top of the semiconductor device 25b via a plurality of bumps. The semiconductor device 25a, the semiconductor device 25b, the semiconductor device 25c, and the semiconductor device 35 are The semiconductor device 25a, the semiconductor device 25b, and the semiconductor device 25c are provided with TSVs 313, respectively. The semiconductor device 25c is electrically connected to the semiconductor device 35 via the TSV 313 and the bump 312. The semiconductor device 35 is connected to the interface via the TSV 313 and the bump 312. It is electrically connected to the interposer 301 .

[0400] The semiconductor device 10p includes a semiconductor device 25a, a semiconductor device 25b, a semiconductor device 25c, and Since the semiconductor device 35 and the semiconductor device 31 are stacked via the bumps 312, the thickness tends to increase. That is, it is difficult to make the semiconductor device 300p thinner. This tends to increase manufacturing costs and reduce yields.

[0401] Next, a semiconductor device 300 using the semiconductor device 10 of one embodiment of the present invention will be described. The semiconductor device 300 is a semiconductor device in that the semiconductor device 10 is used instead of the semiconductor device 10p. The semiconductor device 10 includes a layer 20_1, a layer 20_2, a layer 20_3, and a layer 30. The layer 20_1, the layer 20_2, and the layer 20_3 each have a cell array. The layer 30 includes logic circuits for controlling the layers 20_1, 20_2, and 20_3. The semiconductor substrate shown in the above embodiment can be used as the layer 30. The semiconductor device 10 has been described in the above embodiment, so the details of this embodiment will not be explained. Detailed explanations will be omitted.

[0402] FIG. 29(A) shows an example of a semiconductor device 10 in which the layer 30 is formed using a silicon substrate. The layer 20_1 is provided on the layer 30, the layer 20_2 is provided on the layer 20_1, and the layer 20 The layer 20_1, the layer 20_2, and the layer 20_3 are provided on the layer 20_2. Each of them is formed using a thin film process. No gaps are formed between the layer 20_1 and the layer 20_2, and between the layer 20_2 and the layer 20_3, and the semiconductor device In other words, the semiconductor device 300 can be easily made thinner. The layers 20_1, 20_2, and 20_3 are provided with TSVs 313 and bumps 312. This eliminates the need for a separate wiring, which reduces manufacturing costs and improves manufacturing yields. , the semiconductor device 10 eliminates the use of a silicon substrate compared to the semiconductor device 10p; or Therefore, the manufacturing cost can be reduced compared to the semiconductor device 10p.

[0403] FIG. 29(B) shows that the layer 30 is also a thin film, similar to the layers 20_1, 20_2, and 20_3. 29(B) shows an example of a semiconductor device 10 formed using the process. In the device 10, the layer 30 is formed directly on the interposer 301, so that the layer 30 is The bumps 312 provided between the substrate 30 and the interposer 301 can be omitted. Therefore, it is easier to make the semiconductor device thinner than the semiconductor device 300 shown in FIG. 29(A), and the manufacturing cost is lower. This can reduce costs and improve manufacturing yields.

[0404] 30(A) and (B) correspond to the area between A1 and A2 shown by the dashed line in FIG. 28(B). FIG.

[0405] When a heat sink 360 (heat dissipation plate) is provided on the semiconductor device 300, as shown in FIG. As shown in FIG. 1, it is preferable to align the heights of the integrated circuits provided on the interposer. Specifically, the height h1 of the semiconductor device 10 on the interposer and the GP on the interposer are The height h2 of the U304 and the CPU303 (not shown in FIG. 30(A)) is made approximately equal. It is preferable to align the heights of the integrated circuits mounted on the interposer. The integrated circuit can be in secure contact with the heat sink 360 .

[0406] The transistor uses an oxide semiconductor, a type of metal oxide, in the semiconductor layer where the channel is formed. In OS transistors, the off-state current does not increase even when the operating temperature rises. Therefore, the semiconductor device 10 can be used as an OS transceiver. When forming the register, as shown in FIG. 30(B), the GPU 304 (and the CPU 30 3. Not shown in FIG. 30(B). The semiconductor device 10 may be lower than the h1 may be smaller than h2. This increases the degree of freedom in designing the integrated circuit device 300. By doing so, the heat sink 360 can be omitted.

[0407] In order to mount the semiconductor device 300 on another substrate, electrodes 31 are attached to the bottom of the package substrate 302. 31(A) shows an example in which the electrode 315 is formed by a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 302, a BGA (B 31(B) shows the electrode 315 as a conductive material. The bottom of the package substrate 302 is provided with conductive pins. By providing it in a risk-free manner, PGA (Pin Grid Array) mounting can be achieved.

[0408] The semiconductor device 300 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid A) rray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) ), or QFN (Quad Flat Non-leaded package), etc. The following implementation method can be used.

[0409] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0410] (Embodiment 5) In this embodiment, the semiconductor device and / or electronic component described in the above embodiment is mounted. An example of an electronic device equipped with the above-mentioned technology will be described.

[0411] The semiconductor device and electronic component according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Desktop personal computers, computer monitors, digital signage ( Digital Signage, Pachinko machines and other large game machines In addition to electronic devices with relatively large screens, digital cameras, digital video cameras, digital Photo frames, mobile phones, portable game consoles, personal digital assistants, audio playback devices, etc. Examples include:

[0412] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0413] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Number, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared) It may have.

[0414] The electronic device of one embodiment of the present invention can have various functions. (still images, videos, text images, etc.) on the display, touch panel function, calendar Functions such as displaying date and time, running various software (programs) functions, wireless communication functions, and functions to read programs or data recorded on recording media. It can have functions, etc. Examples of electronic devices are shown in Figures 32 and 33.

[0415] The robot 2100 shown in FIG. 32(A) includes a computing device 2110, an illuminance sensor 2101, a Microphone 2102, upper camera 2103, speaker 2104, display 2105 , a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108. Here, a humanoid robot is shown as an example.

[0416] In the robot 2100, a computing device 2110, an illuminance sensor 2101, an upper camera 21 03, the lower camera 2106 and the obstacle sensor 2107, etc., are provided with the above semiconductor device and / or Alternatively, the above electronic components can be used.

[0417] The microphone 2102 has a function of detecting the user's voice and environmental sounds. The speaker 2104 has a function of emitting sound. The phone 2102 and the speaker 2104 are used to communicate with the user. is possible.

[0418] The display 2105 has the function of displaying various information. The information desired by the user can be displayed on the display 2105. The device 2105 may be equipped with a touch panel.

[0419] The upper camera 2103 and the lower camera 2106 capture images of the surroundings of the robot 2100. The obstacle sensor 2107 detects obstacles when the robot 2100 moves forward on two legs. The robot 2100 can detect the presence or absence of obstacles in its current direction of travel. The camera 2103, the lower camera 2106, and the obstacle sensor 2107 are used to detect the surrounding environment. It is possible to recognize and move safely.

[0420] 32(B) is an external view showing an example of an automobile. The automobile 2980 is equipped with a camera 298 1st place. In addition, the car 2980 is equipped with infrared radar, millimeter wave radar, laser radar, The car 2980 is equipped with various sensors such as a camera 2981. The system analyzes the surrounding traffic conditions, such as whether there are pedestrians, and can then drive autonomously.

[0421] In the automobile 2980, the camera 2981 is provided with the semiconductor device and / or the electronic part. Products can be used.

[0422] Figure 32(C) shows a case where two or more people are communicating in different languages. 2 shows a situation in which a portable electronic device 2130 is used for simultaneous interpretation.

[0423] The portable electronic device 2130 has a microphone and a speaker, etc., and can pick up the user's voice. The portable electronic device 2130 has the function of recognizing the speech and translating it into the language of the person it is speaking to. The semiconductor device and / or the electronic component can be used in a computing device.

[0424] 33(A) is an external view showing the flying object 2120. The flying object 2120 is a computer device 2 121, a propeller 2123, and a camera 2122, and has the function of flying autonomously. do.

[0425] In the flying object 2120, the above-mentioned semiconductor device and and / or the electronic components described above can be used.

[0426] 33(B-1) and 33(B-2) show examples of how the flying object 2120 can be used. As shown in FIG. 33(B-1), the air vehicle 2120 can be used to transport cargo 2124. Also, as shown in FIG. 33(B-2), a container 212 containing pesticides is attached to an aircraft 2120. 5, the aircraft 2120 can be used to spray pesticides.

[0427] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. [Explanation of symbols]

[0428] 10: semiconductor device, 20: layer, 21: control circuit, 25a: semiconductor device, 25b: semiconductor device 25c: semiconductor device; 30: layer; 35: semiconductor device; 40: layer; 41: light receiving portion; 42 : light, 43: driving circuit, 100: capacitance element, 100a: capacitance element, 100b: capacitance element, 112: conductor, 120: conductor, 120a: conductor, 120b: conductor, 130: insulator body, 130a: insulator, 130b: insulator, 150: insulator, 200: transistor, 2 00a: transistor, 200b: transistor, 203: conductor, 203a: conductor, 203b: Electrical conductor, 203c: Electrical conductor, 205: Electrical conductor, 205a: Electrical conductor, 205b: Conductor, 205c: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216 : insulator, 220: insulator, 222: insulator, 224: insulator, 230: oxide, 230 a: oxide, 230b: oxide, 230c: oxide, 230ca: oxide, 230cb: oxide, 231: area, 231a: area, 231b: area, 231c: area, 232: area area, 232a: area, 232b: area, 232c: area, 232d: area, 234: area , 234a: area, 234b: area, 239: area, 240: conductor, 240a: conductor , 240b: conductor, 240c: conductor, 242: layer, 242a: layer, 242b: layer, 2 42c: layer, 250: insulator, 250a: insulator, 250b: insulator, 252: metal oxide substance, 252a: metal oxide, 252b: metal oxide, 260: conductor, 260a: conductor , 260aa: conductor, 260ab: conductor, 260b: conductor, 260ba: conductor, 260bb: conductor, 270: insulator, 270a: insulator, 270b: insulator, 271: insulator, 271a: insulator, 271b: insulator, 272: insulator, 273: insulator, 27 4: insulator, 275: insulator, 275a: insulator, 275b: insulator, 280: insulator, 282: Insulator, 284: Insulator

Claims

1. a cell array, a first drive circuit, and a second drive circuit; the cell array has a first memory cell and a second memory cell; the first drive circuit has a function of supplying a selection signal; the second driver circuit has a function of writing or reading data, the first memory cell includes a first transistor and a first capacitance element; the second memory cell includes a second transistor and a second capacitance element; one of a source and a drain of the first transistor is electrically connected to the first capacitance element; one of a source and a drain of the second transistor is electrically connected to the second capacitance element; the other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are electrically connected to the second driver circuit via a first wiring; each of the first transistor and the second transistor includes a first oxide semiconductor layer and a second oxide semiconductor layer located over the first oxide semiconductor layer; the first transistor includes at least a first channel formation region formed in the second oxide semiconductor layer, a third oxide semiconductor layer located above the first channel formation region, a first gate electrode located above the third oxide semiconductor layer, a first insulator having a region overlapping with an upper surface of the first gate electrode, a second insulator having a region in contact with a side surface of the first gate electrode and a side surface of the first insulator and having a region overlapping with an upper surface of the first gate electrode, and a second gate electrode located below the first channel formation region; the second transistor includes at least a second channel formation region formed in the second oxide semiconductor layer, a fourth oxide semiconductor layer located above the second channel formation region, a third gate electrode located above the fourth oxide semiconductor layer, a third insulator having a region overlapping with an upper surface of the third gate electrode, a fourth insulator having a region in contact with a side surface of the third gate electrode and a side surface of the third insulator and having a region overlapping with an upper surface of the third gate electrode, and a fourth gate electrode located below the second channel formation region; a first conductor having an area overlapping the second insulator and an area overlapping the fourth insulator; a width of the first conductor in a cross-sectional view narrows toward a portion between the second insulator and the fourth insulator, The first conductor functions as the first wiring.

2. In claim 1, the second gate electrode has a second conductor and a third conductor; the third conductor has a region in contact with an inner wall of the second conductor; the fourth gate electrode has a fourth conductor and a fifth conductor; The fifth conductor has a region in contact with an inner wall of the fourth conductor.

3. In claim 1 or claim 2, a second wiring below the second gate electrode; a third wiring is provided below the fourth gate electrode; the second wiring has a sixth conductor and a seventh conductor; the seventh conductor has a region in contact with an inner wall of the sixth conductor, the third wiring has an eighth conductor and a ninth conductor; The ninth conductor has a region in contact with an inner wall of the eighth conductor.

4. In any one of claims 1 to 3, the first drive circuit includes a third transistor; the second drive circuit includes a fourth transistor; the third transistor and the fourth transistor each have a channel formation region formed in a fifth oxide semiconductor layer.

5. In any one of claims 1 to 4, the first capacitance element and the second capacitance element each have an electrode; The electrode includes the second oxide semiconductor layer.

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