Information processor, instruction parallel execution method, and program

Abstract

To provide an information processor suitable for executing parallel processing of a program written in a programming language for parallel processing.SOLUTION: In a central processing unit 13 that executes a plurality of instructions in parallel, a fetch processing unit 23 uses a plurality of program counters included in a program counter group storage unit 31 to read the plurality of instructions into an instruction register group storage unit 33 all at once. A decode processing unit 25 decodes the plurality of instructions read into the instruction register group storage unit 33 and instructs a back-end unit 17 to execute them. An extended logic execution processing unit 41 executes the instruction that is instructed to be executed in one or more execution devices 45 included in an execution device group 43.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an information processing device, an instruction parallel execution method, and a program, and relates to an information processing device or the like that executes a plurality of instructions in parallel. [Background technology]

[0002] For example, processors that use a general-purpose architecture, such as those described in Patent Document 1, must make many sacrifices in order to achieve high performance. In contrast, processors specialized for specific processing can achieve high performance, high reliability, and low power consumption by sacrificing versatility. This approach is known as domain-specific architecture (DSA).

[0003] The programming language Elixir is a functional programming language with excellent parallel distributed processing and fault tolerance. Introducing Elixir has significant benefits, including significantly improved maintainability and reduced power consumption, which in turn reduces electricity bills, significantly improved reliability, and reduced operational and maintenance personnel costs. For example, a cloud application that previously required 300 PC servers can be reduced to 10.

[0004] As described in Non-Patent Document 1, the inventor has proposed an algorithm for performing the Karatsuba method using a multiplier of a DSP slice in which the bit widths of the multiplicand and the multiplier are different. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2023-51994 [Non-patent literature]

[0006] [Non-Patent Document 1] Yamazaki, "Extension of the Karatsuba algorithm when the bit widths of the multiplicand and multiplier are different," IEICE RECONF Study Group, 2023. Summary of the Invention [Problem to be solved by the invention]

[0007] Elixir's parallel distributed processing efficiently executes sequential machine language instruction sequences generated from a program simultaneously, and also assigns them to multiple execution devices (e.g., central processing units (CPUs), CPU cores, etc. CPU cores are divided into physical cores and logical cores depending on the mechanism) to physically execute them simultaneously.

[0008] However, in conventional computers, the number of execution units is fixed and invariable, so Elixir's scheduler must adjust the execution units to execute parallel processes.

[0009] This problem is not limited to Elixir, but is generally recognized when executing a program written in a programming language suitable for parallel processing. Note that Non-Patent Document 1 relates to multiplication.

[0010] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an information processing device or the like that is suitable for executing parallel processing of a program written in a programming language for parallel processing. [Means for solving the problem]

[0011] A first aspect of the present invention is an information processing device that executes multiple instructions in parallel, comprising a front-end unit, an internal memory, and a back-end unit, wherein the front-end unit comprises a fetch processing unit and a decode processing unit, the internal memory comprises a program counter group storage unit and an instruction register group storage unit, and the back-end unit comprises an extended logic execution processing unit and an execution device group, wherein the fetch processing unit uses multiple program counters included in the program counter group storage unit to read multiple instructions into the instruction register group storage unit in bulk, the decode processing unit decodes the multiple instructions read into the instruction register group storage unit and instructs the back-end unit to execute them, and the extended logic execution processing unit executes the instructed instructions in one or more execution devices included in the execution device group.

[0012] A second aspect of the present invention is the information processing device of the first aspect, wherein the decoding processing unit performs decoding processing for an instruction having an opcode identical to a target opcode among a plurality of instructions read into the instruction register group memory unit by combining an operand of the instruction with the target opcode.

[0013] A third aspect of the present invention is an information processing device according to the first or second aspect, wherein the number of program counters included in the program counter group memory unit is greater than the number of instructions that can be executed simultaneously in the execution device group.

[0014] A fourth aspect of the present invention is an information processing device according to any one of the first to third aspects, wherein the internal memory comprises an active mask group storage unit, the front-end unit comprises an active mask group processing unit, the number of program counters included in the program counter group storage unit is n (n is a natural number greater than or equal to 2), the active mask group processing unit comprises n active masks each corresponding to the n program counters, each active mask holds data indicating whether the corresponding program counter is active or not, and the fetch processing unit reads instructions all at once into the instruction register group storage unit using the program counter corresponding to the active mask holding data that is determined to be active.

[0015] A fifth aspect of the present invention is an instruction parallel execution method for executing a plurality of instructions in parallel, comprising: an information processing device comprising a front-end unit, an internal memory, and a back-end unit; the front-end unit comprising a fetch processing unit and a decode processing unit; the internal memory comprising a program counter group storage unit and an instruction register group storage unit; and the back-end unit comprising an extended logic execution processing unit and an execution device group, the method comprising: a fetch step in which the fetch processing unit uses a plurality of program counters included in the program counter group storage unit to read a plurality of instructions into the instruction register group storage unit all at once; a decode step in which the decode processing unit decodes the plurality of instructions read into the instruction register group storage unit and instructs the back-end unit to execute the instructions; and an execution step in which the extended logic execution processing unit executes the instructed instructions in one or more execution devices included in the execution device group.

[0016] A sixth aspect of the present invention is the instruction parallel execution method of the fifth aspect, wherein in the decoding step, the decode processing unit decodes an instruction having an opcode identical to a target opcode among the plurality of instructions read into the instruction register group storage unit by combining an operand of the instruction with the target opcode.

[0017] A seventh aspect of the present invention is an instruction parallel execution method according to the fifth or sixth aspect, wherein the number of program counters included in the program counter group memory unit is greater than the number of instructions that can be executed simultaneously in the execution device group.

[0018] An eighth aspect of the present invention is an instruction parallel execution method according to any one of the fifth to seventh aspects, wherein the internal memory comprises an active mask group storage unit, the front-end unit comprises an active mask group processing unit, the number of program counters included in the program counter group storage unit is n (n is a natural number greater than or equal to 2), the active mask group processing unit comprises n active masks each corresponding to the n program counters, and each active mask holds data indicating whether the corresponding program counter is active or not, and in the fetching step, the fetch processing unit reads instructions all at once into the instruction register group storage unit using the program counter corresponding to the active mask holding data that is to be active.

[0019] A ninth aspect of the present invention is a program for causing a computer to function as the decoding processing unit of any one of the first to fourth aspects.

[0020] In each aspect of the present invention, the decode processing unit may be understood as individually decoding instructions with opcodes different from the target opcode, among the multiple instructions read into the instruction register group storage unit. [Effects of the Invention]

[0021] According to each aspect of the present invention, the number of program counters, n, can be freely set without being limited by the number of execution units included in the execution unit group, etc. Therefore, the required number of instructions can be treated as a vector, and fetching and decoding can be performed in parallel all at once.

[0022] Furthermore, according to the second and sixth aspects of the present invention, the decoding processing unit can perform decoding processing for multiple instructions with the same opcode as the target opcode by combining the target opcode with the operands of each instruction, such as in a SIMD (Single Instruction Multiple Data), vector processor, or GPU (Graphics Processing Unit).

[0023] Furthermore, according to the fourth and eighth aspects of the present invention, by designating the required number of active masks as active, it is possible to use the required number of program counters to fetch instructions from the instruction memory to the instruction register group storage unit in a batch and decode them. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a block diagram showing an example of the configuration of a parallel execution system 1. FIG. [Figure 2] 2 is a flowchart showing an example of the operation of the configuration of parallel execution system 1 of FIG. 1. [Figure 3] FIG. 2 is a diagram for explaining an example of a specific operation of the parallel execution system 1 of FIG. [Figure 4] FIG. 4 is a diagram illustrating an execution device in the example of FIG. 3 in an abstracted manner. [Figure 5] FIG. 5 is a first diagram showing an example in which the number of execution devices included in the execution device group in the example of FIG. 4 is set to two. [Figure 6] FIG. 5 is a second diagram showing an example in which the number of execution devices included in the execution device group in the example of FIG. 4 is set to two. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments.

[0026] FIG. 1 is a block diagram showing an example of the configuration of a parallel execution system 1. As shown in FIG.

[0027] The parallel execution system 1 includes a compiling device 3 and a parallel execution processing device 5 .

[0028] The compiling device 3 includes a source program storage unit 7 and a compiling processing unit 9.

[0029] The parallel execution processing device 5 includes an input / output processing device 11, an execution program storage device 12, and a central processing unit 13. The central processing unit 13 includes a front-end unit 15, a back-end unit 17, and an internal memory 16.

[0030] The front-end unit 15 includes an active mask group processing unit 21, a fetch processing unit 23, and a decode processing unit 25. Each processing unit may be realized using a special circuit, or may be realized using a program or the like.

[0031] The internal memory 16 includes an instruction memory 27, an active mask set storage unit 29, a program counter set storage unit 31, an instruction register set storage unit 33, and a comparison mask set storage unit 35. The internal memory 16 can be realized by using a storage device such as a memory.

[0032] The back-end unit 17 includes an extended logic execution processing unit 41 and an execution device group 43. The execution device group 43 includes m (m is a natural number) execution devices 451, ..., 45 m Each processing unit may be realized using a special circuit or a program.

[0033] The compiling device 3 is an information processing device realized by, for example, a computer operating under a program.

[0034] The source program storage unit 7 stores a source program written in a programming language and is realized by a storage device such as a hard disk.

[0035] The compile processing unit 9 converts the source programs stored in the source program storage unit 7 in a batch to generate an execution program that can be executed and interpreted by the parallel execution processing unit 5. It also analyzes the source programs to generate data that can be used to run the execution program. The compile processing unit 9 can be realized, for example, by a processor that operates under a program. If the source program can be executed and interpreted by the parallel execution processing unit 5, the compile processing unit 9 converts the source program into an execution program.

[0036] The parallel execution processing device 5 is an information processing device realized by, for example, a computer operating under a program.

[0037] The input / output processor 11 is used by the user of the parallel execution processor 5 to input and output data and the like.

[0038] The execution program storage device 12 stores the execution program generated by the compilation processing unit 9.

[0039] The central processing unit 13 is a CPU (Central Processing Unit) and performs control and calculations according to instructions contained in the execution program stored in the execution program storage device 12 .

[0040] The front-end unit 15 is a front-end micro-architecture that reads (fetches) and interprets (decodes) instructions, extracts parallelism from dependencies between instructions, and drives the back-end unit 17 in parallel.

[0041] The back-end unit 17 is a back-end micro-architecture that executes instructions and stores the execution results. It can accept instructions from the front-end unit 15 in parallel and achieves high throughput performance by pipelining. The key to achieving high performance is how to extract high parallelism and how to remove hazard factors that hinder pipeline performance.

[0042] The internal memory 16 stores data necessary for processing in the front-end unit 15 and the back-end unit 17 .

[0043] The instruction memory 27 stores instructions that are currently to be executed by the central processing unit 13 from among the execution programs stored in the execution program storage device 12 .

[0044] The program counter group storage unit 31 stores n program counters (n is a natural number equal to or greater than 2). Each program counter is a register that manages the memory address of the next instruction to be executed in the instruction memory 27. The memory address stored in the program counter is basically incremented each time an instruction is executed, and is set to a value specified by a branch instruction or the like.

[0045] The active mask group storage unit 29 stores n active masks. Each of the n active masks corresponds to n program counters stored in the program counter group storage unit 31, and holds data indicating whether the corresponding program counter is active or not when a vector mask is specified. In the following, if no vector mask is specified in the execution program, all program counters are active and are subject to processing by the fetch processing unit 23 and the decode processing unit 25. If a vector mask is specified, if the active mask is 1, the corresponding program counter is active and is subject to processing by the fetch processing unit 23 and the decode processing unit 25, and if the active mask is 0, the corresponding program counter is not active and is not subject to processing by the fetch processing unit 23 and the decode processing unit 25.

[0046] The instruction register set storage unit 33 stores instructions read from memory addresses indicated by active program counters. Instructions include an operation code (Opcode) and an operand. The operation code is a code (identification number) for identifying the specific operation to be executed by the processor. The operand is an operand and indicates the target of the operation. The instruction register set storage unit 33 serves as an instruction register corresponding to each active program counter. An instruction register is a register that holds the instruction currently being executed. The instruction register set storage unit 33 holds a maximum of n instructions.

[0047] The comparison mask group storage unit 35 stores the comparison results of whether or not the opcode of a specific instruction (hereinafter referred to as the "target opcode") is the same as the opcode of the instruction stored in the instruction register group storage unit 33. The comparison mask group storage unit 35 stores a maximum of n comparison masks. In the following, it is assumed that the n comparison masks correspond to the n instructions stored in the instruction register group storage unit 33, respectively, and that if the opcode of the corresponding instruction is the same as the target opcode, the comparison mask is 1, and if they are different, the comparison mask is 0.

[0048] In the front-end unit 15, an active mask group processing unit 21 manages whether or not a vector mask has been designated, and operates the active masks stored in an active mask group storage unit 29.

[0049] The fetch processing unit 23 performs fetch processing, ie, fetches instructions from the instruction memory 27 to the instruction register group storage unit 33 using the program counter stored in the program counter group storage unit 31 .

[0050] The decode processing unit 25 performs decoding processing, and interprets each instruction stored in the instruction register group storage unit 33. The decode processing unit 25 issues an operation instruction (issue operation) to the back-end unit 17 in accordance with the interpreted instruction.

[0051] In the back-end unit 17, the execution device group 43 includes m (m is a natural number) execution devices 451, ..., 45 m Execution units 451, ..., 45 m Each of the execution units 451, ..., 45 may be realized by using a special circuit or a program. m In the example, one or more instructions can be executed by one or more logical execution units, i.e., execution units 451,...,45 mEach of the logical execution units executes one or more instructions without sharing the architecture for executing the instructions. The multiple logical execution units in a single execution device can execute multiple instructions by sharing the architecture for executing the instructions.

[0052] The extended logic execution processing unit 41 performs processing to execute one or more extended logic execution units in the execution device group 43. Each extended logic execution unit corresponds to an active program counter.

[0053] FIG. 2 is a flow diagram showing an example of the operation of the configuration of parallel execution system 1 of FIG.

[0054] The compilation processing unit 9 converts the source programs stored in the source program storage unit 7 all at once to generate an execution program that can be executed and interpreted by the parallel execution processing unit 5 (step STA1). If necessary, the compilation processing unit 9 analyzes the source programs and generates data that can be used to run the execution program.

[0055] The user of the parallel execution processing device 5 uses the input / output processing device 11 to perform processing to execute the generated execution program (step STA2). For example, the user stores the generated execution program in the execution program storage device 12. In the following processing, the instruction memory 27 stores the instructions of the execution program that are currently to be executed by the central processing unit 13.

[0056] The active mask group processing unit 21 manages whether or not a vector mask has been designated. The active mask group processing unit 21 determines whether or not a vector mask has been designated, for example, by referring to the execution program. If a vector mask has been designated, the active mask group processing unit 21 sets each active mask to be stored in the active mask group storage unit 29 (step STA3).

[0057] The fetch processing unit 23 uses the program counters stored in the program counter group storage unit 31 to perform a process of fetching instructions all at once from the instruction memory 27 to the instruction register group storage unit 33 (step STA4). If no vector mask is specified, the fetch processing unit 23 assumes that all program counters are active and uses all program counters to fetch instructions all at once from the instruction memory 27 to the instruction register group storage unit 33. If a vector mask is specified, the fetch processing unit 23 assumes that the program counters specified as active by each active mask are active and uses the active program counters to fetch instructions all at once from the instruction memory 27 to the instruction register group storage unit 33.

[0058] The decode processing unit 25 performs a process of interpreting the instructions read by the fetch processing unit 23 in step STA4. Here, the decode processing unit 25 compares the opcode of each instruction read by the fetch processing unit 23 with the target opcode and stores the comparison result in the comparison mask group storage unit 35 (step STA5). For instructions for which the comparison results are the same, the decode processing unit 25 instructs the back-end unit 17 to perform an operation based on the result of interpreting the target opcode and the operands of each instruction. Furthermore, for instructions for which the comparison results are different, the decode processing unit 25 instructs the back-end unit 17 to perform an operation based on the result of interpreting each instruction individually (step STA6).

[0059] 1, the front-end unit 15 handles multiple instructions in parallel like a vector computer, and fetches multiple instructions together in step STA4. Furthermore, in steps STA5 and STA6, in addition to handling multiple instructions in parallel like a vector computer, it also performs decoding on operands of multiple instructions that share a common target opcode like SIMD.

[0060] The back-end unit 17 executes commands in accordance with execution instructions from the front-end unit.

[0061] The front-end unit 15 determines whether or not to end the process of executing the execution program (step STA7). If the process is not to be ended, the process returns to step STA3. If the process is to be ended, the process of FIG. 2 ends.

[0062] An example of a specific operation of the parallel execution system 1 in Fig. 1 will be described with reference to Fig. 3. In this example, the case where n, which is the number of program counters, is 8 will be described. However, a vector mask is specified, and 7 program counters are active.

[0063] In the back-end unit, the number of execution devices included in the execution device group, m, is assumed to be 4. The four execution devices are referred to as "Execution Device 1," "Execution Device 2," "Execution Device 3," and "Execution Device 4." Each execution device can execute two instructions using two logic execution units. Execution Device 1 includes Logic Execution Unit 1 and Logic Execution Unit 2. Execution Device 2 includes Logic Execution Unit 3 and Logic Execution Unit 4. Execution Device 3 includes Logic Execution Unit 5 and Logic Execution Unit 6. Execution Device 4 includes Logic Execution Unit 7 and Logic Execution Unit 8.

[0064] The active mask group processing unit manages whether a vector mask has been designated, and sets seven active masks in the active mask group storage unit to 1 and one active mask to 0.

[0065] The program counter set storage unit stores eight program counters.

[0066] The fetch processing unit fetches instructions collectively from memory addresses managed by seven of the eight program counters that are made active by the active mask. The instruction register group storage unit stores the seven fetched instructions.

[0067] The decode processor compares the opcode of each instruction read by the fetch processor with the target opcode and stores the comparison results in the comparison mask group memory. In the example of Figure 3, assume that the opcodes of five instructions are the same as the target opcode. The decode processor can issue a collective instruction to the backend processor for the five instructions with the same comparison results based on the interpretation of the target opcode and the operands of each instruction. These five instructions are referred to as "target inst 1," "target inst 2," "target inst 3," "target inst 4," and "target inst 5." The decode processor also issues an instruction to the backend processor for the two instructions with different comparison results based on the interpretation of each instruction individually. These two instructions are referred to as "inst 6" and "inst 7."

[0068] In the group of execution devices 43, eight instructions can be executed by eight logic execution units. Therefore, in the group of execution devices 43, the extended logic execution processing unit 41 executes target inst 1, target inst 2, target inst 3, target inst 4, and target inst 5 in logic execution units 1, 2, 3, 4, and 5, respectively, and executes inst 6 and inst 7 in logic execution units 6 and 7, respectively.

[0069] Figure 4 shows an abstract understanding of the execution devices in the example of Figure 3. The extended logic execution processing unit 41 can be understood as executing the same number of extended logic execution units as the number of active program counters in one or more execution devices included in the execution device group 43. In other words, it is sufficient for the extended logic execution processing unit 41 to execute seven extended logic execution units using one or more execution devices included in the execution device group 43. For the extended logic execution processing unit 41, neither the number of execution devices belonging to the execution device group nor the number of logic execution units is essential.

[0070] 5 and 6 show an example in which the number m of execution devices included in the execution device group in the example of FIG. 4 is set to 2. The two execution devices are referred to as "execution device 5" and "execution device 6." Each execution device can execute two instructions using two logical execution units. Execution device 5 includes logical execution unit 9 and logical execution unit 10. Execution device 6 includes logical execution unit 11 and logical execution unit 12.

[0071] In the execution device group, four instructions can be executed by four logic execution units. Therefore, referring to Fig. 5, the extended logic execution processing unit 41 executes target inst 1, target inst 2, target inst 3, and target inst 4 by associating extended logic execution unit 1, extended logic execution unit 2, extended logic execution unit 3, and extended logic execution unit 4 with logic execution unit 9, logic execution unit 10, logic execution unit 11, and logic execution unit 12, respectively. Next, referring to Fig. 6, the extended logic execution processing unit 41 executes target inst 5, inst 6, and inst 7 by associating extended logic execution unit 5, extended logic execution unit 6, and extended logic execution unit 7 with logic execution unit 9, logic execution unit 10, and logic execution unit 11, respectively.

[0072] 5 and 6, the number of program counters, n, can be freely set without being limited by the number of execution devices included in the execution device group. For example, the number of program counters, n, can be set to be greater than the number of execution devices in the execution device group and greater than the number of instructions that can be simultaneously executed in the execution device group (e.g., the number of logical execution units). Therefore, the number of program counters, n, can be increased as long as the internal memory capacity allows, regardless of the number of execution devices. This means that the required number of instructions can be treated as a vector and fetched and decoded in parallel in a batch. The number of program counters, etc. can be set without being limited by the execution devices.

[0073] If no vector mask is specified, all of these program counters are considered to be active, and processing can be performed using all of the program counters. On the other hand, there are cases where it is desirable to perform fetch and decode processing in parallel in a batch, for example, for a number of processes that require synchronous processing. In such cases, by specifying a vector mask and selecting and specifying as active the required number of active masks, instructions can be fetched from the instruction memory to the instruction register group storage unit in a batch (for example, synchronized) using the required number of program counters.

[0074] Furthermore, the decode processor performs decoding on the fetched instructions. Here, fetched instructions with the same opcode as the target opcode can be decoded all at once. For example, if five instructions have the same opcode as the target opcode, the target opcode can be combined with the operands of each instruction, as in SIMD, and the interpreted results can be used to issue a collective instruction. Therefore, for example, an opcode that is frequently processed in parallel can be set as the target opcode, and its decoded result can be obtained in advance. Then, for instructions with the same target opcode, the previously obtained decoded result can be used to decode them by combining it with the operands of each instruction. On the other hand, fetched instructions with opcodes different from the target opcode can be decoded individually using the normal decoding process.

[0075] As described above, the present invention allows for the use of any number of program counters and other devices, without being limited by the number of CPUs or other execution devices. Therefore, when executing parallel processing of a program written in a parallel processing programming language such as Elixir, parallel processing can be specified using a vector with any number of elements, and the scheduler does not need to schedule using a fixed number of CPUs or other execution devices. Furthermore, in the decoding process, the target opcode instruction can be executed by combining operands, as in SIMD.

[0076] Therefore, according to the present invention, for example, the role of Elixir's scheduler can be implemented in hardware, effectively matching the number of execution devices (CPUs, CPU cores, etc.) to the concurrency and parallelism required by Elixir software. In principle, Elixir's units of concurrency and parallel processing are processed collectively as vectors, and the backend (backend micro-architecture) is directly driven by decoding each program. This allows for efficient implementation of Elixir's concurrency and parallel processing, while also contributing to increased utilization of the backend. Thus, implementing Elixir and other software in hardware using the DSA approach is expected to further reduce costs.

[0077] Furthermore, the present invention may be considered as a prefetching, fetching, and decoding method for enhancing instruction-level parallelism. The compilation unit 9 is a compiler that converts source programs written in a high-level language into instructions that the CPU can directly interpret. Compilers also generate optimized code to maximize CPU performance. In modern CPU designs, compilers are also designed and developed simultaneously. For example, in functional programming languages, functions may call other functions. The compilation unit 9 generates a data structure (e.g., a tree structure) that represents the relationships between functions calling other functions. The front-end unit 15 prefetches data into cache memory according to this data structure before executing the function, thereby increasing the cache hit rate and contributing to faster execution. Furthermore, by utilizing Elixir's conditional branching and exception handling characteristics, the compiler generates branch prediction hints and reads them when executing a function, improving the accuracy of branch prediction. This allows the front-end and back-end microarchitectures to execute smoothly without waiting, contributing to faster execution. Such ingenuity allows the present invention to be utilized more effectively.

[0078] Furthermore, the present invention can be considered as relating to virtual registers. Compilers may be able to execute programs faster if they can utilize more registers. However, if 32 registers are allocated, specifying a register in a machine language instruction or bytecode instruction requires 5 bits. Specifying three registers in a single instruction requires 15 bits. Short machine language instructions and bytecodes are desirable, and from this perspective, the fewer registers that can be specified in an instruction, the better. Therefore, the present invention can be considered as introducing the concept of virtual memory into registers, significantly increasing the number of registers that a compiler can actually use while keeping the number of registers specified in an instruction low. This reduces the need for compilers to worry about register management, potentially enabling faster program execution. In principle, an instruction is provided that maps the logical register number specified in the instruction to the physical register number, thereby keeping the upper limit of the logical register number low. The front-end micro-architecture treats this instruction like a register renaming instruction and can use the currently specified mapping between logical and physical register numbers to indicate the physical register number to the back-end micro-architecture.

[0079] Furthermore, the present invention may be considered as a front-end micro-architecture with an arbitrary decoder. It may also be considered as a mechanism that allows the later incorporation of logic for decoding / encoding machine instructions of any ISA (Instruction Set Architecture), bytecode corresponding to a high-level language, and encrypted data into the front-end micro-architecture. This enables, for example, Elixir, for execution of an executable program (e.g., Elixir bytecode) generated by the compilation processing unit 9 directly on the CPU. In other words, bytecode with the same level of numerical encoding as a high-level language can be directly executed on the CPU. Moreover, high performance can be expected. It also enables a security mechanism that requires an encryption key to read security information. By adding or modifying the logic to be incorporated later as the programming language or encryption is updated, it is possible to keep up with updates. This logic can be written in a subset of Elixir and generated by a compiler. It is possible to provide an Elixir writing framework integrated with the present invention.

[0080] According to the present invention, for example, Elixir can be designed to interpret machine language instructions compatible with a virtual machine called BEAM, which is established in the processing system of the parent programming language Erlang, making it possible to directly execute the compilation results of the programming language Elixir (a sequence of machine language instructions compatible with BEAM).

[0081] Furthermore, according to the present invention, the logic to be embedded can be generated from program code written in a partial set such as Elixir, which provides an integrated framework, simplifies verification, and reduces development costs.

[0082] Furthermore, the present invention can be understood as simultaneously issuing multiple instructions for multiple-precision multiplication. For example, Elixir has a mechanism for performing multiple-precision integer arithmetic, enabling highly accurate calculations with no upper limit on the numbers it can handle. It also features a mechanism called delayed evaluation, allowing it to handle infinite number sequences. Using multiple-precision integer arithmetic and delayed evaluation, it is possible to build a mechanism for accurately performing numerical calculations with the required precision. By implementing the present invention in a parallelized version of the algorithm proposed in Non-Patent Document 1, it is possible to fully utilize the DSP (Digital Signal Processor) slices in a field programmable gate array (FPGA) capable of performing multiplication, thereby providing a back-end microarchitecture that efficiently executes multiple multiplications simultaneously on integer registers, floating-point registers, and Elixir's multiple-precision integer data. For example, a single DSP slice can perform a 25-bit x 18-bit multiplication, and implementing this in parallel can achieve high numerical calculation performance.

[0083] Furthermore, the present invention can be considered as an accelerator for floating-point number calculations with arbitrary precision / scalar and vector arbitrary precision numerical calculations. While high-speed calculations in AI and image processing often require low-precision, parallel calculations are often performed at high speed, while precision is a top priority in rocket and satellite trajectory calculations. This requires calculations to be performed with the required precision depending on the purpose of the calculation. Elixir's lazy evaluation and multi-precision integer arithmetic mechanisms can be used to perform such calculations. Furthermore, such calculations can be performed in various forms depending on the purpose, such as scalar values, vectors, and matrices. Furthermore, in space applications, the same calculations are performed redundantly at the same time, and the result is determined by majority vote. By linking software and hardware, a system can be realized that enables these calculations to be performed efficiently.

[0084] Furthermore, the present invention can be considered as transparent memory reference using a virtual address that uses the hash value of an immutable memory area. To freely perform distributed parallel processing, one of Elixir's features, efficient calculations can be achieved by storing copies of the same data in local memory. Elixir does not change data once it is created in a memory area, so even if multiple copies of the same data are created, they can be treated as the same data. To quickly determine whether two pieces of data are identical, cryptographic techniques are used to calculate the hash value of the data in advance. If the hash values ​​are identical, the data contents are almost always identical. The hash value of an immutable memory area remains unchanged once calculated. Therefore, by treating the hash value as an offset value of a virtual address to an immutable memory area, data identity can be determined using the virtual address, significantly facilitating appropriate memory management of local copies and facilitating memory management in a distributed parallel environment.

[0085] Furthermore, the present invention can be considered a code generation method that assumes that hazards do not occur. Hazards occur when code with inter-instruction dependencies or conditional branch instructions is executed on a pipelined CPU, requiring the implementation of logic execution to address hazards. Elixir program code, on the other hand, allows dependencies to be fully readable. By consolidating conditional branch instructions at the function entry point through code conversion, conditional branching can be eliminated in the function body. Furthermore, the use of virtual registers can resolve dependencies between instructions that can be resolved by renaming registers. Therefore, when compiling from Elixir, the compiler generates code blocks that perform conditional branching only at the function entry point and do not include conditional branching in the function body. This reduces inter-instruction dependencies using virtual registers, and explicitly specifies the remaining inter-instruction dependencies. This eliminates the need for hazard response on the processor side. This eliminates the possibility of hazards occurring in the function body and eliminates the need to implement logic to address hazards. This reduces circuit area and development time.

[0086] Furthermore, the present invention can be considered as a method for dynamically changing the performance characteristics of a core. In conventional CPUs, the logic is fixed, so the characteristics of the physical core are also fixed. In the present invention, by utilizing the FPGA's ability to dynamically change logic and partially update logic, the performance characteristics of the core can be dynamically changed as needed.

[0087] Furthermore, the present invention may be understood as the generation of branch prediction hints based on coding practices, efficient and reliable exception handling and interrupts, and the generation of logic and software specialized for high-speed web systems of 100G or more.

[0088] The advantage of DSA is that it can extract higher performance than conventional CPUs by specializing it for specific applications. The DSA realized by the present invention can, for example, directly execute compiled results, allowing for a wide range of applications (e.g., web applications, IoT, machine learning, etc.) to be realized while enjoying the high performance of DSA. [Explanation of symbols]

[0089] 1 Parallel Execution System 3 Compilation Device 5 Parallel Execution Processing Unit 7 Source program storage section 9 Compilation processing section 11 Input / output processing unit 12 Executable program storage device 13 Central Processing Unit 15 Front end 16 internal memory 17 Back-end section 21 Active mask group processing unit 23 Fetch processing section 25 Decoding processing section 27 Instruction Memory 29 Active mask group memory unit 31 Program counter group memory unit 33 Instruction register group storage unit 35 Comparison mask group memory section 41 Extended logic execution processing unit 43 Execution Devices 45 Execution Device

Claims

1. An information processing device that executes a plurality of instructions in parallel, The device comprises a front end unit, an internal memory, and a back end unit, the front end unit includes a fetch processing unit and a decode processing unit, the internal memory includes a program counter group storage unit and an instruction register group storage unit; the back-end unit includes an extended logic execution processing unit and an execution device group; the fetch processing unit reads a plurality of instructions into the instruction register group storage unit collectively by using a plurality of program counters included in the program counter group storage unit; the decoding processing unit decodes the instructions read into the instruction register group storage unit and instructs the back-end unit to execute the instructions; The extended logic execution processing unit executes instructions that are instructed to be executed in one or more execution devices included in the group of execution devices.

2. 2. The information processing device according to claim 1, wherein the decoding processing unit performs decoding processing for an instruction having an opcode identical to a target opcode among the plurality of instructions read into the instruction register group storage unit by combining an operand of the instruction with the target opcode.

3. 2. The information processing apparatus according to claim 1, wherein the number of program counters included in said program counter group storage unit is greater than the number of instructions that can be simultaneously executed in said execution unit group.

4. the internal memory includes an active mask set storage unit; the front end unit includes an active mask group processing unit; the number of the program counters included in the program counter group storage unit is n (n is a natural number equal to or greater than 2); the active mask group processing unit includes n active masks corresponding to the n program counters, Each active mask holds data indicating whether a corresponding program counter is active or not; 2. The information processing device according to claim 1, wherein said fetch processing unit reads instructions into said instruction register group storage unit all at once by using a program counter corresponding to said active mask that holds data that is to be active.

5. An instruction parallel execution method for executing a plurality of instructions in parallel, comprising: The information processing device includes a front-end unit, an internal memory, and a back-end unit, the front end unit includes a fetch processing unit and a decode processing unit, the internal memory includes a program counter group storage unit and an instruction register group storage unit; the back-end unit includes an extended logic execution processing unit and an execution device group; a fetch step in which the fetch processing unit reads a plurality of instructions into the instruction register group storage unit all at once using a plurality of program counters included in the program counter group storage unit; a decoding step in which the decoding processing unit decodes the plurality of instructions read into the instruction register group storage unit and instructs the back-end unit to execute the instructions; An instruction parallel execution method including an execution step in which the extended logic execution processing unit executes instructions instructed to be executed in one or more execution devices included in the group of execution devices.

6. A program for causing a computer to function as the decoding processing unit according to claim 1.

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