Semiconductor device

Abstract

To provide a transistor on which shape failure is not likely to occur, a transistor with excellent electric characteristics, and a semiconductor device with excellent electric characteristics.SOLUTION: In a semiconductor device, a transistor 100 has a semiconductor layer 108, a first insulating layer 110 located on the semiconductor layer, a metal oxide layer 114 located on the first insulating layer, a functional layer 113 located on the metal oxide layer, and a conductive layer 112 located on the functional layer. The semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions that overlap with each other. In a channel length direction (A1-A2 direction) of the transistor, end parts of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are located on the inside relative to an end part of the semiconductor layer. An etching rate of the functional layer against an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, chloric acid, and sulfuric acid is lower than that of the conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a display device. One embodiment relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and the like. , electronic device, lighting device, input device, input / output device, driving method thereof, or manufacturing method thereof Semiconductor devices function by utilizing the semiconductor properties. This refers to all devices that can do this. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials that can be used in transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and the plurality of oxide semiconductor layers are Among the oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and By increasing the ratio of indium to that of gallium, the field effect mobility (simply called mobility) can be improved. A semiconductor device with enhanced mobility, or μFE, is disclosed.

[0004] Metal oxides that can be used for the semiconductor layer can be formed using a sputtering method or the like. Therefore, it can be used for the semiconductor layer of a transistor that constitutes a large display device. By improving some of the production facilities for transistors using polycrystalline silicon and amorphous silicon, This allows for the use of metal oxide transistors, which reduces capital investment. The capacitor has a higher field effect mobility than amorphous silicon, so it can be used in the drive circuit. A high-performance display device can be realized.

[0005] In addition, the screen size of display devices is becoming larger, with diagonal sizes of 60 inches or more. Furthermore, development is underway with a view to screen sizes of 120 inches or more diagonally. The screen resolution is also full HD (1920 x 1080 pixels, or "2K" etc.) ), Ultra Hi-Vision (3840 x 2160 pixels, or "4K" ), Super Hi-Vision (pixel count 7680 x 4320, or "8 It is also called "K".) and there is a trend towards higher resolution.

[0006] Larger screen sizes and higher resolutions tend to increase the wiring resistance within the display. In the literature 2, in a liquid crystal display device using amorphous silicon transistors, an increase in wiring resistance In order to suppress the increase in resistance, a technique for forming a low-resistance wiring layer using copper (Cu) has been disclosed. do. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-7399 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-163901 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a transistor that is less likely to have a shape defect. Another object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a semiconductor device with stable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable display device. This is one of the challenges.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter can be extracted from the description, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention includes a transistor. The transistor includes a semiconductor layer and a first insulating layer. a metal oxide layer, a functional layer, and a conductive layer, and a first insulating layer is located on the semiconductor layer. The metal oxide layer is located on the first insulating layer, and the functional layer is located on the metal oxide layer. The conductive layer is located on the functional layer, and the conductive layer is formed by a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. have overlapping regions, and are separated in the channel length direction of the transistor by a first insulating layer, The ends of the metal oxide layer, the functional layer, and the conductive layer are located inside the end of the semiconductor layer, and the functional layer is a semiconductor whose etching rate in one etchant is slower than the etching rate of the conductive layer. It is a device.

[0011] Another embodiment of the present invention includes a transistor. The transistor includes a semiconductor layer and a first The semiconductor device has an insulating layer, a metal oxide layer, a functional layer, and a conductive layer, and the first insulating layer is disposed on the semiconductor layer. a metal oxide layer is located on the first insulating layer, and a functional layer is located on the metal oxide layer. The conductive layer is located on the functional layer, and the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and The conductive layers have overlapping regions, and are arranged in a channel length direction of the transistor, such that the first insulating layer the edges of the edge layer, the metal oxide layer, the functional layer, and the conductive layer are located inside the edges of the semiconductor layer; The functional layer has an etching rate in an etchant containing hydrogen peroxide that is faster than that of the conductive layer. It is a semiconductor device whose switching speed is slower than that of the conventional semiconductor device.

[0012] Another embodiment of the present invention includes a transistor. The transistor includes a semiconductor layer and a first The semiconductor device has an insulating layer, a metal oxide layer, a functional layer, and a conductive layer, and the first insulating layer is disposed on the semiconductor layer. a metal oxide layer is located on the first insulating layer, and a functional layer is located on the metal oxide layer. The conductive layer is located on the functional layer, and the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and The conductive layers have overlapping regions, and are arranged in a channel length direction of the transistor, such that the first insulating layer the edges of the edge layer, the metal oxide layer, the functional layer, and the conductive layer are located inside the edges of the semiconductor layer; The functional layer is etched in an etchant having one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid. The etching rate of the semiconductor device is slower than the etching rate of the conductive layer.

[0013] In the semiconductor device, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are , it is preferable that the top surface shapes are roughly the same.

[0014] In the semiconductor device, the first insulating layer, the metal oxide layer, and the functional layer are formed in a top surface configuration. It is preferable that the shapes of the first and second insulating layers are substantially the same, and the end of the conductive layer is located inside the end of the first insulating layer. .

[0015] In the semiconductor device, the first insulating layer and the metal oxide layer have a top surface shape of approximately The functional layer and the conductive layer have substantially the same top surface shape, and the end of the conductive layer is in contact with the first insulating layer. It is preferable that the position is more inward than the end.

[0016] In the semiconductor device, the metal oxide layer, the functional layer, and the conductive layer have an upper surface shape of approximately It is preferable that they are substantially aligned, and the end of the conductive layer is located more inward than the end of the first insulating layer.

[0017] In the semiconductor device, the metal oxide layer and the functional layer have substantially the same top surface shape. The end of the conductive layer is located inside the end of the metal oxide layer, and the end of the metal oxide layer is located inside the first It is preferable that the insulating layer 1 is positioned inside the end of the insulating layer 1.

[0018] The semiconductor device further includes a second insulating layer, and the semiconductor layer is a first The insulating layer has a first region that does not overlap the first region, and the second insulating layer contacts the first region. The layer preferably comprises silicon, nitrogen and hydrogen. [Effects of the Invention]

[0019] According to one embodiment of the present invention, a transistor that is less likely to have a defective shape can be provided. Therefore, a transistor having good electrical characteristics can be provided. Alternatively, a semiconductor device having stable electrical characteristics can be provided. Alternatively, a semiconductor device having high reliability can be provided. It is possible to provide a semiconductor device with high reliability, or a display device with high reliability.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. can be extracted from descriptions in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0021] [Figure 1] 1A is a top view showing a configuration example of a semiconductor device, and FIGS. 1B and 1C are cross-sectional views showing the configuration example of a semiconductor device. [Figure 2] 2A is a top view showing an example of the configuration of a semiconductor device, and FIGS. 2B and 2C are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 3] 3A is a top view showing an example of the configuration of a semiconductor device, and FIGS. 3B and 3C are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 4] 4A is a top view showing an example of the configuration of a semiconductor device, and FIGS. 4B and 4C are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 5] 5A is a top view showing an example of the configuration of a semiconductor device, and FIGS. 5B and 5C are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 6] 6A, 6B, 6C, 6D, 6E, and 6F are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 7] 7A is a top view showing an example of the configuration of a semiconductor device, and FIGS. 7B and 7C are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 8] 8A, 8B, and 8C are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 9] 9A, 9B, and 9C are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 10] 10A and 10B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 11] 11A and 11B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 12] 12A and 12B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 13] 13A and 13B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 14] 14A and 14B are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 15] 15(A), (B), and (C) are top views of the display device. [Figure 16] FIG. 16 is a cross-sectional view of the display device. [Figure 17] FIG. 17 is a cross-sectional view of the display device. [Figure 18] FIG. 18 is a cross-sectional view of the display device. [Figure 19] FIG. 19 is a cross-sectional view of the display device. [Figure 20] 20(A) is a block diagram of the display device, and FIGS. 20(B) and 20(C) are circuit diagrams of the display device. [Figure 21] 21A, 21C, and 21D are circuit diagrams of the display device, and FIG. 21B is a timing chart of the display device. [Figure 22] 22(A) and (B) show examples of the configuration of a display module. [Figure 23] 23(A) and (B) show examples of the configuration of electronic equipment. [Figure 24] 24(A), (B), (C), (D), and (E) show examples of the configuration of electronic devices. [Figure 25] 25(A), (B), (C), (D), (E), (F), and (G) show examples of the configuration of electronic devices. [Figure 26] 26(A), (B), (C), and (D) show examples of the configuration of electronic devices. [Figure 27] Figures 27(A) and (B) are cross-sectional STEM images. [Figure 28] FIG. 28 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 29] Figures 29(A) and (B) are cross-sectional STEM images. [Figure 30]FIG. 30 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 31] 31(A) and (B) are diagrams showing the cross-sectional structure of the sample. [Figure 32] 32(A) and (B) show the results of TDS analysis. [Figure 33] 33(A) and (B) are diagrams showing hydrogen concentrations. [Figure 34] Fig. 34(A) is a graph showing the hydrogen concentration, and Fig. 34(B) is a graph showing the hydrogen concentration and the carrier density. [Figure 35] FIG. 35 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 36] FIG. 36 is a diagram showing the Id-Vg characteristics of a transistor. [Figure 37] 37(A) and 37(B) are diagrams showing the amount of variation in threshold voltage in a reliability test. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be embodied in various different forms without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various modifications may be made to the embodiments and details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In addition, in each drawing described in this specification, the size, layer thickness, or area of ​​each component may be may be exaggerated for clarity.

[0024] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the number of components. This is added to avoid confusion and is not intended to limit the number.

[0025] In addition, in this specification, the terms "above" and "below" that indicate placement refer to the relationship between components. The positional relationship between the components is used for convenience in explaining the drawings. The positional relationship between the elements changes depending on the direction in which each element is depicted. The terms are not limited to those explained in the detailed description, but may be rephrased appropriately depending on the situation.

[0026] In this specification and the like, the functions of the source and the drain of a transistor are different. When using polarity transistors or when the direction of current changes during circuit operation, etc. For this reason, the terms source and drain are sometimes used interchangeably. It is possible to do so.

[0027] In this specification, the channel length direction of a transistor is the direction in which the source region and the drain region are connected. This refers to one of the directions parallel to the line connecting the gate regions at the shortest distance. The direction corresponds to one of the directions of current flow through the semiconductor layer when the transistor is in the on state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the transistor, the channel length direction and the channel width direction are determined as one. This may not be possible.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0029] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the terms "conductive layer" and "insulating layer" can be interchanged with "conductive film" and "insulating layer." The term "insulating film" may be used interchangeably in some cases.

[0030] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is off. This refers to the drain current when the device is in a non-conducting state (also known as a cut-off state). Unless otherwise specified, for an n-channel transistor, the voltage V between the gate and source gs is the threshold voltage V th (For p-channel transistors, V th Higher than (i) This refers to a state.

[0031] In this specification, a display panel, which is one aspect of a display device, displays (outputs) an image or the like on a display surface. Therefore, a display panel is one aspect of an output device.

[0032] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuit) or TCP (Tape Carrier Packet ge) or a connector such as COG (Chip On Ground) is attached to the board. The IC mounted on the display panel module is called a display module. It may also be called a display panel or simply a display panel.

[0033] In this specification and the like, a touch panel, which is one aspect of a display device, is a device for displaying images and the like on a display surface. The function of displaying the information and detecting when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. It also functions as a touch sensor to detect when something is touching the screen. A rule is one form of input / output device.

[0034] The touch panel is, for example, a display panel (or display device) with a touch sensor, A touch panel can also be called a display panel (or display device) with a touch function. Alternatively, the display panel may have a touch sensor panel. It may also be configured to have a touch sensor function inside or on the surface.

[0035] In addition, in this specification, a touch panel substrate on which a connector or IC is mounted is referred to as a touch panel. , touch panel module, display module, or simply touch panel. be.

[0036] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to one embodiment of the present invention will be described. and explain.

[0037] One embodiment of the present invention is a method for manufacturing a semiconductor device including: a semiconductor layer in which a channel is formed on a formation surface; a gate insulating layer (also called a first insulating layer), a functional layer on the gate insulating layer, and a gate insulating layer on the functional layer. The transistor has a conductive layer (also referred to as a first conductive layer) that functions as an electrode. The semiconductor layer is composed of a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. It is preferable that this be done.

[0038] It is preferable to use a low resistance material for the conductive layer. This reduces the parasitic resistance and makes it possible to provide a transistor with a high on-state current. A semiconductor device with a high current can be obtained. By reducing the wiring resistance in the conductive layer, signal delay can be suppressed, enabling high-speed driving. Copper, silver, gold, aluminum, etc. can be used as the material. Copper is particularly suitable for mass production. This is preferable because

[0039] A shape in which the edge of the layer on which the conductive layer is formed is located inside the edge of the conductive layer, so-called under If a cut occurs, the covering property of the layer formed later will be reduced, and the layer will have steps or voids. Defects such as undercuts can cause variations in the electrical characteristics of transistors. There is a risk of problems such as burns.

[0040] In one embodiment of the present invention, a functional layer is provided as a layer on which a conductive layer is formed, and an etching treatment is performed to process the conductive layer. The etching rate in the etchant is the same as or slower than the conductive layer. This configuration can suppress the occurrence of undercuts and reduce the occurrence of shape defects. Furthermore, it is possible to make a transistor with good electrical characteristics. can be done.

[0041] Furthermore, it is preferable that the functional layer is made of a material that has high adhesion to the conductive layer. The high adhesion between the functional layer and the conductive layer allows the etchant to It can prevent the formation of voids between the functional layer and the conductive layer.

[0042] A more specific example will be described below with reference to the drawings.

[0043] <Configuration example 1> 1A is a top view of a transistor 100, and FIG. 1B is a top view of the transistor 100 shown in FIG. FIG. 1(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line A1-A2 shown in FIG. 1(A). It corresponds to a cross-sectional view of the cut surface taken along the dashed line B1-B2. Some of the components of the transistor 100 (such as a protective layer) are omitted in the illustration. The direction of the line A1-A2 corresponds to the channel length direction, and the direction of the dashed line B1-B2 corresponds to the channel width direction. In addition, top views of the transistors in the following drawings are similar to those in FIG. , some of the components will be omitted in the illustration.

[0044] The transistor 100 is provided on a substrate 102, an insulating layer 103, a semiconductor layer 108, an insulating layer 109, a semiconductor layer 109a, and a semiconductor layer 109b. Edge layer 110, metal oxide layer 114, functional layer 113, conductive layer 112, insulating layer 116, insulating layer The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 11 0 is provided to cover a part of the upper surface of the insulating layer 103 and a part of the upper surface of the semiconductor layer 108. The metal oxide layer 114, the functional layer 113, and the conductive layer 112 are stacked in this order on the insulating layer 110. The semiconductor layer 108 and the insulating layer 106 are provided as layers, and have portions overlapping with the semiconductor layer 108 .

[0045] The insulating layer 110, the metal oxide layer 114, the functional layer 113, and the conductive layer 112 have mutually different top surface shapes. It has been processed to roughly match the original.

[0046] In this specification, the phrase "the upper surface shapes are roughly the same" means that there is at least a small difference between the layers. For example, the upper and lower layers may have the same mask pattern. This includes cases where the entire surface is processed using the same mask pattern, or where part of the surface is processed using the same mask pattern. The edges of the upper layer are located inside the edges of the lower layer, and the edges of the upper layer are located inside the edges of the lower layer. It may be located outside the edge of the layer, in which case it is also said that the "top surface shape roughly matches."

[0047] The insulating layer 116 is formed on the upper and side surfaces of the conductive layer 112, the side surfaces of the functional layer 113, and the metal oxide layer 114. 14, the side of the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and the insulating layer 103 The insulating layer 118 is provided to cover the upper surface of the insulating layer 116. The insulating layer 118 and the insulating layer 116 function as protective layers to prevent the diffusion of impurity elements from the outside. It can be controlled.

[0048] The functional layer 113 and a part of the conductive layer 112 function as a gate electrode. The transistor 100 has a gate insulating layer on the semiconductor layer 108. This is a so-called top-gate transistor in which a top electrode is provided.

[0049] As shown in FIGS. 1A and 1B, the transistor 100 includes an insulating layer 118 The conductive layer 120a and the conductive layer 120b may be disposed on the conductive layer 120a. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. 20b are openings 141a and 20b provided in the insulating layer 118 and the insulating layer 116, respectively. The opening 141b is electrically connected to a region 108N, which will be described later.

[0050] The semiconductor layer 108 preferably comprises a metal oxide.

[0051] For example, the semiconductor layer 108 may be formed of indium and an element M (the element M may be gallium, aluminum, or the like). , silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One or more selected from hafnium, tantalum, tungsten, and magnesium It is preferable that the element M contains aluminum, gallium, yttrium, and zinc. It is preferable to use one or more selected from the group consisting of zinc, zinc oxide, and tin.

[0052] In particular, the semiconductor layer 108 is made of an oxide containing indium, gallium, and zinc. It is preferable.

[0053] The semiconductor layer 108 may be a layer having different compositions, different crystallinity, or different impurity concentrations. Alternatively, a laminated structure may be formed by laminating the above layers.

[0054] The conductive layer 112 may be made of one or more materials selected from copper, silver, gold, and aluminum. In particular, copper is preferable because it has low resistance and is suitable for mass production.

[0055] The metal oxide layer 114 located between the insulating layer 110 and the functional layer 113 is It functions as a barrier film that prevents oxygen contained therein from diffusing toward the conductive layer 112. The metal oxide layer 114 is formed by diffusing hydrogen and water contained in the conductive layer 112 to the insulating layer 110 side. The metal oxide layer 114 also functions as a barrier film to prevent, for example, at least the insulating layer 11 A material that is less permeable to oxygen and hydrogen than 0 can be used.

[0056] The metal oxide layer 114 allows the conductive layer 112 to easily absorb oxygen, such as aluminum or copper. Even if a thin metal material is used, oxygen does not diffuse from the insulating layer 110 to the conductive layer 112. Even when the conductive layer 112 contains hydrogen, the conductive layer 112 Therefore, it is possible to prevent hydrogen from diffusing into the semiconductor layer 108 via the insulating layer 110. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0057] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the oxide layer 114 has insulating properties, it functions as a part of the gate insulating layer. If the metal oxide layer 114 is conductive, it functions as a part of the gate electrode.

[0058] The metal oxide layer 114 is made of an insulating material having a higher dielectric constant than silicon oxide. In particular, an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable. It is preferable to use a film such as a PET film, since the driving voltage can be reduced.

[0059] The metal oxide layer 114 may be, for example, indium oxide or indium tin oxide (ITO). ), or silicon-containing indium tin oxide (ITSO), In particular, conductive oxides containing indium are preferred because of their high conductivity. stomach.

[0060] The metal oxide layer 114 may be an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108. In this case, it is preferable to use the same type of metal oxide layer 114 as the semiconductor layer 108. By applying metal oxide films formed using sputtering targets, equipment can be standardized. This is preferable because it allows

[0061] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When a metal oxide material containing gallium is used, the composition (content ratio) of gallium is higher than that of the semiconductor layer 108. It is preferable to use a material having a high oxygen blocking property. At this time, the semiconductor layer 108 contains a material having a higher indium content than the metal oxide layer 114. By using such a material, the field-effect mobility of the transistor 100 can be increased.

[0062] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an oxide film is formed using a sputtering device, it is formed in an atmosphere containing oxygen gas. This allows oxygen to be suitably added to the insulating layer 110 and the semiconductor layer 108.

[0063] The functional layer 113 located between the metal oxide layer 114 and the conductive layer 112 has oxidation resistance. It is preferable to use a conductive material that has oxidation resistance. This can prevent the resistance of the layer 113 from increasing.

[0064] The metal oxide layer 114 and the functional layer 113 are also formed by etching with an etcher used to process the conductive layer 112. The etching rate of the conductive layer 112 is equal to or slower than that of the conductive layer 112. is preferred.

[0065] If the etching rate of the metal oxide layer 114 and the functional layer 113 is faster than that of the conductive layer 112, The ends of the metal oxide layer 114 and the functional layer 113 are located inside the ends of the conductive layer 112. Undercutting is likely to occur. If undercutting occurs, the insulating layer 116 to be formed later may be damaged. The coverage of the insulating layer 118 is reduced, and the insulating layer 116 and the insulating layer 118 are discontinuous or have low density. This can cause problems such as areas of porosity (also known as pockets).

[0066] In one embodiment of the present invention, the etching rates of the metal oxide layer 114 and the functional layer 113 are By configuring the thickness of the conductive layer 112 to be approximately the same as or slower than the conductive layer 112, the thickness of the undercut can be reduced. This can suppress the generation of defects, making it possible to produce a transistor that is less prone to shape defects. This allows the transistor to have good characteristics.

[0067] In addition, the etchant used to process the conductive layer 112 is used to process the functional layer 113 in the same process. The metal oxide layer 114 and the conductive layer 112 can be formed. The top surface shapes of the active layer 113 and the conductive layer 112 can be made to roughly match each other.

[0068] The etching rate of the insulating layer 110 is the same as that of the metal oxide layer 114, the functional layer 113, and the conductive layer 111. It is preferable that the etching rate of the insulating layer 110 is slower than that of the metal oxide layer 114, the functional layer 116, and the insulating layer 110. By forming the metal oxide layer 114 and the conductive layer 112 in a slower structure than the functional layer 113, In order to reduce the amount of insulating layer 110 that is etched during the formation of layer 113 and conductive layer 112, It is possible.

[0069] In addition, the functional layer 113 has high adhesion to the metal oxide layer 114 and the conductive layer 112. For example, in a configuration in which the conductive layer 112 is formed on the metal oxide layer 114, If the adhesion of these layers is low, etching may occur when forming the metal oxide layer 114 and the conductive layer 112. The chants penetrate between the metal oxide layer 114 and the conductive layer 112, and the metal oxide layer 11 In some cases, a gap may occur between the metal oxide layer 4 and the conductive layer 112. In one embodiment of the present invention, By providing the functional layer 113 between the metal oxide layer 114 and the conductive layer 112, The adhesion between the functional layer 113 and the conductive layer 112 is increased, and the occurrence of voids between these layers is suppressed. This can reduce the occurrence of shape defects in the transistor. This can be a good transistor.

[0070] Furthermore, it is preferable that the functional layer 113 releases a small amount of impurities containing hydrogen. The impurities contained in the functional layer 113 include, for example, hydrogen and water. When the hydrogen is released, it reaches the channel forming region of the semiconductor layer 108. The oxygen in the hole formation region is bonded to the oxygen and released as water, creating an oxygen vacancy (hereafter referred to as oxygen vacancy) in the channel formation region. , V O In addition, oxygen vacancies (V O ) and When hydrogen and oxygen vacancies (V O ) with hydrogen (hereinafter referred to as V O H) V O H acts as a carrier source and improves the electrical and signal characteristics of the transistor. The functional layer 113 that releases less hydrogen-containing impurities may have a negative effect on reliability. By using this, good electrical properties and reliability can be obtained.

[0071] Furthermore, it is preferable that the functional layer 113 releases a small amount of impurities containing oxygen. The impurities contained in the functional layer 113 include, for example, oxygen, water, etc. When oxygen is released, the resistance of the conductive layer 112 increases when the oxygen reaches the conductive layer 112. By using the functional layer 113 that releases less impurities containing oxygen, This can prevent the resistance of the layer 112 from increasing.

[0072] The functional layer 113 can be made of a metal oxide. For example, indium oxide, Indium tin oxide (ITO), silicon-doped indium tin oxide (ITSO) Indium-containing oxides such as ITSO can be used. This makes it difficult for the film to crystallize and provides excellent flatness, which improves adhesion to the film formed on the ITSO. In addition, the indium zinc oxide, zinc oxide, and gallium-containing Metal oxides such as zinc oxide can also be used.

[0073] The functional layer 113 is made of a material containing indium and an element M (the element M is gallium, aluminum, or the like). Aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, or magnesium In particular, the element M may be an oxide containing aluminum, It is preferable to use one or more selected from gallium, yttrium, and tin. For example, in In-Ga-Zn oxide, the atomic ratio of In is larger than that of Ga. In particular, the number of atoms of In, element M, and Zn in the functional layer 113 is preferably The ratio of In:M:Zn is preferably 4:2:3 or close to 4:2:3. The ratio of the numbers of atoms of In, M, and Zn is preferably In:M:Zn=5:1:6 or close to that. In addition, the composition of the semiconductor layer 108 is preferably In, element M, and Zn. The ratio of the number of atoms of In, element M, and Zn may be approximately equal. However, it may contain materials in which In:M:Zn=1:1:1 or a similar ratio.

[0074] The functional layer 113 may be made of aluminum, titanium, chromium, nickel, copper, yttrium, or the like. metals such as aluminum, zirconium, molybdenum, silver, tantalum, or tungsten, or An alloy containing this as a main component can be used.

[0075] The functional layer 113 is preferably made of a material different from that of the metal oxide layer 114 and the conductive layer 112. In this specification and the like, different materials refer to materials having different constituent elements, or materials having different constituent elements. The metal oxide layer 114 is densely packed with the conductive layer 112. Even if the adhesion is low, a metal oxide layer is formed between the metal oxide layer 114 and the conductive layer 112. By providing a functional layer 113 having a different material from the metal oxide layer 114, The adhesiveness to the conductive layer 112 can be improved.

[0076] The functional layer 113 may have a structure in which two or more layers of the above-mentioned materials are laminated.

[0077] The semiconductor layer 108 has a channel forming region that overlaps with the conductive layer 112 via the insulating layer 110. The semiconductor layer 108 has a pair of regions 108N that sandwich the channel formation region. The region 108N is a region in the semiconductor layer 108 where either the conductive layer 112 or the insulating layer 110 is present. The region is a region that does not overlap with the insulating layer 116 at all and is in contact with the insulating layer 116.

[0078] The region 108N is a region having a lower resistance than the channel formation region, a region having a higher carrier density, and an oxide These regions can also be called regions with high density of elementary defects, regions with high impurity concentration, or regions that are n-type. Cut.

[0079] The region 108N is a region containing an impurity element (hereinafter referred to as a first element). Examples of elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. Examples of rare gases include hydrogen, magnesium, and rare gases. These include uranium, neon, argon, krypton, and xenon. In particular, boron, phosphorus, ma It is preferable that the alloy contains magnesium or aluminum. It's fine.

[0080] The insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 are formed of an oxide. It is preferable to use a film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. An oxide film such as a tungsten film can be used. Oxygen released from the insulating layer 103 and the insulating layer 110 by heat treatment in the process is released into the semiconductor layer 1 The oxygen vacancies in the semiconductor layer 108 can be reduced by supplying the oxygen to the channel formation region of the semiconductor layer 108. 1(C) and 1(D), the insulating layer 110 and the insulating layer 103 are shown as single-layer structures. A laminated structure of more than one layer may also be used.

[0081] The insulating layer 103 preferably has a laminated structure of a nitride film and an oxide film on the nitride film. For example, nitride films include silicon nitride, silicon nitride oxide, aluminum nitride, and nitride. Aluminum oxide or the like can be used. By providing a nitride film under the insulating layer 103, This prevents impurities from the layer below the insulating layer 103 from diffusing to the layer above the insulating layer 103. In addition, an oxide film is formed on the upper side of the insulating layer 103 in contact with the channel forming region. By providing the insulating layer 103, oxygen desorbed from the insulating layer 103 can be supplied to the channel formation region. The edge layer 103 may be, for example, a silicon nitride film and a silicon oxynitride film on the silicon nitride film. It can have a laminated structure.

[0082] In this specification and the like, an oxynitride is a compound having a higher oxygen content than nitrogen content. Oxynitride is a substance that has a higher content of oxygen than silicon dioxide. Nitrogen oxide is a type of nitride.

[0083] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 112 has a region that overlaps with the insulating layer 112 and functions as a gate insulating layer.

[0084] Here, the impurity concentration in the region 108N becomes higher as it approaches the insulating layer 116. It is preferable to have a concentration gradient such that a uniform concentration gradient is obtained throughout the region 108N. Since the total amount of the first element in the region 108N can be reduced compared to when the concentration is set to 100%, the manufacturing process can be simplified. The amount of impurities that can diffuse into the channel formation region due to the influence of heat during the process can be kept low. In addition, since the resistance becomes lower toward the upper part of the region 108N, the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced.

[0085] As will be described later, the process of doping the region 108N with the first impurity element is performed by removing the insulating layer 110. This can be done as a mask, which allows the region 108N to be formed in a self-aligned manner.

[0086] The region 108N has an impurity concentration of 1×10 19 atoms / cm 3 That's it, 1×10 23 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 That's it, 5 x 10 2 2 atoms / cm 3 Less than 1×10, more preferably 20 atoms / cm 3 That's it, 1x 10 22 atoms / cm 3 It is preferred to include a region in which:

[0087] The concentration of impurities contained in the region 108N can be measured by, for example, secondary ion mass spectrometry (SIMS). Electron Mass Spectrometry (EIS) and X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) etc. When XPS analysis is used, the image can be analyzed from the front or back side. By combining on-sputtering and XPS analysis, concentration distribution in the depth direction can be determined. can be done.

[0088] In the region 108N, the first element is preferably present in an oxidized state. For example, the first element may be boron, phosphorus, magnesium, aluminum, silicon, etc. It is preferable to use an element that is easily oxidized. Since it can bond with oxygen in 108 and exist stably in an oxidized state, it can be used at high temperatures ( For example, even if temperatures exceed 400°C, 600°C, or 800°C, In addition, the first element removes oxygen from the semiconductor layer 108, Many oxygen vacancies are generated in the region 108N. These oxygen vacancies are combined with hydrogen in the film, This makes the region 108N a carrier supply source, and the region 108N is in an extremely low resistance state.

[0089] When a high temperature treatment is performed in a later step, the film may be heated from the outside or the film near the region 108N. If too much oxygen is supplied to the region 108N, the resistance may increase. Therefore, when performing a high-temperature process, the insulating layer 1 having a high barrier property against oxygen is required. It is preferable to carry out the treatment with the semiconductor layer 108 covered with 16 .

[0090] The insulating layer 116 is provided in contact with the region 108N of the semiconductor layer 108.

[0091] The insulating layer 116 serves as a source of hydrogen for the region 108N. The insulating layer 116 is preferably a film that releases hydrogen when heated. is provided in contact with the region 108N, and a heat treatment is performed after the insulating layer 116 is formed. Hydrogen can be supplied to the 08N to lower the resistance.

[0092] The insulating layer 116 is formed using a gas containing hydrogen element as a film formation gas. This prevents water from entering the region 108N during the formation of the insulating layer 116. It can supply the ingredients effectively.

[0093] The insulating layer 116 may be made of, for example, silicon nitride, silicon nitride oxide, or silicon oxide nitride. An insulating film such as aluminum nitride or aluminum nitride oxide can be used.

[0094] The region 108N is in a state where many oxygen vacancies are included due to the addition of the first element as described above. Therefore, in addition to the hydrogen contained in the semiconductor layer 108, the hydrogen is further released from the insulating layer 116. By supplying hydrogen to the semiconductor, the carrier density can be further increased.

[0095] The insulating layer 118 functions as a protective layer to protect the transistor 100. For example, inorganic insulating materials such as oxides or nitrides can be used as the insulating layer. Specific examples include silicon nitride, silicon nitride oxide, silicon oxynitride, and aluminum oxide. Hafnium, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium aluminum In addition, the insulating layer 118 can be used as a planarizing layer. In this case, an organic resin material can be used as the insulating layer 118. .

[0096] In this example, the protective layer has a laminated structure of an insulating layer 116 and an insulating layer 118. However, if the insulating layer 118 is unnecessary, it may not be provided. A laminated structure may also be used.

[0097] Here, the semiconductor layer 108 and oxygen vacancies that may be formed in the semiconductor layer 108 will be described. and explain.

[0098] The oxygen vacancies formed in the channel formation region of the semiconductor layer 108 affect the transistor characteristics. For example, when oxygen vacancies are formed in the semiconductor layer 108, the oxygen Hydrogen bonds to the vacancies and can become a carrier source. When this occurs, the electrical characteristics of the transistor 100 change, typically the threshold voltage shift. Therefore, it is preferable that the channel formation region has fewer oxygen vacancies. .

[0099] Therefore, in one embodiment of the present invention, the insulating film in the vicinity of the channel formation region of the semiconductor layer 108 Specifically, the insulating layer 110 located above the channel forming region and the insulating layer 111 located below the channel forming region are The insulating layer 103 includes an oxide film. By transferring oxygen from the insulating layer 110 to the channel formation region, the oxygen in the channel formation region It is possible to reduce the element deficiency.

[0100] The semiconductor layer 108 has a region where the atomic ratio of In to the element M is greater than 1. The higher the In content, the more the field effect mobility of the transistor can be improved. can be done.

[0101] In the case of metal oxides containing In, Ga, and Zn, the bonding strength between In and oxygen is greater than that between Ga and oxide. Since the bonding strength is weaker than that of the element, when the In content is high, oxygen vacancies occur in the metal oxide film. In addition, when a metal element represented by M is used instead of Ga, the same tendency is observed. If there are many oxygen vacancies in the metal oxide film, the electrical characteristics of the transistor will be degraded. and reliability will decrease.

[0102] However, in one embodiment of the present invention, the channel formation region of the semiconductor layer 108 containing a metal oxide A metal oxide material with a high In content is used because it can supply an extremely large amount of oxygen to the This makes it possible to achieve extremely high field-effect mobility, stable electrical properties, and high This makes it possible to realize a transistor that combines high reliability with high reliability.

[0103] For example, the atomic ratio of In to element M is 1.5 or more, or 2 or more, or 3 or more. , or 3.5 or more, or 4 or more, can be suitably used.

[0104] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn=4:2. It is preferable that the ratio of the number of In, M, and Zn atoms is 3 or about 3. It is preferable that the composition ratio of In:M:Zn is 5:1:6 or in the vicinity thereof. As the composition, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of In, M, and Zn atoms is In:M:Zn=1:1:1 or It may also include nearby materials.

[0105] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this as a driver, it is possible to provide a display device with a narrow frame width (also called a narrow frame). The above-mentioned high field effect mobility transistor is used as a source driver (especially when the source driver is By using it in a display A display device with a small number of wires connected to the device can be provided.

[0106] The semiconductor layer 108 has a region where the atomic ratio of In to the element M is greater than 1. However, if the semiconductor layer 108 has high crystallinity, the field-effect mobility may be reduced. The crystallinity of the conductor layer 108 can be determined by, for example, X-ray diffraction (XRD). Analysis is performed using a transmission electron microscope (TEM) or Analysis using a Scatter Electron Microscope Cut.

[0107] Here, the channel forming region of the semiconductor layer 108 has a low impurity concentration and a low defect level density. By reducing the oxygen vacancies, the carrier density in the film can be reduced. A transistor using such a metal oxide film in the channel formation region of the semiconductor layer has a threshold The electrical characteristics where the voltage is negative (also called normally on) are rare. In addition, a transistor using such a metal oxide film has the characteristic of having a significantly small off-state current. It is possible.

[0108] When a metal oxide film with high crystallinity is used for the semiconductor layer 108, the semiconductor layer 108 is easily processed. Damage to the insulating layer 110 during film formation can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with a relatively low crystallinity for the semiconductor layer 108, This improves the electrical conductivity and allows for the realization of a transistor with high field-effect mobility.

[0109] The semiconductor layer 108 is a c-axis aligned crystal (CAAC) layer, which will be described later. Metal oxide film with stal structure, nc (nano crystal) structure Metal oxide films or metal oxide films with a mixture of CAAC and nc structures can be used. preferable.

[0110] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0111] For example, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different compositions. For example, when an In-M-Zn oxide is used, the number of atoms of In, M, and Zn is The ratio is In:M:Zn=5:1:6, In:M:Zn=4:2:3, In:M:Zn=1 :1:1, In:M:Zn=2:2:1, In:M:Zn=1:3:4, In:M:Zn =1:3:2 or a film formed using a sputtering target with a ratio of approximately It is preferable to use two or more laminated layers.

[0112] In addition, the semiconductor layer 108 may be formed by stacking two or more metal oxide films having different crystallinity. In this case, by using the same oxide target and changing the film formation conditions, It is preferable that they are formed continuously without touching each other.

[0113] At this time, the semiconductor layer 108 is made of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, a metal oxide film having an nc structure may be formed. A laminated structure of a metal oxide film and a metal oxide film having an nc structure may be used. The functions of metal oxides suitable for use in the film and the structure of the material will be described later. The description of CAC (Cloud-Aligned Composite) can be used.

[0114] For example, the oxygen flow rate during the deposition of the first metal oxide film is set to be equal to the oxygen flow rate during the deposition of the second metal oxide film. The oxygen flow rate ratio is set to be smaller than that during the formation of the first metal oxide film. During film formation, oxygen is not allowed to flow. This prevents oxygen from flowing during film formation of the second metal oxide film. In addition, the first metal oxide film has a higher crystallinity than the second metal oxide film. On the other hand, the second metal oxide provided on the top The metal oxide film has higher crystallinity than the first metal oxide film, so that the semiconductor layer 108 can be easily processed. Also, damage to the insulating layer 110 during film formation can be suppressed.

[0115] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is set to 0% or more and less than 50%. Preferably, it is 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is set to 50% or more and 100% or less, preferably Preferably, it is 60% or more and 100% or less, more preferably, 80% or more and 100% or less, and even more preferably The first metal oxide film is preferably 90% or more and 100% or less, and typically 100%. The conditions for forming the first metal oxide film and the second metal oxide film, such as pressure, temperature, and power, may be different. By keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened, which is preferable. It's nice.

[0116] By adopting such a configuration, the transistor 100 has excellent electrical characteristics and high reliability. This can be achieved.

[0117] Below, a configuration example of a transistor with a part of its configuration different from that of the above-mentioned Configuration Example 1 will be described. In the following, explanations of parts that overlap with the above-mentioned configuration example 1 may be omitted. In the drawings shown below, parts having the same functions as those in the above-mentioned configuration example 1 are indicated by hatching. In some cases, the turns are the same and no symbols are assigned.

[0118] <Configuration example 2> 2A is a top view of the transistor 100A, and FIG. 2B is a top view of the transistor 100B. 2(C) is a cross-sectional view of the channel length direction of the transistor 100A, and FIG. 2(D) is a cross-sectional view of the channel width direction of the transistor 100A. 1 is a cross-sectional view in the direction of the arrow.

[0119] The transistor 100A has a conductive layer 106 between a substrate 102 and an insulating layer 103. The conductive layer 106 is a channel forming region of the semiconductor layer 108. , and has a region overlapping with the functional layer 113 and the conductive layer 112 .

[0120] In the transistor 100A, the conductive layer 106 is a first gate electrode (bottom gate electrode). The functional layer 113 and the conductive layer 112 function as a second gate electrode. A part of the insulating layer 103 functions as a first gate electrode (also referred to as a top gate electrode). A portion of the insulating layer 110 functions as the first gate insulating layer, and a portion of the insulating layer 110 functions as the second gate insulating layer. do.

[0121] At least one of the functional layer 113, the conductive layer 112, and the conductive layer 106 of the semiconductor layer 108 The overlapping portion functions as a channel forming region. The portion of the semiconductor layer 108 overlapping with the functional layer 113 and the conductive layer 112 is defined as a channel formation region. However, in reality, the conductive layer 106 does not overlap with the functional layer 113 and the conductive layer 112. A channel can also be formed in the overlapping portion (portion including region 108N).

[0122] As shown in FIGS. 2A and 2C, the conductive layer 106 is formed of a metal oxide layer 114. , the functional layer 113 and the insulating layer 103 are exposed to each other through openings 142 provided in the insulating layer 110 and the insulating layer 103. The conductive layer 106 and the functional layer 112 may be electrically connected to each other. The same potential can be applied to the conductive layer 113 and the conductive layer 112 .

[0123] The conductive layer 106 is made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, when a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. In addition, the conductive layer 106 may be made of a high melting point metal such as tungsten or molybdenum. If a material containing such a compound is used, processing can be carried out at a high temperature in a subsequent step.

[0124] As shown in FIGS. 2A and 2C, the functional layer 11 3. The conductive layer 112 and the conductive layer 106 protrude outward beyond the edge of the semiconductor layer 108. At this time, as shown in FIG. 2(C), the semiconductor layer 108 is preferably The entire structure is connected to the functional layer 113 and the conductive layer 112 via the insulating layer 110 and the insulating layer 103. The structure is covered with an insulating layer 106.

[0125] With this configuration, the semiconductor layer 108 is subjected to an electric field generated by the pair of gate electrodes. In this case, the conductive layer 106, the functional layer 113, and the It is preferable to apply the same potential to the conductive layer 112. This allows the semiconductor layer 108 to be channeled. Since an electric field for inducing a current can be effectively applied, the on-current of the transistor 100A Therefore, it is possible to miniaturize the transistor 100A. become.

[0126] The functional layer 113 and the conductive layer 112 may not be connected to the conductive layer 106. At this time, a constant potential is applied to one of the pair of gate electrodes, and the transistor 100A is applied to the other. A signal to drive the transistor may be applied. At this time, the potential applied to one of the electrodes It is also possible to control the threshold voltage when driving the transistor 100A with the other electrode.

[0127] This concludes the description of configuration example 2.

[0128] <Configuration example 3> 3A is a top view of the transistor 100B, and FIG. 3B is a top view of the transistor 100C. 3(C) is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 3(D) is a cross-sectional view of the transistor 100B in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0129] In the transistor 100B, the end of the conductive layer 112 is located inside the end of the insulating layer 110. In other words, the insulating layer 110 is at least semi-transparent. On the conductive layer 108, there is a portion that protrudes outward beyond the end of the conductive layer 112. The insulating layer 110, the metal oxide layer 114, and the functional layer 113 have top surface shapes that are approximately the same as each other. do.

[0130] As shown in FIGS. 3B and 3C, the functional layer 112 in the area overlapping with the conductive layer 112 In some cases, the thickness of the functional layer 113 in the region that does not overlap with the conductive layer 112 may be thinner than the thickness of the functional layer 113 in the region that does not overlap with the conductive layer 112. be.

[0131] The insulating layer 116 is formed on the upper and side surfaces of the conductive layer 112, the side surfaces of the functional layer 113, and the metal oxide layer 114. 14, the side of the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and the insulating layer 103 The cover is provided to cover the upper surface of the

[0132] This concludes the description of configuration example 3.

[0133] <Configuration Example 4> 4A is a top view of the transistor 100C, and FIG. 4B is a top view of the transistor 100C. 4(C) is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 4(D) is a cross-sectional view of the transistor 100C in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0134] In the transistor 100C, the ends of the conductive layer 112 and the functional layer 113 are aligned with the ends of the insulating layer 110. The main difference from Configuration Example 1 is that the insulating layer 110 is located inside the insulating layer 110. is located at least on the semiconductor layer 108, and is located closer to the end of the conductive layer 112 and the functional layer 113. The conductive layer 112 and the functional layer 113 have a top surface shape that is different from each other. The insulating layer 110 and the metal oxide layer 114 have top surface shapes that are approximately the same as each other. do.

[0135] As shown in FIGS. 4B and 4C, the conductive layer 112 and the functional layer 113 overlap each other. The thickness of the metal oxide layer 114 in the area where the conductive layer 112 does not overlap is The thickness of the film 114 may become thin.

[0136] The semiconductor layer 108 has a pair of regions 108L sandwiching a channel forming region, and a pair of regions 108L outside the pair of regions 108L. The region 108L is a portion of the semiconductor layer 108 that overlaps with the insulating layer 110. The region 108L is an offset region that does not overlap with the conductive layer 112. It is possible to do so.

[0137] The region 108L is a region having a resistance equal to or lower than that of the channel forming region. The oxygen defect density is the same or higher, the impurity concentration is the same or higher, and the impurity concentration is the same. It can also be called a high or low level area.

[0138] The region 108L has a resistance similar to or higher than the region 108N, and a carrier density Regions with the same or low oxygen vacancy density, regions with the same or low impurity concentration Or it can be called a low region.

[0139] The carrier density in the region 108L does not have to be uniform. In some cases, the carrier density has a gradient that decreases toward the channel formation region. For example, the hydrogen concentration or the oxygen vacancy concentration in the region 108L, or both of them, The concentration has a gradient that decreases from the region 108N side to the channel forming region side. That's fine.

[0140] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. A region overlapping with the conductive layer 112 and functioning as a gate insulating layer and a region not overlapping with the conductive layer 112 are formed. (i.e., the portion overlapping with region 108L).

[0141] The insulating layer 116 is formed on the upper and side surfaces of the conductive layer 112, the side surfaces of the functional layer 113, and the metal oxide layer 114. 14, the side of the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and the insulating layer 103 The region 108L is insulated by the insulating layer 110 therebetween. Since there is no contact with the edge layer 116, less hydrogen is supplied to the region 108N than to the region 108N. The concentration of the impurities in the region 108L is also lower than that in the region 108N. Therefore, the region 108L has a higher resistance than the region 108N. It can be a state.

[0142] As will be described later, since the region 108L can be formed in a self-aligned manner, the region 1 No photomask is required to form O8L, which reduces manufacturing costs. By forming the region 108L in a self-aligned manner, the region 108L, the functional layer 113, and the conductive layer 114 are Since there is no relative displacement of the layer 112, the region 108L in the semiconductor layer 108 The widths of the electrodes can be roughly matched.

[0143] The electric field of the gate is not applied to the region other than the low-resistance region 108N in the semiconductor layer 108. (or less susceptible than the channel formation region) As a result, the source-drain breakdown voltage of the transistor can be improved, and the reliability can be improved. The width of region 108L is 10 nm or more and 10 μm or less. The thickness is preferably 30 nm or more and 5 μm or less, and more preferably 50 nm or more and 1 μm or less. If the width of the region 108L in the channel length direction is long, the effective channel length becomes long, and the The driving speed may become slower. By setting the width as described above, it is possible to obtain a transistor with a fast driving speed. It is possible.

[0144] When a conductive material is used for the metal oxide layer 114, the metal oxide layer 114 is overlapped with the conductive material. The region 108L is not formed because the electric field of the gate is applied to the semiconductor layer 108 in the region.

[0145] This concludes the description of configuration example 4.

[0146] <Configuration example 5> 5A is a top view of transistor 100D, and FIG. 5B is a top view of transistor 100D. 5(C) is a cross-sectional view of the transistor 100D in the channel length direction, and FIG. 5(D) is a cross-sectional view of the transistor 100D in the channel width direction. 1 is a cross-sectional view in the direction of the arrow.

[0147] The transistor 100D is formed by the conductive layer 112, the functional layer 113, and the edge of the metal oxide layer 114. The main difference from Configuration Example 1 is that the insulating layer 110 is located inside the end of the insulating layer 110. In other words, the insulating layer 110 is formed on at least the semiconductor layer 108, and includes the conductive layer 112, the functional layer 113, and the like. The conductive layer 113 and the metal oxide layer 114 have portions that protrude outward from the ends of the conductive layer 113 and the metal oxide layer 114. The top surface shapes of the metal oxide layer 112, the functional layer 113, and the metal oxide layer 114 are generally the same as each other.

[0148] The insulating layer 116 is formed on the upper and side surfaces of the conductive layer 112, the side surfaces of the functional layer 113, and the metal oxide layer 114. 14, the top and side surfaces of the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and the insulating The insulating layer 118 is provided over the insulating layer 116. An enlarged view of the area surrounded by the dashed line in FIG. 5(B) is shown in FIG. 6(A).

[0149] The semiconductor layer 108 has a pair of regions 108L sandwiching a channel forming region, and a pair of regions 108L outside the pair of regions 108L. The semiconductor layer 108 has a region 108N other than the low-resistance region 108N. A region 108L where the electric field of the port is not applied (or is applied less than the channel forming region) is This allows for stable formation without variations, improving the source-drain breakdown voltage of the transistor. This allows for the realization of a highly reliable transistor. By providing the region 108L between the channel forming region and the low resistance region 108N, The current density at the boundary of the region 108N can be relaxed, and the current density at the boundary between the channel and the source or drain can be reduced. Heat generation due to the heat generation is suppressed, and a highly reliable semiconductor device can be obtained.

[0150] When the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 112 and The non-overlapping part of the insulating layer 110 may be etched, resulting in a thinner insulating layer 110. Specifically, as shown in FIG. 6B, the insulating layer 110 in the region overlapping with the conductive layer 112 When the thickness of the insulating layer 110 in the region not overlapping with the conductive layer 112 is smaller than the thickness of the insulating layer 110 in the region In other words, compared with the film thickness of the insulating layer 110 in the region overlapping with the channel formation region, Therefore, the thickness of the insulating layer 110 in the region that does not overlap with the channel formation region may become thin.

[0151] In FIGS. 5B, 5C, 6A, and 6B, the insulating layer 110 is shown as a single layer structure. However, a laminated structure of two or more layers may be used. 1 shows an example of a two-layer structure consisting of an insulating layer 110a and an insulating layer 110b on the insulating layer 110a. The insulating layer 110a and the insulating layer 110b can be made of insulating materials of the same kind. In some cases, the interface between the insulating layer 110a and the insulating layer 110b may not be clearly visible. In this embodiment, the interface between insulating layer 110a and insulating layer 110b is shown by a dashed line.

[0152] The insulating layer 110a in contact with the channel formation region of the semiconductor layer 108 is It is preferable that the defect density in the vicinity of the interface and in the film is low. It is preferable that the concentration of impurities containing hydrogen is low. It is preferable that the damage to the insulating layer 110a is small. By using a film with low thermal conductivity and by using film formation conditions that cause little damage to the semiconductor layer 108, Therefore, a transistor having good electrical characteristics can be obtained.

[0153] For example, when a film containing silicon is used as the insulating layer 110, the insulating layer 110a is formed as follows. In this case, a film formation condition in which the ratio of the silicon-containing gas to the film formation gas used is low can be used. By using deposition conditions with a low ratio of silicon-containing gas to deposition gas, the defect density and In addition, the insulating layer 110a can be formed with a low impurity concentration. By lowering the power, damage to the semiconductor layer 108 can be reduced.

[0154] The insulating layer 110b in contact with the metal oxide layer 114 is formed by etching with an etcher used to process the conductive layer 112. The etching rate at the interface is equal to or slower than that of the conductive layer 112. It is preferable to set the following.

[0155] The insulating layer 110b is preferably a denser film than the insulating layer 110a. The insulating layer 110b can be formed under film-forming conditions that result in a slower film-forming rate than the insulating layer 110a. The insulating layer 110b is formed on a surface thereof so that water is prevented from being adsorbed thereon. By providing an insulating layer 110b on the surface, water is prevented from being adsorbed on the surface of the insulating layer 110. can.

[0156] When water is adsorbed on the surface of the insulating layer 110, hydrogen contained in the adsorbed water is transferred to the channel forming region. When the temperature reaches 1000 K, carriers are generated in the channel formation region, and the electrical characteristics and reliability of the transistor are deteriorated. The insulating layer 110b, which is less likely to adsorb water, is formed on the top surface of the insulating layer 110. By providing the insulating layer, it is possible to suppress the formation of carriers in the channel forming region, and a good electric current can be obtained. This provides excellent thermal characteristics and reliability.

[0157] The insulating layer 110b may be formed under film-forming conditions that result in a slower film-forming rate than the insulating layer 110a. For example, when a film containing silicon is used as the insulating layer 110, the insulating layer 110b In this case, the ratio of the silicon-containing gas to the deposition gas used during deposition can be set low. Furthermore, compared to the insulating layer 110a, the insulating layer 110b can be formed using a higher film-forming power. This makes it possible to provide an insulating layer that is less likely to adsorb water.

[0158] The insulating layer 110b has an etching rate in one etchant that is slower than that of the insulating layer 110a. It is preferable that the insulating layer 110b has a higher film density than the insulating layer 110a. The difference in film density between the insulating layer 110a and the insulating layer 110b can be seen, for example, in a TEM image. It can be evaluated by the density (brightness).

[0159] When the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 112 and The thickness of the insulating layer 110b in the non-overlapping region may be reduced. Preferably, the insulating layer 110b remains in the area where it does not overlap with the conductive layer 112. By configuring the insulating layer 110b to remain in the region that does not overlap with the insulating layer 110b, the insulating layer 110 can be prevented from being adsorbed.

[0160] The insulating layer 110b in the area overlapping the conductive layer 112 is an insulating layer in the area not overlapping the conductive layer 112. It is preferable to form the layer 110b to a thickness that allows the layer 110b to remain. The thickness of the layer 110b is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 10 nm or more and 50 nm or less. Preferably, the thickness is 3 nm or more and 30 nm or less.

[0161] In FIG. 6(E), the insulating layer 110 is made up of an insulating layer 110a and an insulating layer 110b on the insulating layer 110a. 10b, and an insulating layer 110c between insulating layers 110a and 110b. The insulating layers 110a, 110b, and 110c are made of the same insulating material. Since an insulating film can be used, the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be Therefore, in this embodiment, The interfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are shown by dashed lines. do.

[0162] The insulating layer 110c is formed at a faster rate than the insulating layers 110a and 110b. By using the insulating layer 110c having a high deposition rate, the laminated structure The insulating layer 110 having this structure can be formed with high productivity.

[0163] For example, when a film containing silicon is used as the insulating layer 110, the insulating layer 110a and the insulating layer 110b are Compared with the insulating layer 110b, the insulating layer 110c has a higher silicon content than the deposition gas used during deposition. The insulating layer 110c can be formed under conditions where the ratio of the contained gas is high. By increasing the temperature, the insulating layer 110c can be made to have a low impurity content. By increasing the pressure during film formation, an insulating layer with fewer impurities can be obtained.

[0164] The insulating layer 110c has an etching rate in one etchant that is higher than that of the insulating layer 110a and the insulating layer 110b. It is preferable that the insulating layer 110a is faster than the insulating layer 110b. As a result, the film density of the insulating layer 110c may be low. The difference in film density between the insulating layer 110c and the insulating layer 110b can be evaluated, for example, by the density (brightness) of a TEM image. Furthermore, compared with the insulating layer 110a and the insulating layer 110b, the insulating layer 110c has a higher hydrogen concentration in the film. The hydrogen concentrations of the insulating layers 110a, 110b, and 110c may become high. The difference can be evaluated, for example, by secondary ion mass spectrometry.

[0165] When the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 112 and The thickness of the insulating layer 110b in the non-overlapping region may be reduced. Preferably, the insulating layer 110b remains in the area where it does not overlap with the conductive layer 112. By configuring the insulating layer 110b to remain in the region that does not overlap with the insulating layer 110b, the insulating layer 110 can be prevented from being adsorbed.

[0166] As shown in FIGS. 7A, 7B, and 7C, the end of the conductive layer 112 is functional. The electrode 112 may be located inside the ends of the active layer 113 and the metal oxide layer 114. 7(B) is a top view of the transistor 100E, and FIG. 7(C) is a diagram showing the channel length of the transistor 100E. 7(C) is a cross-sectional view of the transistor 100E in the channel width direction. do.

[0167] The transistor 100E includes an end portion of the conductive layer 112, the functional layer 113, and the metal oxide layer 114. The point where the end of the conductive layer 112 is located inside the end of the insulating layer 110 and the point where the end of the conductive layer 112 is located inside the end of the functional layer 113 The main difference from Configuration Example 1 is that the metal oxide layer 114 is located inside the edge of the metal oxide layer 114. In other words, the insulating layer 110 is formed on at least the semiconductor layer 108 so as to separate from the conductive layer 112. , and has a portion that protrudes outward beyond the ends of the functional layer 113 and the metal oxide layer 114. The functional layer 113 and the metal oxide layer 114 are conductive at least on the insulating layer 110. The functional layer 113 and the metal oxide layer 112 have a portion protruding outward from the end of the functional layer 113. The layers 114 have top surface shapes that generally match each other.

[0168] The conductive layer 112 has an etching rate of 1000 .mu.m or less in an etchant used for processing the conductive layer 112. By using a material that is faster than the metal oxide layer 114 and the functional layer 113, the conductive layer 112 The end portion is positioned inside the ends of the functional layer 113 and the metal oxide layer 114. can be done.

[0169] The insulating layer 116 is formed on the upper and side surfaces of the conductive layer 112, the upper and side surfaces of the functional layer 113, and the metal oxide The side surface of the oxide layer 114, the top surface and side surface of the insulating layer 110, the top surface and side surface of the semiconductor layer 108, The insulating layer 118 is provided to cover the upper surface of the insulating layer 116 and the upper surface of the insulating layer 103. It is set up as follows.

[0170] When the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 112 and The non-overlapping part of the insulating layer 110 may be etched, resulting in a thinner insulating layer 110. An enlarged view of the area enclosed by the dashed line in FIG. 7(B) is shown in FIG. 8(A). 1, the thickness of the insulating layer 110 in the area overlapping the conductive layer 112 is In other words, the thickness of the insulating layer 110 in the region not overlapping with the channel 2 may be thin. The thickness of the insulating layer 110 in the region overlapping the channel formation region is compared with the thickness of the insulating layer 110 in the region not overlapping the channel formation region. In some cases, the thickness of the insulating layer 110 in the thin area may be thin.

[0171] Although the insulating layer 110 is shown as a single layer structure in FIGS. 7B, 7C, and 8A, it may be a two-layer structure. 8B, the insulating layer 110 is a layer including an insulating layer 110a and an insulating layer 110b. 8(C) shows an example of a two-layer structure with an insulating layer 110b on a layer 110a. The edge layer 110 is made up of an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110b on the insulating layer 110a. 10B shows an example of a three-layer structure with an insulating layer 110c between insulating layers 110a and 110b.

[0172] When the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 112 and The thickness of the insulating layer 110b in the non-overlapping region may be thin. As shown in FIG. 8(C), the insulating layer 110b remains in the area where it does not overlap with the conductive layer 112. It is preferable that the insulating layer 110b remains in the region where it does not overlap with the conductive layer 112. Therefore, the adsorption of water onto the insulating layer 110 can be suppressed.

[0173] Furthermore, the above-mentioned transistor 100, transistor 100A, transistor 100B, and In the transistor 100C, the insulating layer 110 preferably has a stacked structure. The layer 110 has a two-layer structure consisting of an insulating layer 110a and an insulating layer 110b on the insulating layer 110a. As a result, it is possible to prevent water from being adsorbed onto the surface of the insulating layer 110, and good electrical properties and reliability can be obtained. Furthermore, the insulating layer 110 is divided into an insulating layer 110a and an insulating layer 110b on the insulating layer 110a. and an insulating layer 110c between the insulating layers 110a and 110b, The insulating layer 110 having a laminated structure can be formed with high productivity.

[0174] This concludes the description of configuration example 5.

[0175] <Production method example 1> A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100A illustrated in the above configuration example will be taken as an example for explanation.

[0176] The thin films (insulating films, semiconductor films, conductive films, etc.) that constitute the semiconductor device are formed by sputtering. Chemical Vapor Deposition (CVD) method , vacuum evaporation, pulsed laser deposition (PLD) tion) method, Atomic Layer Deposition (ALD) method ) method, etc. As a CVD method, plasma enhanced chemical vapor deposition (PECVD) There are laser enhanced CVD (laser enhanced CVD) and thermal CVD methods. One of the methods is metal organic chemical vapor deposition (MOCVD). D) There is a law.

[0177] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are formed by spin coating, Dip, spray application, inkjet, dispensing, screen printing, offset Printing methods, doctor knife, slit coat, roll coat, curtain coat, It can be formed using tools (equipment) such as a fukot.

[0178] Furthermore, when processing the thin films that make up the semiconductor device, photolithography and other methods are used. Other methods include nanoimprinting, sandblasting, and lift-off. It is also possible to process a thin film by a film formation method using a shielding mask such as a metal mask. Alternatively, island-shaped thin films may be formed directly.

[0179] There are two typical photolithography methods: A resist mask is formed on the thin film to be processed by etching or the like. The other method is to remove the photomask after forming a photosensitive thin film. Then, the thin film is processed into a desired shape by performing development.

[0180] In photolithography, the light used for exposure is, for example, i-line (wavelength 365 nm), It uses g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can be used. The exposure may also be performed by immersion exposure. Using extreme ultraviolet (EUV) light and X-rays, Also, electron beams can be used instead of light for exposure. The use of light, X-rays or electron beams is preferred because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask It is unnecessary.

[0181] There are three methods for etching thin films: dry etching, wet etching, and sandblasting. Methods such as these can be used.

[0182] 9 to 11 show cross sections of the transistor 100A at various stages in the manufacturing process. In each figure, the channel length direction is on the left side of the central dashed line, and the channel width direction is on the right side. The cross sections are shown side by side.

[0183] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a first gate electrode. A conductive layer 106 is formed to function as a conductive layer.

[0184] [Formation of insulating layer 103] Next, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (FIG. 9(A)). The insulating layer 103 can be formed by using a PECVD method, an ALD method, a sputtering method, or the like.

[0185] When the insulating layer 103 has a laminated structure, the insulating films that become the insulating layer 103 are formed in order. The insulating layer 103 may have a laminated structure of, for example, a nitride film and an oxide film on the nitride film. In this case, the nitride film and the oxide film are formed in this order.

[0186] The insulating layer 103 may have a stacked structure of two or more nitride films. 3, for example, a first silicon nitride film and a second silicon nitride film on the first silicon nitride film. a silicon nitride film, a third silicon nitride film on the second silicon nitride film, and a third silicon nitride film on the third silicon nitride film When a stacked structure with a silicon oxynitride film is formed, the first silicon nitride film, the second silicon nitride film, and the A silicon film, a third silicon nitride film, and a silicon oxynitride film are formed in this order.

[0187] The insulating layer 103 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. In the case of a stacked structure of a silicon nitride film and a silicon oxynitride film, the first silicon nitride film blocks impurities. By providing the first silicon nitride film, it is possible to Impurities from layers below the insulating layer 103 can be prevented from diffusing into layers above the insulating layer 103. The second silicon nitride film preferably has low stress and high dielectric strength. By providing a silicon film, the insulating layer 103 has low stress and high dielectric strength. The third silicon nitride film releases less impurities containing hydrogen and can absorb hydrogen. It is preferable that the third silicon nitride film has a function of blocking impurities. By providing the silicon oxynitride layer, it is possible to suppress the diffusion of hydrogen into the channel forming region. It is preferable that the SiO2 film has a low defect density and releases little hydrogen-containing impurities.

[0188] For example, the insulating layer 103 is formed by plasma deposition using a mixed gas of silane, nitrogen, and ammonia. The first silicon nitride film, which has the function of blocking impurities, is formed by the micro-CVD method. Next, a mixed gas with a higher ammonia flow rate than the first silicon nitride film is used, and the stress is reduced. Next, a second silicon nitride film is formed, which is thin and has a high dielectric strength. A mixed gas with a lower ammonia flow rate than the membrane is used, and the release of hydrogen-containing impurities is reduced. A third silicon nitride film having a function of blocking impurities containing hydrogen is formed. Next, a mixture of silane and nitrous oxide gas was used to form a film with low defect density and hydrogen. The insulating layer 103 can be formed by depositing a silicon oxynitride film that emits less impurities. By switching the film formation conditions in the same chamber, the first silicon nitride film and the second silicon nitride film can be formed. A silicon film, a third silicon nitride film, and a silicon oxynitride film are successively formed in a vacuum. This allows the insulating layer 103 to be formed with high productivity.

[0189] Alternatively, after forming the third silicon nitride film, a plasma treatment is performed in an atmosphere containing oxygen. By oxidizing the surface of the third silicon nitride film, a silicon oxynitride film is formed on the third silicon nitride film. A silicon film can be formed.

[0190] Compared with the first silicon nitride film and the third silicon nitride film, the second silicon nitride film The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film may have a low film density. The difference in film density of the silicon nitride film can be evaluated, for example, by the density (brightness) of the TEM image. Compared with the first silicon nitride film and the third silicon nitride film, the second silicon nitride film The hydrogen concentration in the film may become high. The difference in hydrogen concentration between the first and third silicon nitride films can be evaluated by, for example, secondary ion mass spectrometry. do.

[0191] After the insulating layer 103 is formed, a process of supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be introduced into the insulating layer 103 by plasma ion doping or ion implantation. Note that heat treatment does not necessarily have to be performed after the insulating layer 103 is formed.

[0192] [Formation of Semiconductor Layer 108] Next, a metal oxide film is formed on the insulating layer 103 and processed to form island-shaped semiconductor layers. The conductor layer 108 is formed (FIG. 9(B)).

[0193] The metal oxide film is formed by a sputtering method using a metal oxide target. is preferred.

[0194] In addition, when forming a metal oxide film, oxygen gas and an inert gas (e.g., helium gas) are used. Gases such as argon gas and xenon gas may be mixed. The higher the ratio of oxygen gas to the total deposition gas (hereinafter referred to as the oxygen flow ratio), This makes it possible to improve the crystallinity of the metal oxide film, thereby realizing a highly reliable transistor. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and the higher the on-current. It may be a transistor.

[0195] When the semiconductor layer 108 has a laminated structure, the same sputtering target is used to form the same composition. By continuously forming the films in the film chamber, it is possible to obtain a good interface, which is preferable. The deposition conditions for each metal oxide film were varied under different conditions such as pressure, temperature, and power during deposition. However, by keeping the conditions other than the oxygen flow rate the same, the time required for the film formation process can be shortened. In addition, when metal oxide films of different compositions are laminated, it is preferable to expose the film to the atmosphere. It is preferable to form the films continuously without any additional steps.

[0196] The metal oxide film is classified into two types: a metal oxide film with a CAAC structure and a metal oxide film with an nc structure. The film formation conditions are set so that the metal oxide film has a mixture of the CAAC structure and the nc structure. It is preferable to set the film forming conditions under which the metal oxide film to be formed has a CAAC structure. The deposition conditions for the nc structure depend on the composition of the sputtering target used. Therefore, depending on the composition, the substrate temperature, oxygen flow rate, pressure, power, etc. must be adjusted appropriately. Just set it.

[0197] The metal oxide film is formed under the following conditions: the substrate temperature is preferably from room temperature to 450° C. The substrate temperature is preferably from room temperature to 300° C., more preferably from room temperature to 200° C., and even more preferably Alternatively, the temperature may be set to a temperature above room temperature and below 140° C. For example, the substrate 102 may be a large glass substrate or a resin substrate. When using a plastic substrate, productivity increases if the substrate temperature is set to above room temperature and below 140°C. It is also preferable to form a metal oxide film at room temperature or without heating the substrate. By doing so, the crystallinity can be reduced.

[0198] In addition, before forming the metal oxide film, water, hydrogen, and organic substances adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a treatment for removing components or a treatment for supplying oxygen into the insulating layer 103. For example, heat treatment is preferably performed at a temperature of 70°C or higher and 200°C or lower in a reduced pressure atmosphere. Alternatively, plasma treatment may be performed in an atmosphere containing oxygen. When plasma treatment is performed in an atmosphere containing nitrogen oxide gas, organic substances on the surface of the insulating layer 103 are suitably removed. After such a treatment, the surface of the insulating layer 103 can be removed without being exposed to the atmosphere. It is preferable to subsequently deposit a metal oxide film.

[0199] The metal oxide film is processed by either wet etching or dry etching. In this case, the part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be used. The part may be etched and thinned.

[0200] After forming the metal oxide film or processing it into the semiconductor layer 108, the metal oxide film or the semiconductor layer Heat treatment may be performed to remove hydrogen or water from the layer 108. Typically, the temperature is 150°C or higher but lower than the strain point of the substrate, or 250°C or higher but lower than 450°C, or Alternatively, the temperature can be set to 300°C or higher and 450°C or lower. In this case, heat treatment may not be performed after processing into the semiconductor layer 108. This may be done at any stage after the oxide film is formed. This step may also be combined with the step of

[0201] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. After heating in an atmosphere containing oxygen, heating in an atmosphere containing nitrogen or an atmosphere containing oxygen may be performed. Ultra-dry air (CDA: Clean Dry Air) may be used as the atmosphere. It is preferable that the atmosphere for the heat treatment does not contain hydrogen, water, etc. By using a gas that has been highly purified to a temperature of -100°C or lower, the semiconductor layer 10 This can prevent hydrogen, water, etc. from being taken into the electrode 8 as much as possible. furnace, rapid thermal annealing (RTA) equipment, etc. By using an RTA device, the heat treatment time can be shortened.

[0202] It is preferable to form the insulating film 110f immediately after the semiconductor layer 108 is formed. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed onto the surface of the semiconductor layer 108. When water is adsorbed on the surface of the semiconductor layer 108, the water is absorbed by the semiconductor layer 108 by a subsequent heat treatment or the like. Hydrogen diffuses into 8, and V O H may be formed. V O H can be a carrier generation source Therefore, it is preferable that the amount of adsorbed water on the semiconductor layer 108 is small.

[0203] [Formation of insulating film 110f and metal oxide film 114f] Next, the insulating film 110f and the metal oxide film 110f are deposited over the insulating layer 103 and the semiconductor layer 108. Form 14f.

[0204] The insulating film 110f is a film that will later become the insulating layer 110. For example, the insulating film 110f may be For example, an oxide film such as a silicon oxide film or a silicon oxynitride film is deposited by a plasma chemical vapor deposition apparatus. It is preferable to form the film using a plasma CVD apparatus (PECVD apparatus or simply called a plasma CVD apparatus). It may also be formed by a PECVD method using microwaves.

[0205] When the insulating layer 110 has a laminated structure, the insulating films that will become the insulating layer 110 are formed in order. For example, as shown in FIGS. 6(C), 6(D), and 8(B), the insulating layer 110 In the case of a two-layer structure of the insulating layer 110a and the insulating layer 110b, the insulating layer 110a is A film and an insulating film that will become the insulating layer 110b are formed in this order.

[0206] For example, the insulating layer 110 is formed by plasma C using a mixed gas of silane and dinitrogen monoxide. An insulating film that will become the insulating layer 110a is formed by the VD method. An insulating film that will become the insulating layer 110b is formed under conditions of a lower pressure and a higher power than those of the insulating film. In addition, by changing the film formation conditions in the same chamber, the insulating layer 110 can be formed. The insulating film that will become 110a and the insulating film that will become insulating layer 110b are successively formed in a vacuum. This allows the insulating layer 110 to be formed with high productivity.

[0207] As shown in FIGS. 6(E), 6(F) and 8(C), the insulating layer 110 is In the case of a three-layer structure of insulating layer 110a, insulating layer 110c, and insulating layer 110b, The insulating film to be the insulating layer 110c, the insulating film to be the insulating layer 110b are formed in this order. Form into.

[0208] For example, the insulating layer 110 is formed by plasma C using a mixed gas of silane and dinitrogen monoxide. An insulating film that will become the insulating layer 110a is formed by the VD method. A mixed gas with a higher ratio of silane flow rate to nitrous oxide flow rate was used under high power conditions. Then, an insulating film that will become the insulating layer 110c is formed. Using a mixed gas with a low ratio of silane flow rate to dinitrogen oxide flow rate, insulating layer 1 was formed under low pressure conditions. The insulating film 10b is formed in the same chamber to form the insulating layer 110. By switching the conditions, an insulating film that becomes the insulating layer 110a and an insulating film that becomes the insulating layer 110c can be formed. The insulating film and the insulating film that will become the insulating layer 110b can be formed successively in a vacuum, resulting in high productivity. The insulating layer 110 can be formed.

[0209] After the insulating film 110f is formed, heat treatment is performed to remove impurities and insulating films in the insulating film 110f. The heat treatment may be carried out using one of nitrogen, oxygen, and rare gases. The reaction can be carried out at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing the above. After the insulating film 110f is formed, the heat treatment may not be performed. It may be carried out at any stage after the formation of 0f. It may also be used as a measure.

[0210] The metal oxide film 114f is a film that will later become the metal oxide layer 114. 4f is preferably formed by sputtering in an atmosphere containing oxygen, for example. This allows oxygen to be supplied to the insulating film 110f when the metal oxide film 114f is formed.

[0211] The metal oxide film 114f is formed by an oxide film containing the same metal oxide as that of the semiconductor layer 108. When forming the film by sputtering using a target, the above-mentioned method can be used.

[0212] The metal oxide film 114f is formed by reactive spat deposition using oxygen as a deposition gas and a metal target. When aluminum is used as the metal target, , an aluminum oxide film can be formed.

[0213] When forming the metal oxide film 114f, the total flow rate of the film forming gas introduced into the film forming chamber of the film forming apparatus is The higher the oxygen flow rate ratio to the film thickness (oxygen flow rate ratio) or the oxygen partial pressure in the film formation chamber, the greater the insulating film thickness. The oxygen supplied during the 10f can be increased. The oxygen flow rate or oxygen partial pressure can be increased, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more The oxygen flow rate ratio is preferably 100% or more, and more preferably 90% or more and 100% or less. It is preferable to set the oxygen partial pressure at 00% and make it as close to 100% as possible.

[0214] In this way, the metal oxide film 114f is formed by sputtering in an atmosphere containing oxygen. By forming the insulating film 110f, oxygen is supplied to the insulating film 110f when the metal oxide film 114f is formed. At the same time, oxygen can be prevented from being released from the insulating film 110f. A large amount of oxygen can be trapped in the film 110f. As a result, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, and the Oxygen vacancies can be reduced, and highly reliable transistors can be realized.

[0215] The metal oxide film 114f is formed under the following conditions: the substrate temperature is between room temperature and 450° C.; The substrate temperature is preferably from room temperature to 300° C., more preferably from room temperature to 200° C., and More preferably, the temperature is set to a temperature between room temperature and 140° C. For example, if the substrate 102 is a large glass substrate, When using a plate or a resin substrate, productivity is improved by setting the film formation temperature to room temperature or higher and lower than 140°C. Furthermore, when the deposition temperature of the metal oxide film 114f is high, the temperature of the metal oxide film 114 The crystallinity of the metal oxide film 114f may become high, resulting in a slow etching rate. If the film formation temperature is low, the crystallinity of the metal oxide film 114f becomes low and the etching rate becomes high. There are cases where the metal oxide film 114f is preferably treated with an etchant used for processing the metal oxide film 114f. The deposition temperature of the metal oxide film 114f may be appropriately selected so as to achieve the etching rate.

[0216] After the metal oxide film 114f is formed, a heat treatment is performed to convert the insulating film 110f into a semiconductor Oxygen may be supplied to the layer 108. The heat treatment may be performed using a gas containing at least one of nitrogen, oxygen, and a rare gas. The reaction can be carried out in an atmosphere at a temperature of 200°C to 400°C. After the formation of the film 114f, the heat treatment may not be performed. This may be done at any stage after the formation of the 14f film. This may be combined with the process.

[0217] Subsequently, the metal oxide film 114f, the insulating film 110f, and a part of the insulating layer 103 are etched. By this, an opening reaching the conductive layer 106 is formed (FIG. 9(C)). The functional layer 113 and the conductive layer 112 to be formed are electrically connected to the conductive layer 106 through the opening. can be connected to.

[0218] [Formation of functional film 113f and conductive film 112f] Next, a functional film 113f that will become the functional layer 113 and a conductive layer 11 The conductive film 112f that will become the functional film 113f is formed by depositing a metal or alloy. It is preferable to form the film by sputtering using a gold sputtering target. The conductive film 112f is formed by sputtering using a sputtering target of a metal or alloy. It is preferable to form the film by a coating method.

[0219] [Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112] Then, a resist mask 115 is formed over the conductive film 112f. In the area not covered with the metal oxide film 115, the conductive film 112f, the functional film 113f, and the metal oxide film 113f are The metal oxide film 114f is removed, and the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed. (Figure 10(B)).

[0220] The conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed by wet etching. The wet etching method can be suitably used, for example, a method using a hydrogen peroxide-containing For example, any of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid may be used. In particular, the conductive layer 112 may be made of a material containing copper. When using an etchant containing phosphoric acid, acetic acid, and nitric acid, the etchant can be suitably used. do.

[0221] In one embodiment of the present invention, the etching rates of the metal oxide layer 114 and the functional layer 113 are Since the structure is similar to or slower than the conductive layer 112, the functional layer can be formed in the same process. 113, a metal oxide layer 114, and a conductive layer 112 can be formed. 4. The top surface shapes of the functional layer 113 and the conductive layer 112 can be made to roughly match each other. In addition, since they can be formed in the same process, the process can be simplified and productivity can be improved. can be.

[0222] When the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 112 functions as a In other words, the edge of the conductive layer 112 may be recessed from the conductive layer 113 and the metal oxide layer 114. The conductive layer 112 is located inside the end of the metal oxide layer 114. 3 and the metal oxide layer 114 and the functional layer 1 in the region overlapping with the conductive layer 112. In some cases, the thickness of the functional layer 113 in the region that does not overlap with the conductive layer 112 may be thinner than the thickness of the functional layer 113 in the region that does not overlap with the conductive layer 112. (See Figures 3(A), 3(B) and 3(C)).

[0223] In addition, when the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed, the conductive layer 11 2 and the functional layer 113 may be recessed from the metal oxide layer 114. The ends of the conductive layer 2 and the functional layer 113 are located inside the ends of the metal oxide layer 114. The conductive layer 112 and the functional layer 113 are recessed from the metal oxide layer 114, and the conductive layer 112 The thickness of the metal oxide layer 114 in the area overlapping the functional layer 113 is The thickness of the metal oxide layer 114 in the non-contact area may be reduced (see FIGS. 4(A), 4(B), and 4(C)). See Figure 4(C)).

[0224] The conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed using different etching methods. The etching may be carried out in at least two separate steps using the same etching conditions or techniques. The conductive film 112f is etched first, and then the functional film 113f and The metal oxide film 114f may be etched.

[0225] Next, the insulating film 110f is removed from the area not covered by the resist mask 115. The insulating layer 110 is then formed (FIG. 11(A)). Either or both of a coating method and a dry etching method can be used. The insulating layer 110 may be formed with the resist mask 115 removed. By leaving the mask 115, it is possible to prevent the thickness of the conductive layer 112 from becoming thin.

[0226] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0227] [Formation of insulating layer 116 and region 108N (hydrogen supply process)] Next, a process of supplying hydrogen to the exposed region of the semiconductor layer 108 is performed. The insulating layer 116 containing hydrogen is formed in contact with the exposed region of the semiconductor layer 108. (Figure 11(B)).

[0228] The insulating layer 116 can be formed by a plasma CVD method using a deposition gas containing hydrogen. For example, silicon nitride is formed using a deposition gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen is contained in the film. In addition, even during film formation, the exposed portion of the semiconductor layer 108 may contain It becomes possible to supply hydrogen.

[0229] After the insulating layer 116 is formed, heat treatment is performed to release hydrogen from the insulating layer 116. It is preferable that a part of the nitrogen, oxygen, In an atmosphere containing one or more of the rare gases, the temperature is 150°C or higher and 450°C or lower, preferably 200 It is preferable to carry out the treatment at a temperature of 0.degree. C. or higher and 400.degree. C. or lower.

[0230] By supplying hydrogen in this manner, an extremely low resistance region 108N is formed in the semiconductor layer 108. It can be formed.

[0231] Furthermore, oxygen is introduced from the insulating layer 110 to the channel formation region of the semiconductor layer 108 by the heat treatment. can be supplied.

[0232] [Formation of insulating layer 118] Subsequently, an insulating layer 118 is formed on the insulating layer 116 (FIG. 12(A)).

[0233] When the insulating layer 118 is formed by the plasma CVD method, if the film formation temperature is too high, the region 1 Depending on the impurity contained in the O8N, etc., the impurity may be present in the channel forming region of the semiconductor layer 108. As a result, the resistance of the channel formation region decreases. The resistance of the insulating layer 116 or the insulating layer 108N may increase. The film formation temperature of 118 is, for example, 150° C. or higher and 400° C. or lower, preferably 180° C. or higher. The temperature is preferably 360°C or lower, more preferably 200°C or higher and 250°C or lower. By forming 118 at low temperature, even transistors with short channel lengths can be fabricated with good Electrical properties can be imparted.

[0234] After the insulating layer 118 is formed, heat treatment may be performed.

[0235] [Formation of Openings 141a and 141b] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 118 and a portion of the insulating layer 116 are etched to form an opening 118 reaching the region 108N. 41a and an opening 141b are formed.

[0236] [Formation of Conductive Layer 120a and Conductive Layer 120b] Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. The conductive film is formed and processed into a desired shape to form the conductive layer 120a and the conductive layer 120b. (Figure 12(B)).

[0237] Through the above steps, the transistor 100A can be manufactured.

[0238] <Production method example 2> A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100D illustrated in the above configuration example will be described as an example. Explanation of the parts that overlap with the above will be omitted, and only the parts that differ will be explained.

[0239] 13A and 13B show the steps of manufacturing the transistor 100D. In each figure, the channel length direction is on the left side of the central dashed line, and the channel length direction is on the right side. The cross sections in the width direction of the panel are shown side by side.

[0240] The manufacturing method is the same as that shown in <Manufacturing Method Example 1> up to the formation of the conductive film 112f. Therefore, the manufacturing method of the transistor shown in FIGS. 9A to 9C and FIG. You can take this into consideration.

[0241] [Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112] Subsequently, the conductive film 112f, the functional film 113f, and the metal oxide film 114f are etched. A conductive layer 112, a functional layer 113, and a metal oxide layer 114 are formed (FIG. 13(A)).

[0242] At this time, the ends of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed by the resist matrix. The conductive layer 112, the functional layer 113, and the The metal oxide layer 114 is preferably formed by wet etching. By adjusting the application time, the width of the region 108L can be controlled.

[0243] In addition, the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed by anisotropic etching. The conductive film 112f, the functional film 113f, and the metal oxide film 114f are etched using a etching method. After that, the conductive film 112f, the functional film 113f, and the metal oxide film 112f are removed by isotropic etching. The side surfaces of the oxide film 114f may be etched to recess the end surfaces (side etching). As a result, the end portion is positioned inside the end portion of the insulating layer 110 in plan view. A conductive layer 112, a functional layer 113, and a metal oxide layer 114 can be formed.

[0244] Next, the insulating film 110f is removed from the area not covered by the resist mask 115. Then, the insulating layer 110 is formed (FIG. 13(B)). The insulating layer 110 is formed by wet etching. Either or both of a chipping method and a dry etching method can be used.

[0245] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0246] The following steps can be carried out in accordance with the above description.

[0247] Through the above steps, the transistor 100D can be manufactured.

[0248] <Production method example 3> A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the transistor 100E illustrated in the above configuration example will be described as an example. Explanation of the parts that overlap with the above will be omitted, and only the parts that differ will be explained.

[0249] 14A and 14B show the steps of manufacturing the transistor 100E. In each figure, the channel length direction is on the left side of the central dashed line, and the channel length direction is on the right side. The cross sections in the width direction of the panel are shown side by side.

[0250] The manufacturing method is the same as that shown in <Manufacturing Method Example 1> up to the formation of the conductive film 112f. Therefore, the manufacturing method of the transistor shown in FIGS. 9A to 9C and FIG. You can take this into consideration.

[0251] [Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112] Subsequently, the conductive film 112f, the functional film 113f, and the metal oxide film 114f are etched. A conductive layer 112, a functional layer 113, and a metal oxide layer 114 are formed (FIG. 14(A)).

[0252] At this time, the ends of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed by the resist matrix. The conductive layer 112 is processed so as to be positioned inside the contour of the mask 115. By using a material that has a slower etching rate than the metal oxide layer 114 and the conductive layer 113, The edge of the layer 112 is located inside the edges of the functional layer 113 and the metal oxide layer 114 . The conductive layer 112, the functional layer 113, and the metal oxide layer 114 are formed by a wet etching method. The width of the region 108L can be controlled by adjusting the etching time. can.

[0253] Next, the insulating film 110f is removed from the area not covered by the resist mask 115. The insulating layer 110 is then formed (FIG. 14(B)). Either or both of a chipping method and a dry etching method can be used.

[0254] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0255] The following steps can be carried out in accordance with the above description.

[0256] Through the above steps, the transistor 100E can be manufactured.

[0257] <Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0258] 〔substrate〕 There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, single crystals made of silicon or silicon carbide are required. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates The substrate 102 may be a plate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a substrate having a semiconductor element formed thereon may be referred to as the substrate 102. It may be used.

[0259] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer may be removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 10 can be separated and transferred to another substrate. 0 etc. can be transferred to substrates with poor heat resistance or flexible substrates.

[0260] [Insulating layer 103] The insulating layer 103 can be formed by a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (PLD) method, or the like. The insulating layer 103 can be formed by, for example, an oxide insulating film or a Alternatively, a nitride insulating film can be formed as a single layer or a laminated layer. In order to improve the conductivity, at least the region of the insulating layer 103 that is in contact with the semiconductor layer 108 is made of oxide. The insulating layer 103 is preferably formed of an insulating film. It is preferred to use a membrane.

[0261] The insulating layer 103 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The above may be used, and the layer may be formed as a single layer or a laminate.

[0262] In addition, the insulating layer 103 may have a film other than an oxide film such as a silicon nitride film on the side in contact with the semiconductor layer 108. When the film is used, the surface in contact with the semiconductor layer 108 is pretreated with oxygen plasma or the like. and oxidizing the surface or the vicinity of the surface.

[0263] [Conductive film] The conductive layer 106 and the conductive layer 112 function as a gate electrode, a source electrode, or a drain electrode. The conductive layer 120a functions as one of the electrodes, and the conductive layer 120b functions as the other of the source electrode and the drain electrode. Functional conductive layers 120b include chromium, copper, aluminum, gold, silver, zinc, molybdenum, and the like. selected from the group consisting of tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt Metal elements, alloys containing the above-mentioned metal elements, or combinations of the above-mentioned metal elements Each of them can be formed using an alloy or the like.

[0264] In addition, the conductive layer 106, the conductive layer 112, the conductive layer 120a, and the conductive layer 120b contain In. -Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti -Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. An oxide conductor or a metal oxide film can also be applied.

[0265] Here, we will explain about oxide conductors (OC). For example, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancies. As a result, a donor level is formed near the conduction band. As a result, the metal oxide has high conductivity. The metal oxide that has become a conductor can be called an oxide conductor.

[0266] The conductive layer 106 and the like may be formed of a conductive film containing the oxide conductor (metal oxide) and a metal Alternatively, a laminated structure of a conductive film containing a metal or an alloy may be used. In this case, the insulating layer that functions as a gate insulating film is It is preferable to apply a conductive film containing an oxide conductor to the side in contact with the edge layer.

[0267] The conductive layers 106, 112, 120a, and 120b are made of the above-mentioned gold. Among the group elements, titanium, tungsten, tantalum, and molybdenum are particularly preferred. It is particularly preferable to use a tantalum nitride film. The tantalum nitride film has electrical conductivity and has the following properties with respect to copper, oxygen, or hydrogen: Since the barrier layer 104 has a high barrier property and releases little hydrogen from itself, it is preferable that the barrier layer 104 is in contact with the semiconductor layer 108. It can be suitably used as a conductive film or a conductive film in the vicinity of the semiconductor layer 108 .

[0268] [Insulating layer 110] The insulating layer 110, which functions as a gate insulating film for the transistor 100, etc., is formed by PECVD. The insulating layer 110 can be formed by a sputtering method or the like. silicon nitride film, silicon oxide nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film um film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, One or more of magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating layer 110 may have a two-layer laminate structure or a three-layer or more laminate structure. The above laminated structure may also be used.

[0269] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film. It is more preferable to have a region containing oxygen in excess of the stoichiometric composition. The insulating layer 110 is an insulating film capable of releasing oxygen. For example, The insulating layer 110 is formed by the above method, and the insulating layer 110 after the film formation is subjected to a heat treatment in an oxygen atmosphere. Alternatively, an oxide film may be formed on the insulating layer 110 in an oxygen atmosphere. Oxygen can also be supplied into the insulating layer 110 by, for example, forming a film.

[0270] In addition, the insulating layer 110 is made of a material having a higher dielectric constant than silicon oxide or silicon oxynitride. Materials such as hafnium oxide can also be used. This allows the thickness of the insulating layer 110 to be increased. It is possible to suppress leakage current due to tunnel current. In particular, hafnium oxide, which has crystallinity, It is preferable because it has a higher relative dielectric constant than crystalline hafnium oxide.

[0271] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, in order to form an In-M-Zn oxide film, The sputtering target used in this method has an atomic ratio of In to element M of 1 or more. The atomic ratio of the metal elements in such a sputtering target is preferably In :M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1: 3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4: 2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Z Examples include n=5:1:8, In:M:Zn=6:1:6, and In:M:Zn=5:2:5. can be.

[0272] In addition, a target containing a polycrystalline oxide is used as the sputtering target. This is preferable because the semiconductor layer 108 can be easily formed with crystallinity. The atomic ratio of the semiconductor layer 108 is determined by the atomic ratio of the metal elements contained in the sputtering target. The ratio of the number of atoms may vary by ±40%. When the composition of the ring target is In:Ga:Zn=4:2:4.1 [atomic ratio], film formation The composition of the semiconductor layer 108 is approximately In:Ga:Zn=4:2:3 [atomic ratio]. This may be the case.

[0273] When the atomic ratio is described as In:Ga:Zn=4:2:3 or in the vicinity, it means In When Ga is 4, this includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when describing that the atomic ratio is In:Ga:Zn=5:1:6 or in the vicinity, When n is 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is greater than or equal to 5 and less than or equal to 7. It also includes cases where the atomic ratio is In:Ga:Zn=1:1:1 or in the vicinity. When mounting, when In is 1, Ga is greater than 0.1 and not more than 2, and Zn is 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0274] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this way, by using metal oxides with a wider energy gap than silicon, As a result, the off-state current of the transistor can be reduced.

[0275] The semiconductor layer 108 preferably has a non-single-crystal structure. This includes the CAAC structure, polycrystalline structure, microcrystalline structure, and amorphous structure, which will be described later. In the structure, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density. low.

[0276] Below, we explain about CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0277] The CAAC structure has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, etc., and each nanocrystal has a c-axis oriented in a specific direction and a-axis and The b-axis and b-axis do not have any orientation, and the nanocrystals are continuously connected without forming grain boundaries. In particular, thin films with a CAAC structure have the following characteristics: The c-axis of the thin film is oriented in the thickness direction, the normal direction to the surface on which it is formed, or the normal direction to the surface of the thin film. It has the characteristic of being easy to use.

[0278] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, CAAC-OS has no clear grain boundaries, It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur. Crystallinity can be reduced by the inclusion of impurities or the generation of defects. It can be said that CAAC- is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Oxide semiconductors containing an OS have stable physical properties. Oxide semiconductors are heat resistant and highly reliable.

[0279] In crystallography, the three axes that make up the unit cell, the a-axis, the b-axis, and the c-axis (crystal It is common to take a unit cell with a specific axis as the c-axis for the layer structure. In a crystal with this structure, the two axes parallel to the plane direction of the layers are the a-axis and the b-axis, and the axis intersecting the layers is the The c-axis is generally defined as the plane of the crystal. Graphite is classified as a hexagonal crystal, and the a-axis and b-axis of the unit cell are parallel to the cleavage plane. The c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure The crystal of InGaZnO4 can be classified as a hexagonal system, and the a-axis and The a and b axes are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0280] An oxide semiconductor film with a microcrystalline structure (microcrystalline oxide semiconductor film) is observed by TEM. In some cases, it may not be possible to clearly identify the crystal parts in the microcrystalline oxide semiconductor film. The crystal part to be formed has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often An oxide semiconductor film having nanocrystals (nc) is called nc-OS. (nanocrystalline oxide semiconductor) film In addition, the grain boundaries of the nc-OS film can be clearly seen in the TEM image. It may not be possible.

[0281] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analytical method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the device, the crystal plane is analyzed using the out-of-plane method. In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that of the crystalline part. Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam (for example, 50 nm or larger) When the diffraction pattern is changed to nc-OS film, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less). When electron beam diffraction (also called nanobeam electron diffraction) is performed using the electron beam (bottom), a circle is drawn. A bright area (ring-shaped) is observed, and multiple spots are observed within that area. This may be the case.

[0282] The nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the S film, there is no regularity in the crystal orientation between different crystal parts. Therefore, the nc-OS film The defect density of the nc-OS film is higher than that of the CAAC-OS film. Compared to the OS film, the carrier density is higher and the electron mobility may be higher. A transistor including an -OS film can exhibit high field-effect mobility.

[0283] The nc-OS film can be formed with a smaller oxygen flow rate than the CAAC-OS film. In addition, the nc-OS film can be formed at a lower substrate temperature during film formation than the CAAC-OS film. For example, the nc-OS film can be formed by lowering the substrate temperature (e.g. The film can be formed even when the substrate is heated (for example, at a temperature of 130°C or less) or without heating. It is suitable for use with large glass substrates or resin substrates, and can increase productivity. do.

[0284] An example of the crystal structure of a metal oxide will be described below. Sputtering was performed using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]). The following will be explained as an example of a metal oxide film formed by the ring method. Metal oxide formed by sputtering at a plate temperature of 100°C to 130°C is either the nc (nano crystal) structure or the CAAC structure. On the other hand, if the substrate temperature is set to room temperature (RT), Metal oxides formed by sputtering tend to have an nc crystal structure. The term room temperature (RT) as used herein includes the temperature at which the substrate is not heated.

[0285] <Metal oxide composition> Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0286] In this specification, CAAC (c-axis aligned crystal) l), and when written as CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. Represents an example.

[0287] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. The function of activating the CAC-OS or CAC-metal oxide can be added. In CAC-OS or CAC-metal oxide, each function is separated. By combining these, the functions of both can be maximized.

[0288] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0289] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0290] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0291] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0292] This concludes the description of the components.

[0293] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0294] (Embodiment 2) In this embodiment, an example of a display device including the transistor described in the above embodiment will be described. We will explain about this.

[0295] <Configuration example> 15A shows a top view of a display device 700. The display device 700 is made of a sealing material 712. The first substrate 701 and the second substrate 705 are bonded together. 1, the second substrate 705, and the area sealed by the sealant 712, the first substrate 70 1, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided. The pixel portion 702 is provided with a plurality of display elements.

[0296] In addition, an FPC 716 (FP C: Flexible printed circuit) is connected to the FPC terminal 7 The FPC terminal portion 708 and the signal line 710 are connected by the FPC 716. 7, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706. Various signals are supplied to each of these.

[0297] A plurality of gate driver circuit sections 706 may be provided. The path section 706 and the source driver circuit section 704 are separately formed on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is mounted on the first substrate 70. It can be mounted on a 1 or FPC716.

[0298] The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 have The transistor which is a semiconductor device of one embodiment of the present invention can be used as the transistor.

[0299] Examples of display elements provided in the pixel portion 702 include a liquid crystal element and a light-emitting element. The liquid crystal elements used include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. In addition, LEDs (Light Emitting Diodes) can be used as light emitting elements. Diode), OLED (Organic LED), QLED (Quantum-do Examples of self-luminous light-emitting elements include LEDs, semiconductor lasers, etc. MEMS (Micro Electro Mechanical Systems) using optical interference or optical interferometry l Systems) elements, microcapsule type, electrophoresis type, electrowet Display elements that use the LCD technology or the electronic liquid powder technology (registered trademark) can be used. It can also be done as follows.

[0300] The display device 700A shown in FIG. 15B has a flexible substrate instead of the first substrate 701. A display device to which a resin layer 743 is applied and which can be used as a flexible display This is an example.

[0301] In the display device 700A, the pixel section 702 is not rectangular, but has arc-shaped corners. As shown in the region P1 in FIG. 15(B), the pixel section 702 and the resin layer 743 The pair of gate driver circuit sections 706 are connected to the pixel section 7 The gate driver circuit section 706 is provided on both sides of the pixel section 702. The portion is provided along an arc-shaped contour.

[0302] The resin layer 743 has a protruding shape at the portion where the FPC terminal portion 708 is provided. In addition, a part of the resin layer 743 including the FPC terminal portion 708 is on the back side in the region P2 in FIG. By folding back a part of the resin layer 743, the FPC 716 can be attached to the pixel area. The display device 700A can be mounted on the back side of the display device 702 so that the display device 700A can be mounted on the electronic device. This allows for space saving for electronic devices.

[0303] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as, for example, a source driver circuit. The source driver circuit section 704 in FIG. 00A includes a protection circuit, a buffer circuit, a demultiplexer, The configuration may include at least one of a crossover circuit, a crossover circuit, and the like.

[0304] The display device 700B shown in FIG. 15(C) is suitable for use in electronic devices having large screens. The display device 700B is a display device that can display, for example, a television device, a monitor device, or the like. devices, personal computers (including laptops and desktops), and tablet devices , and can be suitably used for digital signage, etc.

[0305] The display device 700B includes a plurality of source driver ICs 721 and a pair of gate driver circuits. It has a section 722.

[0306] The plurality of source driver ICs 721 are attached to respective FPCs 723. In addition, the plurality of FPCs 723 have terminals on one side connected to the first substrate 701 and terminals on the other side connected to the printed circuit board. The FPC 723 is bent to connect the printed circuit board 7 24 can be disposed on the back side of the pixel section 702 and mounted on the electronic device, thereby reducing the space required for the electronic device. It is possible to pace things up.

[0307] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with narrow frames.

[0308] By adopting such a configuration, a large-sized and high-resolution display device can be realized. The surface size is 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. In addition, it is possible to realize display devices with extremely high resolutions such as 4K2K or 8K4K. This makes it possible to realize a high-resolution display device.

[0309] <Example of cross-sectional configuration> Below, we will discuss configurations using liquid crystal elements and EL elements as display elements. 16 to 19. Note that FIGS. 16 to 18 are the same as those in FIG. 15(A) 15(B) is a cross-sectional view taken along the dashed line QR shown in FIG. 16 and 17 are cross-sectional views of the display device 700A taken along the dashed line ST. 18 and 19 show a configuration using a liquid crystal element as a display element, and FIG. 19 shows a configuration using an EL element. do.

[0310] [Explanation of common parts of the display device] The display device shown in FIGS. 16 to 19 includes a wiring portion 711, a pixel portion 702, and a The wiring section 711 has a driver circuit section 704 and an FPC terminal section 708. , and a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit section 704 includes a transistor 752. In FIG. The case without element 790 is shown.

[0311] The transistor 750 and the transistor 752 are the same as those described in Embodiment 1. can be applied.

[0312] The transistor used in this embodiment is made of a highly purified oxide in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. The off-state current of the transistor can be reduced. The holding time of the image signal can be extended, and the interval between writing of the image signal etc. can also be set to be longer. Since the frequency of refresh operations can be reduced, power consumption can be reduced.

[0313] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using this in a device, the switching transistor in the pixel section and the driver used in the drive circuit section can be In other words, the transistors can be formed on the same substrate as the silicon wafer. It is also possible to configure the display device without using a driving circuit, thereby reducing the number of components in the display device. Even in the elemental section, high-quality images can be provided by using transistors that can be driven at high speed. Cut.

[0314] The capacitor 790 shown in FIGS. 16, 18, and 19 is a capacitor having a first capacitance and a second capacitance. The lower electrode is formed by processing the same film as the gate electrode in 1, and the same metal oxide as the semiconductor layer. and an upper electrode formed by processing a material. The resistance between the lower electrode and the upper electrode is low, similar to the source region and the drain region. A part of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided in the That is, the capacitor 790 has an insulating film sandwiched between a pair of electrodes, which functions as a dielectric film. The upper electrode is a stacked structure in which the source electrode and drain electrode of the transistor are formed. The electrodes are connected to wiring obtained by processing the same film as the electrodes.

[0315] In addition, a planarization insulating film is formed on the transistor 750, the transistor 752, and the capacitor 790. A veneer 770 is provided.

[0316] The transistor 750 included in the pixel portion 702 and the transistor 750 included in the source driver circuit portion 704 are A transistor having a different structure from the transistor 752 may be used. A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. The gate driver circuit section 706 may also be configured to use a source driver. This is the same as the driver circuit section 704.

[0317] The signal line 710 is the same as the source and drain electrodes of the transistors 750 and 752. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it reduces signal delays caused by line resistance and enables display on a large screen.

[0318] The FPC terminal portion 708 includes wiring 760, a part of which functions as a connection electrode, an anisotropic conductive film 78, and a The wiring 760 is connected to the FPC 71 through an anisotropic conductive film 780. 6. Here, the wiring 760 is electrically connected to the terminals of the transistors 750 and 6. The source electrode and drain electrode 752 are formed from the same conductive film.

[0319] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate or a plastic substrate. A flexible substrate such as a plastic substrate can be used. When a substrate that can be used is used, water or a water-soluble substance is provided between the first substrate 701 and the transistor 750 or the like. It is preferable to provide an insulating layer having barrier properties against elements.

[0320] On the second substrate 705 side, there are a light-shielding film 738, a colored film 736, and an insulating film in contact with these. A velum 734 is provided.

[0321] [Configuration example of a display device using a liquid crystal element] The display device 700 shown in FIG. 16 includes a liquid crystal element 775 and a spacer 778. The element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The electrode layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to a source electrode or a drain electrode of the transistor 750. The conductive layer 772 is formed over the planarization insulating film 770 and functions as a pixel electrode. do.

[0322] The conductive layer 772 can be formed using a material that transmits or reflects visible light. The transparent material may be, for example, an oxide material containing indium, zinc, tin, or the like. As the reflective material, for example, a material containing aluminum, silver, etc. is used. It is good.

[0323] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used for the conductive layer 772, the liquid crystal display device becomes a transmissive type. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. A pair of polarizing plates is provided to sandwich the liquid crystal element.

[0324] The display device 700 shown in FIG. 17 includes a liquid crystal element 77 of a horizontal electric field type (for example, FFS mode). 5 is used as a common electrode. A conductive layer 774 is provided. An electric field generated between the conductive layer 772 and the conductive layer 774 The alignment state of the liquid crystal layer 776 can be controlled.

[0325] In FIG. 17, a holding container is formed by a laminated structure of a conductive layer 774, an insulating layer 773, and a conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased. Cut.

[0326] Although not shown in FIGS. 16 and 17, an alignment film in contact with the liquid crystal layer 776 may be provided. In addition, optical members (optical substrates) such as polarizing members, phase difference members, and anti-reflection members may be used. , and light sources such as backlights and sidelights can be provided as appropriate.

[0327] The liquid crystal layer 776 may include a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a polymer dispersion liquid, or the like. Crystal (PDLC: Polymer Dispersed Liquid Crystal) , Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used.

[0328] The liquid crystal element mode is TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-S witching) mode, FFS(Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro- cell) mode, OCB (Optically Compensated Biref ringence mode, ECB (Electrically Controlled Birefringence mode, guest-host mode, etc. .

[0329] In addition, the liquid crystal layer 776 uses a polymer dispersed liquid crystal or a polymer network liquid crystal, A scattering type liquid crystal element can also be used. In this case, black and white display can be achieved without providing the colored film 736. Alternatively, a colored film 736 may be used to perform color display.

[0330] In addition, as a driving method of the liquid crystal element, a time-series additive color mixture method is used to display colors. A split display method (also called a field sequential driving method) may be applied. In this case, the colored film 736 may not be provided. For example, it is necessary to provide sub-pixels that exhibit the respective colors R (red), G (green), and B (blue). This has the advantage of improving the pixel aperture ratio and increasing the definition.

[0331] [Display device using light-emitting elements] The display device 700 shown in FIG. 18 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer The EL layer 786 includes an organic compound. has inorganic compounds such as quantum dots.

[0332] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dots. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, Examples include:

[0333] In the display device 700 shown in FIG. 18, a conductive layer 772 is formed on a planarization insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788. The light-emitting element 782 emits light toward the conductive layer 772. a bottom emission structure in which light is emitted from the bottom of the conductive layer 772 and the conductive film 788; It may also be a dual emission structure.

[0334] The colored film 736 is provided at a position overlapping the light emitting element 782, and the light blocking film 738 is an insulating film. 730, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 is formed in an island shape for each pixel or in a stripe shape for each pixel row, that is, by painting In some cases, the colored film 736 may not be provided.

[0335] FIG. 19 shows the configuration of a display device that can be suitably applied to a flexible display. FIG. 19 is a cross section taken along the dashed line ST in the display device 700A shown in FIG. 15(B). Figure.

[0336] The display device 700A shown in FIG. 19 includes a support substrate instead of the first substrate 701 shown in FIG. It has a structure in which a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated. The transistor 750, the capacitor 790, and the like are formed on an insulating layer 744 provided on a resin layer 743. It is set up in.

[0337] The support substrate 745 is a substrate containing organic resin, glass, or the like, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The resin layer 74 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. 3 and a support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferably thinner than the support substrate 745 .

[0338] 19 includes a protective layer 74 instead of the substrate 705 shown in FIG. The protective layer 740 is attached to the sealing film 732. The protective layer 740 may be a glass substrate or a resin film. Optical components such as polarizing plates and scattering plates, input devices such as touch sensor panels, or A configuration in which two or more layers are stacked may also be applied.

[0339] The EL layer 786 of the light-emitting element 782 is an island on the insulating film 730 and the conductive layer 772. The EL layer 786 is formed so that each sub-pixel emits a different color. Therefore, color display can be realized without using the colored film 736. Also, by covering the light emitting element 782, A protective layer 741 is provided. The protective layer 741 prevents impurities such as water from diffusing into the light emitting element 782. The protective layer 741 preferably uses an inorganic insulating film. It is more preferable to use a laminated structure containing at least one inorganic insulating film and at least one organic insulating film.

[0340] 19 shows a bendable region P2. In the region P2, the support substrate 7 45, in addition to the adhesive layer 742, there is a portion where no inorganic insulating film such as the insulating layer 744 is provided. In the region P2, a resin layer 746 is provided to cover the wiring 760. The bendable region P2 is provided with as little inorganic insulating film as possible, and a conductive film containing a metal or alloy is provided. By stacking only layers containing organic materials and layers containing organic materials, cracks do not occur when the material is bent. In addition, by not providing the support substrate 745 in the region P2, an extremely small A portion of the display device 700A can be bent with a small radius of curvature.

[0341] [Configuration example in which an input device is provided on a display device] 16 to 19 may be provided with an input device. Examples of the sensor include a touch sensor.

[0342] For example, the sensor types include capacitance type, resistive film type, surface acoustic wave type, and infrared type. Various methods can be used, such as electrical, optical, and pressure-sensitive methods. Or, two or more of these can be used. may be used in combination.

[0343] The touch panel has a so-called in-cell structure in which the input device is formed between a pair of substrates. touch panel, an input device formed on a display device, so-called on-cell type touch panel, or or a so-called out-cell type touch panel which is attached to a display device.

[0344] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly This can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0345] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0346] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0347] The display device shown in FIG. 20A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 50 6 and a terminal portion 507. Note that the protection circuit 506 may not be provided. .

[0348] The transistors included in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also be formed by using a transistor of one embodiment of the present invention. Good too.

[0349] The pixel section 502 is a plurality of pixels arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The display device has a plurality of pixel circuits 501 for driving a number of display elements.

[0350] The driving circuit unit 504 includes gate drivers that output scanning signals to the scanning lines GL_1 to GL_X. a source driver 504a that supplies data signals to the data lines DL_1 to DL_Y; The gate driver 504a has at least a shift register. The source driver 504b may be configured to have, for example, a plurality of analog switches. Also, the source driver 504b is configured using a shift register or the like. may be configured.

[0351] The terminal unit 507 is used to input power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for connecting the power supply to the power source are provided.

[0352] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, Various wirings such as the data line DL which is the wiring between the source driver 504b and the pixel circuit 501 Connected.

[0353] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film) circuit board) by COG or TAB (Tape Automated Bonding) It may also be configured to be mounted on a substrate.

[0354] 20(B) and 20(C) are connected to the pixel circuits 501 shown in FIG. 20(A). The configuration shown in (C) can be used.

[0355] The pixel circuit 501 shown in FIG. 20B includes a liquid crystal element 570, a transistor 550, and a capacitor. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_ m, a potential supply line VL, etc. are connected.

[0356] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. One of the electrodes may be given a different potential.

[0357] The pixel circuit 501 shown in FIG. 20C includes transistors 552 and 554 and a capacitor. The pixel circuit 501 also includes a data line DL_n , scanning line GL_m, potential supply line VL_a, potential supply line VL_b, etc. are connected to the pixel electrodes GL_m, GL_m, GL_a, GL_b, etc.

[0358] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. The other terminal is supplied with a low power supply potential VSS. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0359] The configuration examples exemplified in this embodiment and the corresponding drawings etc. are at least partly This can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0360] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0361] (Fourth embodiment) In the following, a pixel circuit having a memory for correcting the gradation displayed in the pixel and a The transistors exemplified in Embodiment 1 will be described below. The present invention can be applied to transistors used in pixel circuits.

[0362] <Circuit configuration> 21A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. The wiring S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0363] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, and The other of the source and drain is connected to one electrode of the capacitor C1. M2 has a gate connected to the wiring G2, one of the source and drain connected to the wiring S2, and one of the source and drain connected to the wiring S3. The other end of the input is connected to the other electrode of the capacitor C1 and the circuit 401, respectively.

[0364] The circuit 401 is a circuit including at least one display element. Representative examples include light-emitting elements such as organic EL elements and LED elements, and liquid crystal element, or MEMS (Micro Electro Mechanical Systems) EMS) elements, etc. can be applied.

[0365] The node connecting the transistor M1 and the capacitor C1 is connected to the node N1, and the transistor M2 is connected to the node N2. The node connecting to the path 401 is node N2.

[0366] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the potential of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the node By writing a predetermined potential to node N1, the voltage at node N1 is increased by capacitive coupling via capacitor C1. The potential of the node N2 can be changed in accordance with the change in potential.

[0367] Here, one or both of the transistors M1 and M2 may be The transistor using an oxide semiconductor, as exemplified in 1, can be applied. The low off-state current allows the potentials of the nodes N1 and N2 to be maintained for a long period of time. When the period for which the potential of each node is held is short (specifically, when the frame frequency is 30 Hz or less), In the above cases, a transistor using a semiconductor such as silicon may be used.

[0368] <Driving method example> Next, an example of a method of operating the pixel circuit 400 will be described with reference to FIG. (B) is a timing chart relating to the operation of the pixel circuit 400. For ease of understanding, various resistances such as wiring resistance, parasitic capacitances of transistors and wiring, The influence of the threshold voltage of the transistor and the like is not taken into consideration.

[0369] In the operation shown in FIG. 21(B), one frame period is divided into a period T1 and a period T2. T1 is a period during which a potential is written to node N2, and T2 is a period during which a potential is written to node N1. It is a period.

[0370] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the wiring S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supply.

[0371] The node N1 is connected to the line S1 via the transistor M1. ref is given. The node N2 is supplied with a first data potential V w is given. Therefore, the potential difference V across the capacitance C1 w -V ref is maintained.

[0372] [Period T2] Subsequently, in a period T2, a potential that turns on the transistor M1 is applied to the wiring G1. A potential that turns off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may be in a locking state.

[0373] The node N1 is supplied with a second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N That is, the first data potential Vw and the potential In FIG. 21(B), the potential dV is a positive value. However, it may be a negative value. That is, the second data potential V da ta is the potential V ref It may be lower.

[0374] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV is Data potential V data The potential is close to

[0375] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the circuit 401 can be generated, the gradation can be corrected within the pixel circuit 400. It becomes possible.

[0376] Furthermore, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when using liquid crystal elements, overdriving is possible. It is possible to realize drive, etc.

[0377] <Application example> [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 21C includes a circuit 401LC. has a liquid crystal element LC and a capacitor C2.

[0378] The liquid crystal element LC has one electrode connected to the other electrode of the capacitor C1, the source of the transistor M2, and The other electrode of the drain is connected to one electrode of the capacitor C2, and the other electrode is connected to the potential V com2 is given The capacitor C2 is connected to the wiring where the other electrode is connected to the potential V com1 and the wiring is given Connect.

[0379] The capacitor C2 functions as a storage capacitor. Note that the capacitor C2 can be omitted if not required.

[0380] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, By realizing high-speed display through live driving and applying liquid crystal materials with high driving voltage, In addition, by supplying a correction signal to the wire S1 or wire S2, it is possible to adjust the operating temperature and liquid temperature. The gradation can also be corrected depending on the deterioration state of the liquid crystal element LC.

[0381] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 21D includes a circuit 401EL. includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0382] The transistor M3 has a gate connected to one electrode of the capacitor C2 and a source and a drain connected to one of the electrodes. Potential V H The other end is connected to one electrode of the light-emitting element EL. The capacitance C2 is the capacitance when the other electrode is at potential V com The light-emitting element EL is connected to a wiring that is given a , the other electrode is at potential V L Connect with the wiring given.

[0383] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0384] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. H and potential V L You can change the value accordingly.

[0385] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, for example, HDR display can be realized. Also, by supplying a correction signal to the wiring S1 or wiring S2, the transistor M3 and the light emitting It is also possible to correct variations in the electrical characteristics of the element EL.

[0386] The circuit is not limited to the circuits illustrated in FIGS. 21(C) and 21(D), and may include additional transistors and A configuration in which capacitance or the like is added may also be adopted.

[0387] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0388] (Embodiment 5) In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described. do.

[0389] The display module 6000 shown in FIG. 22(A) includes an upper cover 6001 and a lower cover 6002. Between the display device 6006 and the frame 6009, the FPC 6005 is connected. The device has a main board 6010 and a battery 6011.

[0390] For example, a display device manufactured according to one embodiment of the present invention can be used as the display device 6006. The display device 6006 can realize a display module with extremely low power consumption. do.

[0391] The upper cover 6001 and the lower cover 6002 are designed to fit the size of the display device 6006. The shape and dimensions can be changed as appropriate.

[0392] The display device 6006 may have a function as a touch panel.

[0393] The frame 6009 has a function of protecting the display device 6006 and a function of preventing the display device 6006 from being damaged by the operation of the printed circuit board 6010. The insulating film may have a function of blocking electromagnetic waves generated by the insulating film, a function as a heat sink, etc.

[0394] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. It has a signal processing circuit, a battery control circuit, etc.

[0395] FIG. 22(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. is.

[0396] The display module 6000 includes a light emitting section 6015 and a receiving section 6016 provided on a printed circuit board 6010. The optical unit 6016 is enclosed by an upper cover 6001 and a lower cover 6002. The region has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b).

[0397] The display device 6006 is connected to a printed circuit board 6010 and a battery via a frame 6009. The display device 6006 and the frame 6009 are provided so as to overlap with the light guide unit 6011. 017a and fixed to the light guiding portion 6017b.

[0398] Light 6018 emitted from the light emitting unit 6015 is guided to the display device 600 by the light guiding unit 6017a. 6, and reaches the light receiving part 6016 through the light guiding part 6017b. When the light 6018 is blocked by a detection object such as an illustration, the touch operation can be detected. do.

[0399] A plurality of light emitting sections 6015 are provided along two adjacent sides of the display device 6006, for example. A plurality of light receiving sections 6016 are provided at positions facing the light emitting sections 6015. Information on the location where the touch operation was performed can be obtained.

[0400] The light emitting unit 6015 can use a light source such as an LED element, and in particular, can emit infrared light. It is preferable to use a light source that emits light. A photoelectric element that receives light and converts it into an electrical signal can be used. A photodiode such as a photodiode can be used.

[0401] The light emitting section 6015 and the light guiding section 6017a and the light guiding section 6017b transmit light 6018. The light receiving unit 6016 can be disposed below the display device 6006, and external light is received by the light receiving unit 601. 6 and prevent the touch sensor from malfunctioning. By using a resin that allows wires to pass through, malfunction of the touch sensor can be more effectively suppressed.

[0402] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0403] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described. Reveal.

[0404] The electronic device 6500 shown in FIG. 23(A) is a mobile phone that can be used as a smartphone. It is a mobile information terminal.

[0405] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, and a 504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0406] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0407] FIG. 23B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0408] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. The space surrounded by the protective member 6510 is provided with a display panel 6511, an optical member 6512, a tab The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. There are.

[0409] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The flannel 6513 is fixed by an adhesive layer (not shown).

[0410] In addition, in the area outside the display portion 6502, a part of the display panel 6511 is folded back. In addition, the FPC6515 is connected to the folded part. The 6515 is mounted with IC6516. The FPC6515 is a printed circuit board 6 517.

[0411] The flexible display panel of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Because it is thin, it can be equipped with a large-capacity battery 6518 while keeping the thickness of the electronic device small. In addition, a part of the display panel 6511 is folded back and the FPC 6515 is attached to the back of the pixel area. By arranging the connection portion, an electronic device with a narrow frame can be realized.

[0412] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0413] (Embodiment 7) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described. and explain.

[0414] The electronic devices exemplified below include a display device according to one embodiment of the present invention in a display portion. Therefore, it is an electronic device that has achieved high resolution. Also, high resolution and a large screen It is possible to make an electronic device that is compatible with both.

[0415] The display unit of the electronic device according to one embodiment of the present invention may be configured to display, for example, full high-definition, 4K2K, 8K4 It can display images with resolutions of 16K, 16K, 8K, or higher.

[0416] Examples of electronic devices include television sets, notebook personal computers, Equipped with relatively large screens such as monitor devices, digital signage, pachinko machines, and game machines In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, Examples of such devices include mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0417] An electronic device to which one aspect of the present invention is applied may be installed on the interior or exterior walls of a house or building, or the interior of a car or the like. It can be incorporated along a flat or curved surface of the packaging or exterior.

[0418] FIG. 24(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. This is a diagram.

[0419] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. The camera 8000 has a button 8004 and the like. The camera 8000 also has a detachable lens 8006. It is attached.

[0420] The camera 8000 may have the lens 8006 and the housing integrated together.

[0421] The camera 8000 can be operated by pressing the shutter button 8004 or by using the touch panel. An image can be captured by touching the display unit 8002.

[0422] The housing 8001 has a mount with electrodes, and is equipped with a finder 8100 and a strobe. It is possible to connect devices such as

[0423] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc. .

[0424] The housing 8101 is configured to mount the camera 8000 by a mount that engages with the mount of the camera 8000. The finder 8100 is attached to the camera 8000. It can be displayed on the display unit 8102.

[0425] The button 8103 has a function such as a power button.

[0426] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are The display device according to one embodiment of the present invention can be applied to a camera 8000 having a built-in finder. may be.

[0427] FIG. 24B is a diagram showing the appearance of the head mounted display 8200.

[0428] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 82 8203, a display unit 8204, a cable 8205, etc. It has a built-in 8206 battery.

[0429] A cable 8205 supplies power from a battery 8206 to the main body 8203. 203 is equipped with a wireless receiver and the like, and can display received video information on a display unit 8204. The main body 8203 is also equipped with a camera, and can input information on the movements of the user's eyes and eyelids. It can be used as a step.

[0430] In addition, the attachment part 8201 has a flow sensor that moves in accordance with the movement of the user's eyeball at a position where it comes into contact with the user. A plurality of electrodes capable of detecting the current passing through the sensor may be provided, and the sensor may have a function of recognizing the line of sight. In addition, the device may have a function of monitoring the pulse of the user by measuring the current flowing through the electrodes. The mounting part 8201 is equipped with various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. The display unit 8204 may have a function to display the user's biological information, and the head of the user may have a function to display the user's biological information. The display unit 8204 may have a function of changing the image displayed on the display unit 8204 in accordance with the user's movements.

[0431] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0432] 24(C), 24(D), and 24(E) show the head mounted display 830. 83. The head-mounted display 8300 includes a housing 8301 and a display It has a display part 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0433] The user can view the display on the display unit 8302 through the lens 8305. The curved arrangement of the portion 8302 is preferred because it allows the user to feel a high sense of realism. In addition, different images displayed in different areas of the display unit 8302 can be projected through the lens 8305. By viewing the image from the display unit 83, it is possible to perform a three-dimensional display using parallax. The present invention is not limited to a configuration in which one display unit 8302 is provided, but two display units 8302 may be provided, one for each eye of the user. One display unit may be provided.

[0434] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device having the semiconductor device has extremely high definition, the lens as shown in FIG. Even when enlarged using the 8305, the pixels are not visible to the user, resulting in a more realistic image. It can display high quality images.

[0435] The electronic devices shown in FIGS. 25A to 25G include a housing 9000, a display portion 9001, a screen Speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminal Child 9006, sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), It has 9008, etc.

[0436] The electronic devices shown in FIGS. 25A to 25G have various functions. Function to display various information (still images, videos, text images, etc.) on the display, touch panel function , calendar, date or time display functions, various software (programs) a function to control processing by wireless communication, a program recorded on a recording medium, or The electronic device can have the function of reading and processing data. The electronic device may have a variety of functions, including but not limited to the above. In addition, a camera or the like may be provided in the electronic device to take still images or videos and store them on a recording medium (external). It has functions such as saving the captured image to a memory card (built-in to the camera or the internal memory) and displaying the captured image on the display. It may be possible.

[0437] The electronic devices shown in FIGS. 25A to 25G will be described in detail below.

[0438] FIG. 25(A) is a perspective view showing a television device 9100. 100 is a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more It is possible to incorporate.

[0439] 25(B) is a perspective view showing a portable information terminal 9101. For example, the mobile information terminal 9101 can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple screens. 9 shows an example of displaying an icon 9050. Also, information 9051 shown in a dashed rectangle is displayed. It may also be displayed on another surface of the display unit 9001. An example of the information 9051 is an e-mail. Notifications of incoming emails, SNS, phone calls, etc., the subject of emails and SNS, the sender name, the date and time, The information includes the time, remaining battery power, and antenna reception strength. An icon 9050 or the like may be displayed at the position where the icon is displayed.

[0440] 25(C) is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 is , and has the function of displaying information on three or more surfaces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different surfaces. The person holds the mobile information terminal 9102 in the breast pocket of his / her clothes. The user can also check the information 9053 displayed in a position that can be observed from above. The display can be checked without taking the mobile information terminal 9102 out of a pocket, and for example, a telephone call can be made. You can decide whether to accept it or not.

[0441] 25(D) is a perspective view showing a wristwatch-type portable information terminal 9200. The display unit 9001 can be used as a smart watch, for example. The display surface is curved, and the display can be performed along the curved display surface. In addition, the mobile information terminal 9200 can communicate with, for example, a wireless headset. Therefore, hands-free calling is also possible. The terminal 9006 can transmit data to and from other information terminals and can also charge the device. Charging can also be performed by wireless power supply.

[0442] 25(E), 25(F), and 25(G) show a foldable mobile information terminal 920. 25(E) is a perspective view showing the mobile information terminal 9201 in an unfolded state, and FIG. 25(G) is the folded state, and Fig. 25(F) is the state of Fig. 25(E) and Fig. 25(G) from one side to the other. 9 is a perspective view of the mobile information terminal 9201 in the folded state. It is highly portable and has a seamless, large display area when unfolded, making it easy to see the display. The display unit 9001 of the portable information terminal 9201 is connected by a hinge 9055. It is supported by three housings 9000. For example, the display unit 9001 has a curvature radius of 1 mm or more. It can be bent to less than 150mm.

[0443] FIG. 26A shows an example of a television device. The television device 7100 has a housing 7 The display unit 7500 is built into the housing 7101. 101 is shown as a supported configuration.

[0444] The television device 7100 shown in FIG. 26A is operated by an operation switch provided in the housing 7101. This can be done by a separate remote control 7111 or a display unit 75. A touch panel is applied to the television device 7100, and the television device 7100 can be operated by touching the touch panel. The remote control device 7111 may have a display unit in addition to the operation buttons.

[0445] The television device 7100 may be a television broadcast receiver or a network connection device. The communication device may include:

[0446] FIG. 26(B) shows a notebook personal computer 7200. The mobile computer 7200 includes a housing 7211, a keyboard 7212, a pointing device, and a The housing 7211 includes a display unit 7500 and an external connection port 7214. It is embedded.

[0447] Figures 26(C) and 26(D) show the digital signage. An example of a digital signage (ge: electronic sign) is shown below.

[0448] The digital signage 7300 shown in FIG. 26C includes a housing 7301, a display unit 7500, and a speaker 7303. In addition, LED lamps, operation keys (power switch, It may have a variety of functions, including a control switch, connection terminals, various sensors, a microphone, etc. Cut.

[0449] FIG. 26(D) shows a digital signage 740 attached to a cylindrical pillar 7401. The digital signage 7400 is a display unit provided along the curved surface of a pillar 7401. It has 7500.

[0450] The larger the display 7500, the more information can be displayed at once, and the closer it is to the human eye. It is easy to attach to the surface, which has the effect of increasing the advertising effectiveness of advertisements, for example.

[0451] It is preferable that the display unit 7500 be configured as a touch panel so that a user can operate it. This will enable the information to be used not only for advertising purposes but also for route information, traffic information, and commercial facility guidance information. It can also be used to provide information that users are looking for.

[0452] Also, as shown in FIG. 26(C) and FIG. 26(D), a digital signage 7300 or The digital signage 7400 is an information terminal device 73 such as a smartphone owned by a user. 11 via wireless communication. The information of the advertisement to be displayed on the screen of the information terminal 7311, By operating it, the display on the display unit 7500 can be switched.

[0453] In addition, the Digital Signage 7300 or Digital Signage 7400 can be used with an information terminal. It is also possible to run games using the 7311 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0454] The display portion 7500 in FIGS. 26A to 26D includes a display device according to one embodiment of the present invention. can be applied.

[0455] Although the electronic device of this embodiment has a display unit, the present invention can also be applied to electronic devices that do not have a display unit. One aspect of the present invention can also be applied.

[0456] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination. [Example]

[0457] In this embodiment, the conductive layer 112, the functional layer 113, the metal oxide layer 114 or the insulating layer 110 Examples of materials that can be used include copper, titanium, molybdenum, ITSO, and metal oxides. The etching rate of silicon oxynitride was evaluated. Three types of films with different properties (silicon oxynitride 1, silicon oxynitride 2, and silicon oxynitride) 3) was evaluated.

[0458] For the evaluation, samples in which various films were formed on glass substrates were used.

[0459] The copper film used in this example was formed by sputtering using a Cu target. The deposition was performed under the conditions of a pressure of 1.0 Pa and a power supply of 15 kW (DC). The substrate temperature during deposition was 100°C. Argon gas was used as the deposition gas.

[0460] The titanium film used in this example was formed by sputtering using a Ti target. The deposition was carried out under the conditions of 0.3 Pa pressure and 8 kW (DC power). Argon gas was used as the deposition gas.

[0461] The molybdenum film used in this example was formed by sputtering using a Mo target. The deposition was carried out under the conditions of a pressure of 0.85 Pa and a power supply of 35 kW (DC). The temperature was set to 80° C. Argon gas was used as the deposition gas.

[0462] The ITSO film used in this example was formed using an ITSO target (In2O3:SnO2: SiO2 = 85:10:5 [weight ratio]) was sputtered at a pressure of 0.15 The deposition was carried out under the conditions of 1 Pa, 1 kW (DC) power supply, and the substrate temperature during deposition was 80°C. Argon gas was used as the gas.

[0463] The metal oxide film used in this example was formed using an In-Ga-Zn oxide target (In: The sputtering method was carried out using a Ga:Zn=4:2:4.1 (atomic ratio) under a pressure of 0. The deposition was performed under the conditions of 6 Pa and 2.5 kW (AC) power supply. The substrate temperature during deposition was room temperature. A mixture of oxygen and argon gas was used as the deposition gas, and the oxygen flow rate ratio was set to 10%. The target composition was In:Ga:Zn=4:2:4.1 [atomic ratio]. The film composition of the sample thus obtained was approximately In:Ga:Zn=4:2:3 [atomic ratio].

[0464] The silicon oxynitride film 1 used in this example was formed using silane gas at a flow rate of 24 sccm, and nitrous oxide gas at a flow rate of 18,000 sccm. The pressure was 200 Pa and the deposition power was 130 W. The substrate temperature during deposition was 350°C. The silicon oxynitride film 1 corresponds to the insulating layer 110a shown in the first embodiment.

[0465] The silicon oxynitride film 2 used in this example was formed using silane gas at a flow rate of 200 sccm. and 10,000 sccm of nitrous oxide gas mixture. The deposition was carried out under the conditions of a pressure of 300 Pa and a deposition power of 750 W. The substrate temperature during deposition was 350°C. The silicon oxynitride film 2 corresponds to the insulating layer 110c shown in the first embodiment.

[0466] The silicon oxynitride film 3 used in this example was formed using silane gas at a flow rate of 20 sccm, The pressure was measured by the PECVD method using a mixture of nitrous oxide gas and a flow rate of 3000 sccm. The deposition was carried out under the conditions of a pressure of 40 Pa and a deposition power of 500 W. The substrate temperature during deposition was 350°C. The silicon oxynitride film 3 corresponds to the insulating layer 110b shown in the first embodiment.

[0467] The two etchant chemicals, Chemical A and Chemical B, were mixed in a 5:1 volume ratio just before use. Chemical solution A was a mixture of phosphoric acid (less than 5 weight%) and hydrofluoric acid (1 weight%, nitric acid (less than 10 weight%), additives (22 weight% Chemical solution B was an aqueous solution of hydrogen peroxide (31% by weight). The etchant temperature during etching was set to 30°C.

[0468] The etching rates of various films are shown in Table 1. In Table 1, the etching rates of IGZO (4:2:3 ) refers to the metal oxide film mentioned above, and SiON1 refers to the oxide film mentioned above. The term "SiON2" refers to the silicon nitride film 1, and the term "SiON2" refers to the silicon oxynitride film 2 mentioned above. The term "SiON3" refers to the silicon oxynitride film 3 described above.

[0469] [Table 1]

[0470] As shown in Table 1, compared to copper, titanium, molybdenum, ITSO, metal oxides, and oxides The etching rates of silicon nitride 1, silicon oxynitride 2, and silicon oxynitride 3 are slow. It was also confirmed that the silicon oxynitride film 3 that can be used for the insulating layer 110b is The silicon oxynitride film 1 that can be used for the insulating layer 110a and the silicon oxynitride film 2 that can be used for the insulating layer 110c It was confirmed that the etching rate was slower than that of the silicon oxynitride film 2. The silicon oxynitride film 2 that can be used for the insulating layer 110a can be used for the insulating layer 110c. The silicon oxynitride film 1 that can be used for the insulating layer 110b is It was confirmed that the etching rate was faster than that of silicon film 3. [Example]

[0471] In this example, a sample (sample A) corresponding to the transistor 100B shown in FIG. were prepared and the cross-sectional shape was evaluated.

[0472] <Sample preparation> First, a 100 nm thick tungsten film was formed on a glass substrate by sputtering. This was then processed to obtain the first gate electrode.

[0473] Next, a first silicon nitride film having a thickness of 50 nm is formed as a first gate insulating layer, and a second silicon nitride film having a thickness of 20 nm is formed as a second gate insulating layer. 0 nm thick second silicon nitride film, 50 nm thick third silicon nitride film, and 3 nm thick The first silicon oxynitride film and the second silicon oxynitride film were formed in this order.

[0474] The first silicon nitride film and the third silicon nitride film were formed at a flow rate of 200 scc. m of silane gas, 2000 sccm of nitrogen gas, and 100 sccm of ammonia gas. The PECVD method using a mixture of gases was performed under the conditions of a pressure of 100 Pa and a film-forming power of 2000 W. The substrate temperature during film formation was 350°C.

[0475] The second silicon nitride film was formed using silane gas with a flow rate of 290 sccm and a flow rate of 2000 sccm. PECV using a mixture of nitrogen gas at a flow rate of 2000 sccm and ammonia gas at a flow rate of 2000 sccm The deposition was carried out by the D method under the conditions of a pressure of 200 Pa and a deposition power of 3000 W. The substrate temperature during deposition was The temperature was set to 350°C.

[0476] The first silicon oxynitride film was formed using silane gas at a flow rate of 20 sccm and The PECVD method was performed using a mixed gas of 0 sccm of nitrous oxide and 40 Pa at a pressure of 40 Pa. The deposition was performed under the condition of a deposition power of 3000 W. The substrate temperature during deposition was 350°C.

[0477] Subsequently, a first metal oxide film having a thickness of 30 nm was formed on the first gate insulating layer. The metal oxide film of 1 was formed using an In-Ga-Zn oxide target (In:Ga:Zn=4 The sputtering method was carried out using a pressure of 0.6 Pa and a power supply voltage of 100 V. The deposition was performed under the condition of a power of 2.5 kW. The substrate temperature during deposition was room temperature. Oxygen gas was used as the deposition gas. A mixed gas of argon and oxygen was used, and the oxygen flow rate ratio was set to 10%.

[0478] Next, the material was heated at 370°C for 1 hour in a nitrogen atmosphere, and then mixed with nitrogen and oxygen. Heat treatment at 370°C for 1 hour in a gas atmosphere (nitrogen gas flow rate: oxygen gas flow rate = 1:1) An oven was used for the heat treatment.

[0479] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0480] Next, a second silicon oxynitride film having a thickness of 5 nm is formed as a second gate insulating layer, and a second silicon oxynitride film having a thickness of 1 nm is formed as a second gate insulating layer. A third silicon oxynitride film having a thickness of 30 nm and a fourth silicon oxynitride film having a thickness of 5 nm are formed on this The films were formed in this order.

[0481] The second silicon oxynitride film was formed (film formation condition 1) using silane gas at a flow rate of 24 sccm. and 18,000 sccm of nitrous oxide gas mixture. The deposition was carried out under the conditions of a pressure of 200 Pa and a deposition power of 130 W. The substrate temperature during deposition was 350°C. The second silicon oxynitride film corresponds to the insulating layer 110a described in Embodiment 1. do.

[0482] The third silicon oxynitride film was formed (film formation condition 2) using silane gas at a flow rate of 200 sccm. and nitrous oxide gas at a flow rate of 10,000 sccm. The deposition was carried out under the conditions of a pressure of 300 Pa and a deposition power of 750 W. The substrate temperature during deposition was 350°C. The third silicon oxynitride film corresponds to the insulating layer 110c shown in the first embodiment. do.

[0483] The fourth silicon oxynitride film was formed (film formation condition 3) using silane gas at a flow rate of 20 sccm. and nitrous oxide gas at a flow rate of 3000 sccm by PECVD method. The deposition was carried out under conditions of a pressure of 40 Pa and a deposition power of 500 W. The substrate temperature during deposition was 350°C. The fourth silicon oxynitride film corresponds to the insulating layer 110b described in the first embodiment.

[0484] Second silicon oxynitride film (film formation condition 1), third silicon oxynitride film (film formation condition 2) The deposition rate and etching rate of the fourth silicon oxynitride film (deposition condition 3) are shown in Table 2. In Table 2, etching rate 1 is the etching rate in the etchant shown in Example 1. The etching rate 2 is the etching rate in 0.5 weight percent hydrofluoric acid. It shows the speed.

[0485] [Table 2]

[0486] Next, the sample was heated at 370°C for 1 hour in a nitrogen atmosphere. The device was used.

[0487] Subsequently, a second metal oxide film having a thickness of 20 nm is formed on the fourth silicon oxynitride film. The second metal oxide film was formed using an In-Ga-Zn oxide target (In:Ga:Z n = 4:2:4.1 [atomic ratio]) at a pressure of 0.6 Pa. The power supply was 2.5 kW. The substrate temperature during film formation was 200°C. Oxygen gas (oxygen flow rate ratio 100%) was used.

[0488] Next, a 10 nm thick ITSO film and a 100 nm thick copper film were deposited on the second metal oxide film. The ITSO film and copper film were deposited by sputtering. The SO film was formed using an ITSO target (In2O3:SnO2:SiO2 = 85:10: 5 [weight ratio]) was used. A Cu target was used to form the copper film.

[0489] Next, a resist mask is formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film are formed. The second metal oxide layer, the ITSO layer, and the copper layer were formed by wet etching. For details about the etchant, please refer to the description in Example 1. A detailed explanation will be omitted.

[0490] Next, the second silicon oxynitride film is etched using the resist mask. The second gate insulating layer was formed by etching. The resist mask was removed.

[0491] Next, a fourth silicon nitride film with a thickness of 100 nm is deposited as a protective layer covering the transistor. A fourth silicon nitride film having a thickness of 300 nm was then deposited in this order. The silicon oxide nitride film and the fifth silicon oxynitride film were formed by plasma CVD. The substrate temperature during film formation was The temperature was set to 350°C.

[0492] Through the above steps, sample A was obtained.

[0493] <Cross-section observation of sample> Next, sample A was irradiated with a focused ion beam (FIB). The cross section of sample A was observed by STEM.

[0494] STEM images of the cross section of sample A are shown in Figures 27(A) and 27(B). 7(A) is a transmission electron image (TE image) at 100,000 magnification. Figure 27(B) shows the same area as Figure 27(A) at 100,000 times magnification. This is a Z contrast image (ZC image). In the image, the larger the atomic number of a material, the brighter it appears. As shown, no undercuts were observed and it was confirmed that the shape was good. [Example]

[0495] In this embodiment, a transistor (sample) corresponding to the transistor 100B shown in FIG. The electrical characteristics of the transistor 100B were evaluated. A transistor (sample B2) without the conductive layer 106 serving as an electrode was also fabricated. The electrical properties were evaluated.

[0496] <Sample preparation> The structure of the fabricated transistor can be that of the transistor 100B illustrated in FIG.

[0497] The fourth silicon nitride film, which is a protective layer, and the fifth silicon oxynitride film are formed in the same manner as described above. The description in Example 2 can be used, so a detailed description will be omitted.

[0498] Next, a part of the protective layer covering the transistor is opened and a 100 nm thick molybdenum film is After forming the film by sputtering, it was processed to obtain the source electrode and the drain electrode. After that, an acrylic resin film with a thickness of about 1.5 μm was formed as a flattening layer, and then, under a nitrogen atmosphere, The heat treatment was carried out at a temperature of 250°C for 1 hour.

[0499] Through the above steps, a transistor formed on a glass substrate was obtained.

[0500] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistor fabricated above were measured.

[0501] The measurement conditions for the Id-Vg characteristics of the transistor are as follows: (hereinafter also referred to as gate voltage (Vg)), and the voltage applied to the second gate electrode (Vbg ) was applied from -15V to +20V in 0.25V steps. The voltage applied to the source electrode (hereinafter referred to as source voltage (Vs)) is set to 0 V (common). The voltage applied to the drain electrode (hereinafter referred to as drain voltage (Vd)) is set to 0.1 V and 5.1V.

[0502] The Id-Vg characteristics of the transistor are shown in FIG. 28. In FIG. 28, the first gate electrode is shown at the top. and sample B2, which does not have the first gate electrode. The condition where the channel length of the transistor is different in the lateral direction is also shown. ,Three types of transistors with channel lengths of 2 μm, 3 μm, and 6 μm, and channel widths of 50 μm. In FIG. 28, the horizontal axis represents the gate voltage (Vg), and the vertical axis on the left represents the The axis shows the drain current (Id), and the right vertical axis shows the saturation mobility (μFE) at Vd = 5.1 V. In Figure 28, the horizontal axis is shown on a linear scale, and the left end is Vg=-15V. The right end is Vg = 20 V. The left vertical axis is in logarithmic scale, and the bottom end is Id = 1×10 -12 A, and the upper limit is Id=1×10 -2 A. The vertical axis on the right is the linear scale. The lower end is μFE=0cm 2 / Vs, and the upper limit is μFE=100cm 2 / Vs. The Id-Vg characteristics of 20 transistors were measured for each sample. .

[0503] As shown in FIG. 28, good electrical properties were obtained in all samples. [Example]

[0504] In this example, a sample (sample C) corresponding to the transistor 100E shown in FIG. were prepared and the cross-sectional shape was evaluated.

[0505] <Sample preparation> First, a 30 nm thick titanium film and a 100 nm thick copper film were deposited on a glass substrate in this order. The first gate electrode was formed by sputtering and processed.

[0506] Next, a first silicon nitride film having a thickness of 50 nm is formed as a first gate insulating layer, and a second silicon nitride film having a thickness of 20 nm is formed as a second gate insulating layer. 0 nm thick second silicon nitride film, 50 nm thick third silicon nitride film, and 3 nm thick The first gate insulating layer was formed by plasma CVD. The substrate temperature during film formation was 350°C.

[0507] Subsequently, a first metal oxide film having a thickness of 30 nm was formed on the first gate insulating layer. The metal oxide film of 1 was formed using an In-Ga-Zn oxide target (In:Ga:Zn=4 The sputtering method was carried out using a pressure of 0.6 Pa and a power supply voltage of 100 V. The deposition was performed under the condition of a power of 2.5 kW. The substrate temperature during deposition was room temperature. Oxygen gas was used as the deposition gas. A mixed gas of argon and oxygen was used, and the oxygen flow rate ratio was set to 10%.

[0508] Next, the material was heated at 370°C for 1 hour in a nitrogen atmosphere, and then mixed with nitrogen and oxygen. Heat treatment at 370°C for 1 hour in a gas atmosphere (nitrogen gas flow rate: oxygen gas flow rate = 1:1) An oven was used for the heat treatment.

[0509] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0510] Next, a second silicon oxynitride film having a thickness of 5 nm is formed as a second gate insulating layer, and a second silicon oxynitride film having a thickness of 1 nm is formed as a second gate insulating layer. A third silicon oxynitride film having a thickness of 25 nm and a fourth silicon oxynitride film having a thickness of 10 nm were then formed. The second gate insulating layer was formed by plasma CVD, and the substrate temperature during film formation was The temperature was set to 350°C.

[0511] The second silicon oxynitride film was formed under the film forming conditions 1 shown in Example 2, and the third silicon oxynitride film was formed under the film forming conditions 1 shown in Example 2. The silicon film was formed under film formation condition 2, and the fourth silicon oxynitride film was formed under film formation condition 3. Ta.

[0512] Next, the sample was heated at 370°C for 1 hour in a nitrogen atmosphere. The device was used.

[0513] Subsequently, a second metal oxide film having a thickness of 20 nm is formed on the fourth silicon oxynitride film. The second metal oxide film was formed using an In-Ga-Zn oxide target (In:Ga:Z n = 4:2:4.1 [atomic ratio]) at a pressure of 0.6 Pa. The power supply was 2.5 kW. The substrate temperature during film formation was 200°C. Oxygen gas (oxygen flow rate ratio 100%) was used.

[0514] Next, a 10 nm thick ITSO film and a 100 nm thick copper film were deposited on the second metal oxide film. The ITSO film and copper film were deposited by sputtering. The SO film was formed using an ITSO target (In2O3:SnO2:SiO2 = 85:10: 5 [weight ratio]) was used. A Cu target was used to form the copper film.

[0515] Next, a resist mask is formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film are formed. The second metal oxide layer, the ITSO layer, and the copper layer were formed by wet etching. For details about the etchant, please refer to the description in Example 1. A detailed explanation will be omitted.

[0516] Next, the second silicon oxynitride film is etched using the resist mask. The second gate insulating layer was formed by etching. The resist mask was removed.

[0517] Next, a fourth silicon nitride film with a thickness of 100 nm is deposited as a protective layer covering the transistor. A fourth silicon nitride film having a thickness of 300 nm was then deposited in this order. The silicon oxide nitride film and the fifth silicon oxynitride film were formed by plasma CVD. The substrate temperature during film formation was The temperature was set to 350°C.

[0518] Through the above steps, sample C was obtained.

[0519] <Cross-section observation of sample> Next, sample C was irradiated with a focused ion beam (FIB). The cross section of sample C was observed by STEM.

[0520] STEM images of the cross section of sample C are shown in Figures 29(A) and 29(B). 9(A) is a transmission electron image (TE image) at a magnification of 100,000 times. 29(A) and 29(B) are Z-contrast images (ZC images) at 100,000 times magnification of the same area. As shown in 9(B), no undercuts were observed and it was confirmed that the shape was good. In addition, the edges of the metal oxide layer, the ITSO layer, and the copper layer are closer to the edge of the silicon oxynitride layer. and the end of the copper layer is located inside the ends of the ITSO layer and the copper layer. In addition, the width of the region corresponding to the region 108L shown in FIG. 7(B) is about 200 nm. It was confirmed that this was the case. [Example]

[0521] In this embodiment, a transistor (sample) corresponding to the transistor 100E shown in FIG. e D) was fabricated and its electrical properties were evaluated.

[0522] <Sample preparation> The structure of the fabricated transistor can be that of the transistor 100E illustrated in FIG.

[0523] The fourth silicon nitride film, which is a protective layer, and the fifth silicon oxynitride film are formed in the same manner as described above. The description in Example 4 can be used, so a detailed description will be omitted.

[0524] Next, a part of the protective layer covering the transistor is opened, and a titanium film with a thickness of 30 nm and a After forming a 100 nm copper film in this order by sputtering, it is processed to form a source. After that, a 1.5 μm thick acrylic resin layer was applied as a planarization layer. The film was formed and then heat-treated in a nitrogen atmosphere at 250°C for 1 hour.

[0525] Through the above steps, a transistor formed on a glass substrate was obtained.

[0526] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistor fabricated above were measured.

[0527] The measurement conditions for the Id-Vg characteristics of the transistor are as follows: (hereinafter also referred to as gate voltage (Vg)), and the voltage applied to the second gate electrode (Vbg ) was applied from -15V to +20V in 0.25V steps. The voltage applied to the source electrode (hereinafter referred to as source voltage (Vs)) is set to 0 V (common). The voltage applied to the drain electrode (hereinafter referred to as drain voltage (Vd)) is set to 0.1 V and 5.1V.

[0528] The Id-Vg characteristics of the transistor are shown in Figure 30. In Figure 30, the Id-Vg characteristics of the transistor are shown in the vertical direction. The channel length is shown as 1.5 μm, 2 μm, 3 μm, and 6 μm. The figure shows four types of transistors with a channel width of 50 μm and a channel width of 50 μm. The horizontal axis is a linear scale, with the left end at Vg=-15V and the right end at Vg=20 V. The left vertical axis is shown in logarithmic scale, and the bottom is Id=1×10 -12 A is , the upper end is Id=1×10 -2 A. The vertical axis on the right is a linear scale, and the bottom is μFE=0cm 2 / Vs, and the upper limit is μFE=100cm 2 / Vs. The Id-Vg characteristics of 20 transistors were measured for each sample.

[0529] As shown in Figure 30, good electrical characteristics are obtained even in transistors with short channel lengths. I was able to do it. [Example]

[0530] In this example, a sample (sample) having a laminated structure of an insulating film, a metal oxide film, a functional film, and a conductive film was prepared. Samples E1 and E2 were prepared and the amount of water adsorbed on the insulating film was evaluated. The cross-sectional structure of sample E1 is shown in Figure 31(A), and the cross-sectional structure of sample E2 is shown in Figure 31(B). show.

[0531] <Sample preparation> First, a first silicon oxynitride film having a thickness of 5 nm was formed on a glass substrate 200 as an insulating film 210. The silicon nitride film 210A has a thickness of 130 nm, the second silicon oxynitride film 210B has a thickness of 130 nm, and the third silicon oxynitride film 210C has a thickness of 130 nm. A silicon nitride film 210C was formed in this order. The film forming condition 1 shown in Example 2 was used for forming the second silicon oxynitride film 210B. Condition 2: The third silicon oxynitride film 210C was formed under the film formation condition 3. The thickness of the third silicon oxynitride film 210C is 5 nm for sample E1, and The thickness of the third silicon oxynitride film 210C was set to 10 nm.

[0532] Next, the sample was heated at 370°C for 1 hour in a nitrogen atmosphere. The device was used.

[0533] Subsequently, a metal oxide film 214 having a thickness of 20 nm is formed on the third silicon oxynitride film 210C. The metal oxide film 214 was formed using an In—Ga—Zn oxide target (In: The sputtering method was carried out using a Ga:Zn=4:2:4.1 (atomic ratio) under a pressure of 0. The deposition was performed under the conditions of 6 Pa and 2.5 kW power supply. The substrate temperature during deposition was 200°C. Oxygen gas (oxygen flow rate ratio 100%) was used as the gas.

[0534] Next, a 10 nm thick ITSO film 213 and a 100 nm thick SiO2 film 214 are formed on the metal oxide film 214. The ITSO film 213 and the copper film 212 were formed in this order. The ITSO film 213 was formed by a deposition method using an ITSO target (In2O3:S The copper film 212 was formed using a CuO2 / SiO2 (weight ratio: 85:10:5). target was used.

[0535] Subsequently, the metal oxide film 214, the ITSO film 213, and the copper film 212 were removed by wet etching. For both sample E1 and sample E2, the etchant temperature during wet etching was set to 30 °C, and the etching time was set to 60 sec. Regarding the etchant, since the description in Example 1 above can be referred to, detailed explanation is omitted.

[0536] Subsequently, the film thickness was measured. From the measurement results of the film thickness, it was confirmed that in sample E1, a part of the surface side of the third silicon oxynitride film 210C and the second silicon oxynitride film 210B was also removed, and the surface of the second silicon oxynitride film 210B was exposed. Similarly, in sample E2, it was confirmed that a part of the surface side of the third silicon oxynitride film 210C was removed and the surface of the third silicon oxynitride film 210C was exposed.

[0537]

[0538] In the above steps, sample E1 and sample E2 were obtained. <TDS analysis>

[0539] Subsequently, using the temperature-programmed desorption gas analysis method (TDS: Thermal Desorption Spectrometry), the desorbed gases from sample E1 and sample E2 were evaluated. In the TDS measurement, the substrate temperature was raised from about 50 °C to about 550 °C at a heating rate of 30 °C / min. The TDS analysis results of sample E1 are shown in Fig. 32(A), and those of sample E2 are shown in Fig. 32(B). In Fig. 32(A) and Fig. 32(B), the horizontal axis represents the substrate temperature (Tsub).

[0540]

[0541] The vertical axis shows the detection intensity at a mass-to-charge ratio of 18 (M / z=18). The gas with a mass-to-charge ratio of 18 (M / z=18) is mainly water (H2O) molecules.

[0540] As shown in Figure 32(A), in sample E1, the mass-charge A peak with a charge ratio of 18 (M / z=18) was observed. The peak is thought to be due to adsorbed water on the sample surface. By exposing the surface of B, water in the atmosphere is allowed to reach the surface of the second silicon oxynitride film 210B. It is thought that it was adsorbed.

[0541] On the other hand, as shown in Figure 32(B), sample E2 has a mass-to-charge ratio of 18 (M / z = 18) The peak of the third silicon oxynitride film 210C was very small. However, since a film that is difficult to adsorb water is used as the third silicon oxynitride film 210C, It is believed that adsorption of water from the atmosphere was suppressed. [Example]

[0542] In this example, the influence of impurities containing hydrogen on metal oxides was evaluated.

[0543] For the evaluation, a sample was used in which a metal oxide film with a thickness of 200 nm was formed on a glass substrate. As the metal oxide film, In-Ga-Zn oxide was used.

[0544] The metal oxide film used in this example was formed using an In-Ga-Zn oxide target (In: The sputtering method was carried out using a Ga:Zn=4:2:4.1 (atomic ratio) under a pressure of 0. The deposition was carried out under the conditions of 4 Pa ​​and 0.2 kW (DC) power supply. The substrate temperature during deposition was 350°C. A mixture of oxygen gas and argon gas was used as the deposition gas, and the oxygen flow rate ratio was set to 33%. The target used had a composition of In:Ga:Zn=4:2:4.1 [atomic ratio]. The film composition of the sample thus formed was approximately In:Ga:Zn=4:2:3 [atomic ratio]. The glass substrate was heated immediately before the formation of the metal oxide film to prevent the metal oxide from adsorbing on the glass substrate. The glass substrate was heat-treated in a vacuum atmosphere at 350°C for 5 minutes.

[0545] After the metal oxide film was formed, the surface of the metal oxide film was exposed to a clean room atmosphere. The time was about one week.

[0546] Next, the samples were subjected to heat treatment. The heat treatment was performed in the following ways: no heat treatment, 250°C for 10 min, 250°C for 10 min, 20min, 250℃30min, 250℃60min, 300℃10min, 300℃ 20min, 300℃30min, 300℃60min, 350℃10min, 350℃ The heat treatment was carried out at 13 different temperatures: 20 min, 350°C for 30 min, and 350°C for 60 min. The experiment was carried out in a vacuum atmosphere.

[0547] <Evaluation of hydrogen concentration> The hydrogen concentration in the metal oxide film of the above sample was evaluated using secondary ion mass spectrometry. The IMS measurement was performed using a CAMECA IMS-6f, with the primary ion species being Cs + , primary acceleration The voltage was 5.0 kV and the detection area was 30 μm in diameter. The detection limit (BG) was approximately 5 × 1 0 17 atoms / cm 3 It was.

[0548] The sample without heat treatment (marked "none") and the sample with heat treatment at 250°C for 10 min each The hydrogen concentration profiles of the samples heat treated for 20 min, 30 min, and 60 min were The results are shown in Figure 33(A). The hydrogen concentration profiles of the samples heat treated for 20 min, 30 min, and 60 min were The results are shown in Figure 33(B). The hydrogen concentration profiles of the samples heat treated for 20 min, 30 min, and 60 min were Shown in Figure 34(A).

[0549] In Fig. 33(A), Fig. 33(B) and Fig. 34(A), the horizontal axis represents the distance from the surface of the metal oxide film. The vertical axis shows the depth of the sample, and the vertical axis shows the hydrogen concentration. vinegar.

[0550] As shown in Figure 33(A), compared to the condition without heat treatment, the The hydrogen concentration on the surface of the metal oxide film was high. When exposed to air, water is adsorbed onto the surface of the metal oxide film, and the hydrogen contained in the adsorbed water is released by heating. It is thought that the metal oxide film was diffused by the heat treatment. The hydrogen concentration in the metal oxide film tended to increase as the heat treatment time increased. It is believed that this increases the amount of hydrogen diffusing into the metal oxide film.

[0551] As shown in Figure 33(B), the results are as follows: In all cases, the hydrogen concentration in the metal oxide film tended to increase. No particular difference was observed.

[0552] As shown in Figure 34(A), compared to the condition without heat treatment, the The hydrogen concentration in the metal oxide film was higher on the glass substrate side. The hydrogen concentration on the surface side of the film tended to be low. It is thought that the hydrogen that had diffused once was desorbed from the metal oxide surface side. The longer the heating time, the lower the hydrogen concentration in the metal oxide film becomes, especially on the surface of the metal oxide film. The hydrogen concentration on the metal oxide surface side decreased. It is thought that the amount of hydrogen released from the atmosphere increased.

[0553] <Evaluation of carrier density> The carrier density was evaluated for the sample obtained under the above-mentioned 250°C 10 min condition.

[0554] In this example, the carrier density in the thickness direction of the metal oxide film was evaluated. After that, the surface was partially etched away to make the film thinner. Then, the film thickness and resistance were measured again. This process was repeated.

[0555] The carrier density was calculated from the resistivity obtained by the resistance measurement. In this case, the mobility μ of the metal oxide is 16.50 cm 2 / V·s, electron charge q is 1.602×1 0 -19 I chose C.

[0556] The carrier density and hydrogen concentration in the metal oxide film are shown in FIG. In this figure, the horizontal axis represents the depth from the surface of the metal oxide film, and the vertical axis represents the carrier density. (Carrier density) and hydrogen concentration (H Concentration) The hydrogen concentration shown in FIG. 34(B) is the same data as the hydrogen concentration shown in FIG. 33(A). It is Ta.

[0557] As shown in FIG. 34(B), the hydrogen concentration and carrier density in the thickness direction of the metal oxide film are almost the same. Since the results are almost identical, it is thought that hydrogen in the metal oxide film generates carriers. Therefore, when a metal oxide is used as the semiconductor layer, the gate insulating film is formed immediately after the semiconductor layer is formed. It has been found that forming a layer is preferable. [Example]

[0558] In this example, after the first metal oxide film was formed, the heat treatment conditions were varied. In this example, a sample was prepared corresponding to the transistor 100A shown in FIG. The corresponding transistors (sample F1 to sample F4) and the transistor shown in FIG. Transistors corresponding to the transistor 100 (sample G1 to sample G4 ) was produced.

[0559] <Sample preparation> First, a tungsten film with a thickness of approximately 100 nm was formed on a glass substrate by sputtering. This was processed to obtain the first gate electrode.

[0560] Next, a first silicon nitride film having a thickness of 50 nm is formed as a first gate insulating layer, and a second silicon nitride film having a thickness of 20 nm is formed as a second gate insulating layer. 0 nm thick second silicon nitride film, 50 nm thick third silicon nitride film, and 3 nm thick The first gate insulating layer was formed by plasma CVD. The substrate temperature during film formation was 350°C.

[0561] Subsequently, a first metal oxide film having a thickness of 30 nm was formed on the first gate insulating layer. The metal oxide film of 1 was formed using an In-Ga-Zn oxide target (In:Ga:Zn=4 The sputtering method was carried out using a pressure of 0.6 Pa and a power supply voltage of 100 V. The deposition was performed under the condition of a power of 2.5 kW. The substrate temperature during deposition was room temperature. Oxygen gas was used as the deposition gas. A mixed gas of argon and oxygen was used, and the oxygen flow rate ratio was set to 10%.

[0562] Next, heat treatment was carried out using an oven. e G1 was subjected to heat treatment at 370°C for 1 hour in a nitrogen atmosphere, and then the mixture of nitrogen and oxygen was Heat treatment at 370°C for 1 hour in a mixed gas atmosphere (nitrogen gas flow rate: oxygen gas flow rate = 1:1) Sample F2 and sample G2 were heated at 370°C for 2 hours under a nitrogen atmosphere. Sample F3 and sample G3 were heated with nitrogen and oxygen. Heating at 370°C for 2 hours under a mixed gas atmosphere (nitrogen gas flow rate: oxygen gas flow rate = 1:1) Sample F4 and sample G4 were treated at 370 The mixture was then heated at ℃ for 2 hours.

[0563] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0564] Next, a second silicon oxynitride film having a thickness of 5 nm is formed as a second gate insulating layer, and a second silicon oxynitride film having a thickness of 1 nm is formed as a second gate insulating layer. A third silicon oxynitride film having a thickness of 25 nm and a fourth silicon oxynitride film having a thickness of 10 nm were then formed. The second gate insulating layer was formed by plasma CVD, and the substrate temperature during film formation was The temperature was set to 350°C.

[0565] The second silicon oxynitride film was formed under the film forming conditions 1 shown in Example 2, and the third silicon oxynitride film was formed under the film forming conditions 1 shown in Example 2. The silicon film was formed under film formation condition 2, and the fourth silicon oxynitride film was formed under film formation condition 3. Ta.

[0566] Next, the sample was heated at 370°C for 1 hour in a nitrogen atmosphere. The device was used.

[0567] Subsequently, a second metal oxide film having a thickness of 20 nm is formed on the fourth silicon oxynitride film. The second metal oxide film was formed using an In-Ga-Zn oxide target (In:Ga:Z n = 4:2:4.1 [atomic ratio]) at a pressure of 0.6 Pa. The power supply was 2.5 kW. The substrate temperature during film formation was 200°C. Oxygen gas (oxygen flow rate ratio 100%) was used.

[0568] Subsequently, a 50 nm thick molybdenum film and a 200 nm thick SiO 2 film are formed on the second metal oxide film. An aluminum film and a 50 nm thick titanium film were deposited in this order. The aluminum film and titanium film were formed by sputtering.

[0569] The aluminum film used in this example was formed by sputtering using an Al target. The deposition was carried out under the conditions of a pressure of 0.3 Pa and a power supply of 10 kW (DC). The temperature was set at 70°C. Argon gas was used as the deposition gas. As for the membrane, the description in the above-mentioned Example 1 can be referred to, and therefore a detailed description thereof will be omitted.

[0570] Next, a resist mask is formed on the titanium film, and a second metal oxide film, a molybdenum film, The aluminum film and titanium film are processed, and a second metal oxide layer, a molybdenum layer, and an aluminum The aluminum layer and titanium layer were formed. The processing was performed using wet etching. For details, the description in the first embodiment can be referred to, and therefore a detailed description will be omitted.

[0571] Next, the second silicon oxynitride film is etched using the resist mask. The second gate insulating layer was formed by etching. The resist mask was removed.

[0572] Next, a fourth silicon nitride film with a thickness of 100 nm is deposited as a protective layer covering the transistor. A third silicon oxynitride film having a thickness of 300 nm was then deposited in this order. The silicon oxide nitride film and the third silicon oxynitride film were formed by plasma CVD. The substrate temperature during film formation was The temperature was set to 350°C.

[0573] Next, a part of the protective layer covering the transistor is opened and a 100 nm thick molybdenum film is After forming the film by sputtering, it was processed to obtain the source electrode and the drain electrode. After that, an acrylic resin film with a thickness of about 1.5 μm was formed as a flattening layer, and then, under a nitrogen atmosphere, The heat treatment was carried out at a temperature of 250°C for 1 hour.

[0574] Through the above steps, a transistor formed on a glass substrate was obtained.

[0575] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistor fabricated above were measured.

[0576] The measurement conditions for the Id-Vg characteristics of the transistor are as follows: (hereinafter also referred to as gate voltage (Vg)), and the voltage applied to the second gate electrode (Vbg ) was applied from -15V to +20V in 0.25V steps. The voltage applied to the source electrode (hereinafter referred to as source voltage (Vs)) is set to 0 V (common). The voltage applied to the drain electrode (hereinafter referred to as drain voltage (Vd)) is set to 0.1 V and 5.1V.

[0577] The Id-Vg characteristics of the transistors in samples F1 to F4 are FIG. 35 shows the Id-Vg of the transistors in samples G1 to G4. The characteristics are shown in Fig. 36. In Fig. 35 and Fig. 36, the heating after the first metal oxide film formation in the lateral direction The processing conditions are shown. Also, the conditions for different channel lengths of the transistors in the vertical direction are shown. The channel lengths are 2 μm, 3 μm, and 6 μm, and the channel width is 50 μm. 35 and 36, the horizontal axis represents the gate voltage ( The left vertical axis shows the drain current (Id) and the right vertical axis shows the drain current (Id) at Vd=5.1V. 35 and 36, the horizontal axis is shown on a linear scale. The left end is Vg=-15V and the right end is Vg=20V. The vertical axis on the left is a logarithmic scale. The lower end is Id=1×10 -12 A, and the upper limit is Id=1×10 -2 A The vertical axis on the right is a linear scale, with the bottom end at μFE=0 cm 2 / Vs, The upper end is μFE=100cm 2 / Vs. For each sample, 20 transistors were The Id-Vg characteristics of the capacitor were measured.

[0578] As shown in Figures 35 and 36, good electrical properties were obtained in all samples. Done.

[0579] <Transistor reliability> Next, the reliability of the transistor fabricated above was evaluated.

[0580] A gate bias stress test (GBT test) was conducted as a reliability evaluation. The substrate on which the transistor is formed is kept at 60°C, and 0 A voltage of 0.1 V was applied to the electrode and 20 V to the gate, and this state was maintained for 1 hour. The boundary was kept dark.

[0581] The change in threshold voltage (ΔVth) was evaluated before and after the gate bias stress test. For a transistor with a channel length of 3 μm and a channel width of 50 μm, e. The fluctuation value (ΔVth) of the threshold voltage of sample F1 to sample F4 is shown in FIG. , the fluctuation value (ΔVth) of the threshold voltage of sample G1 to sample G4 is shown. 37(B).

[0582] As shown in Figures 37(A) and 37(B), the threshold voltage of the fabricated transistor It was confirmed that the fluctuations were extremely small.

[0583] From the above, it can be seen that the transistor of one embodiment of the present invention has favorable electrical characteristics and high reliability. I was able to confirm that I was prepared. [Explanation of symbols]

[0584] 100: Transistor, 100A: Transistor, 100B: Transistor, 100C: Transistor, 100D: Transistor, 100E: Transistor, 102: Substrate, 10 3: insulating layer, 106: conductive layer, 108: semiconductor layer, 108L: region, 108N: region, 1 10: insulating layer, 110a: insulating layer, 110b: insulating layer, 110c: insulating layer, 110f: insulating layer Membrane, 112: Conductive layer, 112f: Conductive film, 113: Functional layer, 113f: Functional film, 114 : metal oxide layer, 114f: metal oxide film, 115: resist mask, 116: insulating layer, 118: insulating layer, 120a: conductive layer, 120b: conductive layer, 141a: opening, 141b: Opening, 142: Opening, 200: Glass substrate, 210: Insulating film, 210A: Silicon oxide nitride silicon film, 210B: silicon oxynitride film, 210C: silicon oxynitride film, 212: copper Membrane, 213: ITSO membrane, 214: Metal oxide membrane

Claims

[Claim 1] A transistor is included. the transistor includes a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer; the first insulating layer is located on the semiconductor layer; the metal oxide layer is located on the first insulating layer; the functional layer is located on the metal oxide layer; the conductive layer is located on the functional layer; the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have overlapping regions; in a channel length direction of the transistor, ends of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are located inside an end of the semiconductor layer; A semiconductor device, wherein the etching rate of the functional layer in one etchant is slower than the etching rate of the conductive layer.

Images