Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of forming a suitable plug, and the manufacturing method thereof.SOLUTION: According to an embodiment, a semiconductor device comprises a first insulating film, a first plug provided in the first insulating film, and a first wiring layer provided on the first insulating film. The device further comprises a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface. In addition, the device comprises a second wiring layer including a first portion provided on the first insulating film and the first plug, a second portion provided on the first region, a third portion provided on the second region, and a bonding pad.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] When a wiring layer including a bonding pad is disposed on a plug, problems may occur in the plug after the wiring layer is formed. For example, the plug may be damaged when a probe needle is applied to the bonding pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. US2021 / 0217768 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of forming a suitable plug and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a first insulating film, a first plug provided in the first insulating film, and a first wiring layer provided on the first insulating film. The device further includes a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface. The device further includes a second wiring layer including a first portion provided on the first insulating film and the first plug, a second portion provided on the first region, and a third portion provided on the second region, and including a bonding pad. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is an enlarged cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 4 is a cross-sectional view (1 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (2 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 4 is a cross-sectional view (3 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 4 is a cross-sectional view (4 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 8] 3 is a cross-sectional view (1 / 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 4 is a cross-sectional view (2 / 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 3 is a cross-sectional view (3 / 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 10 is a cross-sectional view (1 / 2) illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment. [Figure 12] 10 is a cross-sectional view (2 / 2) illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment. [Figure 13] 10 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. [Figure 14] 10 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a first modified example of the first embodiment. FIG. [Figure 15] 1 is a plan view showing the structure of a semiconductor device according to a first embodiment. [Figure 16] 1A to 1C are plan views (1 / 3) showing various examples of the structure of the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are plan views (2 / 3) showing various examples of the structure of the semiconductor device according to the first embodiment. [Figure 18]3A to 3C are plan views (3 / 3) showing various examples of the structure of the semiconductor device according to the first embodiment. [Figure 19] 4 is a cross-sectional view (1 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 4 is a cross-sectional view (2 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] 4 is a cross-sectional view (3 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 4 is a cross-sectional view (4 / 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 23] 5A to 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment. [Figure 24] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 25] 4 is a cross-sectional view (1 / 2) showing a first example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 26] 4 is a cross-sectional view (2 / 2) showing a first example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 27] 10 is a cross-sectional view (1 / 2) showing a second example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 28] 10 is a cross-sectional view (2 / 2) showing a second example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 29] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment. [Figure 30] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third modified example of the first embodiment. [Figure 31] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fourth modified example of the first embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fifth modified example of the first embodiment. [Figure 33] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a sixth modified example of the first embodiment. [Figure 34] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the first embodiment. [Figure 35]FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the first embodiment. [Figure 36] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the first embodiment. [Figure 37] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. [Figure 38] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device of a first comparative example of the second embodiment. [Figure 39] 10 is a cross-sectional view for comparing the semiconductor device of the second embodiment with a semiconductor device of a first comparative example of the second embodiment. FIG. [Figure 40] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first modified example of the second embodiment. [Figure 41] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a second modification of the second embodiment. [Figure 42] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a third modified example of the second embodiment. [Figure 43] 10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fourth modified example of the second embodiment. [Figure 44] 10A to 10C are cross-sectional views showing the structures of semiconductor devices according to fifth and sixth modifications of the second embodiment. [Figure 45] 13A and 13B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a seventh modified example of the second embodiment. [Figure 46] 13A and 13B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to an eighth modified example of the second embodiment. [Figure 47] 13A and 13B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a ninth modified example of the second embodiment. [Figure 48] 13A and 13B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a tenth modification of the second embodiment. [Figure 49] 13A to 13C are cross-sectional views showing the structures of semiconductor devices according to eleventh and twelfth modifications of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 49, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0009] The semiconductor device of this embodiment includes, for example, a three-dimensional semiconductor memory. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer including an array chip 1 and a circuit wafer including a circuit chip 2 together.

[0010] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, and an interlayer insulating film 12 below the memory cell array 11. The interlayer insulating film 12 is, for example, a stacked film including an SiO2 film (silicon oxide film) and other insulating films. The interlayer insulating film 12 is an example of a first insulating film.

[0011] The circuit chip 2 is provided below the array chip 1. FIG. 1 shows the bonding surface S between the array chip 1 and the circuit chip 2. The circuit chip 2 includes an interlayer insulating film 13 below the interlayer insulating film 12, and a substrate 14 below the interlayer insulating film 13. The interlayer insulating film 13 is, for example, a laminated film including an SiO2 film and other insulating films. The substrate 14 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The substrate 14 is an example of a first substrate.

[0012] 1 shows an X direction and a Y direction that are parallel to the surface of the substrate 14 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate 14. The X direction, the Y direction, and the Z direction intersect with each other. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity.

[0013] The array chip 1 includes a plurality of word lines WL, source side select lines SGS, and drain side select lines SGD as electrode layers in a memory cell array 11. The source side select lines SGS are arranged above the word lines WL, and the drain side select lines SGD are arranged below the word lines WL. The memory cell array 11 includes a plurality of pillars CL that penetrate the word lines WL, source side select lines SGS, and drain side select lines SGD. These pillars CL extend in the Z direction.

[0014] FIG. 1 shows a staircase structure 21 in a memory cell array 11 and a plurality of beams 22 provided in the staircase structure 21. These beams 22 extend in the Z direction. Each word line WL is electrically connected to a word wiring layer 24 via a contact plug 23. Each columnar portion CL is electrically connected to a bit line BL via a via plug 25 and is also electrically connected to a source line SL. The source line SL is provided above the source-side select line SGS, and the bit line BL is provided below the drain-side select line SGD. The source line SL is provided on each columnar portion CL so as to contact the columnar portion CL. The source line SL is part of the memory cell array 11.

[0015] The circuit chip 2 further includes a plurality of transistors 31 , a plurality of contact plugs 32 , a wiring layer 33 , a wiring layer 34 , a wiring layer 35 , a plurality of via plugs 36 , and a plurality of metal pads 37 in the interlayer insulating film 13 .

[0016] Each transistor 31 includes a gate insulating film 31a and a gate electrode 31b provided in this order on the substrate 14, and a source region and a drain region (not shown) provided within the substrate 14. Each contact plug 32 is provided on the gate electrode 31b, the source region, or the drain region of the corresponding transistor 31. A wiring layer 33 is provided on the contact plug 32 and includes multiple wirings. A wiring layer 34 is provided on the wiring layer 33 and includes multiple wirings. A wiring layer 35 is provided on the wiring layer 34 and includes multiple wirings. A via plug 36 is provided on the wiring layer 35. A metal pad 37 is provided on the via plug 36. The metal pad 37 is, for example, a metal layer including a Cu (copper) layer. The circuit chip 2 functions as a circuit that controls the operation of the array chip 1. This circuit is composed of the transistor 31 and other components and is electrically connected to the metal pad 37.

[0017] The array chip 1 further includes a plurality of metal pads 41, a plurality of via plugs 42, a wiring layer 43, a wiring layer 44, and a plurality of via plugs 45 in the interlayer insulating film 12. The via plugs 45 are examples of the first and second plugs.

[0018] The metal pad 41 is provided on the metal pad 37. The metal pad 41 is, for example, a metal layer including a Cu layer. The above circuit is electrically connected to the memory cell array 11 via the metal pads 37, 41, etc., and controls the operation of the memory cell array 11 via the metal pads 37, 41, etc. The via plug 42 is provided on the metal pad 41. The wiring layer 43 is provided on the via plug 42 and includes a plurality of wirings. The wiring layer 44 is provided on the wiring layer 43 and includes a plurality of wirings. The above bit line BL is included in the wiring layer 44. The via plug 45 is provided on the wiring layer 44. The via plug 45 is, for example, a metal plug including a W (tungsten) layer.

[0019] The array chip 1 further includes a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, a passivation insulating film 55, solder 56, and a bonding wire 57 on the interlayer insulating film 12. The wiring layer 51 is an example of a first wiring layer. The insulating film 53 is an example of a second insulating film. The wiring layer 54 is an example of a second wiring layer.

[0020] The wiring layer 51 is disposed on the interlayer insulating film 12 and above the source-side select line SGS. The wiring layer 51 is, for example, a metal layer including a W layer. The wiring layer 51 includes a plurality of wirings such as the wiring 51a. The wiring 51a is provided on the plurality of columnar portions CL and is electrically connected to these columnar portions CL. The wiring 51a is the source line SL. At least a portion of the wiring layer 51 may be a semiconductor layer such as a polysilicon layer.

[0021] The insulating film 52 is formed on the wiring layer 51. The insulating film 52 is, for example, a laminated film including a plurality of insulating films.

[0022] The insulating film 53 is formed on the interlayer insulating film 12, the wiring layer 51, and the insulating film 52. The insulating film 53 is, for example, a SiO2 film.

[0023] The wiring layer 54 is formed on the interlayer insulating film 12 via a wiring layer 51, an insulating film 52, and an insulating film 53. The wiring layer 54 is, for example, a metal layer including an Al (aluminum) layer. The wiring layer 54 includes a plurality of wirings such as wiring 54a. The wiring 54a is disposed on the interlayer insulating film 12, the via plug 45, and the insulating film 53, and is electrically connected to the via plug 45. A portion of the wiring 54a functions as an external connection pad (bonding pad) of the semiconductor device of this embodiment.

[0024] The passivation insulating film 55 is formed on the insulating film 53 and the wiring layer 54, and has an opening P that exposes the surface of the wiring 54a. The portion of the wiring 54a exposed in the opening P functions as the external connection pad. The wiring 54a can be connected to a mounting substrate or other devices via a bonding wire, a solder ball, a metal bump, or the like through the opening P. FIG. 1 shows a bonding wire 57 electrically connected to the wiring 54a (bonding pad) by solder 56. The passivation insulating film 55 is, for example, a laminated film including an SiO2 film and an SiN (silicon nitride) film.

[0025] FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0026] FIG. 2 shows the memory cell array 11 shown in FIG. 1. The memory cell array 11 includes a stacked film 61 including multiple electrode layers 61a and multiple insulating films 61b alternately stacked in the Z direction. These electrode layers 61a are spaced apart from one another in the Z direction. Each electrode layer 61a functions, for example, as the word line WL, source-side select line SGS, or drain-side select line SGD. In FIG. 2, the top electrode layer 61a functions as the source-side select line SGS, the bottom electrode layer 61a functions as the drain-side select line SGD, and the other electrode layers 61a function as word lines WL. Each electrode layer 61a is, for example, a metal layer including a W layer. Each insulating film 61b is, for example, a SiO2 film.

[0027] 2 further shows one of the plurality of pillar-shaped portions CL shown in FIG. 1. Each pillar-shaped portion CL is provided in a stacked film 61 and has a pillar-shaped shape extending in the Z direction. Each pillar-shaped portion CL includes a block insulating film 62 provided on a side surface of the stacked film 61, a charge storage layer 63 provided on a side surface of the block insulating film 62, a tunnel insulating film 64 provided on a side surface of the charge storage layer 63, a channel semiconductor layer 65 provided on a side surface of the tunnel insulating film 64, and a core insulating film 66 provided on a side surface of the channel semiconductor layer 65. Each pillar-shaped portion CL constitutes a cell transistor (memory cell) together with a word line WL, a source-side select transistor together with a source-side select line SGS, and a drain-side select transistor together with a drain-side select line SGD.

[0028] The block insulating film 62 is, for example, an SiO2 film. The charge storage layer 63 is, for example, an insulating film such as an SiN film. The charge storage layer 63 may be a semiconductor layer such as a polysilicon layer. The charge storage layer 63 is capable of storing signal charges of the three-dimensional semiconductor memory. The tunnel insulating film 64 is, for example, an SiO2 film or an SiON film (silicon oxynitride film). The channel semiconductor layer 65 is, for example, a polysilicon layer. The channel semiconductor layer 65 functions as a channel of the three-dimensional semiconductor memory. The core insulating film 66 is, for example, an SiO2 film.

[0029] 3 to 6 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0030] 3 shows an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2. The orientation of the array wafer W1 in FIG. 3 is opposite to the orientation of the array chip 1 in FIG. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. FIG. 3 shows the array wafer W1 before its orientation is reversed for bonding, and FIG. 1 shows the array chip 1 after its orientation is reversed for bonding, bonding, and dicing.

[0031] 3 further shows the top surface S1 of the array wafer W1 and the top surface S2 of the circuit wafer W2. The array wafer W1 includes a substrate 15 below the memory cell array 11. The substrate 15 is, for example, a semiconductor substrate such as a Si substrate.

[0032] In this embodiment, first, as shown in FIG. 3, the memory cell array 11, interlayer insulating film 12, staircase structure 21, metal pads 41, via plugs 45, etc. are formed on the substrate 15 of the array wafer W1, and then the interlayer insulating film 13, transistors 31, contact plugs 32, metal pads 37, etc. are formed on the substrate 14 of the circuit wafer W2. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the upper surface S1 and the upper surface S2 face each other. This bonds the interlayer insulating film 12 and the interlayer insulating film 13. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pads 41 and the metal pads 37. In this way, the substrate 15 and the substrate 14 are bonded together with the interlayer insulating films 12 and 13 sandwiched therebetween, and the memory cell array 11, via plugs 45, etc. are formed (arranged) above the substrate 14.

[0033] Next, the substrate 15 is removed by CMP (Chemical Mechanical Polishing) or wet etching, and the substrate 14 is thinned by CMP or wet etching (FIG. 5), thereby exposing the interlayer insulating film 12, the columnar portions CL, the beam portions 22, the via plugs 45, and the like.

[0034] Next, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed in this order on the interlayer insulating film 12, the columnar portions CL, the beam portions 22, and the via plugs 45 (FIG. 6). The wiring 51a (source lines SL) in the wiring layer 51 are formed in the columnar portions CL and the beam portions 22. The wiring 54a in the wiring layer 54 is formed on the interlayer insulating film 12, the via plugs 45, and the insulating film 53, and is exposed in the openings P of the passivation insulating film 55. Next, after the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips, bonding wires 57 are electrically connected to the wiring 54a (bonding pads) by solder 56 (FIG. 6). In this manner, the semiconductor device shown in FIG. 1 is manufactured.

[0035] 1 shows the boundary surface between interlayer insulating film 12 and interlayer insulating film 13 and the boundary surface between metal pad 41 and metal pad 37, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of metal pad 41 or the side surface of metal pad 37, or the positional deviation between the side surface of metal pad 41 and the side surface of metal pad 37.

[0036] FIG. 7 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0037] Fig. 7 shows an enlarged view of a portion of Fig. 1. Specifically, Fig. 7 shows the interlayer insulating film 12, the wiring layer 51, the insulating film 52, the insulating film 53, the wiring layer 54, the passivation insulating film 55, the solder 56, and the bonding wire 57.

[0038] The wiring layer 51 and the insulating film 52 are formed in this order on the interlayer insulating film 12. The insulating film 52 includes an insulating film 71 formed on the wiring layer 51, an insulating film 72 formed on the insulating film 71, and an insulating film 73 formed on the insulating film 72.

[0039] The insulating film 53 includes a region A1 formed on the wiring layer 51 via the insulating film 52, a region A2 formed on the side surfaces of the wiring layer 51 and the insulating film 52, and a region A3 formed on the interlayer insulating film 12. As described below, the insulating film 53 is formed on the interlayer insulating film 12, the wiring layer 51, and the insulating film 52 after the wiring layer 51 and the insulating film 52 are formed on the interlayer insulating film 12 and portions of the wiring layer 51 and the insulating film 52 are removed by etching. Therefore, the insulating film 53 includes not only the region A1 but also the regions A2 and A3. The upper surface of the region A1 is higher than the upper surface of the region A3. The region A3 is an example of a first region having a first upper surface. The region A1 is an example of a second region having a second upper surface.

[0040] The wiring layer 54 is formed on the interlayer insulating film 12 via the wiring layer 51, the insulating film 52, and the insulating film 53. As will be described later, the wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45, and the insulating film 53 after forming the insulating film 53 and removing a portion of the insulating film 53 by etching. Therefore, the wiring 54a shown in FIG. 7 includes a portion formed on the interlayer insulating film 12 and the via plug 45, a portion formed on the region A3 of the insulating film 53, and a portion formed on the region A1 of the insulating film 53. The portion on the interlayer insulating film 12 and the via plug 45 is an example of a first portion. The portion on the region A3 of the insulating film 53 is an example of a second portion. The portion on the region A1 of the insulating film 53 is an example of a third portion. In FIG. 7, the top surface of the second portion is higher than the top surface of the first portion, and the top surface of the third portion is higher than the top surface of the second portion.

[0041] The portions of the wiring 54a on the interlayer insulating film 12 and the via plugs 45 include a portion B1 provided on the interlayer insulating film 12 and a plurality of portions B2 protruding downward from the portion B1. Each portion B2 is provided on a corresponding via plug 45. In FIG. 7, the left portion B2 is provided on the left via plug 45, and the right portion B2 is provided on the right via plug 45, and these portions B2 are separated from each other. The height of the upper end (upper surface) of each via plug 45, i.e., the height of the lower surface of each portion B2, is lower than the height of the lower surface of portion B1. The portion B1 is an example of an upper portion. The portion B2 is an example of a lower portion (first and second lower portions). In FIG. 7, each portion B2 is provided on a corresponding via plug 45 and on the interlayer insulating film 12 around this via plug 45.

[0042] In FIG. 7, a probe mark C is formed on the wiring 54a (bonding pad). The probe mark C shown in FIG. 7 is formed at the boundary between a portion of the wiring 54a on the interlayer insulating film 12 (first portion) and a portion on the region A3 (second portion). As will be described later, the probe mark C is formed when a probe needle is applied to the bonding pad to inspect the semiconductor device of this embodiment. The first and second portions of the wiring 54a may be separated by the probe mark C, or may be connected to each other at a portion other than the probe mark C. When the first and second portions are separated by the probe mark C, the first and second portions are electrically connected to each other by solder 56.

[0043] In this embodiment, openings are formed in the wiring layer 51 and the insulating film 52, and a portion of the insulating film 53 is formed in the openings. FIG. 7 shows a region BA in which the openings are formed. Because the insulating film 53 has a recessed shape in the region BA, the wiring layer 54 has a recessed shape in the region TV. In this embodiment, openings are also formed in the insulating film 53, and a portion of the wiring layer 54 is formed in the openings. FIG. 7 shows a region VA in which the openings are formed. Regions A3 and the like of the insulating film 53 are included in the region BA, a second portion and the like of the wiring layer 54 are included in the region TV, and a first portion and the like of the wiring layer 54 are included in the region VA. Further details of the regions BA, TV, and VA will be described later.

[0044] 8 to 10 are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment, illustrating the steps for forming the structure shown in FIG.

[0045] First, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed on the interlayer insulating film 12 (FIG. 8). Next, a probe needle 74 is applied to the wiring 54a (bonding pad) to inspect the semiconductor device of this embodiment (FIG. 9). As a result, the wiring 54a in the region R is pressed by the probe needle 74, and a probe mark C is formed on the wiring 54a (FIG. 10). Thereafter, a bonding wire 57 is electrically connected to the wiring 54a by solder 56.

[0046] 9 shows the width PR of the probe needle 74 in the X direction. In this embodiment, the width PR of the probe needle 74 is shorter than the width of the opening P of the passivation insulating film 55 in the X direction. This makes it possible to insert the probe needle 74 into the opening P. In this embodiment, the width PR of the probe needle 74 is also longer than the width of the portions B1 and B2 (first portions) of the wiring 54a in the X direction. This makes it possible to effectively protect the portions B1 and B2 from the probe needle 74 (details will be described later). In FIG. 9, the width of the portions B1 and B2 in the X direction is the width of the top surface of the portion B1 in the X direction.

[0047] The width PR of the probe needle 74 is, for example, 10 μm or more. In this embodiment, the width PR is 10 μm or more and 20 μm or less, for example, 12 μm to 20 μm. On the other hand, the width in the X direction of the portions B1 and B2 of the wiring 54a is, for example, less than 10 μm.

[0048] Next, the semiconductor device of the first embodiment and the semiconductor device of the first comparative example of the first embodiment will be compared.

[0049] 11 and 12 are cross-sectional views showing a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment, which correspond to FIGS. 8 and 9, respectively.

[0050] First, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed on the interlayer insulating film 12 (FIG. 11). The insulating film 53 of this comparative example has regions A1 and A2, but does not have region A3. Also, in this comparative example, the wiring 54a has portion B1 but does not have portion B2, and the height of the upper end of each via plug 45 is higher than the height of the lower surface of portion B1. Therefore, the upper part of each via plug 45 protrudes into the interior of the wiring 54a.

[0051] Next, the semiconductor device of this comparative example is inspected by applying a probe needle 74 to the wiring 54a (bonding pad) (FIG. 12). At this time, the pressure from the probe needle 74 may damage the via plug 45. For example, as shown by arrow D1, a crack may occur in the via plug 45, or the upper part of the via plug 45 may be chipped as shown by arrow D2.

[0052] On the other hand, the insulating film 53 of this embodiment has regions A1 to A3 (FIG. 8). Also, in this embodiment, the wiring 54a has portions B1 and B2, and the height of the upper end of each via plug 45 is lower than the height of the lower surface of portion B1 (FIG. 8). This makes it possible to prevent cracks from occurring in the via plugs 45 and damage to the upper portions of the via plugs 45 (FIG. 9). The first reason is that the region A3 can prevent the probe needle 74 from getting too close to the via plug 45. The second reason is that the upper portions of the via plugs 45 are less likely to be damaged because they do not protrude into the wiring 54a.

[0053] As described above, in this embodiment, the width PR of the probe needle 74 in the X direction is longer than the width of the portions B1 and B2 of the wiring 54a in the X direction. As a result, when the probe needle 74 approaches the via plug 45, the lower surface of the probe needle 74 hits the upper surface of the region A3. This makes it possible for the region A3 to prevent the probe needle 74 from getting too close to the via plug 45. Because the width PR of the probe needle 74 is longer than the width of the portions B1 and B2, even if the position of the probe needle 74 is shifted in the X direction, the probe needle 74 will hit the region A3.

[0054] Figures 13 and 14 are cross-sectional views showing a method for manufacturing a semiconductor device according to a first modification of the first embodiment. Figures 11 and 12 correspond to Figures 8 and 9, respectively.

[0055] First, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, and a passivation insulating film 55 are formed on the interlayer insulating film 12 (FIG. 13). The insulating film 53 of this modification has regions A1 to A3. This is similar to the first embodiment. On the other hand, in this modification, the wiring 54a has a portion B1 but does not have a portion B2, and the height of the upper end of each via plug 45 is higher than the height of the lower surface of portion B1. Therefore, the upper part of each via plug 45 protrudes into the interior of the wiring 54a. This is similar to the first comparative example.

[0056] According to this modification, it is possible to prevent cracks from occurring in the via plug 45 and damage to the upper portion of the via plug 45 (FIG. 14). This is because the region A3 can prevent the probe needle 74 from coming too close to the via plug 45. This is the same as in the first embodiment.

[0057] On the other hand, according to the first embodiment, it is possible to further suppress the occurrence of cracks in the via plug 45 and the damage to the upper portion of the via plug 45 (FIG. 9). This is because the upper portion of the via plug 45 does not protrude into the wiring 54a, and therefore the upper portion of the via plug 45 is less likely to be damaged.

[0058] [Planar structure of the semiconductor device according to the first embodiment] FIG. 15 is a plan view showing the structure of the semiconductor device of the first embodiment.

[0059] 15 shows the region TV and region VA shown in FIG. 7, and a plurality of via plugs 45 provided under the region VA. The shape of the region TV is generally square, but may be other shapes (e.g., rectangular). Similarly, the shape of the region VA is a rectangle extending in the Y direction, but may be other shapes (e.g., square). The region VA shown in FIG. 15 is located within the region TV.

[0060] In Fig. 15, the number of via plugs 45 is 45 (=3 × 15), but a different number may be used. Since Fig. 7 is an XZ cross-sectional view of the plan view of Fig. 15, the number of via plugs 45 shown in Fig. 7 should be exactly three. However, for convenience of drawing, Fig. 7 shows only two via plugs 45.

[0061] 16 to 18 are plan views showing various examples of the structure of the semiconductor device according to the first embodiment.

[0062] Fig. 16(a) shows the region TV and the region VA provided within the region TV, similar to Fig. 15. However, Fig. 16(a) does not show the via plug 45 provided below the region VA (the same applies below).

[0063] Each of Figures 16(b) to 16(d) shows an area TV and an area VA provided within the area TV, similar to Figure 16(a). However, the area VA in Figure 16(a) is located near the center of the area TV, whereas the area VA in Figure 16(b) is located near the edge of the area TV. The area VA in Figure 16(c) is located outside the area TV. The area VA in Figure 16(d) is located so as to partially overlap with the area TV. Therefore, part of the area VA in Figure 16(d) is located within the area TV, and the rest of the area VA in Figure 16(d) is located outside the area TV.

[0064] 17(a) to 17(d) each show an area TV and a plurality of areas VA provided within the area TV. Each area VA is arranged within the area TV, outside the area TV, or so as to partially overlap the area TV.

[0065] Each of Figures 18(a) to 18(d) shows an area TV and one or more areas VA provided within the area TV. These areas VA have various shapes. For example, the area VA in Figure 18(c) has a shape formed by combining three rectangles. The area VA in Figure 18(d) has a shape formed by combining four rectangles, and has a ring shape.

[0066] [Method for manufacturing the semiconductor device according to the first embodiment] 19 to 22 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment. Figures 19(a) to 22(b) show details of the step shown in Figure 8.

[0067] First, the wiring layer 51 and the insulating film 52 are formed in this order on the interlayer insulating film 12 and the via plug 45 (FIG. 19(a)). The insulating film 52 is formed by forming insulating films 71, 72, and 73 in this order on the wiring layer 51. The via plug 45 is formed in the interlayer insulating film 12 before the array wafer W1 and the circuit wafer W2 are bonded together (see FIG. 3). In FIG. 19(a), the height of the upper end of the via plug 45 is higher than the height of the upper surface of the interlayer insulating film 12 (the lower surface of the wiring layer 51).

[0068] Next, a recess H1 is formed in the insulating film 52 and the wiring layer 51 by lithography and RIE (Reactive Ion Etching) (FIG. 19(b)). As a result, the upper end of the via plug 45 is exposed in the recess H1. Furthermore, a wiring 51a (source line SL) is formed in the wiring layer 51. The shape of the above-mentioned region BA is determined by the shape of the recess H1. The recess H1 is an example of a first recess.

[0069] Next, an insulating film 53 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, and the insulating film 52 (FIG. 20(a)). As a result, the upper end of the via plug 45 is covered with the insulating film 53. The insulating film 53 is formed to include the regions A1, A2, and A3.

[0070] Next, a recess H2 is formed in the insulating film 53 by lithography and RIE (FIG. 20(b)). As a result, the upper end of the via plug 45 is exposed in the recess H2. Furthermore, the region A3 of the insulating film 53 is partially removed and processed into the shape shown in FIG. 7. The shape of the above-mentioned region VA is determined by the shape of the recess H2. The recess H2 is an example of a second recess.

[0071] Next, the exposed portions of the via plugs 45 in the recesses H2 and the exposed surface of the interlayer insulating film 12 are etched (FIG. 21(a)). As a result, the height of the upper ends of the via plugs 45 and the height of the upper surface of the interlayer insulating film 12 in the recesses H2 become lower than before etching. In this embodiment, the via plugs 45 outside the interlayer insulating film 12 are removed, and further, the via plugs 45 inside the interlayer insulating film 12 are also partially removed. As a result, recesses H3 are formed in the interlayer insulating film 12 near each via plug 45, and the upper ends of each via plug 45 are lowered to the bottom of the recesses H3. FIG. 21(a) shows a left recess H3 formed on the left via plug 45 and a right recess H3 formed on the right via plug 45. The recesses H3 are an example of a third recess. Further details of the process of FIG. 21(a) will be described later.

[0072] Next, a wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53, and the wiring layer 54 is processed by lithography and RIE (FIG. 21(b)). As a result, the upper end of the via plug 45 is covered with the wiring layer 54. The wiring layer 54 is formed and processed to include a wiring 54a. The wiring 54a shown in FIG. 21(b) includes a portion (first portion) formed on the interlayer insulating film 12 and the via plug 45, a portion (second portion) formed on region A3 of the insulating film 53, and a portion (third portion) formed on region A1 of the insulating film 53. The portion of the wiring 54a above the interlayer insulating film 12 and the via plug 45 includes a portion B1 provided on the interlayer insulating film 12 and a plurality of portions B2 protruding downward from portion B1. Portion B1 is formed in recess H2, and portion B2 is formed in recess H3.

[0073] Next, a passivation insulating film 55 is formed on the wiring layer 54 (FIG. 22(a)), and the passivation insulating film 55 is processed by lithography and RIE (FIG. 22(b)). As a result, an opening P is formed in the passivation insulating film 55, and the portion of the wiring 54a exposed in the opening P becomes a bonding pad.

[0074] Next, a comparison will be made between the method for manufacturing the semiconductor device of the first embodiment and the method for manufacturing the semiconductor device of the first comparative example of the first embodiment.

[0075] FIG. 23 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first comparative example of the first embodiment.

[0076] 23(a) corresponds to FIG. 20(b). In this comparative example, the exposed portions of the via plugs 45 in the recesses H2 and the exposed surface of the interlayer insulating film 12 are processed by etching (FIG. 23(b)). As a result, the height of the upper ends of the via plugs 45 and the height of the upper surface of the interlayer insulating film 12 in the recesses H2 become lower than before etching.

[0077] In FIG. 23(b), the lowering distance of the upper surface of the interlayer insulating film 12 is indicated by an arrow E1, and the lowering distance of the upper end of the via plug 45 is indicated by an arrow E2. The etching in this comparative example is performed so that the lowering distance E1 of the upper surface of the interlayer insulating film 12 and the lowering distance E2 of the upper end of the via plug 45 are approximately equal. Therefore, the height of the upper end of the via plug 45 in FIG. 23(b) is higher than the height of the upper surface of the interlayer insulating film 12 near the via plug 45, as in FIG. 23(a). Specifically, the difference in height between the upper end of the via plug 45 and the upper surface of the interlayer insulating film 12 near the via plug 45 is approximately the same in FIG. 23(a) and FIG. 23(b). The etching in this comparative example is, for example, RIE.

[0078] 24A to 24C are cross-sectional views illustrating a method for manufacturing the semiconductor device of the first embodiment.

[0079] Figure 24(a) corresponds to Figure 20(b). In this embodiment, the exposed portion of the via plug 45 in the recess H2 and the exposed surface of the interlayer insulating film 12 are processed by etching (Figure 24(b)). As a result, the height of the upper end of the via plug 45 and the height of the upper surface of the interlayer insulating film 12 in the recess H2 become lower than before etching. Figure 24(b) corresponds to Figure 21(a).

[0080] 24(b), the lowering distance of the upper surface of the interlayer insulating film 12 is indicated by an arrow E1, and the lowering distance of the upper end of the via plug 45 is indicated by an arrow E2. The etching in this embodiment is performed so that the lowering distance E2 of the upper end of the via plug 45 is larger than the lowering distance E1 of the upper surface of the interlayer insulating film 12. Therefore, the height of the upper end of the via plug 45 in FIG. 24(b) is lower than the height of the upper surface of the interlayer insulating film 12 near the via plug 45. An example of the etching in this embodiment will be described later.

[0081] 25 and 26 are cross-sectional views showing a first example of the method for manufacturing the semiconductor device according to the first embodiment.

[0082] FIG. 25(a) corresponds to FIG. 20(b). In this example, first, a sacrificial film 77 is formed on the interlayer insulating film 12, the via plugs 45, the wiring layer 51, the insulating film 52, and the insulating film 53 (FIG. 25(b)). The sacrificial film 77 is, for example, a metal film formed by PVD (Physical Vapor Deposition). The sacrificial film 77 is formed to include a portion 77a formed on the surfaces of the interlayer insulating film 12, the wiring layer 51, the insulating film 52, and the insulating film 53, and a portion 77b formed near the upper end of the via plugs 45. In FIG. 25(b), a part of each via plug 45 is exposed between the portion 77a and the portion 77b. The sacrificial film 77 is an example of a first film.

[0083] Next, the sacrificial film 77 and the via plugs 45 are processed by isotropic etching (FIG. 25(b)). This isotropic etching is performed by simultaneously introducing an etchant gas and an ion beam into a chamber accommodating the array wafer W1 and the circuit wafer W2. The ion beam is introduced into the chamber so as to travel in a direction tilted with respect to the surface (XY plane) of the substrate 14, as indicated by the arrow in FIG. 25(b). Therefore, the ion beam is incident on the exposed portion of each via plug 45 from an oblique direction (a direction tilted with respect to the XY plane). As a result, the exposed portion of each via plug 45 is etched laterally from the side surface of each via plug 45 by the ion beam. At this time, the sacrificial film 77 is also etched by the etchant gas and the ion beam. If the sacrificial film 77 remains after the isotropic etching is completed, the remaining sacrificial film 77 is removed.

[0084] FIG. 26(a) shows the array wafer W1 after isotropic etching has been completed. The isotropic etching is performed with the surface of the interlayer insulating film 12 covered with a sacrificial film 77. This allows the isotropic etching to be performed so that the lowering distance E2 of the upper ends of the via plugs 45 is greater than the lowering distance E1 of the upper surface of the interlayer insulating film 12 (see FIG. 24(b)). As a result, recesses H3 are formed in the interlayer insulating film 12 near each via plug 45, and the upper ends of each via plug 45 are lowered to the bottom of the recesses H3. FIG. 26(a) corresponds to FIG. 21(a).

[0085] Next, a wiring layer 54 is formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53, and the wiring layer 54 is processed by lithography and RIE (FIG. 26(b)). As a result, the upper end of the via plug 45 is covered with the wiring layer 54. FIG. 26(b) corresponds to FIG. 21(b).

[0086] 22(a) and 22(b) are then carried out, followed by the steps shown in Figures 9 and 10. As a result, a semiconductor device having the structure shown in Figure 7 is manufactured.

[0087] 27 and 28 are cross-sectional views showing a second example of the method for manufacturing the semiconductor device according to the first embodiment.

[0088] FIG. 27(a) corresponds to FIG. 20(b). In this example, first, an insulating film 78 is formed on the interlayer insulating film 12, the via plugs 45, the wiring layer 51, the insulating film 52, and the insulating film 53 (FIG. 27(b)). The insulating film 78 is, for example, a SiO2 film formed by CVD (Chemical Vapor Deposition). The insulating film 78 is formed so as to cover each via plug 45. Therefore, each via plug 45 shown in FIG. 27(b) is buried in the interlayer insulating film 12 and the insulating film 78. The insulating film 78 is an example of a third insulating film.

[0089] Next, the insulating film 78 is processed by RIE etch-back (FIG. 28(a)). As a result, the insulating film 78 is thinned by etching, and the upper end of each via plug 45 is exposed from the insulating film 78. Furthermore, a recess H3' is formed in the insulating film 78 near each via plug 45, and the upper end of each via plug 45 is lowered to the bottom of the recess H3'. In FIG. 28(a), the height of the upper end of each via plug 45 is lower than the height of the upper surface of the insulating film 78 outside the recess H3' and higher than the height of the upper surface of the interlayer insulating film 12 near each via plug 45. The recess H3' is an example of a fourth recess.

[0090] Next, a wiring layer 54 is formed on the via plug 45 and the insulating film 78, and the wiring layer 54 is processed by lithography and RIE (FIG. 28(b)). As a result, the upper end of the via plug 45 is covered with the wiring layer 54. The wiring layer 54 is formed and processed to include a wiring 54a. The wiring 54a shown in FIG. 28(b) is formed on the interlayer insulating film 12 via the insulating film 78, and includes a portion (first portion) formed on the via plug 45, a portion (second portion) formed on the region A3 of the insulating film 53 via the insulating film 78, and a portion (third portion) formed on the region A1 of the insulating film 53 via the insulating film 78. The first portion includes a portion B1 provided on the interlayer insulating film 12 via the insulating film 78 and a plurality of portions B2 protruding downward from the portion B1. In FIG. 28(b), the portion B1 is formed in the recess H2, and the portion B2 is formed in the recess H3'.

[0091] 22(a) and 22(b) are then carried out. Furthermore, the steps shown in Figures 9 and 10 are carried out. As a result, a semiconductor device is manufactured in which an insulating film 78 is added to the structure shown in Figure 7.

[0092] [Semiconductor device according to a modification of the first embodiment] FIG. 29 is a cross-sectional view showing the structure of a semiconductor device according to a second modification of the first embodiment.

[0093] The semiconductor device of this modification has the same structure as the semiconductor device shown in Fig. 7. However, the height of the upper end of the via plug 45 of this modification is higher than the height of the lower surface of the portion B1 of the wiring 54a. Therefore, the wiring 54a of this modification does not include the portion B2.

[0094] Moreover, the wiring layer 54 of this modification includes a metal layer 75 formed on the interlayer insulating film 12, the via plug 45, the wiring layer 51, the insulating film 52, and the insulating film 53, and a metal layer 76 formed on the metal layer 75. The metal layer 76 is formed of a material different from that of the metal layer 75. The metal layer 75 is, for example, a stacked film including a W layer, a TiN (titanium nitride) layer, and a Ti (titanium) layer. The metal layer 76 is, for example, an Al layer. The metal layers 75 and 76 are examples of the first and second layers, respectively.

[0095] According to this modification, it is possible to prevent cracks from occurring in the via plug 45 and damage to the upper portion of the via plug 45. The first reason is that the region A3 can prevent the probe needle 74 (see FIG. 9) from getting too close to the via plug 45. The second reason is that the upper portion of the via plug 45 is protected by the metal layer 75, making it difficult for the upper portion of the via plug 45 to be damaged. When the metal layer 75 includes a W layer, the W layer has a high Young's modulus, and therefore the upper portion of the via plug 45 can be effectively protected by the metal layer 75.

[0096] The semiconductor device of this modified example can be manufactured by the method shown in Figures 13 and 14. In the step shown in Figure 13, the wiring layer 54 is formed in a state where the upper end of the via plug 45 is higher than the bottom surface of the recess H2 (the upper surface of the interlayer insulating film 12 near the via plug 45). At this time, the wiring layer 54 of this modified example is formed by sequentially forming metal layers 75 and 76. This realizes the structure shown in Figure 29.

[0097] FIG. 30 is a cross-sectional view showing the structure of a semiconductor device according to a third modification of the first embodiment.

[0098] The semiconductor device of this modification has a similar structure to the semiconductor device of the second modification shown in Fig. 29. However, while the width in the X direction of portion B1 of wiring 54a of the second modification is shorter than the width PR in the X direction of probe needle 74 (see Fig. 9), the width in the X direction of portion B1 of wiring 54a of this modification is longer than the width PR in the X direction of probe needle 74. Region A3 of the second modification is arranged at a position that partially overlaps with opening P in plan view, but region A3 of this modification is arranged at a position that does not overlap with opening P in plan view.

[0099] According to the second modification, for the first and second reasons, it is possible to prevent cracks from occurring in the via plug 45 and damage to the upper part of the via plug 45. On the other hand, according to the present modification, for the second reason, it is possible to prevent cracks from occurring in the via plug 45 and damage to the upper part of the via plug 45.

[0100] FIG. 31 is a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the first embodiment.

[0101] The semiconductor device of this modified example has the same structure as the semiconductor device shown in Fig. 7. However, the wiring 54a of this modified example has one portion B2 on a plurality of via plugs 45. In other words, the portion B2 shown in Fig. 31 is shared by the left via plug 45 and the right via plug 45. According to the portion B2 of this modified example, it is possible to obtain the same effect as the portion B2 shown in Fig. 7.

[0102] FIG. 32 is a cross-sectional view showing the structure of a semiconductor device according to a fifth modification of the first embodiment.

[0103] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the second modification shown in Fig. 29. However, whereas the metal layer 75 of the second modification covers the upper portions of the via plugs 45 individually, the metal layer 75 of this modification collectively covers the upper portions of the via plugs 45. Therefore, while Fig. 29 shows two protruding portions of the metal layer 75, Fig. 32 shows one protruding portion of the metal layer 75. The wiring 54a of this modification can achieve the same effect as the wiring 54a of the second modification.

[0104] FIG. 33 is a cross-sectional view showing the structure of a semiconductor device according to a sixth modification of the first embodiment.

[0105] FIG. 33 shows an array region R1 and a pad region R2 included in the semiconductor device of this modified example. The array region R1 includes a memory cell array 11 (see FIG. 1), and the pad region R2 includes wiring 54a that functions as a bonding pad. The pad region R2 shown in FIG. 33 has a structure similar to the cross section shown in FIG. 7. However, the wiring 51a (source line SL) of this modified example is not arranged near the wiring 54a but is arranged within the array region R1. FIG. 33 shows a plurality of columnar portions CL arranged below the wiring 51a in the array region R1.

[0106] The wiring layer 54 of this modification includes a wiring 54a included in the pad region R2 and wirings 54b and 54c included in the array region R1. The wiring 54b is formed on the interlayer insulating film 12, the via plug 45, and the insulating film 53, and is electrically connected to the via plug 45. The wiring 54c is formed on the wiring 51a, the insulating film 52, and the insulating film 53, and is electrically connected to the wiring 51a.

[0107] The wiring 54b includes a portion B3 having a shape similar to that of the portion B1 of the wiring 54a and a portion B4 having a shape similar to that of the portion B2 of the wiring 54a. The portion B3 is provided on the interlayer insulating film 12. The portion B4 protrudes downward from the portion B3 and is provided on the via plug 45. However, the wiring 54b is not exposed in the opening P of the passivation insulating film 55 and does not function as a bonding pad.

[0108] According to the wiring 54a in the pad region R2 of this modification, it is possible to obtain the same effect as the wiring 54a shown in FIG.

[0109] FIG. 34 is a cross-sectional view showing the structure of a semiconductor device according to a seventh modification of the first embodiment.

[0110] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the sixth modification shown in Fig. 33. However, the wiring 54b of this modification has a structure that includes the portion B3 but does not include the portion B4. In other words, the wiring 54b of this modification has a structure similar to that of the wiring 54a shown in Fig. 13, which includes the portion B1 but does not include the portion B2.

[0111] In this modification, the wiring 54a functions as a bonding pad, but the wiring 54b does not function as a bonding pad. Therefore, the inspection shown in Fig. 9 is not performed on the wiring 54b. Therefore, the wiring 54b may be formed so as not to include the portion B4, as in this modification.

[0112] FIG. 35 is a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the first embodiment.

[0113] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the sixth modification shown in FIG. 33. However, the wiring layer 54 of this modification includes metal layers 75 and 76. In this modification, the wiring 54a includes the portion B1 but not the portion B2, and the wiring 54b includes the portion B3 but not the portion B4. In other words, the wirings 54a and 54b of this modification have a structure similar to that of the wiring 54a shown in FIG.

[0114] According to the wiring 54a in the pad region R2 of this modification, it is possible to obtain the same effect as the wiring 54a shown in FIG.

[0115] FIG. 36 is a cross-sectional view showing the structure of a semiconductor device according to a ninth modification of the first embodiment.

[0116] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the eighth modification shown in Fig. 35. However, the wiring layer 54 of this modification includes metal layers 75 and 76 in the pad region R2, but includes only the metal layer 76 in the array region R1. Thus, in this modification, the wiring 54a includes the metal layers 75 and 76, but the wirings 54b and 54c include only the metal layer 76.

[0117] In this modification, the wiring 54a functions as a bonding pad, but the wiring 54b does not function as a bonding pad. Therefore, the inspection shown in Fig. 9 is not performed on the wiring 54b. Therefore, the wiring 54b may be formed so as not to include the metal layer 75, as in this modification.

[0118] As described above, the semiconductor device of this embodiment includes the insulating film 53 having the regions A1 to A3, and the wiring layer 54 including the bonding pad and provided on the insulating film 53 and the via plug 45. Therefore, this embodiment makes it possible to form a suitable via plug 45. For example, it makes it possible to prevent damage to the via plug 45 when the probe needle 74 is brought into contact with the bonding pad.

[0119] (Second embodiment) FIG. 37 is a plan view and a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0120] The semiconductor device of this embodiment has a structure similar to that of the semiconductor device shown in Fig. 7. Fig. 37(a) shows a planar structure of the semiconductor device of this embodiment. Fig. 37(b) shows an XZ cross section taken along line XX' in Fig. 37(a). Fig. 37(c) shows a YZ cross section taken along line YY' in Fig. 37(a).

[0121] 37(b) and 37(c), the semiconductor device of this embodiment includes an interlayer insulating film 12, a plurality of via plugs 45, a wiring layer 51, an insulating film 52, an insulating film 53, a wiring layer 54, a passivation insulating film 55, solder 56, and a bonding wire 57. The passivation insulating film 55 includes an insulating film 81, an insulating film 82, and an insulating film 83 formed in this order on the insulating film 53 and the wiring layer 54.

[0122] 37(b) and 37(c), the wiring layer 54 includes a wiring 54a including a bonding pad, and the wiring layer 51 includes a wiring 51b different from the wiring 51a (source line SL). The wiring 51b is provided below the wiring 54a via insulating films 53 and 52 and is not in contact with the wiring 54a. FIG. 37(a) shows the planar shapes of the region TV, the region VA, the wiring 51a, and the wiring 54b.

[0123] As shown in FIGS. 37(a) to 37(c), the semiconductor device of this embodiment further includes a plurality of dummy plugs 45' arranged at the same height as the via plugs 45. Each via plug 45 functions as a control plug for the semiconductor device of this embodiment, whereas each dummy plug 45' does not function as a control plug for the semiconductor device of this embodiment. For example, each via plug 45 is used as a plug for supplying a power supply voltage or a signal voltage to devices such as the memory cell array 11 or the transistor 31 (see FIG. 1), or as a plug to which a signal voltage is supplied from the device, but each dummy plug 45' is not used as such a plug. In FIGS. 37(a) to 37(c), each dummy plug 45' is not electrically connected to devices or bonding pads within the semiconductor device of this embodiment. In FIGS. 37(a) to 37(c), in order to distinguish between the via plugs 45 and the dummy plugs 45', the via plugs 45 are indicated by sparse hatching and the dummy plugs 45' are indicated by dense hatching. The dummy plug 45' is an example of a third plug.

[0124] 37(b) and 37(c), a dummy plug 45' is provided on the underside of the wiring 51b in the interlayer insulating film 12 and is electrically connected to the wiring 51b. Like the dummy plug 45', the wiring 51b is not electrically connected to the devices or bonding pads in the semiconductor device of this embodiment. The dummy plug 45' of this embodiment is formed simultaneously with the via plug 45 using the same material as the via plug 45 in the process shown in FIG. 3. Therefore, the dummy plug 45' is, for example, a metal plug including a W layer, like the via plug 45. In this embodiment, each via plug 45 is disposed on the wiring layer 44, and each dummy plug 45' is not disposed on the wiring layer 44.

[0125] 37(a) shows the planar shapes of the via plug 45 and the dummy plug 45'. While the planar shape of the via plug 45 in the first embodiment is circular (see FIG. 15), the planar shapes of the via plug 45 and the dummy plug 45' in this embodiment are rectangular extending in the X direction. However, the via plug 45 and the dummy plug 45' in this embodiment may have other planar shapes.

[0126] FIG. 38 is a plan view and a cross-sectional view showing the structure of a semiconductor device of a first comparative example of the second embodiment.

[0127] Fig. 38(a) shows the planar structure of the semiconductor device of this comparative example. Fig. 38(b) shows an XZ cross section along line XX' shown in Fig. 38(a). Fig. 38(c) shows a YZ cross section along line YY' shown in Fig. 38(a).

[0128] The semiconductor device of this comparative example has a structure similar to that of the semiconductor device of the second embodiment. However, the semiconductor device of this comparative example does not include a dummy plug 45′ and a wiring 54b. Furthermore, the planar shape of the via plug 45 of this comparative example is circular.

[0129] FIG. 39 is a cross-sectional view for comparing the semiconductor device of the second embodiment with the semiconductor device of the first comparative example of the second embodiment.

[0130] FIG. 39(a), like FIG. 38(b), shows an XZ cross section of a semiconductor device according to a first comparative example of the second embodiment. FIG. 39(a) shows stress F1 applied to the wiring 54a within the region TV and stress F2 applied to the wiring 54a outside the region TV. The stress applied to the wiring 54a tends to concentrate in an area where a hard layer exists below the wiring 54a. The wiring 54a within the region TV is disposed on the via plug 45, which is a hard layer. Therefore, in FIG. 39(a), a large stress F1 is likely to be applied to the wiring 54a within the region TV. As a result, the via plug 45 may be damaged. A large stress is likely to be applied to the wiring 54a when a probe needle 74 is applied to the wiring 54a or when a bonding wire 57 is disposed on the wiring 54a.

[0131] On the other hand, FIG. 39(b) shows an XZ cross section of the semiconductor device of the second embodiment, similar to FIG. 37(b). FIG. 39(b) shows stress F3 applied to the wiring 54a in the region TV and stress F4 applied to the wiring 54a outside the region TV. In FIG. 39(b), the wiring 54a in the region TV is disposed on the via plug 45, which is a hard layer, and the wiring 54a outside the region TV is disposed above the wiring 51b and the dummy plug 45′, which are hard layers. Therefore, in FIG. 39(b), a large stress F3 is unlikely to be applied to the wiring 54a in the region TV. This is because the stress applied to the wiring 54a is dispersed into stress F3 and stress F4. This makes it possible to prevent damage to the via plug 45.

[0132] [Semiconductor device according to a modification of the second embodiment] 40A and 40B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a first modified example of the second embodiment. Fig. 40A shows the planar structure of the semiconductor device according to this modified example. Fig. 40B shows the YZ cross section along the YY' line shown in Fig. 40A.

[0133] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the second embodiment. However, the wiring layer 51 of this modification includes wiring 51b and wiring 51c provided on the underside of wiring 54a. The wirings 51b and 51c of this modification are in contact with and electrically connected to wiring 54a. Figure 40(b) shows a dummy plug 45' provided on the underside of wiring 51b and a dummy plug 45' provided on the underside of wiring 51c.

[0134] Each dummy plug 45' in the second embodiment is not electrically connected to a device or a bonding pad in the semiconductor device. On the other hand, each dummy plug 45' in this modification is electrically connected to a device or a bonding pad in the semiconductor device. This is because each dummy plug 45' in this modification is electrically connected to the wiring 54a (bonding pad) via the wirings 51b and 51c, and is electrically connected to devices such as the memory cell array 11 and the transistor 31 via the via plug 45. However, each dummy plug 45' in this modification does not function as a plug for controlling the semiconductor device of this modification. This is because the power supply voltage and signal voltage supplied from the wiring 54a to the device are supplied to the device via the via plug 45, not via the dummy plug 45'. The same applies to the signal voltage supplied from the device to the wiring 54a.

[0135] The wirings 51b, 51c and dummy plugs 45' of this modification can provide the same effects as the wirings 51b and dummy plugs 45' of the second embodiment. Note that each dummy plug 45' of this modification may be disposed on the wiring layer 44 as long as the wirings 54a are not electrically connected to the device via the dummy plugs 45'. This also applies to the modifications described below. For the same reason, each dummy plug 45' of the second embodiment may also be disposed on the wiring layer 44.

[0136] Figure 41 shows a plan view and a cross-sectional view illustrating the structure of a semiconductor device according to a second modification of the second embodiment. Figure 41(a) shows the planar structure of the semiconductor device according to this modification. Figure 41(b) shows the YZ cross section along the Y-Y' line shown in Figure 41(a).

[0137] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the second embodiment. However, the wiring layer 51 of this modification does not include the wiring 51b. FIG. 41(b) shows a plurality of dummy plugs 45' provided on the lower surface of the wiring 54a. These dummy plugs 45' are in contact with the wiring 54a and are electrically connected to the wiring 54a. The dummy plugs 45' of this modification can achieve the same effects as the wiring 51b and dummy plugs 45' of the second embodiment.

[0138] Figure 42 shows a plan view and a cross-sectional view illustrating the structure of a semiconductor device according to a third modified example of the second embodiment. Figure 42(a) shows the planar structure of the semiconductor device according to this modified example. Figure 42(b) shows the XZ cross section along the XX' line shown in Figure 42(a).

[0139] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the second embodiment. However, the wiring layer 51 of this modification includes wiring 51b provided over a wide area on the lower surface of wiring 54a. The wiring 51b of this modification is in contact with the wiring 54a and is electrically connected to the wiring 54a. FIG. 42(b) shows a plurality of dummy plugs 45' provided on the lower surface of the wiring 51b. The wiring 51b and dummy plugs 45' of this modification can achieve the same effects as the wiring 51b and dummy plugs 45' of the second embodiment.

[0140] Figure 43 is a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fourth modification of the second embodiment. Figure 43(a) shows the planar structure of the semiconductor device according to this modification. Figure 43(b) shows the XZ cross section along the XX' line shown in Figure 43(a).

[0141] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the second embodiment. However, the wiring 54a of this modification includes a portion P1 having a flat plate shape and a plurality of portions P2 protruding downward from the portion P1. As shown in FIGS. 43(a) and 43(b), each portion P2 extends in the Y direction and is disposed on a plurality of via plugs 45. The wiring 51b and dummy plugs 45′ of this modification can achieve the same effects as those of the wiring 51b and dummy plugs 45′ of the second embodiment.

[0142] FIG. 44 is a cross-sectional view showing the structures of semiconductor devices according to fifth and sixth modifications of the second embodiment.

[0143] 44(a) shows an XZ cross section of a semiconductor device according to a fifth modified example of the second embodiment. The semiconductor device according to this modified example has a similar structure to the semiconductor device according to the second embodiment. However, the wiring 54a according to this modified example has portions B1 and B2, similar to the wiring 54a shown in FIG. 7. This allows this modified example to also achieve the effects of the first embodiment.

[0144] 44(b) shows an XZ cross section of a semiconductor device according to a sixth modified example of the second embodiment. The semiconductor device according to this modified example has a similar structure to the semiconductor device according to the second embodiment. However, the wiring 54a according to this modified example includes metal layers 75 and 76, similar to the wiring 54a shown in FIG. 29. This allows this modified example to also achieve the effects of the first embodiment.

[0145] Figure 45 is a plan view and a cross-sectional view showing the structure of a semiconductor device according to a seventh modified example of the second embodiment. Figure 45(a) shows the planar structure of the semiconductor device according to this modified example. Figure 45(b) shows the YZ cross section along the Y-Y' line shown in Figure 45(a).

[0146] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the first modification of the second embodiment. However, the planar shapes of the via plugs 45 and the dummy plugs 45′ of this modification are circular. According to this modification, it is possible to obtain the same effects as those of the first modification.

[0147] Figure 46 is a plan view and a cross-sectional view showing the structure of a semiconductor device according to an eighth modification of the second embodiment. Figure 46(a) shows the planar structure of the semiconductor device according to this modification. Figure 46(b) shows the YZ cross section along the Y-Y' line shown in Figure 46(a).

[0148] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the second modification of the second embodiment. However, the planar shapes of the via plugs 45 and the dummy plugs 45′ of this modification are circular. According to this modification, it is possible to obtain the same effects as those of the second modification.

[0149] Figure 47 shows a plan view and a cross-sectional view illustrating the structure of a semiconductor device according to a ninth modification of the second embodiment. Figure 47(a) shows the planar structure of the semiconductor device according to this modification. Figure 47(b) shows an XZ cross section taken along the XX' line shown in Figure 47(a).

[0150] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the third modification of the second embodiment. However, the planar shapes of the via plugs 45 and the dummy plugs 45′ of this modification are circular. According to this modification, it is possible to obtain the same effects as those of the third modification.

[0151] Fig. 48 is a plan view and a cross-sectional view showing the structure of a semiconductor device according to a tenth modified example of the second embodiment. Fig. 48(a) shows the planar structure of the semiconductor device according to this modified example. Fig. 48(b) shows the XZ cross section along the XX' line shown in Fig. 48(a).

[0152] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the fourth modification of the second embodiment. However, the planar shapes of the via plugs 45 and the dummy plugs 45′ of this modification are circular. This modification can achieve the same effects as the fourth modification.

[0153] FIG. 49 is a cross-sectional view showing the structures of semiconductor devices according to the eleventh and twelfth modifications of the second embodiment.

[0154] FIG. 49(a) shows an XZ cross section of a semiconductor device according to an eleventh modified example of the second embodiment. The semiconductor device according to this modified example has a similar structure to the semiconductor device according to the fifth modified example of the second embodiment. However, the planar shapes of the via plugs 45 and dummy plugs 45′ according to this modified example are circular. According to this modified example, it is possible to obtain the same effects as those of the fifth modified example.

[0155] FIG. 49(b) shows an XZ cross section of a semiconductor device according to a twelfth modification of the second embodiment.

[0156] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the sixth modification of the second embodiment. However, the planar shapes of the via plugs 45 and the dummy plugs 45′ of this modification are circular. According to this modification, it is possible to obtain the same effects as those of the sixth modification.

[0157] As described above, the semiconductor device of this embodiment includes a dummy plug 45' below the bonding pad (wiring 54a). Therefore, this embodiment makes it possible to form a suitable via plug 45. For example, it is possible to prevent damage to the via plug 45 when the probe needle 74 is brought into contact with the wiring 54a or when the bonding wire 57 is placed on the wiring 54a.

[0158] As described above, the planar shape of the via plug 45 may be circular, rectangular, or another shape. Making the planar shape of the via plug 45 rectangular has the advantage that, for example, damage to the via plug 45 can be more easily prevented than making the planar shape of the via plug 45 circular.

[0159] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0160] 1: Array chip, 2: Circuit chip, 11: memory cell array; 12: interlayer insulating film; 13: interlayer insulating film, 14: substrate, 15: substrate, 21: staircase structure portion, 22: beam portion, 23: contact plug, 24: word wiring layer, 25: via plug, 31: transistor, 31a: gate insulating film, 31b: gate electrode, 32: contact plug, 33: wiring layer, 34: wiring layer, 35: wiring layer, 36: via plug, 37: metal pad, 41: metal pad, 42: via plug, 43: wiring layer, 44: wiring layer, 45: via plug, 45': dummy plug, 51: wiring layer, 51a: wiring, 51b: wiring, 51c: wiring, 52: insulating film, 53: insulating film, 54: wiring layer, 54a: wiring, 54b: wiring, 54c: wiring, 55: Passivation insulating film, 56: Solder, 57: Bonding wire, 61: laminated film, 61a: electrode layer, 61b: insulating film, 62: Block insulating film, 63: Charge storage layer, 64: Tunnel insulating film, 65: channel semiconductor layer; 66: core insulating film; 71: insulating film, 72: insulating film, 73: insulating film, 74: probe needle, 75: metal layer, 76: metal layer, 77: sacrificial film, 77a: part, 77b: part, 78: insulating film, 81: insulating film, 82: insulating film, 83: insulating film

Claims

1. a first insulating film; a first plug provided in the first insulating film; a first wiring layer provided on the first insulating film; a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface; a second wiring layer including a first portion provided on the first insulating film and the first plug, a second portion provided on the first region, and a third portion provided on the second region, and including a bonding pad; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said first portion includes an upper portion provided on said first insulating film, and a lower portion protruding downward from said upper portion and provided on at least said first plug.

3. 3. The semiconductor device according to claim 2, wherein the height of the upper end of said first plug is lower than the height of the lower surface of said upper portion.

4. The semiconductor device according to claim 1 , wherein the height of the upper end of said first plug is higher than the height of the lower surface of said first portion.

5. 5. The semiconductor device according to claim 4, wherein said second wiring layer includes a first layer provided on said first insulating film and said first plug, and a second layer provided on said first layer.

6. a second plug provided in the first insulating film; 2. The semiconductor device according to claim 1, wherein said first portion is provided on said first insulating film, said first plug, and said second plug.

7. 7. The semiconductor device according to claim 6, wherein the first portion includes an upper portion provided on the first insulating film, a first lower portion protruding downward from the upper portion and provided on at least the first plug, and a second lower portion protruding downward from the upper portion and provided on at least the second plug.

8. 7. The semiconductor device according to claim 6, wherein said first portion includes an upper portion provided on said first insulating film, and a lower portion protruding downward from said upper portion and provided on at least said first plug and said second plug.

9. a third insulating film provided on the first insulating film and the second insulating film and provided below the second wiring layer; the first plug is provided in the first insulating film and the third insulating film; the first portion is provided on the first insulating film via the third insulating film and is provided on the first plug, the second portion is provided on the first region via the third insulating film, and the third portion is provided on the second region via the third insulating film; 2. The semiconductor device according to claim 1, wherein the first portion includes an upper portion provided on the first insulating film via the third insulating film, and a lower portion protruding downward from the upper portion and provided on at least the first plug.

10. 2. The semiconductor device according to claim 1, further comprising a third plug provided below said bonding pad and on the underside of said first wiring layer or said second wiring layer, said third plug not functioning as a plug for controlling said semiconductor device.

11. forming a first insulating film; forming a first plug in the first insulating film; forming a first wiring layer on the first insulating film; forming a second insulating film including a first region provided on the first insulating film and having a first upper surface, and a second region provided on the first wiring layer and having a second upper surface higher than the first upper surface; forming a second wiring layer including a first portion provided on the first insulating film and the first plug, a second portion provided on the first region, and a third portion provided on the second region, and including a bonding pad; A method for manufacturing a semiconductor device, comprising:

12. forming a first recess in the first wiring layer to expose an upper end of the first plug in the first recess; The method for manufacturing a semiconductor device according to claim 11 , wherein the second insulating film is formed after the first recess is formed.

13. forming a second recess in the second insulating film to expose an upper end of the first plug in the second recess; The method for manufacturing a semiconductor device according to claim 12 , wherein the second wiring layer is formed after the second recess is formed.

14. After forming the second recess, processing the exposed portion of the first plug and forming a third recess in the first insulating film, so that an upper end of the first plug is lowered to a bottom of the third recess; The method for manufacturing a semiconductor device according to claim 13 , wherein the second wiring layer is formed after the third recess is formed.

15. The method for manufacturing a semiconductor device according to claim 14 , wherein the exposed portion of the first plug is processed by isotropic etching.

16. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the isotropic etching is performed using an etchant gas and an ion beam after forming a first film on the first insulating film, the second insulating film, and the first plug.

17. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the ion beam is incident on the first plug at an angle with respect to the surface of the first substrate on which the first insulating film is provided.

18. forming a third insulating film on the first insulating film, the second insulating film, and the first plug after forming the second recess; forming a fourth recess in the third insulating film, and exposing an upper end of the first plug at a bottom of the fourth recess; It further includes: The method for manufacturing a semiconductor device according to claim 13 , wherein the second wiring layer is formed after the fourth recess is formed.

19. 14. The method for manufacturing a semiconductor device according to claim 13, wherein said second wiring layer is formed in a state in which an upper end of said first plug is higher than a bottom surface of said second recess.

20. further comprising applying a probe needle to the bonding pad; The method for manufacturing a semiconductor device according to claim 11 , wherein the width of the probe needle is greater than the width of the first portion.

Images