Insulating chip and semiconductor device

Abstract

To increase the breakdown voltage of an insulating chip.SOLUTION: An insulating chip 70 includes a first coil 41 and a fourth coil 44 that are apart from each other in an X direction in an element insulating layer 72 provided on a semiconductor substrate 71, a second coil 42 disposed facing the first coil 41 in a Z direction, and a third coil 43 disposed facing the fourth coil 44 in the Z direction. The semiconductor substrate 71 includes a first semiconductor region 131 and a second semiconductor region 132, and an insulating region 140 that insulates between the first semiconductor region 131 and the second semiconductor region 132. The first coil 41 and the second coil 42 are apart from the second semiconductor region 132 in the plan view and disposed so that at least a part thereof overlaps with the first semiconductor region 131. The third coil 43 and the fourth coil 44 are apart from the first semiconductor region 131 in the plan view and disposed so that at least a part thereof overlaps with the second semiconductor region 132.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to insulating chips and semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a module including a controller chip and a transformer chip arranged on a first die pad and a driver chip arranged on a second die pad. The transformer chip includes a substrate, an insulating layer stack structure formed on a main surface of the substrate, and an upper coil and a lower coil formed on different insulating layers in the insulating layer stack structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-78169

[0004] [overview] In the above-mentioned modules, there are cases where a high withstand voltage is required.

[0005] An insulating chip according to one embodiment of the present disclosure includes a semiconductor substrate, an element insulating layer provided on the semiconductor substrate, a first insulating element and a fourth insulating element provided in the element insulating layer and spaced apart from each other in a first direction intersecting a thickness direction of the element insulating layer, a second insulating element arranged opposite the first insulating element in the thickness direction, and a third insulating element arranged opposite the fourth insulating element in the thickness direction, wherein the semiconductor substrate includes a first semiconductor region, a second semiconductor region arranged spaced apart from the first semiconductor region in the first direction, and an insulating region insulating the first semiconductor region from the second semiconductor region, wherein, as viewed from the thickness direction, both the first insulating element and the second insulating element are spaced apart from the second semiconductor region and are arranged so that at least a portion of them overlap with the first semiconductor region, and when viewed from the thickness direction, both the third insulating element and the fourth insulating element are spaced apart from the first semiconductor region and are arranged so that at least a portion of them overlap with the second semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing the internal structure of the semiconductor device of the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view of the insulating chip in the semiconductor device of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing the first coil and the fourth coil of the insulating chip of FIG. [Figure 6] FIG. 6 is a schematic bottom view of an insulating chip. [Figure 7] FIG. 7 is a schematic cross-sectional view of the insulating chip taken along line F7-F7 in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the insulating chip taken along line F8-F8 in FIG. [Figure 9]FIG. 9 is a schematic plan view of a semiconductor substrate for explaining an exemplary manufacturing process for the insulating chip of the first embodiment. [Figure 10] FIG. 10 is a schematic end view of the semiconductor substrate taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic end view of the semiconductor substrate taken along line F12-F12 in FIG. [Figure 13] FIG. 13 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic end view of the semiconductor substrate taken along line F14-F14 in FIG. [Figure 15] FIG. 15 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 16] FIG. 16 is a schematic end view of the semiconductor substrate taken along line F16-F16 in FIG. [Figure 17] FIG. 17 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic end view of the semiconductor substrate taken along line F18-F18 in FIG. [Figure 19] FIG. 19 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 20] FIG. 20 is a schematic end view of the semiconductor substrate taken along line F20-F20 in FIG. [Figure 21] FIG. 21 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 22] FIG. 22 is a schematic end view of the semiconductor substrate taken along line F22-F22 in FIG. [Figure 23] FIG. 23 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 24] FIG. 24 is a schematic end view of the semiconductor substrate taken along line F24-F24 in FIG. [Figure 25]FIG. 25 is a schematic plan view showing a manufacturing step subsequent to the step shown in FIG. [Figure 26] FIG. 26 is a schematic end view of the semiconductor substrate taken along line F26-F26 in FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view of the semiconductor device of the second embodiment. [Figure 28] FIG. 28 is a schematic plan view of the insulating chip in the semiconductor device of FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view of the insulating chip taken along line F29-F29 in FIG. [Figure 30] FIG. 30 is a schematic perspective view showing an exemplary manufacturing process for the insulating chip of the second embodiment. [Figure 31] 31A to 31C are schematic cross-sectional views illustrating an exemplary manufacturing process for the insulating chip of the second embodiment. [Figure 32] FIG. 32 is a circuit diagram of the semiconductor device of the third embodiment. [Figure 33] FIG. 33 is a schematic plan view of an insulating chip in the semiconductor device of the third embodiment. [Figure 34] 34 is a schematic cross-sectional view showing a first electrode plate of a first capacitor and a second electrode plate of a second capacitor in the insulating chip of FIG. [Figure 35] FIG. 35 is a schematic cross-sectional view of the insulating chip taken along line F35-F35 in FIG. [Figure 36] FIG. 36 is a circuit diagram of the semiconductor device of the fourth embodiment. [Figure 37] FIG. 37 is a schematic plan view of an insulating chip in the semiconductor device of the fourth embodiment. [Figure 38] 38 is a schematic cross-sectional view showing the first coil, the fourth coil, the fifth coil, and the eighth coil of the insulating chip of FIG. [Figure 39] FIG. 39 is a schematic cross-sectional view of the insulating chip taken along line F39-F39 in FIG. [Figure 40] FIG. 40 is a schematic cross-sectional view showing the first to fourth coils and their surroundings in an enlarged manner in FIG. [Figure 41] FIG. 41 is a schematic cross-sectional view showing an enlargement of the third to sixth coils and their surroundings in FIG. [Figure 42] FIG. 42 is a schematic cross-sectional view showing an enlargement of the fifth to eighth coils and their surroundings in FIG. [Figure 43] FIG. 43 is a schematic plan view of an insulating chip in a semiconductor device according to the fifth embodiment. [Figure 44] FIG. 44 is a schematic cross-sectional view of the insulating chip taken along line F44-F44 in FIG. [Figure 45] FIG. 45 is a circuit diagram of a semiconductor device according to the sixth embodiment. [Figure 46] FIG. 46 is a schematic plan view of an insulating chip in a semiconductor device according to the sixth embodiment. [Figure 47] 47 is a schematic cross-sectional view showing the first electrode plate of the first capacitor, the second electrode plate of the second capacitor, the first electrode plate of the third capacitor, and the second electrode plate of the fourth capacitor of the insulating chip of FIG. [Figure 48] FIG. 48 is a schematic cross-sectional view of the insulating chip taken along line F48-F48 in FIG. [Figure 49] FIG. 49 is a schematic plan view of an insulating chip in the semiconductor device of the seventh embodiment. [Figure 50] 50 is a schematic cross-sectional view showing the first coil, the fourth coil, the fifth coil, the eighth coil, the ninth coil, and the twelfth coil of the insulating chip of FIG. [Figure 51] FIG. 51 is a schematic cross-sectional view of a modified insulating tip. [Figure 52] FIG. 52 is a schematic cross-sectional view of a modified insulating tip. [Figure 53] FIG. 53 is a schematic bottom view of a modified insulating tip. [Figure 54] FIG. 54 is a schematic bottom view of a modified insulating tip. [Figure 55] FIG. 55 is a schematic bottom view of a modified insulating tip. [Figure 56] FIG. 56 is a schematic bottom view of a modified insulating tip. [Figure 57] FIG. 57 is a schematic cross-sectional view of a modified insulating tip. [Figure 58] FIG. 58 is a schematic plan view of a modified insulating tip. [Figure 59] 59 is a schematic cross-sectional view showing the first coil, the fourth coil, the fifth coil, and the eighth coil of the insulating chip of FIG. [Figure 60] FIG. 60 is a schematic plan view of a modified insulating chip. [Figure 61] 61 is a schematic cross-sectional view showing the first coil, the fourth coil, the fifth coil, and the eighth coil of the insulating chip of FIG. 60. FIG.

[0007] [Detailed explanation] Hereinafter, several embodiments of the insulating chip and semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this specification, the phrases "the dimensions (thickness, width, depth) of A are equal to the dimensions (thickness, width, depth) of B" or "the dimensions (thickness, width, depth) of A and the dimensions (thickness, width, depth) of B are equal to each other" also include a relationship in which the difference between the dimensions (thickness, width, depth) of A and the dimensions (thickness, width, depth) of B is within 10% of the dimensions (thickness, width, depth) of A, for example.

[0011] First Embodiment [Schematic configuration of semiconductor device] The schematic configuration of a semiconductor device 10 according to the first embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 schematically shows the circuit configuration of the semiconductor device 10 according to the first embodiment. FIG. 2 schematically shows an example of the internal planar structure of the semiconductor device 10. In FIG. 2, a sealing resin 100 (described later) is indicated by a two-dot chain line to show the internal structure of the semiconductor device 10. FIG. 3 schematically shows the cross-sectional structure of the semiconductor device 10 of FIG. 2 taken along line F3-F3.

[0012] 1 shows a simplified circuit configuration of the semiconductor device 10, the number of external terminals of the semiconductor device 10 in Fig. 2 is greater than the number of external terminals of the semiconductor device 10 in Fig. 1. Here, the number of external terminals of the semiconductor device 10 refers to the number of external electrodes that can connect the semiconductor device 10 to electronic components external to the semiconductor device 10.

[0013] (Circuit configuration of semiconductor device) 1, the semiconductor device 10 includes a first circuit 20, a second circuit 30, and a transformer 40. The transformer 40 electrically insulates the first circuit 20 from the second circuit 30.

[0014] The first circuit 20 is configured to operate using a first voltage V1. In one example, the first circuit 20 includes a transmitting circuit or a receiving circuit. In the first embodiment, the first circuit 20 includes a transmitting circuit 21. The transmitting circuit 21 includes at least one transistor. The second circuit 30 is configured to operate using a second voltage V2. In one example, the second circuit 30 includes a transmitting circuit or a receiving circuit. In the first embodiment, the second circuit 30 includes a receiving circuit 31. The receiving circuit 31 includes at least one transistor. The first voltage V1 and the second voltage V2 may be the same or different from each other. In one example, the second voltage V2 is equal to the first voltage V1. The semiconductor device 10 may be referred to as a digital isolator. Therefore, the semiconductor device 10 can also be referred to as a signal transmission device that transmits a signal from the first circuit 20 to the second circuit 30. In the first embodiment, a ground GND1 of the first circuit 20 and a ground GND2 of the second circuit 30 are provided independently.

[0015] The transformer 40 is configured to transmit a signal from the first circuit 20 to the second circuit 30. This signal is, for example, a signal for driving a switching element. The transformer 40 includes a first coil 41, a second coil 42, a third coil 43, and a fourth coil 44. The first coil 41 and the second coil 42 are electrically insulated from each other and configured to be magnetically coupled. The second coil 42 and the third coil 43 are electrically connected to each other. The third coil 43 and the fourth coil 44 are electrically insulated from each other and configured to be magnetically coupled. Here, the first coil 41 is an example of a "first insulating element," the second coil 42 is an example of a "second insulating element," the third coil 43 is an example of a "third insulating element," and the fourth coil 44 is an example of a "fourth insulating element."

[0016] The first coil 41 is electrically connected to the transmitting circuit 21 of the first circuit 20. More specifically, a first end of the first coil 41 is electrically connected to the transmitting circuit 21. A second end of the first coil 41 is electrically connected to ground GND1. The fourth coil 44 is electrically connected to the receiving circuit 31 of the second circuit 30. More specifically, a first end of the fourth coil 44 is electrically connected to the receiving circuit 31. A second end of the fourth coil 44 is electrically connected to ground GND2. The second coil 42 and the third coil 43 are in an electrically floating state.

[0017] The transmitting circuit 21 of the first circuit 20 receives an input signal and pulse-drives the transformer 40. The pulse signal excited in the first coil 41 is transmitted to the fourth coil 44 via the second coil 42 and the third coil 43, and then input to the receiving circuit 31 of the second circuit 30. The receiving circuit 31 outputs an output signal based on the input pulse signal.

[0018] (Internal structure of semiconductor device) 2, the semiconductor device 10 is a semiconductor device in which a plurality of semiconductor chips are packaged together. The semiconductor device 10 includes a first chip 50, a second chip 60, and an insulating chip 70 as the semiconductor chips.

[0019] The package format of the semiconductor device 10 is an SO (Small Outline) type, which is an SOP (Small Outline Package) in the first embodiment. The package format of the semiconductor device 10 can be changed as desired. The package format is not limited to SOP, and may be a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or various similar package structures.

[0020] The semiconductor device 10 further includes a first lead frame 80, a second lead frame 90, and a sealing resin 100. The sealing resin 100 is configured to seal the first chip 50, the second chip 60, and the insulating chip 70, and also partially seal the first lead frame 80 and the second lead frame 90. The sealing resin 100 is configured to seal a first die pad 81 (described later) of the first lead frame 80 and a second die pad 91 (described later) of the second lead frame 90. The sealing resin 100 is made of an electrically insulating resin material. This resin material includes, for example, a black epoxy resin. The sealing resin 100 is formed in the shape of a rectangular plate with its thickness direction aligned in the Z direction. The sealing resin 100 has four sealing side surfaces 101 to 104. More specifically, the sealing resin 100 has sealing side surfaces 101 and 102 as both end surfaces in the X direction and sealing side surfaces 103 and 104 as both end surfaces in the Y direction. The X and Y directions are perpendicular to the Z direction. The X and Y directions are perpendicular to each other when viewed from the Z direction. In one example, the sealing resin 100 has a rectangular shape with its long side oriented in the X direction and its short side oriented in the Y direction when viewed from the Z direction. Here, the X direction corresponds to the "first direction." In the following description, "plan view" means viewing the semiconductor device 10 from the Z direction. The shape of the sealing resin 100 in plan view can be changed as desired. In one example, the sealing resin 100 may have a rectangular shape with its long side oriented in the Y direction and its short side oriented in the X direction when viewed from the Z direction.

[0021] Each of the first lead frame 80 and the second lead frame 90 is a conductor and is formed from a material containing, for example, Cu (copper), Fe (iron), Al (aluminum), etc. Each of the lead frames 80, 90 is provided straddling the inside and outside of the sealing resin 100. Each of the first lead frame 80 and the second lead frame 90 is in the form of a thin plate with its thickness direction in the Z direction.

[0022] The first lead frame 80 has a first die pad 81 disposed within the sealing resin 100, and a plurality of first leads 82 disposed across the inside and outside of the sealing resin 100. Each of the first leads 82 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0023] In a plan view, the first die pad 81 is disposed so that its center in the Y direction is closer to the sealing side surface 101 than the center in the X direction of the sealing resin 100. In the first embodiment, the first die pad 81 is not exposed from the sealing resin 100. In one example, the first die pad 81 has a rectangular shape in a plan view. The first chip 50 is mounted on the first die pad 81.

[0024] The multiple first leads 82 are arranged spaced apart from each other in the Y direction. Of the multiple first leads 82, a pair of first leads 82 at both ends in the Y direction are integrated with the first die pad 81. The remaining first leads 82 are arranged spaced apart from the first die pad 81 in the X direction. A portion of each first lead 82 protrudes from the sealing side surface 103 towards the outside of the sealing resin 100.

[0025] The second lead frame 90 has a second die pad 91 disposed within the sealing resin 100, and a plurality of second leads 92 disposed across the inside and outside of the sealing resin 100. Each second lead 92 constitutes an external terminal that electrically connects the semiconductor device 10 to an external electronic device.

[0026] In a plan view, the second die pad 91 is disposed closer to the encapsulation side surface 102 in the X direction than the first die pad 81. That is, the first die pad 81 and the second die pad 91 are arranged at a distance from each other in the X direction. Therefore, the X direction can also be said to be the arrangement direction of both die pads 81, 91. The first chip 50 and the second die pad 60 are arranged at a distance from each other in the X direction. The first die pad 81 and the second die pad 91 are insulated from each other. In the first embodiment, the second die pad 91 is not exposed from the encapsulation resin 100. In one example, the second die pad 91 has a rectangular shape in a plan view. The second die 60 is mounted on the second die pad 91.

[0027] The multiple second leads 92 are arranged spaced apart from each other in the Y direction. Of the multiple second leads 92, a pair of second leads 92 at both ends in the Y direction are integrated with the second die pad 91. The remaining second leads 92 are arranged spaced apart from the second die pad 91 in the Y direction. A portion of each second lead 92 protrudes from the sealing side surface 104 toward the outside of the sealing resin 100.

[0028] In the first embodiment, the number of second leads 92 is the same as the number of first leads 82. As can be seen from FIG. 2, the multiple first leads 82 and the multiple second leads 92 are arranged in a direction (Y direction) perpendicular to the arrangement direction (X direction) of the first die pad 81 and the second die pad 91 in a plan view. Note that the number of second leads 92 and the number of first leads 82 can each be changed arbitrarily. In one example, the number of first leads 82 and the number of second leads 92 may be different from each other.

[0029] In the first embodiment, the first die pad 81 is supported by a pair of first leads 82 that are integrated with the first die pad 81. The second die pad 91 is supported by a pair of second leads 92 that are integrated with the second die pad 91. Therefore, each die pad 81, 91 is not provided with a suspension lead that is exposed from the sealing side surfaces 103, 104. This allows a large insulation distance (creepage distance) to be secured between the first lead frame 80 and the second lead frame 90.

[0030] The first chip 50 mounted on the first die pad 81 is a semiconductor chip including the first circuit 20 of FIG. 1. The first chip 50 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the first chip 50 is mounted on the first die pad 81 so that the long sides are aligned in the Y direction and the short sides are aligned in the X direction.

[0031] As shown in FIG. 3, the first chip 50 includes a first semiconductor substrate 51, a first insulating layer 52, and a plurality of electrode pads 53. The first semiconductor substrate 51 is made of a material containing, for example, silicon (Si). In one example, the first semiconductor substrate 51 is a Si substrate. The first insulating layer 52 is formed on the first semiconductor substrate 51. The first insulating layer 52 includes, for example, at least one of a silicon oxide film (SiO2) and a silicon nitride film (SiN). The first insulating layer 52 is provided with connection wiring that electrically connects the first semiconductor substrate 51 and the plurality of electrode pads 53. The plurality of electrode pads 53 are provided on the first insulating layer 52. The plurality of electrode pads 53 are exposed from the first insulating layer 52 in the Z direction. Here, the first semiconductor substrate 51 is an example of a "semiconductor substrate for the first chip."

[0032] The first chip 50 is bonded to the first die pad 81 by a bonding material 111. The bonding material 111 is interposed between the first die pad 81 and the first chip 50. The bonding material 111 bonds the first semiconductor substrate 51 and the first die pad 81. In the first embodiment, a conductive bonding material is used as the bonding material 111. Examples of the conductive bonding material that can be used include solder paste and silver (Ag) paste.

[0033] 2, the second chip 60 mounted on the second die pad 91 is a semiconductor chip including the second circuit 30 of FIG. 1. The second chip 60 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the second chip 60 is mounted on the second die pad 91 so that the long sides are aligned in the Y direction and the short sides are aligned in the X direction.

[0034] As shown in FIG. 3, the second chip 60 includes a second semiconductor substrate 61, a second insulating layer 62, and a plurality of electrode pads 63. The second semiconductor substrate 61 is made of a material containing, for example, Si. In one example, the second semiconductor substrate 61 is a Si substrate. The second insulating layer 62 is formed on the second semiconductor substrate 61. The second insulating layer 62 includes, for example, at least one of a silicon oxide film and a silicon nitride film. The second insulating layer 62 is provided with connection wiring that electrically connects the second semiconductor substrate 61 and the plurality of electrode pads 63. The plurality of electrode pads 63 are provided on the second insulating layer 62. The plurality of electrode pads 63 are exposed from the second insulating layer 62 in the Z direction. Here, the second semiconductor substrate 61 is an example of a "semiconductor substrate for the second chip."

[0035] The second chip 60 is bonded to the second die pad 91 by a bonding material 112. The bonding material 112 is interposed between the second die pad 91 and the second chip 60. The bonding material 112 bonds the second semiconductor substrate 61 and the second die pad 91. In the first embodiment, a conductive bonding material is used as the bonding material 112. Examples of the conductive bonding material that can be used include solder paste and Ag paste.

[0036] 2, the insulating chip 70 is disposed between the first chip 50 and the second chip 60 in the X direction. The insulating chip 70 is mounted on the first die pad 81 and the second die pad 91 so as to straddle the gap between the first die pad 81 and the second die pad 91 in the X direction. The insulating chip 70 is disposed between the first chip 50 and the second chip 60 in the X direction.

[0037] The insulating chip 70 is a semiconductor chip including the transformer 40 shown in Fig. 1. The insulating chip 70 is formed in a rectangular shape having short and long sides in a plan view. In a plan view, the insulating chip 70 is mounted on the first die pad 81 and the second die pad 91 so that the long sides are aligned in the X direction and the short sides are aligned in the Y direction.

[0038] As shown in FIG. 3, the insulating chip 70 includes a semiconductor substrate 71, an element insulating layer 72, a plurality of first pads 73, and a plurality of second pads 74. The semiconductor substrate 71 is made of, for example, a material containing Si. In one example, a Si substrate is used for the semiconductor substrate 71. The element insulating layer 72 is provided on the semiconductor substrate 71. The first to fourth coils 41 to 44 of the transformer 40 are provided on the element insulating layer 72. The pads 73 and 74 are exposed from the element insulating layer 72 in the Z direction.

[0039] The insulating chip 70 is bonded to the first die pad 81 by a first bonding material 121. The insulating chip 70 is bonded to the second die pad 91 by a second bonding material 122. The first bonding material 121 is interposed between the first die pad 81 and the insulating chip 70. The first bonding material 121 bonds the semiconductor substrate 71 to the first die pad 81. The second bonding material 122 is interposed between the second die pad 91 and the insulating chip 70. The second bonding material 122 bonds the semiconductor substrate 71 to the second die pad 91. A conductive bonding material is used for each of the bonding materials 121, 122. For example, solder paste, Ag paste, etc. are used as the conductive bonding material.

[0040] 2 and 3, a plurality of wires W1 to W4 are connected to each of the first chip 50, the insulating chip 70, and the second chip 60. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor containing, for example, gold (Au), Al, Cu, etc.

[0041] 2, the first chip 50 is electrically connected to the first lead frame 80 by wires W1. More specifically, the electrode pads 53 of the first chip 50 are individually connected to the first leads 82 by the wires W1. Some of the wires W1 are individually connected to a pair of first leads 82 integrated with the first die pad 81. In the first embodiment, the pair of first leads 82 integrated with the first die pad 81 constitute ground terminals. Therefore, the first die pad 81 has the same potential as the ground GND1 of the first circuit 20 (see FIG. 1).

[0042] The second chip 60 is electrically connected to the second lead frame 90 by wires W4. More specifically, the electrode pads 63 of the second chip 60 are individually connected to the second leads 92 by the wires W4. Some of the wires W4 are individually connected to a pair of second leads 92 integrated with the second die pad 91. In the first embodiment, the pair of second leads 92 integrated with the second die pad 91 constitute ground terminals. Therefore, the second die pad 91 has the same potential as the ground GND2 (see FIG. 1) of the second circuit 30.

[0043] The insulating chip 70 is electrically connected to the first chip 50 by wire W2. The insulating chip 70 is electrically connected to the second chip 60 by wire W3. More specifically, the multiple first pads 73 of the insulating chip 70 are individually connected to the multiple electrode pads 53 of the first chip 50 by multiple wires W2. The multiple second pads 74 of the insulating chip 70 are individually connected to the multiple electrode pads 63 of the second chip 60 by multiple wires W3. The first coil 41 is electrically connected to the ground GND1 of the first circuit 20 via wire W2, the first chip 50, etc. The fourth coil 44 is electrically connected to the ground GND2 of the second circuit 30 via wire W3, the second chip 60, etc.

[0044] Note that the first semiconductor substrate 51, the second semiconductor substrate 61, and the semiconductor substrate 71 shown in FIG. 3 may be made of a wide bandgap semiconductor or a compound semiconductor instead of a Si substrate. A wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. The wide bandgap semiconductor may be silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or the like. The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of aluminum nitride (AlN), indium nitride (InN), GaN, and gallium arsenide (GaAs).

[0045] [Insulation chip configuration] An example of the configuration of the insulating chip 70 will be described with reference to FIGS. In the following description, the direction from the semiconductor substrate 71 of the insulating chip 70 toward the element insulating layer 72 shown in Fig. 7 will be referred to as "upward," and the direction from the element insulating layer 72 toward the semiconductor substrate 71 will be referred to as "downward." Note that, for convenience, wires W2 and W3 are omitted from Fig. 7.

[0046] FIG. 4 schematically shows the planar structure of the insulating chip 70. FIG. 5 schematically shows the cross-sectional structure of the insulating chip 70 cut in the XY plane at the Z-direction position of the first coil 41 and the second coil 42. FIG. 6 schematically shows the back surface structure of the insulating chip 70. FIG. 7 schematically shows the cross-sectional structure of the insulating chip 70 cut along line F7-F7 in FIG. 4. FIG. 8 schematically shows the cross-sectional structure of the insulating chip 70 cut along line F8-F8 in FIG. 4. In FIGS. 7 and 8, the insulating chip 70 is mounted on the first die pad 81 and the second die pad 91.

[0047] As shown in FIGS. 4 and 7, the insulating chip 70 includes a chip top surface 70S and a chip bottom surface 70R facing opposite directions in the Z direction, and first to fourth chip side surfaces 70A to 70D connecting the chip top surface 70S and the chip bottom surface 70R. The chip bottom surface 70R is formed of a semiconductor substrate 71. Both the first pads 73 and the second pads 74 are exposed from the chip top surface 70S. The first chip side surface 70A and the second chip side surface 70B form both end surfaces of the insulating chip 70 in the X direction. The third chip side surface 70C and the fourth chip side surface 70D form both end surfaces of the insulating chip 70 in the Y direction.

[0048] 4 and 5, the insulating chip 70 includes first to fourth coils 41 to 44. The insulating chip 70 is a semiconductor chip that integrates the transformer 40 into a single chip. In other words, the insulating chip 70 is provided separately from the first chip 50 and the second chip 60 (both see FIG. 3).

[0049] 5, the first coil 41 and the fourth coil 44 are arranged spaced apart from each other in the X direction. When viewed from the X direction, the first coil 41 and the fourth coil 44 are arranged in positions where they overlap each other. The first coil 41 is arranged closer to the first chip side surface 70A than the fourth coil 44. The fourth coil 44 is arranged closer to the second chip side surface 70B than the first coil 41.

[0050] 4, the second coil 42 and the third coil 43 are disposed spaced apart from each other in the X direction. When viewed from the X direction, the second coil 42 and the third coil 43 are disposed in positions where they overlap each other. The second coil 42 is disposed closer to the first chip side surface 70A than the third coil 43. The third coil 43 is disposed closer to the second chip side surface 70B than the second coil 42.

[0051] As shown in FIG. 7 , the first coil 41 and the fourth coil 44 are arranged at the same position as each other in the Z direction. The second coil 42 and the third coil 43 are arranged at the same position as each other in the Z direction. The second coil 42 and the third coil 43 are arranged higher than the first coil 41 and the fourth coil 44 in the Z direction. In other words, the first coil 41 is arranged closer to the semiconductor substrate 71 than the second coil 42 in the Z direction. The fourth coil 44 is arranged closer to the semiconductor substrate 71 than the third coil 43 in the Z direction. The second coil 42 is arranged opposite the first coil 41 in the Z direction. The third coil 43 is arranged opposite the fourth coil 44 in the Z direction.

[0052] The first to fourth coils 41 to 44 have a spiral shape in a plan view. The first to fourth coils 41 to 44 are made of a material containing one or more appropriately selected from titanium (Ti), titanium nitride (TiN), Au, Ag, Cu, Al, and tungsten (W). In one example, the first to fourth coils 41 to 44 are made of a material containing Cu.

[0053] The transformer 40 is disposed closer to the center of the insulating chip 70 in the X direction than either end thereof in a plan view. In one example, each first pad 73 and each second pad 74 is disposed at a position that does not overlap with the transformer 40 in a plan view. Each first pad 73 is disposed closer to the first chip side surface 70A than the transformer 40 in a plan view. Each second pad 74 is disposed closer to the second chip side surface 70B than the transformer 40 in a plan view. Each first pad 73 is electrically connected to the first coil 41. Each second pad 74 is electrically connected to the fourth coil 44. It can be said that each first pad 73 is disposed on the opposite side of the first coil 41 from the fourth coil 44 in the X direction. It can be said that each second pad 74 is disposed on the opposite side of the fourth coil 44 from the first coil 41 in the X direction.

[0054] Each of the pads 73 and 74 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. Each of the pads 73 and 74 is made of a material containing Al, for example.

[0055] In the following description, for convenience, the multiple first pads 73 may be referred to as "first pads 73A, 73B," and the multiple second pads 74 may be referred to as "second pads 74A, 74B." The first pad 73A is arranged closer to the third chip side surface 70C than the first pad 73B. The second pad 74A is arranged closer to the third chip side surface 70C than the second pad 74B.

[0056] The element insulating layer 72 provided on the semiconductor substrate 71 includes a plurality of insulating films 75 stacked in the Z direction from the semiconductor substrate 71. In other words, the Z direction can be said to be the thickness direction of the element insulating layer 72. The Z direction can also be said to be the stacking direction of the plurality of insulating films 75.

[0057] The insulating film 75 includes a first insulating film 75A and a second insulating film 75B formed on the first insulating film 75A. The first insulating film 75A is a thin film, such as an etching stopper layer. The first insulating film 75A is made of a material containing SiN, SiC, SiCN (nitrogen-doped silicon carbide), or the like. In the first embodiment, the first insulating film 75A is made of a material containing SiN. The second insulating film 75B is, for example, an interlayer insulating film. The second insulating film 75B is made of a material containing SiO2. The thickness of the second insulating film 75B is thicker than the thickness of the first insulating film 75A. The thickness of the first insulating film 75A may be 100 nm or more and less than 1000 nm. The thickness of the second insulating film 75B may be 1000 nm or more and 3000 nm or less. In one example, the thickness of the first insulating film 75A is approximately 300 nm, and the thickness of the second insulating film 75B is approximately 2000 nm.

[0058] The lowest insulating film 75L of the element insulating layer 72, which is in contact with the semiconductor substrate 71, is composed of the second insulating film 75B. In one example, the thickness of the lowest insulating film 75L is thinner than the thickness of the other second insulating films 75B. The thickness of the lowest insulating film 75L is equal to or greater than the thickness of the first insulating film 75A.

[0059] The thickness of the lowermost insulating film 75L can be changed as desired. For example, the thickness of the lowermost insulating film 75L may be equal to or greater than the thickness of the second insulating film 75B. The thickness of the lowermost insulating film 75L may be equal to or greater than the thickness of the insulating film 75 formed by the first insulating film 75A and the second insulating film 75B.

[0060] As shown in FIG. 7, the insulating chip 70 includes a protective layer 76 that protects the device insulating layer 72 . The protective layer 76 can be considered a surface protective film for the insulating chip 70. The protective layer 76 covers the upper surface of the element insulating layer 72. In one example, the protective layer 76 may have a laminated structure of a passivation film and a resin layer. The passivation film covers the element insulating layer 72. The resin layer is provided on the passivation film. The passivation film contains at least one of a material containing SiO2 and a material containing SiN, for example. The resin layer is made of a material containing polyimide (PI), for example.

[0061] Both the first pad 73 and the second pad 74 are provided on the uppermost insulating film 75U. A protective layer 76 covers the first pad 73 and the second pad 74. The protective layer 76 has openings that expose portions of both the first pad 73 and the second pad 74. As a result, the first pad 73 has an exposed surface for connecting a wire W2 (see FIG. 3). The second pad 74 has an exposed surface for connecting a wire W3 (see FIG. 3).

[0062] 5, 7, and 8, the insulating chip 70 includes an inner connecting wiring 45A that electrically connects an inner end of the first coil 41 to a first pad 73A, and an outer connecting wiring 46A that electrically connects an outer end of the first coil 41 to a first pad 73B. Both the inner connecting wiring 45A and the outer connecting wiring 46A are provided on the element insulating layer 72.

[0063] The inner connecting wiring 45A and the outer connecting wiring 46A are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the inner connecting wiring 45A and the outer connecting wiring 46A are made of a material containing Cu. In other words, the inner connecting wiring 45A and the outer connecting wiring 46A may be made of the same material as the first coil 41.

[0064] As shown in FIGS. 5 and 8, the inner connection wiring 45A includes a coil connection portion 45AA, a connection wiring 45AB, and a pad connection portion 45AC. The connection wiring 45AB is L-shaped in a plan view. More specifically, the connection wiring 45AB includes a first portion extending in the Y direction from a position overlapping the inner end of the first coil 41, and a second portion extending in the X direction from the Y-direction end of the first portion toward the first pad 73A. As shown in FIG. 8 , the connection wiring 45AB is disposed closer to the semiconductor substrate 71 than the first coil 41 in the Z direction.

[0065] The connection wiring 45AB is electrically connected to the inner end of the first coil 41 by the coil connection portion 45AA. The coil connection portion 45AA is provided at a position overlapping both the inner end of the first coil 41 and the connection wiring 45AB in a plan view. The coil connection portion 45AA is formed of, for example, a via.

[0066] The connection wiring 45AB is electrically connected to the first pad 73A by a pad connection portion 45AC. The pad connection portion 45AC is provided at a position overlapping both the first pad 73A and the connection wiring 45AB in a plan view. In one example, the pad connection portion 45AC penetrates from the insulating film 75 immediately below the uppermost insulating film 75U to the insulating film 75 two layers above the lowermost insulating film 75L among the multiple insulating films 75. The pad connection portion 45AC includes a laminated structure of a flat wiring portion and multiple vias. The wiring portion is disposed at the same position as the first coil 41 and the second coil 42 in the Z direction. The multiple vias are provided between the two wiring portions in the Z direction, between the upper wiring portion and the first pad 73A in the Z direction, and between the lower wiring portion and the connection wiring 45AB in the Z direction.

[0067] As shown in FIG. 7, the outer connection wiring 46A includes a connection wiring 46AA and a pad connection portion 46AB. 5, the connection wiring 46AA extends in the X direction from the outer end of the first coil 41 toward the first pad 73B in a plan view. As shown in Fig. 7, the connection wiring 46AA is disposed at the same position as the first coil 41 in the Z direction. In one example, the connection wiring 46AA may be provided integrally with the first coil 41.

[0068] The connection wiring 46AA is electrically connected to the first pad 73B by a pad connection portion 46AB. The pad connection portion 46AB is provided at a position overlapping both the first pad 73B and the connection wiring 46AA in a plan view. In one example, the pad connection portion 46AB penetrates from the insulating film 75 immediately below the uppermost insulating film 75U to the insulating film 75 three layers above the lowermost insulating film 75L among the multiple insulating films 75. The pad connection portion 46AB includes a laminated structure of a flat wiring portion and multiple vias. The wiring portion is disposed at the same position as the second coil 42 in the Z direction. The multiple vias are provided between the wiring portion and the first pad 73B in the Z direction and between the wiring portion and the connection wiring 45AB in the Z direction.

[0069] 5, 7, and 8, the insulating chip 70 includes an inner connection wiring 45B that electrically connects an inner end of the fourth coil 44 to a second pad 74A, and an outer connection wiring 46B that electrically connects an outer end of the fourth coil 44 to the second pad 74B. Both the inner connection wiring 45B and the outer connection wiring 46B are provided in the element insulating layer 72. Note that the material forming the inner connection wiring 45B and the outer connection wiring 46B may be the same as the material forming the inner connection wiring 45A and the outer connection wiring 46A, for example.

[0070] The inner connection wiring 45B includes a coil connection portion 45BA, a connection wiring 45BB, and a pad connection portion 45BC. The configurations of the coil connection portion 45BA, the connection wiring 45BB, and the pad connection portion 45BC are the same as the configurations of the coil connection portion 45AA, the connection wiring 45AB, and the pad connection portion 45AC of the inner connection wiring 45A, respectively.

[0071] The outer connection wiring 46B includes a connection wiring 46BA and a pad connection portion 46BB. The configurations of the connection wiring 46BA and the pad connection portion 46BB are the same as the configurations of the connection wiring 46AA and the pad connection portion 46AB of the outer connection wiring 46A.

[0072] 4 and 7, the insulating chip 70 includes a connection wiring 47 that electrically connects the second coil 42 and the third coil 43. The connection wiring 47 is provided in the element insulating layer 72.

[0073] The connection wiring 47 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. In one example, the connection wiring 47 is made of a material containing Cu. In other words, the connection wiring 47 may be made of the same material as the second coil 42 and the third coil 43.

[0074] As shown in Figure 4, the connection wiring 47 includes a first connection wiring 47A that electrically connects the inner end of the second coil 42 and the inner end of the third coil 43, and a second connection wiring 47B that electrically connects the outer end of the second coil 42 and the outer end of the third coil 43.

[0075] 7, the first connection wiring 47A is disposed above the second coil 42 and the third coil 43. In other words, the first connection wiring 47A is disposed on the opposite side of the second coil 42 and the third coil 43 from the first coil 41 and the fourth coil 44 in the Z direction. In other words, the first connection wiring 47A is disposed on the opposite side of the semiconductor substrate 71 from the second coil 42 and the third coil 43 in the Z direction.

[0076] The first connection wiring 47A includes a first coil connection portion 47AA, a coil connection wiring 47AB, and a second coil connection portion 47AC. The coil connection wiring 47AB extends in the X direction from the inner end of the second coil 42 to the inner end of the third coil 43 in a plan view. The coil connection wiring 47AB is electrically connected to the second coil 42 by the first coil connection portion 47AA. The coil connection wiring 47AB is electrically connected to the third coil 43 by the second coil connection portion 47AC. The coil connection wiring 47AB is disposed, for example, at the same position as the first pad 73 and the second pad 74 in the Z direction. In one example, the coil connection wiring 47AB is provided on the uppermost insulating film 75U. The coil connection wiring 47AB is covered by the protective layer 76. The coil connection wiring 47AB is not exposed from the protective layer 76.

[0077] Both the first coil connection portion 47AA and the second coil connection portion 47AC are formed by, for example, vias. The first coil connection portion 47AA connects one of the X-direction ends of the coil connection wiring 47AB that is closer to the second coil 42 to an inner end of the second coil 42. The second coil connection portion 47AC connects one of the X-direction ends of the coil connection wiring 47AB that is closer to the third coil 43 to an inner end of the third coil 43.

[0078] As shown in FIG. 7 , the second connection wiring 47B is disposed at the same position as the second coil 42 and the third coil 43 in the Z direction. As shown in FIG. 4 , the second connection wiring 47B extends along the X direction to connect the outer end of the second coil 42 and the outer end of the third coil 43. More specifically, the outer end of the second coil 42 is provided at one of both ends of the second coil 42 in the X direction that is closer to the third coil 43. The outer end of the third coil 43 is provided at one of both ends of the third coil 43 in the X direction that is closer to the second coil 42. In the Y direction, the outer end of the second coil 42 and the outer end of the third coil 43 are at the same position. The second connection wiring 47B is disposed between the second coil 42 and the third coil 43 in the X direction and connects the outer end of the second coil 42 and the outer end of the third coil 43.

[0079] (Configuration of semiconductor substrate) Next, the detailed configuration of the semiconductor substrate 71 will be described with reference to Figures 6 and 7. In Figure 6, insulating regions 140 are indicated by dots to facilitate understanding of the drawing.

[0080] 6 and 7, semiconductor substrate 71 includes a substrate upper surface 71A, a substrate lower surface 71B, and first to fourth substrate side surfaces 71C to 71F that connect substrate upper surface 71A and substrate lower surface 71B. Substrate lower surface 71B constitutes chip lower surface 70R. First substrate side surface 71C and second substrate side surface 71D constitute both end surfaces of semiconductor substrate 71 in the X direction. Third substrate side surface 71E and fourth substrate side surface 71F constitute both end surfaces of semiconductor substrate 71 in the Y direction.

[0081] The semiconductor substrate 71 includes a first semiconductor region 131, a second semiconductor region 132, a peripheral region 133, and an insulating region 140. The insulating region 140 is a region that separates the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 from the semiconductor substrate 71. The insulating region 140 insulates the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 from one another.

[0082] The first semiconductor region 131 is disposed closer to the first substrate side surface 71C in a planar view. In one example, the first semiconductor region 131 includes a region that overlaps with at least a portion of both the first coil 41 and the second coil 42 in a planar view. Meanwhile, both the first coil 41 and the second coil 42 are disposed at positions spaced apart from the second semiconductor region 132 in a planar view. In one example, the first semiconductor region 131 has a rectangular shape in a planar view.

[0083] The second semiconductor region 132 is disposed apart from the first semiconductor region 131 in the X direction. The second semiconductor region 132 is disposed closer to the second substrate side surface 71D in a planar view. In one example, the second semiconductor region 132 includes a region that overlaps with at least a portion of both the third coil 43 and the fourth coil 44 in a planar view. Meanwhile, both the third coil 43 and the fourth coil 44 are disposed at a position spaced apart from the first semiconductor region 131 in a planar view. In one example, the second semiconductor region 132 has a rectangular shape in a planar view. In one example, the area of ​​the second semiconductor region 132 is equal to the area of ​​the first semiconductor region 131.

[0084] The peripheral region 133 is frame-shaped in a plan view, surrounding the first semiconductor region 131 and the second semiconductor region 132, and has a predetermined width. It can also be said that the peripheral region 133 surrounds the insulating region 140 in a plan view. In one example, the peripheral region 133 is square-shaped in a plan view. In one example, the first to fourth coils 41 to 44 are disposed at positions spaced apart from the peripheral region 133 in a plan view. The first to fourth coils 41 to 44 are positioned inward of the peripheral region 133 in a plan view.

[0085] Since the semiconductor substrate 71 is made of a material containing Si, the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 are each made of a material containing Si. In other words, the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 are each made of the same material as the semiconductor substrate 71.

[0086] The insulating region 140 penetrates the semiconductor substrate 71 in the Z direction. The insulating region 140 includes a frame-shaped first insulating region 141 that surrounds the first semiconductor region 131 in a plan view, and a frame-shaped second insulating region 142 that surrounds the second semiconductor region 132 in a plan view. In one example, both the first insulating region 141 and the second insulating region 142 have a rectangular frame shape in a plan view. Note that the shape of the first insulating region 141 and the shape of the second insulating region 142 in a plan view are not limited to a rectangular frame shape and can be changed as desired.

[0087] 6, the first insulating region 141 and the second insulating region 142 are integrated. As a result, the insulating region 140 includes an intermediate insulating region 143 that serves as both the first insulating region 141 and the second insulating region 142. The intermediate insulating region 143 is provided in the center of the semiconductor substrate 71 in the X direction. It can be said that the intermediate insulating region 143 is provided between the first semiconductor region 131 and the second semiconductor region 132 in the X direction. In a plan view, the intermediate insulating region 143 extends in the Y direction.

[0088] 7, the width dimension WR of the insulating region 140 (see FIG. 6) is smaller than the dimension HR of the insulating region 140 in the thickness direction (Z direction). Here, the width dimension WR of the insulating region 140 can be defined as the dimension in a direction perpendicular to the direction in which the insulating region 140 extends in a plan view. The dimension HR of the insulating region 140 in the thickness direction can be defined as the distance in the Z direction between the upper surface of the insulating region 140 exposed from the substrate upper surface 71A of the semiconductor substrate 71 and the lower surface of the insulating region 140 exposed from the substrate lower surface 71B.

[0089] In one example, the width dimension WR1 of the first insulating region 141 and the width dimension WR2 of the second insulating region 142 are equal to each other. In one example, the thickness direction dimension HR1 of the first insulating region 141 and the thickness direction dimension HR2 of the second insulating region 142 are equal to each other. In one example, the width dimension WR1 of the portion of the first insulating region 141 other than the intermediate insulating region 143 is equal to the width dimension WR3 of the intermediate insulating region 143. In one example, the width dimension WR2 of the portion of the second insulating region 142 other than the intermediate insulating region 143 is equal to the width dimension WR3 of the intermediate insulating region 143. In one example, the thickness direction dimension HR1 of the portion of the first insulating region 141 other than the intermediate insulating region 143 is equal to the thickness direction dimension HR3 of the intermediate insulating region 143. In one example, the thickness direction dimension HR2 of the portion of the second insulating region 142 other than the intermediate insulating region 143 is equal to the thickness direction dimension HR3 of the intermediate insulating region 143.

[0090] The dimension HR of the insulating region 140 in the thickness direction is equal to the thickness of the semiconductor substrate 71. Here, the thickness of the semiconductor substrate 71 can be defined as the distance between the substrate upper surface 71A and the substrate lower surface 71B of the semiconductor substrate 71 in the Z direction.

[0091] The insulating region 140 is made of an insulating material. In one example, the insulating region 140 is made of SiO2. In one example, the insulating region 140 is formed by thermally oxidizing the semiconductor substrate 71. The insulating material that makes up the insulating region 140 can be changed as desired, and may be made of a material containing SiN, for example.

[0092] 7, when the insulating chip 70 is mounted on the first die pad 81 and the second die pad 91, the first bonding material 121 contacts the first semiconductor region 131 of the semiconductor substrate 71, and the second bonding material 122 contacts the second semiconductor region 132 of the semiconductor substrate 71. In other words, the first semiconductor region 131 is bonded to the first die pad 81 by the first bonding material 121. The second semiconductor region 132 is bonded to the second die pad 91 by the second bonding material 122. On the other hand, neither the first bonding material 121 nor the second bonding material 122 contacts the outer periphery region 133 of the semiconductor substrate 71.

[0093] 7, the first bonding material 121 is in partial contact with the first semiconductor region 131 and spaced apart from the first insulating region 141 in a plan view. The second bonding material 122 is in partial contact with the second semiconductor region 132 and spaced apart from the second insulating region 142 in a plan view. Both the first bonding material 121 and the second bonding material 122 are spaced apart from the intermediate insulating region 143 in a plan view. Therefore, an area that is not in contact with the first bonding material 121 is provided at an end of the first semiconductor region 131 closer to the intermediate insulating region 143 in a plan view. An area that is not in contact with the second bonding material 122 is provided at an end of the second semiconductor region 132 closer to the intermediate insulating region 143 in a plan view.

[0094] As described above, the first bonding material 121 is not in contact with the peripheral region 133 of the semiconductor substrate 71, but is in contact with the first semiconductor region 131. The second bonding material 122 is not in contact with the peripheral region 133 of the semiconductor substrate 71, but is in contact with the second semiconductor region 132. Therefore, the first semiconductor region 131 is bonded to the first die pad 81 by the first bonding material 121. The second semiconductor region 132 is bonded to the second die pad 91 by the second bonding material 122. Meanwhile, a sealing resin 100 (see FIG. 3 ) is interposed between the peripheral region 133 and the first die pad 81 in the Z direction. The sealing resin 100 is interposed between the peripheral region 133 and the second die pad 91 in the Z direction.

[0095] 7, the inter-region distance DR between the first semiconductor region 131 and the second semiconductor region 132 in the X direction is smaller than the inter-pad distance PR between the first die pad 81 and the second die pad 91 in the X direction. In the first embodiment, the first semiconductor region 131 and the second semiconductor region 132 are partitioned in the X direction by the intermediate insulating region 143, and therefore the inter-region distance DR is equal to the width dimension WR3 of the intermediate insulating region 143. For this reason, it can also be said that the width dimension WR3 of the intermediate insulating region 143 is smaller than the inter-pad distance PR.

[0096] The inter-region distance DR is smaller than the distance DC in the X direction between the first coil 41 and the fourth coil 44. The inter-region distance DR is smaller than the distance DD in the X direction between the second coil 42 and the third coil 43. Note that the distance DC and the distance DD may be equal to each other.

[0097] On the other hand, the inter-region distance DR is greater than the distance DA in the Z direction between the first coil 41 and the second coil 42. The inter-region distance DR is greater than the distance DB in the Z direction between the third coil 43 and the fourth coil 44. Note that the distance DA and the distance DB may be equal to each other.

[0098] The inter-pad distance PR is smaller than the distance DC between the first coil 41 and the fourth coil 44 in the X direction. The inter-pad distance PR is smaller than the distance DD between the second coil 42 and the third coil 43 in the X direction. The inter-pad distance PR is larger than the distance DA between the first coil 41 and the second coil 42 in the Z direction. The inter-pad distance PR is larger than the distance DB between the third coil 43 and the fourth coil 44 in the Z direction.

[0099] As shown in FIG. 3, the thickness TR of the semiconductor substrate 71 of the insulating chip 70 is smaller than the thickness TA of the first semiconductor substrate 51 of the first chip 50 and the thickness TB of the second semiconductor substrate 61 of the second chip 60.

[0100] [Insulating chip manufacturing method] An example of a method for manufacturing the insulating chip 70 will be described with reference to FIGS. 9 and 10, the method for manufacturing insulating chip 70 includes the step of preparing a semiconductor substrate 800. Fig. 9 shows the planar structure of semiconductor substrate 800. Fig. 10 shows the end surface structure of semiconductor substrate 800 cut along line F10-F10 in Fig. 9.

[0101] The semiconductor substrate 800 is made of a material containing Si, for example. In one example, the semiconductor substrate 800 is a Si substrate. The semiconductor substrate 800 is a semiconductor substrate that constitutes the semiconductor substrate 71 shown in FIG. 7. The semiconductor substrate 800 includes a substrate upper surface 801 and a substrate lower surface 802. The thickness of the semiconductor substrate 800 is greater than the thickness of the semiconductor substrate 71. Here, the thickness of the semiconductor substrate 800 can be defined as the distance between the substrate upper surface 801 and the substrate lower surface 802 in the Z direction. Here, the substrate upper surface 801 is an example of a "first substrate surface," and the substrate lower surface 802 is an example of a "second substrate surface."

[0102] As shown in FIGS. 9 and 10, the method for manufacturing the insulating chip 70 includes a step of forming an insulating layer 811 on a semiconductor substrate 800. In this step, at least one trench 810 is first formed in the semiconductor substrate 800 by etching. The trench 810 is formed by digging from the substrate upper surface 801 toward the substrate lower surface 802. The bottom surface of the trench 810 is located closer to the substrate upper surface 801 than the substrate lower surface 802. The trench 810 forms a first semiconductor region 131, a second semiconductor region 132, and a peripheral region 133. The first semiconductor region 131 and the second semiconductor region 132 are regions surrounded by the trench 810 in a planar view. The second semiconductor region 132 is disposed spaced apart from the first semiconductor region 131 in the X direction. The peripheral region 133 is a region between the trench 810 and the outer periphery of the substrate upper surface 801 of the semiconductor substrate 800 in a planar view. The peripheral region 133 is formed in a quadrangular ring shape in a planar view. The shape of the trench 810 in a planar view is not limited to the shape shown in FIG. 9. The trench 810 may include at least a trench formed between the first semiconductor region 131 and the second semiconductor region 132.

[0103] Next, the semiconductor substrate 800 is thermally oxidized to form an insulating layer 811. The insulating layer 811 is formed in the trench 810 and on the substrate upper surface 801, and is also formed by thermally oxidizing the sidewalls and bottom wall of the trench 810. This insulating layer 811 is made of SiO2. Thereafter, the insulating layer 811 formed on the substrate upper surface 801 is removed. As a result, the insulating layer 811 separates the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 in a planar view. In this state, the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 are electrically connected.

[0104] 9 and 10 show one trench 810 for ease of understanding, but multiple trenches 810 may be formed depending on the width dimension of the insulating layer 811. In this case, by thermally oxidizing the semiconductor substrate 800, an oxide film is formed spanning the multiple trenches 810, and the wall portions of the semiconductor substrate 800 between the trenches 810 are oxidized to form the insulating layer 811. In this way, the insulating layer 811 is composed of an insulating film buried in the multiple trenches 810, oxide formed on the sidewalls and bottom walls of each trench 810, and oxide as the wall portions between the trenches. The multiple trenches 810 may be formed so that the distance between the trenches 810 is equal to or less than the thickness of the oxide film.

[0105] 11 to 14, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the element insulating layer 72, forming a portion of the inner connecting wirings 45A and 45B, and forming a portion of the element insulating layer 72. FIG. 11 shows a planar structure of a semiconductor substrate 800 including the lowermost insulating film 75L. FIG. 12 shows an end surface structure obtained by cutting the semiconductor substrate 800 along line F12-F12 in FIG. 11. FIG. 13 shows a planar structure of the semiconductor substrate 800 including a portion of the element insulating layer 72. FIG. 14 shows an end surface structure obtained by cutting the semiconductor substrate 800 along line F14-F14 in FIG. 13.

[0106] 11 and 12, in the step of forming a part of the element insulating layer 72, a lowermost insulating film 75L is formed. The insulating film 75L is formed on the substrate upper surface 801 of the semiconductor substrate 800 by, for example, chemical vapor deposition (CVD). In one example, the insulating film 75L is made of SiO2.

[0107] Subsequently, in the process of forming a portion of the inner connection wirings 45A, 45B, the connection wirings 45AB, 45BB and wiring portions below the pad connection portions 45AC, 45BC are formed on the insulating film 75L by, for example, at least one of a sputtering method and electrolytic plating. The connection wirings 45AB, 45BB and the wiring portions below the pad connection portions 45AC, 45BC are made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W.

[0108] 13 and 14, in the step of forming a part of the element insulating layer 72, two insulating films 75 are formed on the lowermost insulating film 75L. The insulating films 75 are deposited on the insulating film 75L by CVD, similar to the insulating film 75L. The insulating film 75 includes a first insulating film 75A and a second insulating film 75B.

[0109] Next, in the process of forming a portion of the inner connection wirings 45A, 45B, first, through-holes are formed in the insulating film 75 by, for example, etching, to expose the ends of the connection wirings 45AB, 45BB that are farther from the wiring portions. Through-holes are also formed in the insulating film 75 to expose portions of the wiring portions. Next, vias are formed in the through-holes by, for example, at least one of sputtering and electroplating. This results in the formation of the coil connection portions 45AA, 45BA and the vias in the pad connection portions 45AC, 45BC. The coil connection portions 45AA, 45BA and the vias in the pad connection portions 45AC, 45BC are made of a material containing, for example, one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriate.

[0110] 15 and 16, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the element insulating layer 72, forming the first coil 41 and the fourth coil 44, and forming portions of the inner connecting wirings 45A and 45B and the outer connecting wirings 46A and 46B. Fig. 15 shows a planar structure of a semiconductor substrate 800 including a portion of the element insulating layer 72. Fig. 16 shows an end surface structure obtained by cutting the semiconductor substrate 800 along line F16-F16 in Fig. 15.

[0111] In the step of forming a part of the element insulating layer 72, one layer of insulating film 75 is formed on the insulating film 75 shown in Fig. 14. The insulating film 75 is deposited on the insulating film 75 shown in Fig. 14 by, for example, CVD. The insulating film 75 includes a first insulating film 75A and a second insulating film 75B.

[0112] Next, in the process of forming the first coil 41 and the fourth coil 44, first, coil grooves are formed in the insulating film 75 in regions where the first coil 41 and the fourth coil 44 are to be formed, for example, by etching. The coil grooves are formed as grooves that penetrate, for example, one layer of the insulating film 75 in the Z direction. Next, a material containing one or more appropriately selected elements of Ti, TiN, Au, Ag, Cu, Al, and W is filled into the coil grooves by, for example, at least one of sputtering and electroplating. This forms the first coil 41 and the fourth coil 44. In one example, Cu is filled into the coil grooves. As a result, the first coil 41 and the fourth coil 44 are formed from Cu.

[0113] In addition, in the process of forming a portion of the inner connection wiring 45A, 45B, through-holes exposing the vias of the pad connection portions 45AC, 45BC are formed, for example, by etching. The through-holes are formed, for example, in the same process as the coil grooves. Then, vias are formed in the through-holes by at least one of sputtering and electrolytic plating. The vias are made of a material containing one or more appropriately selected from the group consisting of Ti, TiN, Au, Ag, Cu, Al, and W.

[0114] In the process of forming the outer connection wirings 46A and 46B, first, wiring grooves are formed in the insulating film 75 in regions where the outer connection wirings 46A and 46B are to be formed, for example, by etching. The wiring grooves are formed, for example, as grooves penetrating one layer of the insulating film 75 in the Z direction. The wiring grooves are formed, for example, in the same process as the coil grooves. Next, a material containing one or more appropriately selected elements selected from Ti, TiN, Au, Ag, Cu, Al, and W is filled into the wiring grooves by, for example, at least one of sputtering and electrolytic plating. This forms the connection wirings 46AA and 46BA and the wiring portions of the pad connection portions 46AB and 46BB.

[0115] The outer connection wirings 46A, 46B may be formed simultaneously with the first coil 41 and the fourth coil 44. That is, after a coil groove and a wiring groove communicating with the coil groove are formed in the insulating film 75, a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W is filled into the coil groove and the wiring groove. This simultaneously forms the first coil 41, the fourth coil 44, the connection wirings 46AA, 46BA, and the wiring portions of the pad connection portions 46AB, 46BB.

[0116] 17 and 18, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the element insulating layer 72 and forming portions of the inner connecting wirings 45A and 45B and the outer connecting wirings 46A and 46B. Fig. 17 shows a planar structure of a semiconductor substrate 800 including a portion of the element insulating layer 72. Fig. 18 shows an end surface structure obtained by cutting the semiconductor substrate 800 along line F18-F18 in Fig. 17.

[0117] In the step of forming a part of the element insulating layer 72, a three-layer insulating film 75 is formed on the insulating film 75 shown in Fig. 16. The insulating film 75 is deposited on the insulating film 75 shown in Fig. 16 by, for example, CVD. The insulating film 75 includes a first insulating film 75A and a second insulating film 75B.

[0118] In the process of forming a portion of the inner connection wiring 45A, 45B, through holes exposing the vias of the pad connection portions 45AC, 45BC are formed, for example, by etching. Then, vias are formed in the through holes by at least one of sputtering and electrolytic plating. The vias are made of a material containing one or more appropriately selected from the group consisting of Ti, TiN, Au, Ag, Cu, Al, and W.

[0119] In the process of forming a portion of the outer connection wirings 46A, 46B, through holes are formed by, for example, etching, exposing a portion of the wiring portion of the pad connection portions 46AB, 46BB. Subsequently, vias are formed in the through holes by, for example, at least one of sputtering and electrolytic plating. The vias are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. After one layer of insulating film 75 is formed, the process of forming the vias of the inner connection wirings 45A, 45B and the vias of the outer connection wirings 46A, 46B may be repeated three times.

[0120] 19 and 20, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the element insulating layer 72, forming the second coil 42 and the third coil 43, forming portions of the inner connecting wirings 45A and 45B and portions of the outer connecting wirings 46A and 46B, and forming a portion of the connecting wiring 47. Fig. 19 shows the planar structure of a semiconductor substrate 800 including a portion of the element insulating layer 72. Fig. 20 shows the end surface structure of the semiconductor substrate 800 cut along line F20-F20 in Fig. 19.

[0121] In the step of forming a part of the element insulating layer 72, one layer of insulating film 75 is formed on the insulating film 75 shown in Fig. 18. The insulating film 75 is deposited on the insulating film 75 shown in Fig. 18 by, for example, CVD. The insulating film 75 includes a first insulating film 75A and a second insulating film 75B.

[0122] Next, in the process of forming the second coil 42 and the third coil 43, first, coil grooves are formed in the insulating film 75 in regions where the second coil 42 and the third coil 43 are to be formed, for example, by etching. The coil grooves are formed as grooves that penetrate, for example, one layer of the insulating film 75 in the Z direction. Next, a material containing one or more appropriately selected elements from Ti, TiN, Au, Ag, Cu, Al, and W is filled into the coil grooves by, for example, at least one of sputtering and electroplating. This forms the second coil 42 and the third coil 43. In one example, Cu is filled into the coil grooves. As a result, the second coil 42 and the third coil 43 are formed from Cu.

[0123] In addition, in the process of forming a portion of the inner connection wiring 45A, 45B, through-holes are formed by, for example, etching, exposing the entire vias of the pad connection portions 45AC, 45BC. The through-holes are formed, for example, in the same process as the coil grooves. Subsequently, wiring portions are formed in the through-holes by, for example, at least one of sputtering and electrolytic plating. The wiring portions are made of a material containing one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W.

[0124] In the process of forming the outer connection wirings 46A and 46B, first, through-holes are formed in the insulating film 75 by, for example, etching, exposing the entire vias of the pad connection portions 46AB and 46BB. The through-holes are formed, for example, in the same process as the coil grooves. Next, a material containing one or more appropriately selected elements selected from Ti, TiN, Au, Ag, Cu, Al, and W is filled into the through-holes by, for example, at least one of sputtering and electroplating. This forms the wiring portions of the pad connection portions 46AB and 46BB.

[0125] In the process of forming a portion of the connection wiring 47, a wiring groove communicating with the coil groove is first formed, for example, by etching. The wiring groove is formed as a groove penetrating, for example, one layer of the insulating film 75 in the Z direction. Next, a material containing one or more appropriately selected elements of, for example, Ti, TiN, Au, Ag, Cu, Al, and W is filled into the wiring groove by, for example, at least one of sputtering and electroplating. This forms the second connection wiring 47B.

[0126] 21 and 22, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the element insulating layer 72, forming portions of the inner connecting wirings 45A and 45B and portions of the outer connecting wirings 46A and 46B, and forming a portion of the connecting wiring 47. Fig. 21 shows the planar structure of a semiconductor substrate 800 including a portion of the element insulating layer 72. Fig. 22 shows the end surface structure of the semiconductor substrate 800 cut along line F22-F22 in Fig. 21.

[0127] In the step of forming a part of the element insulating layer 72, an insulating film 75 is formed on the insulating film 75 shown in Fig. 20. The insulating film 75 is deposited on the insulating film 75 shown in Fig. 20 by, for example, CVD. The insulating film 75 includes a first insulating film 75A and a second insulating film 75B.

[0128] Next, in the process of forming a portion of the inner connection wiring 45A, 45B, through holes are formed by, for example, etching, exposing a portion of the wiring portion of the pad connection portion 45AC, 45BC. Then, vias are formed in the through holes by, for example, at least one of sputtering and electrolytic plating. The vias are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. Through these processes, the inner connection wiring 45A, 45B is formed.

[0129] In the process of forming the outer connection wirings 46A and 46B, first, through holes are formed in the insulating film 75 by, for example, etching, exposing portions of the wiring portions of the pad connection portions 46AB and 46BB. Next, vias are formed in the through holes by, for example, at least one of sputtering and electrolytic plating. The vias are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. Through the above steps, the outer connection wirings 46A and 46B are formed.

[0130] In the process of forming a portion of the connection wiring 47, first, through holes are formed by, for example, etching, exposing the inner ends of the second coil 42 and the third coil 43. Next, vias are formed in the through holes by, for example, at least one of sputtering and electrolytic plating. The vias are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. This forms the first coil connection portion 47AA and the second coil connection portion 47AC of the first connection wiring 47A in the connection wiring 47.

[0131] 23 and 24, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the connection wiring 47 and forming the first pads 73 and the second pads 74. Fig. 23 shows the planar structure of the element insulating layer 72. Fig. 24 shows the end surface structure obtained by cutting the semiconductor substrate 800 along line F24-F24 in Fig. 23.

[0132] In the step of forming a part of the connection wiring 47, a coil connection wiring 47AB connecting the first coil connection portion 47AA and the second coil connection portion 47AC is formed on the insulating film 75 below one of the uppermost insulating films 75U by, for example, at least one of sputtering and electrolytic plating. Through the above steps, the connection wiring 47 is formed.

[0133] In the step of forming the first pad 73 and the second pad 74, the first pad 73 and the second pad 74 are formed on the insulating film 75 below one of the uppermost insulating films 75U by, for example, at least one of a sputtering method and electrolytic plating. Note that the coil connection wiring 47AB, the first pad 73, and the second pad 74 may be formed in a common step.

[0134] 25 and 26, the method for manufacturing the insulating chip 70 includes the steps of forming a portion of the element insulating layer 72, forming a protective layer 76, and forming an insulating region 140. Fig. 25 shows the planar structure of the protective layer 76. Fig. 26 shows the end surface structure obtained by cutting the semiconductor substrate 800 along line F26-F26 in Fig. 25.

[0135] In the step of forming a part of the element insulating layer 72, an uppermost insulating film 75U is formed on the insulating film 75 shown in FIG. 24. The insulating film 75U is deposited on the insulating film 75 shown in FIG. 24 by, for example, CVD. The insulating film 75U surrounds the first pad 73, the second pad 74, and the coil connection wiring 47AB in plan view. The insulating film 75U includes a first insulating film 75A and a second insulating film 75B. Through the above steps, the element insulating layer 72 is formed.

[0136] In the step of forming the protective layer 76, the protective layer 76 is formed by, for example, CVD so as to be deposited on the upper surface of the element insulating layer 72. The protective layer 76 covers the coil connection wiring 47AB, the first pad 73, and the second pad 74. Subsequently, openings are formed by, for example, etching so as to expose portions of both the first pad 73 and the second pad 74.

[0137] The step of forming the insulating region 140 includes a step of grinding the semiconductor substrate 800. In the step of grinding the semiconductor substrate 800, the substrate lower surface 802 of the semiconductor substrate 800 is ground by, for example, chemical mechanical polishing (CMP). In one example, the semiconductor substrate 800 is ground down to the dashed-dotted line CL shown in FIG. 26 . As a result, the insulating layer 811 is exposed from the substrate lower surface 802 of the ground semiconductor substrate 800. As a result, the insulating region 140 is formed, which insulates the first semiconductor region 131, the second semiconductor region 132, and the outer periphery region 133 from one another. The insulating region 140 includes a first insulating region 141 and a second insulating region 142. In other words, the step of forming the insulating region 140 includes forming a frame-shaped first insulating region 141 that surrounds the first semiconductor region 131 in a plan view, and forming a frame-shaped second insulating region 142 that surrounds the second semiconductor region 132 in a plan view. Through the above steps, the insulating chip 70 is manufactured.

[0138] [Operation of the first embodiment] The operation of the first embodiment will be described. When the semiconductor substrate of the insulating chip is bonded to the first die pad 81 and the second die pad 91 with a conductive adhesive, the first die pad 81 and the second die pad 91 are electrically connected through the semiconductor substrate. As a result, the potential of the semiconductor substrate depends on the first die pad 81 or the second die pad 91, which may reduce the dielectric strength of the insulating chip.

[0139] In this regard, in the first embodiment, the insulating region 140 of the semiconductor substrate 71 electrically insulates the first semiconductor region 131 from the second semiconductor region 132. The first semiconductor region 131 is bonded to the first die pad 81 by a first bonding material 121, which is a conductive bonding material, and the second semiconductor region 132 is bonded to the second die pad 91 by a second bonding material 122, which is a conductive bonding material. This reduces the dependence of the first semiconductor region 131 on the potential of the second die pad 91, and reduces the dependence of the second semiconductor region 132 on the potential of the first die pad 81. The first semiconductor region 131 is located at a position overlapping both the first coil 41 and the second coil 42 in a plan view, and the second semiconductor region 132 is located at a position overlapping both the third coil 43 and the fourth coil 44 in a plan view. This prevents the dielectric strength voltage of the insulating chip 70 from decreasing due to the distance in the Z direction between the first coil 41, which is closer to the first semiconductor region 131 than the second coil 42, and the first semiconductor region 131, or the distance in the Z direction between the fourth coil 44, which is closer to the second semiconductor region 132 than the third coil 43, and the second semiconductor region 132.

[0140] [Effects of the first embodiment] The insulating chip 70 and semiconductor device 10 of the first embodiment provide the following advantages. (1-1) The insulating chip 70 includes a semiconductor substrate 71, an element insulating layer 72 provided on the semiconductor substrate 71, and a first coil 41 and a fourth coil 44 provided on the element insulating layer 72 and spaced apart from each other in the X direction, a second coil 42 arranged opposite the first coil 41 in the Z direction, and a third coil 43 arranged opposite the fourth coil 44 in the Z direction. The semiconductor substrate 71 includes a first semiconductor region 131, a second semiconductor region 132 arranged opposite the first semiconductor region 131 in the X direction, and an insulating region 140 that insulates the first semiconductor region 131 from the second semiconductor region 132. In a plan view, both the first coil 41 and the second coil 42 are spaced apart from the second semiconductor region 132 and are arranged so that at least a portion of each coil overlaps with the first semiconductor region 131. In a plan view, both the third coil 43 and the fourth coil 44 are disposed so as to be spaced apart from the first semiconductor region 131 and so as to overlap at least a portion of the second semiconductor region 132.

[0141] According to this configuration, a double insulation structure is formed by the first to fourth coils 41 to 44, thereby achieving a high withstand voltage for the insulating chip 70. In addition, a decrease in the withstand voltage of the insulating chip 70 due to the distance between the first semiconductor region 131 and the first coil 41 and the distance between the second semiconductor region 132 and the fourth coil 44 can be suppressed.

[0142] (1-2) Both the first semiconductor region 131 and the second semiconductor region 132 are made of a material containing Si. The insulating region 140 is made of SiO2. According to this configuration, the insulating region 140 can be formed by, for example, thermally oxidizing the semiconductor substrate 71, and therefore the insulating region 140 can be easily formed.

[0143] (1-3) The width dimension WR of the insulating region 140 is smaller than the dimension HR of the insulating region 140 in the thickness direction. According to this configuration, the strength of the insulating chip 70 is ensured by the thickness of the semiconductor substrate 71, and insulation between the first semiconductor region 131 and the second semiconductor region 132 can be ensured.

[0144] (1-4) The insulating region 140 includes a frame-shaped first insulating region 141 that surrounds the first semiconductor region 131 in a planar view, and a frame-shaped second insulating region 142 that surrounds the second semiconductor region 132 in a planar view.

[0145] According to this configuration, both the first semiconductor region 131 and the second semiconductor region 132 are surrounded by the insulating region 140 in a plan view, and therefore the first semiconductor region 131 and the second semiconductor region 132 can be reliably insulated from each other.

[0146] (1-5) The insulating region 140 includes an intermediate insulating region 143 provided between the first semiconductor region 131 and the second semiconductor region 132 in the X direction. The intermediate insulating region 143 constitutes a part of the first insulating region 141 and the second insulating region 142.

[0147] According to this configuration, the first insulating region 141 and the second insulating region 142 are integrated by the intermediate insulating region 143. This allows the semiconductor substrate 71 to be made smaller in size in the X direction compared to a configuration in which the first insulating region 141 and the second insulating region 142 are provided spaced apart in the X direction. Therefore, the insulating chip 70 can be made smaller.

[0148] (1-6) The insulating chip 70 includes a connection wiring 47 that is provided on the element insulating layer 72 and electrically connects the second coil 42 and the third coil 43. With this configuration, the conductive path between the second coil 42 and the third coil 43 can be made shorter than when the second coil 42 and the third coil 43 are electrically connected by a wire outside the insulating chip, for example. Therefore, the inductance caused by the length of this conductive path can be reduced.

[0149] (1-7) The semiconductor device 10 includes a first die pad 81, a second die pad 91 disposed apart from the first die pad 81 in the X direction, and an insulating chip 70 disposed so as to straddle the first die pad 81 and the second die pad 91 in the X direction. The insulating chip 70 includes a semiconductor substrate 71, an element insulating layer 72 provided on the semiconductor substrate 71, a first coil 41 and a fourth coil 44 embedded in the element insulating layer 72 and disposed apart from each other in the X direction, a second coil 42 disposed opposite the first coil 41 in the Z direction, and a third coil 43 disposed opposite the fourth coil 44 in the Z direction. The semiconductor substrate 71 includes a first semiconductor region 131, a second semiconductor region 132 disposed apart from the first semiconductor region 131 in the X direction, and an insulating region 140 that insulates the first semiconductor region 131 from the second semiconductor region 132. In a plan view, both the first coil 41 and the second coil 42 are spaced apart from the second semiconductor region 132 and are arranged so that at least a portion of each coil overlaps with the first semiconductor region 131. In a plan view, both the third coil 43 and the fourth coil 44 are spaced apart from the first semiconductor region 131 and are arranged so that at least a portion of each coil overlaps with the second semiconductor region 132.

[0150] According to this configuration, a double insulation structure is formed by the first to fourth coils 41 to 44, thereby increasing the withstand voltage of the insulating chip 70. In addition, because the first to fourth coils 41 to 44 are provided on a single insulating chip, the semiconductor device 10 can be made more compact than in a configuration in which a first insulating chip including the first coil 41 and the second coil 42 and a second insulating chip including the third coil 43 and the fourth coil 44 are provided. In addition, a decrease in the withstand voltage of the insulating chip 70 due to the distance between the first semiconductor region 131 and the first coil 41 and the distance between the second semiconductor region 132 and the fourth coil 44 can be suppressed.

[0151] (1-8) The first semiconductor region 131 is bonded to the first die pad 81 by a conductive first bonding material 121. The second semiconductor region 132 is bonded to the second die pad 91 by a conductive second bonding material 122. The insulating region 140 includes a frame-shaped first insulating region 141 that surrounds the first semiconductor region 131 in a planar view, and a frame-shaped second insulating region 142 that surrounds the second semiconductor region 132 in a planar view. The semiconductor substrate 71 includes a peripheral region 133 that surrounds the first insulating region 141 and the second insulating region 142. The first bonding material 121 is not in contact with the peripheral region 133 of the semiconductor substrate 71, but is in contact with the first semiconductor region 131. The second bonding material 122 is not in contact with the peripheral region 133 of the semiconductor substrate 71, but is in contact with the second semiconductor region 132.

[0152] This configuration can prevent the first semiconductor region 131 and the outer periphery region 133 from being electrically connected via the first bonding material 121, and can prevent the second semiconductor region 132 and the outer periphery region 133 from being electrically connected via the second bonding material 122. Therefore, it is possible to prevent a decrease in the dielectric strength voltage of the insulating chip 70 due to the distance between the first coil 41 and the fourth coil 44 and the outer periphery region 133.

[0153] (1-9) The first chip 50 includes a first semiconductor substrate 51. The second chip 60 includes a second semiconductor substrate 61. A thickness TR of the semiconductor substrate 71 of the insulating chip 70 is thinner than a thickness TA of the first semiconductor substrate 51 and a thickness TB of the second semiconductor substrate 61. With this configuration, the insulating chip 70 can be made thinner.

[0154] (1-10) The inter-region distance DR between the first semiconductor region 131 and the second semiconductor region 132 in the X direction is smaller than the inter-pad distance PR between the first die pad 81 and the second die pad 91 in the X direction. This configuration can prevent a decrease in the dielectric strength voltage of the insulating chip 70 due to the inter-pad distance PR.

[0155] (1-11) The inter-region distance DR between the first semiconductor region 131 and the second semiconductor region 132 in the X direction is greater than the distance DA between the first coil 41 and the second coil 42 in the Z direction. This configuration can prevent the insulation withstand voltage of the insulating chip 70 from decreasing due to the inter-region distance DR.

[0156] Second Embodiment 27 to 32, the semiconductor device 10 of the second embodiment will be described. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the insulating chip 70. In the following, components common to the semiconductor device 10 of the first embodiment will be given the same reference numerals, and descriptions thereof will be omitted.

[0157] 27, the insulating chip 70 includes a first unit 150 and a second unit 160 disposed on the first unit 150. In one example, the second unit 160 is electrically insulated from the first unit 150.

[0158] 29, the first unit 150 includes a first semiconductor substrate 151, a first element insulating layer 152 provided on the first semiconductor substrate 151, and a first coil 41 and a fourth coil 44. The first coil 41 and the fourth coil 44 are embedded in the first element insulating layer 152. The first coil 41 and the fourth coil 44 are electrically insulated from each other, similar to the first embodiment.

[0159] The first semiconductor substrate 151 includes the same configuration as the semiconductor substrate 71 of the first embodiment (see FIGS. 6 and 7). That is, the first semiconductor substrate 151 includes a first semiconductor region 131, a second semiconductor region 132, a peripheral region 133, and an insulating region 140. The first semiconductor substrate 151 may be made of a material containing Si. The insulating region 140 may be made of SiO2. The insulating region 140 may include a first insulating region 141, a second insulating region 142, and an intermediate insulating region 143.

[0160] The first element insulating layer 152 has the same configuration as the element insulating layer 72 of the first embodiment (see FIG. 7). The first coil 41 and the fourth coil 44 are arranged closer to the first semiconductor substrate 151 than the center of the first element insulating layer 152 in the Z direction. As in the first embodiment, the first element insulating layer 152 is provided with inner connecting wirings 45A and 45B and outer connecting wirings 46A and 46B.

[0161] The first unit 150 includes a first pad 73 and a second pad 74 provided on a first element insulating layer 152 , and a first protective layer 153 covering the first element insulating layer 152 . The number and arrangement of the first pads 73 and the second pads 74 are the same as those in the first embodiment. The configurations of the first pads 73 and the second pads 74 are the same as those in the first embodiment. The configuration of the first protective layer 153 is the same as that of the protective layer 76 in the first embodiment.

[0162] 28, the second unit 160 has a rectangular shape that is slightly smaller than the first unit 150 in a plan view. Therefore, in a state where the second unit 160 is arranged on the first unit 150 (hereinafter referred to as the "unit arranged state"), the first pad 73 and the second pad 74 of the first unit 150 are arranged in different positions from the second unit 160.

[0163] 29, the second unit 160 includes a second semiconductor substrate 161, a second element insulating layer 162 stacked on the second semiconductor substrate 161, and a second coil 42 and a third coil 43. The second coil 42 and the third coil 43 are embedded in the second element insulating layer 162.

[0164] The second semiconductor substrate 161 is made of a material containing Si, similar to the first semiconductor substrate 151. However, unlike the first semiconductor substrate 151, the second semiconductor substrate 161 does not include an insulating region 140. The second semiconductor substrate 161 is disposed on the opposite side of the second element insulating layer 162 from the first unit 150 in the Z direction.

[0165] The second element insulating layer 162 has the same configuration as the first element insulating layer 152. The second coil 42 and the third coil 43 are arranged closer to the second semiconductor substrate 161 than the center of the second element insulating layer 162 in the Z direction. As in the first embodiment, a connection wiring 47 is provided in the second element insulating layer 162. This electrically connects the second coil 42 and the third coil 43 to each other.

[0166] The first connection wiring 47A of the connection wiring 47 is arranged on the opposite side of the first unit 150 in the Z direction with respect to the second coil 42 and the third coil 43. The second connection wiring 47B is arranged in the same position in the Z direction as the second coil 42 and the third coil 43. Thus, in the second embodiment as well, the connection wiring 47 is not arranged between the first coil 41 and the second coil 42 (between the third coil 43 and the fourth coil 44) in the Z direction.

[0167] The second unit 160 includes a second protective layer 163 that covers the second element insulating layer 162. The configuration of the second protective layer 163 is the same as, for example, the configuration of the first protective layer 153. In one example, in the unit arrangement state, the second protective layer 163 contacts the first protective layer 153.

[0168] 29, in the unit arrangement state, the first coil 41 and the second coil 42 face each other in the Z direction. The third coil 43 and the fourth coil 44 face each other in the Z direction.

[0169] The distance DA between the first coil 41 and the second coil 42 in the Z direction is equal to the distance DB between the third coil 43 and the fourth coil 44 in the Z direction. The distance DC between the first coil 41 and the fourth coil 44 in the X direction is equal to the distance DD between the second coil 42 and the third coil 43 in the X direction.

[0170] The distance DC between the first coil 41 and the fourth coil 44 in the X direction (the distance DD between the second coil 42 and the third coil 43 in the X direction) is larger than the width dimension WR3 of the intermediate insulating region 143. The distance DA between the first coil 41 and the second coil 42 in the Z direction (the distance DB between the third coil 43 and the fourth coil 44 in the Z direction) is equal to or larger than the width dimension WR3 of the intermediate insulating region 143. Therefore, it can be said that the inter-region distance DR is smaller than the distance DC between the first coil 41 and the fourth coil 44 in the X direction (the distance DD between the second coil 42 and the third coil 43 in the X direction). It can be said that the inter-region distance DR is equal to or smaller than the distance DA between the first coil 41 and the second coil 42 in the Z direction (the distance DB between the third coil 43 and the fourth coil 44 in the Z direction). As in the first embodiment, the inter-region distance DR (the width dimension WR3 of the intermediate insulating region 143) is smaller than the inter-pad distance PR (see FIG. 27 ).

[0171] The first semiconductor region 131 of the first semiconductor substrate 151 of the first unit 150 is bonded to the first die pad 81 by a first bonding material 121. The second semiconductor region 132 of the first semiconductor substrate 151 is bonded to the second die pad 91 by a second bonding material 122. The bonding between the first semiconductor substrate 151 and the first die pad 81 by the first bonding material 121 and the bonding between the first semiconductor substrate 151 and the second die pad 91 by the second bonding material 122 are the same as those in the first embodiment. As shown in FIG. 28 , the thickness TS of the first semiconductor substrate 151 is thinner than the thickness TA of the first semiconductor substrate 51 of the first chip 50 and the thickness TB of the second semiconductor substrate 61 of the second chip 60.

[0172] [Insulating chip manufacturing method] An example of a manufacturing method for the insulating chip 70 of the second embodiment will be described with reference to Figures 30 and 31. Figure 30 schematically shows a perspective view of an example of the manufacturing process for the insulating chip 70. Figure 31 schematically shows a cross-sectional view of an example of the manufacturing process for the insulating chip 70.

[0173] As shown in FIG. 30, the method for manufacturing an insulating chip 70 includes preparing a first semiconductor wafer 910 and a second semiconductor wafer 920. The first semiconductor wafer 910 is a wafer on which a plurality of first units 150 are formed. For example, a Si wafer is used as the first semiconductor wafer 910. The second semiconductor wafer 920 is a wafer on which a plurality of second units 160 are formed. For example, a Si wafer is used as the second semiconductor wafer 920.

[0174] Next, the method for manufacturing the insulating chip 70 includes dividing the second semiconductor wafer 920 into individual pieces. In one example, the second semiconductor wafer 920 is cut by a dicing process. More specifically, the second semiconductor wafer 920 is placed on a dicing tape 930. Then, the second semiconductor wafer 920 is cut by a dicing blade 940. As a result, a plurality of second units 160 are manufactured.

[0175] Next, the method for manufacturing the insulating chip 70 includes a step of bonding a plurality of second units 160 to the first semiconductor wafer 910. More specifically, in this step, as shown in FIG. 31 , the second units 160 are bonded to the regions of the first semiconductor wafer 910 where the first units 150 are formed. The second units 160 are placed on the first units 150 so that the second protective layer 163 contacts the first protective layer 153 of the first units 150. Then, the first protective layer 153 and the second protective layer 163 are bonded to each other.

[0176] Next, the method for manufacturing the insulating chip 70 includes a step of dividing the first semiconductor wafer 910 into individual pieces. In one example, the first semiconductor wafer 910 is cut by a dicing process. Through the above steps, the insulating chip 70 is manufactured.

[0177] [effect] The insulating chip 70 and semiconductor device 10 of the second embodiment provide the following advantages. (2-1) The insulating chip 70 includes a first unit 150 and a second unit 160 arranged on the first unit 150. The first unit 150 includes a first semiconductor substrate 151, a first element insulating layer 152 provided on the first semiconductor substrate 151, and a first coil 41 and a fourth coil 44 embedded in the first element insulating layer 152, arranged spaced apart from each other in the X direction, and electrically insulated from each other. The first semiconductor substrate 151 includes a first semiconductor region 131, a second semiconductor region 132 arranged spaced apart from the first semiconductor region 131 in the X direction, and an insulating region 140 that insulates the first semiconductor region 131 from the second semiconductor region 132. The second unit 160 includes a second element insulating layer 162 provided on the first element insulating layer 152, and a second coil 42 and a third coil 43 embedded in the second element insulating layer 162, spaced apart from each other in the X direction, and electrically connected to each other. The first coil 41 and the second coil 42 are arranged opposite each other in the Z direction. The third coil 43 and the fourth coil 44 are arranged opposite each other in the Z direction.

[0178] According to this configuration, a double insulation structure is formed by the first to fourth coils 41 to 44, thereby achieving a high withstand voltage for the insulating chip 70. In addition, a decrease in the withstand voltage of the insulating chip 70 due to the distance between the first semiconductor region 131 and the first coil 41 and the distance between the second semiconductor region 132 and the fourth coil 44 can be suppressed.

[0179] In addition, the element insulating layer between the first coil 41 and the second coil 42 in the Z direction and the element insulating layer between the third coil 43 and the fourth coil 44 in the Z direction can be provided separately in the Z direction, such as the first element insulating layer 152 and the second element insulating layer 162. Furthermore, since the first to fourth coils 41 to 44 are provided in the element insulating layer provided by the first element insulating layer 152 and the second element insulating layer 162 stacked in the Z direction, it is possible to increase the distance DA between the first coil 41 and the second coil 42 in the Z direction and the distance DB between the third coil 43 and the fourth coil 44 in the Z direction. This allows the insulation chip 70 to have an improved dielectric strength.

[0180] (2-2) The first unit 150 includes a first pad 73 electrically connected to the first coil 41 and exposed in the Z direction from the first element insulating layer 152, and a second pad 74 electrically connected to the fourth coil 44 and exposed in the Z direction from the first element insulating layer 152.

[0181] According to this configuration, the length of the conductive path between the first pad 73 and the first coil 41 and the length of the conductive path between the second pad 74 and the fourth coil 44 can be shortened compared to a configuration in which the first pad 73 and the second pad 74 are provided in the second unit 160. In addition, because the first pad 73 and the second pad 74 are each provided in the first element insulating layer 152, the first pad 73 and the second pad 74 can each be formed more easily compared to, for example, a configuration in which the first pad 73 and the second pad 74 are provided so as to penetrate the second semiconductor substrate 161.

[0182] (2-3) The second unit 160 is smaller in plan view than the first unit 150. The first pad 73 and the second pad 74 are both provided at positions different from those of the second unit 160 in plan view.

[0183] According to this configuration, since second unit 160 is smaller than first unit 150 in a plan view, first pad 73 and second pad 74 are exposed from second unit 160 even without providing second unit 160 with a configuration for exposing first pad 73 and second pad 74. Therefore, second unit 160 can have a simple shape such as a rectangle. Therefore, the manufacturing cost of second unit 160 can be reduced.

[0184] (2-4) The first coil 41 and the fourth coil 44 are disposed closer to the first semiconductor substrate 151 than the center of the first element insulating layer 152 in the Z direction. This configuration allows the distance DA between the first coil 41 and the second coil 42 in the Z direction and the distance DB between the third coil 43 and the fourth coil 44 in the Z direction to be increased, thereby improving the dielectric strength of the insulating chip 70.

[0185] (2-5) The second coil 42 and the third coil 43 are disposed closer to the second semiconductor substrate 161 than the center of the second element insulating layer 162 in the Z direction. This configuration allows the distance DA between the first coil 41 and the second coil 42 in the Z direction and the distance DB between the third coil 43 and the fourth coil 44 in the Z direction to be increased, thereby improving the dielectric strength of the insulating chip 70.

[0186] Third Embodiment 32 to 35, the semiconductor device 10 of the third embodiment will be described. The semiconductor device 10 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the insulating chip 70. In the following, components common to the semiconductor device 10 of the first embodiment are given the same reference numerals, and descriptions thereof will be omitted.

[0187] Fig. 32 shows a simplified example of the circuit configuration of the semiconductor device 10 of the third embodiment. Fig. 33 schematically shows the planar structure of the insulating chip 70. Fig. 34 schematically shows the cross-sectional structure of the insulating chip 70 cut along the XY plane. Fig. 35 schematically shows the cross-sectional structure of the insulating chip 70 cut along line F34-F34 in Fig. 33.

[0188] 32, the semiconductor device 10 includes a capacitor 170 instead of the transformer 40. The capacitor 170 is configured to transmit a signal from the first circuit 20 to the second circuit 30 while electrically insulating the first circuit 20 from the second circuit 30. The capacitor 170 includes a first capacitor 171 and a second capacitor 172 connected in series to each other.

[0189] First capacitor 171 includes first electrode plate 171A and second electrode plate 171B that constitute the electrodes of first capacitor 171. Second capacitor 172 includes first electrode plate 172A and second electrode plate 172B that constitute the electrodes of second capacitor 172.

[0190] First capacitor 171 is electrically connected to first circuit 20, and second capacitor 172 is electrically connected to second circuit 30. More specifically, first electrode plate 171A of first capacitor 171 is electrically connected to first circuit 20. Second electrode plate 172B of second capacitor 172 is electrically connected to second circuit 30. Second electrode plate 171B of first capacitor 171 and first electrode plate 172A of second capacitor 172 are electrically connected to each other. Therefore, second electrode plate 171B and first electrode plate 172A are in an electrically floating state.

[0191] In the third embodiment, first electrode plate 171A of capacitor 171 is an example of a "first insulating element," and second electrode plate 171B is an example of a "second insulating element." First electrode plate 172A of capacitor 172 is an example of a "third insulating element," and second electrode plate 172B is an example of a "fourth insulating element."

[0192] 33 to 35, the insulating chip 70 of the semiconductor device 10 includes a capacitor 170 instead of the transformer 40 (see FIG. 1). The semiconductor substrate 71 and the element insulating layer 72 in the insulating chip 70 are the same as those in the first embodiment. The insulating chip 70 includes a first pad 73 and a second pad 74. In the third embodiment, there is one each of the first pad 73 and the second pad 74.

[0193] Each of the first electrode plates 171A, 172A and the second electrode plates 171B, 172B of the first capacitor 171 and the second capacitor 172 is flat with its thickness direction in the Z direction. As shown in Figures 33 and 34, the first electrode plates 171A, 172A and the second electrode plates 171B, 172B are rectangular in plan view. Each of the first electrode plates 171A, 172A and the second electrode plates 171B, 172B is provided on the element insulating layer 72.

[0194] As shown in FIG. 35, the first electrode plate 171A and the second electrode plate 172B are disposed at the same position in the Z direction and spaced apart from each other in the X direction. The first electrode plate 171A and the second electrode plate 172B are disposed closer to the semiconductor substrate 71 than the center of the element insulating layer 72 in the Z direction. In the example shown in FIG. 35, the first electrode plate 171A and the second electrode plate 172B are disposed so as to penetrate in the Z direction through the insulating film 75 that is three layers above the lowest insulating film 75L of the element insulating layer 72. The positions of the first electrode plate 171A and the second electrode plate 172B in the Z direction can be changed as desired. In one example, the first electrode plate 171A and the second electrode plate 172B may be disposed on the lowest insulating film 75L of the element insulating layer 72.

[0195] The second electrode plate 171B and the first electrode plate 172A are arranged at the same position in the Z direction and spaced apart from each other in the X direction. The second electrode plate 171B and the first electrode plate 172A are arranged above the center of the element insulating layer 72 in the Z direction. In one example, the second electrode plate 171B and the first electrode plate 172A are provided so as to penetrate in the Z direction through the insulating film 75 that is two layers below the uppermost insulating film 75U of the element insulating layer 72. The first electrode plate 171A and the second electrode plate 171B face each other in the Z direction. The first electrode plate 172A and the second electrode plate 172B face each other in the Z direction.

[0196] The second electrode plate 171B and the first electrode plate 172A may be provided on the upper surface of the element insulating layer 72. In this case, the second electrode plate 171B and the first electrode plate 172A are covered with a protective layer .

[0197] 35 , the inter-region distance DR between the first semiconductor region 131 and the second semiconductor region 132 in the X direction is smaller than the inter-pad distance PR between the first die pad 81 and the second die pad 91 in the X direction. In the third embodiment, the first semiconductor region 131 and the second semiconductor region 132 are partitioned in the X direction by the intermediate insulating region 143, and therefore the inter-region distance DR is equal to the width dimension WR3 of the intermediate insulating region 143. For this reason, it can also be said that the width dimension WR3 of the intermediate insulating region 143 is smaller than the inter-pad distance PR.

[0198] The inter-region distance DR is smaller than the distance EC between the first electrode plate 171A and the second electrode plate 172B in the X direction. The inter-region distance DR is smaller than the distance ED between the second electrode plate 171B and the first electrode plate 172A in the X direction. Note that the distances EC and ED may be equal to each other.

[0199] On the other hand, the inter-region distance DR is greater than the distance EA between the first electrode plate 171A and the second electrode plate 171B in the Z direction. The inter-region distance DR is greater than the distance EB between the first electrode plate 172A and the second electrode plate 172B in the Z direction. Note that the distances EA and EB may be equal to each other.

[0200] The inter-pad distance PR is smaller than the distance EC between the first electrode plate 171A and the second electrode plate 172B in the X direction. The inter-pad distance PR is smaller than the distance ED between the second electrode plate 171B and the first electrode plate 172A in the X direction. The inter-pad distance PR is larger than the distance EA between the first electrode plate 171A and the second electrode plate 171B in the Z direction. The inter-pad distance PR is larger than the distance EB between the first electrode plate 172A and the second electrode plate 172B in the Z direction.

[0201] The insulating chip 70 includes a first connection wiring 181, a second connection wiring 182, and a third connection wiring 183. The first connection wiring 181 electrically connects the first electrode plate 171A of the first capacitor 171 to the first pad 73. The second connection wiring 182 electrically connects the second electrode plate 172B of the second capacitor 172 to the second pad 74. The third connection wiring 183 electrically connects the second electrode plate 171B of the first capacitor 171 to the first electrode plate 172A of the second capacitor 172.

[0202] The first connection wiring 181 includes an electrode connection portion 181A and a pad connection portion 181B. The electrode connection portion 181A is connected to the first electrode plate 171A of the first capacitor 171. The electrode connection portion 181A is disposed at the same position as the first electrode plate 171A in the Z direction. The electrode connection portion 181A is a wiring that extends in the X direction from the first electrode plate 171A.

[0203] The pad connection portion 181B connects the electrode connection portion 181A and the first pad 73. The pad connection portion 181B is provided at a position overlapping both the electrode connection portion 181A and the first pad 73 in a plan view. The pad connection portion 181B has a laminated structure of a plurality of vias and a plurality of wiring portions. The wiring portions of the pad connection portion 181B are provided at the same positions as the first electrode plate 171A and the second electrode plate 171B in the Z direction. The plurality of vias are provided to connect the lower wiring portion with the upper wiring portion. The vias are also provided to connect the upper wiring portion with the first pad 73.

[0204] The second connection wiring 182 includes an electrode connection portion 182A and a pad connection portion 182B. The electrode connection portion 182A is connected to the second electrode plate 172B of the second capacitor 172. The pad connection portion 182B is connected to the second pad 74. The electrode connection portion 182A and the pad connection portion 182B are connected to each other. The configurations of the electrode connection portion 182A and the pad connection portion 182B are the same as the configurations of the electrode connection portion 181A and the pad connection portion 181B.

[0205] The third connection wiring 183 is located at the same position in the Z direction as the second electrode plate 171B of the first capacitor 171 and the first electrode plate 172A of the second capacitor 172, and is arranged between the second electrode plate 171B and the first electrode plate 172A in the X direction.

[0206] The bonding between the insulating chip 70 and the first die pad 81 by the first bonding material 121 and the bonding between the insulating chip 70 and the second die pad 91 by the second bonding material 122 are the same as in the first embodiment.

[0207] [effect] The insulating chip 70 and semiconductor device 10 of the third embodiment provide the following advantages. (3-1) The insulating chip 70 includes a capacitor 170. The capacitor 170 includes a first capacitor 171 including a first electrode plate 171A and a second electrode plate 171B arranged opposite each other in the Z direction, and a second capacitor 172 including a first electrode plate 172A and a second electrode plate 172B arranged opposite each other in the Z direction.

[0208] According to this configuration, a double insulation structure is formed by the first capacitor 171 and the second capacitor 172, thereby enabling the insulating chip 70 to withstand a high voltage. In addition, the wiring structure electrically connecting the first capacitor 171, the second capacitor 172, the first pad 73, and the second pad 74 can be simplified, and the number of first pads 73 and second pads 74 can be reduced. Therefore, the insulating chip 70 can be simply configured.

[0209] <Fourth embodiment> 36 to 42, the semiconductor device 10 of the fourth embodiment will be described. The semiconductor device 10 of the fourth embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the insulating chip 70. In the following, components common to the semiconductor device 10 of the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0210] [Circuit configuration of semiconductor device] The circuit configuration of the semiconductor device 10 of the fourth embodiment will be described with reference to Fig. 36. Fig. 36 schematically shows the circuit configuration of the semiconductor device 10 of the fourth embodiment.

[0211] As shown in FIG. 36, the transformer 40 of the semiconductor device 10 includes first to eighth coils 201 to 208. The first coil 201 and the second coil 202 are electrically insulated from each other and are configured to be magnetically coupled. The second coil 202 and the third coil 203 are electrically connected to each other. The third coil 203 and the fourth coil 204 are electrically insulated from each other and are configured to be magnetically coupled. The fourth coil 204 and the fifth coil 205 are electrically connected to each other. The fifth coil 205 and the sixth coil 206 are electrically insulated from each other and are configured to be magnetically coupled. The sixth coil 206 and the seventh coil 207 are electrically connected to each other. The seventh coil 207 and the eighth coil 208 are electrically insulated from each other and are configured to be magnetically coupled.

[0212] The first coil 201 is electrically connected to the transmitting circuit 21 of the first circuit 20. More specifically, a first end of the first coil 201 is electrically connected to the transmitting circuit 21. A second end of the first coil 201 is electrically connected to ground GND1. The eighth coil 208 is electrically connected to the receiving circuit 31 of the second circuit 30. More specifically, a first end of the eighth coil 208 is electrically connected to the receiving circuit 31. A second end of the eighth coil 208 is electrically connected to ground GND2. The second to seventh coils 202 to 207 are in an electrically floating state.

[0213] The transmission circuit 21 receives an input signal and pulse-drives the transformer 40. The pulse signal excited in the first coil 201 is transmitted to the eighth coil 208 via the second to seventh coils 202 to 207, and then input to the reception circuit 31. The reception circuit 31 outputs an output signal based on the input pulse signal.

[0214] [Insulation chip configuration] The configuration of the insulating chip 70 will be described with reference to FIGS. 37 to 42. FIG. 37 schematically illustrates an example of the planar structure of the insulating chip 70 in the semiconductor device 10. FIG. 38 schematically illustrates a cross-sectional structure of the insulating chip 70, showing the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208. FIG. 39 schematically illustrates a cross-sectional structure of the insulating chip 70 of FIG. 38 taken along line F39-F39. FIG. 40 schematically illustrates an enlarged cross-sectional structure of the insulating chip 70 of FIG. 39, showing the first to fourth coils 201 to 204 and their surrounding areas. FIG. 41 schematically illustrates an enlarged cross-sectional structure of the insulating chip 70 of FIG. 39, showing the third to sixth coils 203 to 206 and their surrounding areas. FIG. 42 schematically illustrates an enlarged cross-sectional structure of the insulating chip 70 of FIG. 39, showing the fifth to eighth coils 205 to 208 and their surrounding areas.

[0215] (Coil arrangement) As shown in FIG. 39, the first to eighth coils 201 to 208 are provided on the element insulating layer 72. As shown in FIG. 38, the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are arranged at the same positions in the Y direction and spaced apart from each other in the X direction. The fourth coil 204 and the fifth coil 205 are arranged between the first coil 201 and the eighth coil 208 in the X direction. The fourth coil 204 is arranged closer to the first coil 201 than the fifth coil 205 in a plan view. The first coil 201 is arranged closer to the first chip side surface 70A than the fourth coil 204, the fifth coil 205, and the eighth coil 208. The eighth coil 208 is arranged closer to the second chip side surface 70B than the first coil 201, the fourth coil 204, and the fifth coil 205. 37 , the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The third coil 203 and the sixth coil 206 are arranged between the second coil 202 and the seventh coil 207 in the X direction. The third coil 203 is arranged closer to the second coil 202 than the sixth coil 206 in a plan view. The second coil 202 is arranged closer to the first chip side surface 70A than the third coil 203, the sixth coil 206, and the seventh coil 207. The seventh coil 207 is arranged closer to the second chip side surface 70B than the second coil 202, the third coil 203, and the sixth coil 206.

[0216] 39 , the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are arranged at the same position in the Z direction. The second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are arranged at the same position in the Z direction. The second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are arranged above the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208. In other words, the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are arranged closer to the semiconductor substrate 71 in the Z direction than the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207. The first coil 201 is arranged opposite the second coil 202 in the Z direction. The third coil 203 is disposed opposite the fourth coil 204 in the Z direction. The fifth coil 205 is disposed opposite the sixth coil 206 in the Z direction. The seventh coil 207 is disposed opposite the eighth coil 208 in the Z direction. The shapes and materials of the first to eighth coils 201 to 208 may be the same as, for example, the first to fourth coils 41 to 44 of the first embodiment (see FIG. 7).

[0217] Here, the first coil 201 is an example of a "first insulating element." The second coil 202 is an example of a "second insulating element." The third coil 203 is an example of a "third insulating element." The fourth coil 204 is an example of a "fourth insulating element." The fifth coil 205 is an example of a "fifth insulating element." The sixth coil 206 is an example of a "sixth insulating element." The seventh coil 207 is an example of a "seventh insulating element." The eighth coil 208 is an example of an "eighth insulating element."

[0218] Each of the first pads 73 and each of the second pads 74 is provided at both ends of the insulating chip 70 in the X direction in a plan view. The transformer 40 (first to eighth coils 201 to 208) is disposed between each of the first pads 73 and each of the second pads 74 in the X direction in a plan view. Each of the first pads 73 is disposed closer to the first chip side surface 70A than the transformer 40 in a plan view. Each of the second pads 74 is disposed closer to the second chip side surface 70B than the transformer 40 in a plan view. It can be said that each of the first pads 73 is disposed on the opposite side of the first coil 201 (second coil 202) from the fourth coil 204 (third coil 203) in the X direction. It can be said that each of the second pads 74 is disposed on the opposite side of the eighth coil 208 (seventh coil 207) from the fifth coil 205 (sixth coil 206) in the X direction.

[0219] (Coil connection configuration) 37 to 39, the insulating chip 70 includes first to fifth inner connecting wirings 221 to 225 and first to fifth outer connecting wirings 231 to 235. The first to fifth inner connecting wirings 221 to 225 and the first to fifth outer connecting wirings 231 to 235 are provided in an element insulating layer 72.

[0220] Here, the first inner connecting wiring 221 and the first outer connecting wiring 231 are an example of a "first connecting wiring." The second inner connecting wiring 222 and the second outer connecting wiring 232 are an example of a "second connecting wiring." The third inner connecting wiring 223 and the third outer connecting wiring 233 are an example of a "third connecting wiring." The fourth inner connecting wiring 224 and the fourth outer connecting wiring 234 are an example of a "fourth connecting wiring." The fifth inner connecting wiring 225 and the fifth outer connecting wiring 235 are an example of a "fifth connecting wiring."

[0221] The first inner connecting wiring 221 electrically connects the inner end of the first coil 201 to the first pad 73A. The first outer connecting wiring 231 electrically connects the outer end of the first coil 201 to the first pad 73B. The configuration of the first inner connecting wiring 221 is the same as that of the inner connecting wiring 45A of the first embodiment (see FIG. 8). The configuration of the first outer connecting wiring 231 is the same as that of the outer connecting wiring 46A of the first embodiment (see FIG. 7).

[0222] The second inner connecting wiring 222 and the second outer connecting wiring 232 electrically connect the second coil 202 and the third coil 203 to each other. The second inner connecting wiring 222 is disposed above the second coil 202 and the third coil 203. In other words, the second inner connecting wiring 222 is disposed on the opposite side of the second coil 202 and the third coil 203 from the first coil 201 and the fourth coil 204. It can also be said that the second inner connecting wiring 222 is disposed on the opposite side of the semiconductor substrate 71 from the second coil 202 and the third coil 203. The second inner connecting wiring 222 electrically connects the inner end of the second coil 202 and the inner end of the third coil 203.

[0223] The second outer connection wiring 232 is disposed at the same position in the Z direction as the second coil 202 and the third coil 203. The second outer connection wiring 232 electrically connects the outer end of the second coil 202 and the outer end of the third coil 203. The second outer connection wiring 232 extends along the X direction.

[0224] The third inner connecting wiring 223 and the third outer connecting wiring 233 electrically connect the fourth coil 204 and the fifth coil 205 to each other. The third inner connecting wiring 223 is disposed below the fourth coil 204 and the fifth coil 205. In other words, the third inner connecting wiring 223 is disposed closer to the semiconductor substrate 71 than the fourth coil 204 and the fifth coil 205. The third inner connecting wiring 223 electrically connects the inner end of the fourth coil 204 and the inner end of the fifth coil 205.

[0225] The third outer connection wiring 233 is disposed at the same position in the Z direction as the fourth coil 204 and the fifth coil 205. The third outer connection wiring 233 electrically connects the outer end of the fourth coil 204 and the outer end of the fifth coil 205. The third outer connection wiring 233 extends along the X direction.

[0226] The fourth inner connecting wiring 224 and the fourth outer connecting wiring 234 electrically connect the sixth coil 206 and the seventh coil 207. The fourth inner connecting wiring 224 has the same configuration as the second inner connecting wiring 222, and the fourth outer connecting wiring 234 has the same configuration as the second outer connecting wiring 232.

[0227] The fifth inner connecting wiring 225 electrically connects the inner end of the eighth coil 208 to the second pad 74A. The fifth outer connecting wiring 235 electrically connects the outer end of the eighth coil 208 to the second pad 74B. The configuration of the fifth inner connecting wiring 225 is the same as that of the inner connecting wiring 45B of the first embodiment (see FIG. 8). The configuration of the fifth outer connecting wiring 235 is the same as that of the outer connecting wiring 46B of the first embodiment (see FIG. 7).

[0228] (Configuration of semiconductor substrate) 37 to 39, the semiconductor substrate 71 includes first to fourth semiconductor regions 241 to 244, a peripheral region 249, and an insulating region 250. The insulating region 250 is a region that separates the first to fourth semiconductor regions 241 to 244 and the peripheral region 249 from the semiconductor substrate 71. The first to fourth semiconductor regions 241 to 244 and the peripheral region 249 are insulated from each other by the insulating region 250. The materials that make up the first to fourth semiconductor regions 241 to 244 and the peripheral region 249 are the same as those of the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 of the first embodiment, for example.

[0229] The first to fourth semiconductor regions 241 to 244 are arranged side by side in the X direction in a planar view. The second semiconductor region 242 and the third semiconductor region 243 are arranged between the first semiconductor region 241 and the fourth semiconductor region 244 in the X direction in a planar view. The second semiconductor region 242 is arranged closer to the first semiconductor region 241 than the third semiconductor region 243 in a planar view. The first semiconductor region 241 is arranged closer to the first chip side surface 70A than the second to fourth semiconductor regions 242 to 244 in a planar view. The fourth semiconductor region 244 is arranged closer to the second chip side surface 70B than the first to third semiconductor regions 241 to 243 in a planar view. In one example, each of the first to fourth semiconductor regions 241 to 244 has a rectangular shape in a planar view.

[0230] The first semiconductor region 241 includes a region that overlaps with at least a portion of both the first coil 201 and the second coil 202 in a planar view. On the other hand, both the first coil 201 and the second coil 202 are disposed at positions spaced apart from the second to fourth semiconductor regions 242 to 244 in a planar view.

[0231] The second semiconductor region 242 includes a region that overlaps with at least a portion of both the third coil 203 and the fourth coil 204 in a planar view. On the other hand, both the third coil 203 and the fourth coil 204 are disposed at positions spaced apart from the first semiconductor region 241, the third semiconductor region 243, and the fourth semiconductor region 244 in a planar view.

[0232] The third semiconductor region 243 includes a region that overlaps with at least a portion of both the fifth coil 205 and the sixth coil 206 in a planar view. On the other hand, both the fifth coil 205 and the sixth coil 206 are disposed at positions spaced apart from the first semiconductor region 241, the second semiconductor region 242, and the fourth semiconductor region 244 in a planar view.

[0233] The fourth semiconductor region 244 is a region that overlaps, in plan view, with at least a portion of both the seventh coil 207 and the eighth coil 208. On the other hand, both the seventh coil 207 and the eighth coil 208 are disposed at positions spaced apart from the first to third semiconductor regions 241 to 243 in plan view.

[0234] The outer circumferential region 249 is in the shape of a frame having a predetermined width and surrounds the first to fourth semiconductor regions 241 to 244 in a plan view. It can also be said that the outer circumferential region 249 surrounds the insulating region 250 in a plan view. In one example, the outer circumferential region 249 is in the shape of a rectangular frame in a plan view. In one example, the first to eighth coils 201 to 208 are located inward of the outer circumferential region 249 in a plan view.

[0235] The insulating region 250 penetrates the semiconductor substrate 71 in the Z direction. The insulating region 250 includes first to fourth insulating regions 251 to 254 in a planar view. The first insulating region 251 has a frame shape surrounding the first semiconductor region 241 in a planar view. The second insulating region 252 has a frame shape surrounding the second semiconductor region 242 in a planar view. The third insulating region 253 has a frame shape surrounding the third semiconductor region 243 in a planar view. The fourth insulating region 254 has a frame shape surrounding the fourth semiconductor region 244 in a planar view. In one example, each of the first to fourth insulating regions 251 to 254 has a rectangular frame shape in a planar view. Note that the shape of each of the first to fourth insulating regions 251 to 254 in a planar view is not limited to a rectangular frame shape and can be changed as desired.

[0236] 37 and 38, the first to fourth insulating regions 251 to 254 are integrated. As a result, the insulating region 250 includes first to third intermediate insulating regions 261 to 263. The first intermediate insulating region 261 is a region that serves both the first insulating region 251 and the second insulating region 252. The first intermediate insulating region 261 is provided between the first semiconductor region 241 and the second semiconductor region 242 in the X direction. The second intermediate insulating region 262 is a region that serves both the second insulating region 252 and the third insulating region 253. The second intermediate insulating region 262 is provided between the second semiconductor region 242 and the third semiconductor region 243 in the X direction. The third intermediate insulating region 263 is a region that serves both the third insulating region 253 and the fourth insulating region 254. The third intermediate insulating region 263 is provided between the third semiconductor region 243 and the fourth semiconductor region 244 in the X direction. Each of the first to third intermediate insulating regions 261 to 263 extends in the Y direction in a plan view. The width and thickness dimensions of the insulating region 250 may be equal to the width dimensions WR1 to WR3 and thickness dimension HR of the insulating region 140 of the first embodiment (both see FIG. 8). The material of the insulating region 250 may be the same as the material of the insulating region 140 of the first embodiment.

[0237] 39 , when the insulating chip 70 is mounted on the first die pad 81 and the second die pad 91, the first bonding material 121 contacts the first semiconductor region 241 of the semiconductor substrate 71, and the second bonding material 122 contacts the fourth semiconductor region 244 of the semiconductor substrate 71. In other words, the first semiconductor region 241 is bonded to the first die pad 81 by the first bonding material 121. The fourth semiconductor region 244 is bonded to the second die pad 91 by the second bonding material 122. On the other hand, neither the first bonding material 121 nor the second bonding material 122 contacts the outer periphery region 249 of the semiconductor substrate 71.

[0238] In the example shown in FIG. 39, the first bonding material 121 is not in contact with the first insulating region 251 or the first intermediate insulating region 261. The first bonding material 121 is in contact with the entire first semiconductor region 241. The second bonding material 122 is not in contact with either the fourth insulating region 254 or the third intermediate insulating region 263. The second bonding material 122 is in contact with the entire fourth semiconductor region 244. Sealing resin 100 (see FIG. 3) is interposed between the outer periphery region 249 and the first die pad 81 in the Z direction, and between the outer periphery region 249 and the second die pad 91 in the Z direction.

[0239] As shown in FIG. 41 , the first inter-region distance DR1 between the first semiconductor region 241 and the second semiconductor region 242 in the X direction is smaller than the inter-pad distance PR. The second inter-region distance DR2 between the second semiconductor region 242 and the third semiconductor region 243 in the X direction is smaller than the inter-pad distance PR. The third inter-region distance DR3 between the third semiconductor region 243 and the fourth semiconductor region 244 in the X direction is smaller than the inter-pad distance PR. The first inter-region distance DR1 is equal to the width dimension WC1 of the first intermediate insulating region 261. The second inter-region distance DR2 is equal to the width dimension WC2 of the second intermediate insulating region 262. The third inter-region distance DR3 is equal to the width dimension WC3 of the third intermediate insulating region 263. Therefore, each of the width dimensions WC1 to WC3 is smaller than the inter-pad distance PR.

[0240] Here, the width dimension WC1 of the first intermediate insulating region 261 can be defined by the dimension in a direction perpendicular to the extension direction of the first intermediate insulating region 261 in a plan view. In the example of FIG. 41, the width dimension WC1 is the dimension of the first intermediate insulating region 261 in the X direction. The width dimension WC2 of the second intermediate insulating region 262 can be defined by the dimension in a direction perpendicular to the extension direction of the second intermediate insulating region 262 in a plan view. In the example of FIG. 41, the width dimension WC2 is the dimension of the second intermediate insulating region 262 in the X direction. The width dimension WC3 of the third intermediate insulating region 263 can be defined by the dimension in a direction perpendicular to the extension direction of the third intermediate insulating region 263 in a plan view. In the example of FIG. 41, the width dimension WC3 is the dimension of the third intermediate insulating region 263 in the X direction.

[0241] As shown in FIG. 40, the first inter-region distance DR1 is smaller than the first distance DC1 between the first coil 201 and the fourth coil 204 in the X direction. The first inter-region distance DR1 is smaller than the first distance DD1 between the second coil 202 and the third coil 203 in the X direction. On the other hand, the first inter-region distance DR1 is larger than the first distance D1 between the first coil 201 and the second coil 202 in the Z direction. The first inter-region distance DR1 is larger than the second distance D2 between the third coil 203 and the fourth coil 204 in the Z direction. The first distance D1 and the second distance D2 may be equal to each other. The first distance DC1 and the first distance DD1 may be equal to each other. In FIGS. 39 to 42, the thickness of the element insulating layer 72 is shown thick to facilitate understanding of the drawings.

[0242] 41, the second inter-region distance DR2 is smaller than the second distance DC2 between the fourth coil 204 and the fifth coil 205 in the X direction. The second inter-region distance DR2 is smaller than the second distance DD2 between the third coil 203 and the sixth coil 206 in the X direction. The second distance DC2 and the second distance DD2 may be equal to each other. On the other hand, the second inter-region distance DR2 is larger than the second distance D2. The second inter-region distance DR2 is larger than the third distance D3 between the fifth coil 205 and the sixth coil 206 in the Z direction. The second distance D2 and the third distance D3 may be equal to each other.

[0243] 42, the third inter-region distance DR3 is smaller than the third distance DC3 between the fifth coil 205 and the eighth coil 208 in the X direction. The third inter-region distance DR3 is smaller than the third distance DD3 between the sixth coil 206 and the seventh coil 207 in the X direction. On the other hand, the third inter-region distance DR3 is larger than the third distance D3. The third inter-region distance DR3 is larger than the fourth distance D4 between the seventh coil 207 and the eighth coil 208 in the Z direction. Note that the third distance D3 and the fourth distance D4 may be equal to each other. Also, the third distance DC3 and the third distance DD3 may be equal to each other.

[0244] 41, the second semiconductor region 242 and the third semiconductor region 243 are arranged in a plan view between the first die pad 81 and the second die pad 91 in the X direction. The first to third intermediate insulating regions 261 to 263 are arranged in a plan view between the first die pad 81 and the second die pad 91 in the X direction. As shown in FIG. 41, in the fourth embodiment, the inter-pad distance PR is greater than the sum of the X-direction dimension of the second semiconductor region 242, the X-direction dimension of the third semiconductor region 243, and the first to third region distances DR1 to DR3.

[0245] [Insulating chip manufacturing method] Next, an example of a manufacturing method for the insulating chip 70 of the fourth embodiment will be described. The manufacturing method for the insulating chip 70 of the fourth embodiment is generally the same as the manufacturing method for the insulating chip 70 of the first embodiment. Below, differences from the first embodiment will be described.

[0246] The method for manufacturing the insulating chip 70 of the fourth embodiment differs from the method for manufacturing the insulating chip 70 of the first embodiment in that the shapes of the trenches 810 and the insulating layer 811 are different in the step of forming the insulating layer 811 in the semiconductor substrate 800 (see FIGS. 9 and 10). That is, in the fourth embodiment, the trenches 810 form the first to fourth semiconductor regions 241 to 244 and the peripheral region 249 in the semiconductor substrate 800. Then, as in the first embodiment, the insulating layer 811 is formed by thermally oxidizing the trenches 810 in the semiconductor substrate 800.

[0247] The method for manufacturing the insulating chip 70 of the fourth embodiment includes, instead of the step of forming the inner connecting wirings 45A and 45B of the first embodiment (see FIGS. 13 to 22), a step of forming a first inner connecting wiring 221 and a fifth inner connecting wiring 225. The method for forming the first inner connecting wiring 221 and the fifth inner connecting wiring 225 is the same as the method for forming the inner connecting wirings 45A and 45B.

[0248] The method for manufacturing the insulating chip 70 of the fourth embodiment includes the steps of forming the third inner connecting wiring 223 and the steps of forming the second inner connecting wiring 222 and the fourth inner connecting wiring 224. The step of forming the third inner connection wiring 223 is performed in the same manner as, for example, the step of forming parts of the inner connection wirings 45A and 45B of the first embodiment (see FIGS. 11 to 14). In the step of forming the third inner connection wiring 223, parts of the third inner connection wiring 223 are formed on the insulating film 75L by, for example, at least one of sputtering and electrolytic plating. Then, an insulating film 75 is deposited on the insulating film 75L by, for example, CVD. Then, through holes are formed in the insulating film 75 by, for example, etching. Then, vias that are parts of the third inner connection wiring 223 are formed in the through holes by, for example, at least one of sputtering and electrolytic plating. Through the above steps, the third inner connection wiring 223 is formed.

[0249] The process of forming the second inner connecting wiring 222 and the fourth inner connecting wiring 224 is performed in place of the process of forming the connecting wirings 47A and 47B of the first embodiment (see FIGS. 21 to 24). The method of forming the second inner connecting wiring 222 and the fourth inner connecting wiring 224 is the same as the method of forming the connecting wirings 47A and 47B.

[0250] The method for manufacturing the insulating chip 70 of the fourth embodiment includes, instead of the step of forming the first coil 41 and the fourth coil 44 (see FIGS. 15 and 16), the step of forming the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208. The method for forming the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 is the same as the method for forming the first coil 41 and the fourth coil 44.

[0251] The method for manufacturing the insulating chip 70 of the fourth embodiment includes, instead of the step of forming the second coil 42 and the third coil 43 (see FIGS. 19 and 20 ), the step of forming the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207. The method for forming the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 is the same as the method for forming the second coil 42 and the third coil 43.

[0252] The method for manufacturing the insulating chip 70 of the fourth embodiment includes, instead of the step of forming the outer connecting wirings 46A and 46B of the first embodiment (see FIGS. 15 to 22), a step of forming the first outer connecting wiring 231 and the fifth outer connecting wiring 235. The method for forming the first outer connecting wiring 231 and the fifth outer connecting wiring 235 is the same as the method for forming the outer connecting wirings 46A and 46B.

[0253] The method for manufacturing the insulating chip 70 of the fourth embodiment includes the steps of forming the third outer connecting wiring 233 and the steps of forming the second outer connecting wiring 232 and the fourth outer connecting wiring 234. The step of forming the third outer connection wiring 233 is carried out simultaneously with the steps of forming, for example, the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208. The method of forming the third outer connection wiring 233 is the same as the method of forming the second connection wiring 47B (see FIGS. 19 and 20).

[0254] The process of forming the second outer connection wiring 232 and the fourth outer connection wiring 234 is performed instead of the process of forming a part of the connection wiring 47 of the first embodiment (see FIGS. 19 and 20). The process of forming the second outer connection wiring 232 and the fourth outer connection wiring 234 is performed simultaneously with the process of forming the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207, for example. The process of forming the second outer connection wiring 232 and the fourth outer connection wiring 234 is the same as the method of forming the second connection wiring 47B (see FIGS. 19 and 20).

[0255] [Effects of the fourth embodiment] The insulating chip 70 and semiconductor device 10 of the fourth embodiment provide the following effects. (4-1) The insulating chip 70 includes a fifth coil 205 and an eighth coil 208 that are spaced apart from each other in the X direction, a sixth coil 206 that is arranged opposite the fifth coil 205 in the Z direction, and a seventh coil 207 that is arranged opposite the eighth coil 208 in the Z direction. The fifth coil 205 and the eighth coil 208 are arranged spaced apart from both the first coil 201 and the fourth coil 204 when viewed from the Z direction. The sixth coil 206 and the seventh coil 207 are arranged spaced apart from both the second coil 202 and the third coil 203 when viewed from the Z direction. The semiconductor substrate 71 includes a third semiconductor region 243 disposed at a distance from the first semiconductor region 241 and the second semiconductor region 242 when viewed from the Z direction, and a fourth semiconductor region 244 disposed at a distance from the first semiconductor region 241, the second semiconductor region 242, and the third semiconductor region 243 when viewed from the Z direction. The insulating region 250 is configured to insulate the first semiconductor region 241, the second semiconductor region 242, the third semiconductor region 243, and the fourth semiconductor region 244 from one another. When viewed from the Z direction, both the fifth coil 205 and the sixth coil 206 are disposed at a distance from the first semiconductor region 241, the second semiconductor region 242, and the fourth semiconductor region 244, and so as to at least partially overlap the third semiconductor region 243. When viewed from the Z direction, both the seventh coil 207 and the eighth coil 208 are positioned so as to be spaced apart from the first semiconductor region 241, the second semiconductor region 242, and the third semiconductor region 243, and so as to overlap at least a portion of the fourth semiconductor region 244.

[0256] With this configuration, the first to eighth coils 201 to 208 connect a plurality of insulating structures in series, thereby achieving a higher withstand voltage of the insulating chip 70. More specifically, the first to fourth semiconductor regions 241 to 244 are insulated from one another by the insulating region 250, which reduces the dependency of the first to third semiconductor regions 241 to 243 on the potential of the second die pad 91 and reduces the dependency of the second to fourth semiconductor regions 242 to 244 on the potential of the first die pad 81. This reduces a decrease in the withstand voltage of the insulating chip 70 due to the distance in the Z direction between the first coil 201 and the first semiconductor region 241, the distance in the Z direction between the fourth coil 204 and the second semiconductor region 242, the distance in the Z direction between the fifth coil 205 and the third semiconductor region 243, and the distance in the Z direction between the eighth coil 208 and the fourth semiconductor region 244. Furthermore, the second coil 202 and the third coil 203, which are electrically connected to each other, the fourth coil 204 and the fifth coil 205, which are electrically connected to each other, and the sixth coil 206 and the seventh coil 207, which are electrically connected to each other, each have an intermediate potential between the first coil 201 and the eighth coil 208. In other words, the insulating chip 70 has a plurality of intermediate potentials. This allows the insulating chip 70 to withstand a higher voltage.

[0257] (4-2) The insulating region 250 includes a frame-shaped first insulating region 251 that surrounds the first semiconductor region 241 when viewed from the Z direction, a frame-shaped second insulating region 252 that surrounds the second semiconductor region 242 when viewed from the Z direction, a frame-shaped third insulating region 253 that surrounds the third semiconductor region 243 when viewed from the Z direction, and a frame-shaped fourth insulating region 254 that surrounds the fourth semiconductor region 244 when viewed from the Z direction.

[0258] According to this configuration, each of the first to fourth semiconductor regions 241 to 244 is surrounded by the insulating region 250, and therefore the first to fourth semiconductor regions 241 to 244 can be reliably insulated from one another.

[0259] (4-3) The semiconductor device includes a first intermediate insulating region 261 provided between the first semiconductor region 241 and the second semiconductor region 242, a second intermediate insulating region 262 provided between the second semiconductor region 242 and the third semiconductor region 243, and a third intermediate insulating region 263 provided between the third semiconductor region 243 and the fourth semiconductor region 244. The first intermediate insulating region 261 constitutes part of the first insulating region 251 and the second insulating region 252. The second intermediate insulating region 262 constitutes part of the second insulating region 252 and the third insulating region 253. The third intermediate insulating region 263 constitutes part of the third insulating region 253 and the fourth insulating region 254.

[0260] According to this configuration, the first insulating region 251 and the second insulating region 252 are integrated by the first intermediate insulating region 261, the second insulating region 252 and the third insulating region 253 are integrated by the second intermediate insulating region 262, and the third insulating region 253 and the fourth insulating region 254 are integrated by the third intermediate insulating region 263. This makes it possible to reduce the size of the semiconductor substrate 71 in the X direction compared to a configuration in which the first to fourth insulating regions 251 to 254 are provided spaced apart in the X direction.

[0261] Fifth Embodiment 43 and 44, the semiconductor device 10 of the fifth embodiment will be described. The semiconductor device 10 of the fifth embodiment differs from the semiconductor device 10 of the second embodiment mainly in the configuration of the insulating chip 70. In the following, components common to the semiconductor device 10 of the second embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0262] [Insulation chip configuration] Fig. 43 schematically shows the planar structure of the insulating chip 70 of the fifth embodiment. Fig. 44 schematically shows the cross-sectional structure of the insulating chip 70 taken along line F44-F44 in Fig. 43. Note that in Fig. 44, the thicknesses of the first element insulating layer 152 and the second element insulating layer 162 are shown as being greater than the actual thickness in order to make the drawing easier to understand.

[0263] As shown in FIGS. 43 and 44, the fifth embodiment differs mainly in the configurations of the first unit 150 and the second unit 160 of the insulating tip 70. The first unit 150 includes a first coil 201, a fourth coil 204, a fifth coil 205, and an eighth coil 208 instead of the first coil 41 and the fourth coil 44 (both see FIG. 29). The second unit 160 includes a second coil 202, a third coil 203, a sixth coil 206, and a seventh coil 207 instead of the second coil 42 and the third coil 43 (both see FIG. 29). The configuration and arrangement of the first to eighth coils 201 to 208 are the same as those in the fourth embodiment. Furthermore, the connection configuration of the first to eighth coils 201 to 208 is the same as that in the fourth embodiment.

[0264] In the fifth embodiment, the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are each embedded in the first element insulating layer 152. The first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are arranged closer to the first semiconductor substrate 151 than the center of the first element insulating layer 152 in the Z direction.

[0265] The second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are each embedded in the second element insulating layer 162. The second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are arranged on the opposite side of the center of the second element insulating layer 162 from the first unit 150 in the Z direction.

[0266] The first semiconductor substrate 151 of the first unit 150 of the fifth embodiment includes the same configuration as the first semiconductor substrate 71 of the fourth embodiment (see FIG. 39). That is, the first semiconductor substrate 151 includes first to fourth semiconductor regions 241 to 244, a peripheral region 249, and an insulating region 250. The positional relationship between the first to eighth coils 201 to 208 and the first to fourth semiconductor regions 241 to 244 is the same as in the fourth embodiment.

[0267] Since the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are arranged at a distance in the X direction, the dimension in the X direction of the first unit 150 is larger than the dimension in the X direction of the first unit 150 of the second embodiment. On the other hand, the dimension in the Y direction of the first unit 150 of the fifth embodiment is equal to the dimension in the Y direction of the first unit 150 of the second embodiment.

[0268] Because the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are arranged at a distance in the X direction, the dimension in the X direction of the second unit 160 is larger than the dimension in the X direction of the second unit 160 of the second embodiment. On the other hand, the dimension in the Y direction of the second unit 160 of the fifth embodiment is equal to the dimension in the Y direction of the second unit 160 of the second embodiment. Therefore, the second unit 160 of the fifth embodiment has a rectangular shape that is slightly smaller than the first unit 150 of the fifth embodiment in a plan view. As in the second embodiment, in the unit arrangement state, the first pad 73 and the second pad 74 of the first unit 150 are arranged in positions different from those of the second unit 160.

[0269] In the unit arrangement state, the first coil 201 and the second coil 202 face each other in the Z direction. The third coil 203 and the fourth coil 204 face each other in the Z direction. The fifth coil 205 and the sixth coil 206 face each other in the Z direction. The seventh coil 207 and the eighth coil 208 face each other in the Z direction.

[0270] In the example shown in Figure 44, the first distance D1 between the first coil 201 and the second coil 202 in the Z direction, the second distance D2 between the third coil 203 and the fourth coil 204 in the Z direction, the third distance D3 between the fifth coil 205 and the sixth coil 206 in the Z direction, and the fourth distance D4 between the seventh coil 207 and the eighth coil 208 in the Z direction are all equal to each other.

[0271] The first distance D1 is smaller than the first distance DC1 between the first coil 201 and the fourth coil 204 in the X direction. The first distance D1 is smaller than the first distance DD1 between the second coil 202 and the third coil 203 in the X direction. Note that the first distance DC1 and the first distance DD1 may be equal to each other. The second distance D2 is smaller than the second distance DC2 between the fourth coil 204 and the fifth coil 205 in the X direction. The second distance D2 is smaller than the second distance DD2 between the third coil 203 and the sixth coil 206 in the X direction. Note that the second distance DC2 and the second distance DD2 may be equal to each other. The third distance D3 is smaller than the third distance DC3 between the fifth coil 205 and the eighth coil 208 in the X direction. The third distance D3 is smaller than the third distance DD3 between the sixth coil 206 and the seventh coil 207 in the X direction. The third distance DC3 and the third distance DD3 may be equal to each other. The fourth distance D4 is greater than the third distance DC3. The fourth distance D4 is smaller than the third distance DD3. The first to fourth distances D1 to D4 of the fifth embodiment may be greater than the first to fourth distances D1 to D4 of the fourth embodiment.

[0272] The first unit 150 includes a first inner connecting wiring 221 and a first outer connecting wiring 231, a third inner connecting wiring 223 and a third outer connecting wiring 233, and a fifth inner connecting wiring 225 and a fifth outer connecting wiring 235. The second unit 160 includes a second inner connecting wiring 222 and a second outer connecting wiring 232, and a fourth inner connecting wiring 224 and a fourth outer connecting wiring 234.

[0273] [Effects of the fifth embodiment] The insulating chip 70 and semiconductor device 10 of the fifth embodiment provide the following effects. (5-1) The first unit 150 includes a fifth coil 205 and an eighth coil 208 that are spaced apart in the X direction and electrically insulated from each other. The fifth coil 205 and the eighth coil 208 are embedded in the first element insulating layer 152. The fifth coil 205 and the eighth coil 208 are spaced apart from the first coil 201 and the fourth coil 204. The second unit 160 includes a sixth coil 206 and a seventh coil 207 that are spaced apart in the X direction and electrically insulated from each other. The sixth coil 206 and the seventh coil 207 are embedded in the second element insulating layer 162. The sixth coil 206 and the seventh coil 207 are spaced apart from the second coil 202 and the third coil 203. The fifth coil 205 and the sixth coil 206 are disposed opposite each other in the Z direction. The seventh coil 207 and the eighth coil 208 are disposed opposite each other in the Z direction.

[0274] According to this configuration, the element insulating layer between the first coil 201 and the second coil 202 in the Z direction, the element insulating layer between the third coil 203 and the fourth coil 204 in the Z direction, the element insulating layer between the fifth coil 205 and the sixth coil 206 in the Z direction, and the element insulating layer between the seventh coil 207 and the eighth coil 208 in the Z direction can each be provided individually in the Z direction, like the first element insulating layer 152 and the second element insulating layer 162. The first to eighth coils 201 to 208 are then provided in the element insulating layer provided by the first element insulating layer 152 and the second element insulating layer 162 stacked in the Z direction. Therefore, it is possible to increase the first distance D1 between the first coil 201 and the second coil 202 in the Z direction, the second distance D2 between the third coil 203 and the fourth coil 204 in the Z direction, the third distance D3 between the fifth coil 205 and the sixth coil 206 in the Z direction, and the fourth distance D4 between the seventh coil 207 and the eighth coil 208 in the Z direction. This allows the insulating chip 70 to have a further improved dielectric strength.

[0275] (5-2) The first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 are arranged closer to the first semiconductor substrate 151 than the center of the first element insulating layer 152 in the Z direction.

[0276] This configuration makes it possible to increase the first distance D1 between the first coil 201 and the second coil 202 in the Z direction, the second distance D2 between the third coil 203 and the fourth coil 204 in the Z direction, the third distance D3 between the fifth coil 205 and the sixth coil 206 in the Z direction, and the fourth distance D4 between the seventh coil 207 and the eighth coil 208 in the Z direction. This therefore makes it possible to further improve the dielectric strength of the insulating chip 70.

[0277] (5-3) The second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 are arranged on the opposite side of the center of the second element insulating layer 162 from the first unit 150 in the Z direction.

[0278] This configuration makes it possible to increase the first distance D1 between the first coil 201 and the second coil 202 in the Z direction, the second distance D2 between the third coil 203 and the fourth coil 204 in the Z direction, the third distance D3 between the fifth coil 205 and the sixth coil 206 in the Z direction, and the fourth distance D4 between the seventh coil 207 and the eighth coil 208 in the Z direction. This therefore makes it possible to further improve the dielectric strength of the insulating chip 70.

[0279] Sixth Embodiment 45 to 48, the semiconductor device 10 of the sixth embodiment will be described. The semiconductor device 10 of the sixth embodiment differs from the semiconductor device 10 of the third embodiment mainly in the configuration of the insulating chip 70. In the following, components common to the semiconductor device 10 of the third embodiment will be given the same reference numerals, and descriptions thereof will be omitted.

[0280] FIG. 45 schematically illustrates the circuit configuration of a semiconductor device 10 according to a sixth embodiment. FIG. 46 schematically illustrates an example of the planar structure of an insulating chip 70 in the semiconductor device 10. FIG. 47 schematically illustrates an example of a cross-sectional structure of a capacitor 300, which will be described later, including a first electrode plate 301A of a first capacitor 301, a second electrode plate 302B of a second capacitor 302, a first electrode plate 303A of a third capacitor 303, and a second electrode plate 304B of a fourth capacitor 304. FIG. 48 schematically illustrates a cross-sectional structure of the insulating chip 70 of FIG. 46 taken along line F48-F48. Note that in FIG. 48, the thickness of the element insulating layer 72 is exaggerated for ease of understanding.

[0281] [Circuit configuration of semiconductor device] As shown in FIG. 45, the semiconductor device 10 of the sixth embodiment includes a capacitor 300 instead of the capacitor 170 of the third embodiment (see FIG. 32). The capacitor 300 includes first to fourth capacitors 301 to 304 connected in series. The first capacitor 301 includes a first electrode plate 301A and a second electrode plate 301B. The second capacitor 302 includes a first electrode plate 302A and a second electrode plate 302B. The third capacitor 303 includes a first electrode plate 303A and a second electrode plate 303B. The fourth capacitor 304 includes a first electrode plate 304A and a second electrode plate 304B.

[0282] The first capacitor 301 is electrically connected to the first circuit 20, and the fourth capacitor 304 is electrically connected to the second circuit 30. More specifically, the first electrode plate 301A of the first capacitor 301 is electrically connected to the transmitting circuit 21 of the first circuit 20. The second electrode plate 304B of the fourth capacitor 304 is electrically connected to the receiving circuit 31 of the second circuit 30. The second electrode plate 301B of the first capacitor 301 is electrically connected to the first electrode plate 302A of the second capacitor 302. The second electrode plate 302B of the second capacitor 302 is electrically connected to the first electrode plate 303A of the third capacitor 303. The second electrode plate 303B of the third capacitor 303 is electrically connected to the first electrode plate 304A of the fourth capacitor 304.

[0283] [Insulation chip configuration] As shown in Fig. 48, capacitors 300 are provided on the element insulating layer 72 of the insulating chip 70. First electrode plates 301A-304A and second electrode plates 301B-304B of the first to fourth capacitors 301-304 have the same configurations as the first electrode plate 171A and second electrode plate 171B of the third embodiment (see Fig. 35).

[0284] As shown in FIGS. 46 to 48, the first to fourth capacitors 301 to 304 are spaced apart from one another in the X direction. A first electrode plate 301A of the first capacitor 301, a second electrode plate 302B of the second capacitor 302, a first electrode plate 303A of the third capacitor 303, and a second electrode plate 304B of the fourth capacitor 304 are located at the same position in the Z direction and spaced apart from one another in the X direction. These electrode plates 301A, 302B, 303A, and 304B are located closer to the semiconductor substrate 71 than the center of the element insulating layer 72 in the Z direction. The positions of these electrode plates 301A, 302B, 303A, and 304B in the Z direction can be changed as desired. In one example, these electrode plates 301A, 302B, 303A, and 304B may be located on the lowest insulating film 75L of the element insulating layer 72.

[0285] The second electrode plate 301B of the first capacitor 301, the first electrode plate 302A of the second capacitor 302, the second electrode plate 303B of the third capacitor 303, and the first electrode plate 304A of the fourth capacitor 304 are disposed at the same position in the Z direction and spaced apart from one another in the X direction. These electrode plates 301B, 302A, 303B, and 304A are disposed above the center of the element insulating layer 72 in the Z direction. The positions of these electrode plates 301B, 302A, 303B, and 304A in the Z direction can be changed as desired. In one example, these electrode plates 301B, 302A, 303B, and 304A may be provided on the upper surface of the element insulating layer 72. In this case, these electrode plates 301B, 302A, 303B, and 304A are covered by the protective layer 76.

[0286] The first electrode plate 301A and the second electrode plate 301B face each other in the Z direction. The first electrode plate 302A and the second electrode plate 302B face each other in the Z direction. The first electrode plate 303A and the second electrode plate 303B face each other in the Z direction. The first electrode plate 304A and the second electrode plate 304B face each other in the Z direction.

[0287] The semiconductor substrate 71 of the sixth embodiment includes first to fourth semiconductor regions 241 to 244, a peripheral region 249, and an insulating region 250. The configurations of the first to fourth semiconductor regions 241 to 244, the peripheral region 249, and the insulating region 250 are similar to those of the fourth embodiment.

[0288] First semiconductor region 241 includes a region that overlaps, in plan view, with at least a portion of both first electrode plate 301A and second electrode plate 301B of first capacitor 301. Meanwhile, both first electrode plate 301A and second electrode plate 301B are disposed at positions spaced apart from second to fourth semiconductor regions 242 to 244 in plan view.

[0289] Second semiconductor region 242 includes a region that overlaps with at least a portion of both first electrode plate 302A and second electrode plate 302B of second capacitor 302 in a planar view. On the other hand, both first electrode plate 302A and second electrode plate 302B are disposed at positions spaced apart from first semiconductor region 241, third semiconductor region 243, and fourth semiconductor region 244 in a planar view.

[0290] Third semiconductor region 243 includes a region that overlaps with at least a portion of both first electrode plate 303A and second electrode plate 303B of third capacitor 303 in a planar view. On the other hand, both first electrode plate 303A and second electrode plate 303B are disposed at positions spaced apart from first semiconductor region 241, second semiconductor region 242, and fourth semiconductor region 244 in a planar view.

[0291] The fourth semiconductor region 244 is a region that overlaps, in plan view, with at least a portion of both the first electrode plate 304A and the second electrode plate 304B of the fourth capacitor 304. On the other hand, both the first electrode plate 304A and the second electrode plate 304B are disposed at positions spaced apart from the first to third semiconductor regions 241 to 243 in plan view.

[0292] The positional relationship between the first electrode plates 301A to 304A and the second electrode plates 301B to 304B of the first to fourth capacitors 301 to 304 is the same as that of the first to eighth coils 201 to 208 of the fourth embodiment.

[0293] The insulating chip 70 includes first to fifth connection wirings 311 to 315. The first to fifth connection wirings 311 to 315 are provided on the element insulating layer 72. The first connection wiring 311 electrically connects the first electrode plate 301A of the first capacitor 301 to the first pad 73. The second connection wiring 312 electrically connects the second electrode plate 301B of the first capacitor 301 to the first electrode plate 302A of the second capacitor 302. The third connection wiring 313 electrically connects the second electrode plate 302B of the second capacitor 302 to the first electrode plate 303A of the third capacitor 303. The fourth connection wiring 314 electrically connects the second electrode plate 303B of the third capacitor 303 to the first electrode plate 304A of the fourth capacitor 304. The fifth connection wiring 315 electrically connects the second electrode plate 304B of the fourth capacitor 304 and the second pad 74. The first connection wiring 311 has the same configuration as the first connection wiring 181 (see FIG. 35) of the third embodiment. The second to fourth connection wirings 312 to 314 have the same configuration as the second connection wiring 182 (see FIG. 35) of the third embodiment. The fifth connection wiring 315 has the same configuration as the third connection wiring 183 (see FIG. 35) of the third embodiment.

[0294] [Effects of the sixth embodiment] The insulating chip 70 and semiconductor device 10 of the sixth embodiment provide the following effects. (6-1) The insulating chip 70 includes a capacitor 300. The capacitor 300 includes first to fourth capacitors 301 to 304, each including first electrode plates 301A to 304A and second electrode plates 301B to 304B arranged opposite each other in the Z direction.

[0295] According to this configuration, the first to fourth capacitors 301 to 304 form a configuration in which a plurality of insulating structures are connected in series, thereby enabling the insulating chip 70 to withstand a higher voltage. In addition, the wiring structure electrically connecting the first to fourth capacitors 301 to 304, the first pads 73, and the second pads 74 can be simplified, and the number of first pads 73 and second pads 74 can be reduced. Therefore, the insulating chip 70 can be simplified.

[0296] Seventh Embodiment 49 and 50, the semiconductor device 10 of the seventh embodiment will be described. The semiconductor device 10 of the seventh embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the insulating chip 70. In the following, components common to the semiconductor device 10 of the first embodiment will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0297] Fig. 49 schematically shows the planar structure of the insulating chip 70 in the semiconductor device 10 of the seventh embodiment. Fig. 50 schematically shows the cross-sectional structure of the insulating chip 70 of Fig. 49 cut along the XY plane.

[0298] [Insulation chip configuration] (Coil arrangement) 49 and 50, the insulating chip 70 includes first to twelfth coils 201 to 212. The first to twelfth coils 201 to 212 are provided on the element insulating layer 72 (see FIG. 7). The shapes and materials of the first to twelfth coils 201 to 212 are the same as, for example, the configuration of the first to eighth coils 201 to 208 (see FIG. 39) of the fourth embodiment.

[0299] The first coil 201, the fourth coil 204, the fifth coil 205, the eighth coil 208, the ninth coil 209, and the twelfth coil 212 are arranged at the same positions as one another in the Z direction. The second coil 202, the third coil 203, the sixth coil 206, the seventh coil 207, the tenth coil 210, and the eleventh coil 211 are arranged at the same positions as one another in the Z direction. The first coil 201, the fourth coil 204, the fifth coil 205, the eighth coil 208, the ninth coil 209, and the twelfth coil 212 are arranged closer to the semiconductor substrate 71 (see FIG. 7 ) than the second coil 202, the third coil 203, the sixth coil 206, the seventh coil 207, the tenth coil 210, and the eleventh coil 211.

[0300] 50 , the first coil 201, the fourth coil 204, the ninth coil 209, and the twelfth coil 212 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The fourth coil 204 and the ninth coil 209 are disposed between the first coil 201 and the twelfth coil 212 in the X direction. The fourth coil 204 is disposed closer to the first coil 201 than the ninth coil 209 in a plan view. The first coil 201 is disposed closer to the first chip side surface 70A than the fourth coil 204, the ninth coil 209, and the twelfth coil 212. The twelfth coil 212 is disposed closer to the second chip side surface 70B than the first coil 201, the fourth coil 204, and the ninth coil 209.

[0301] The fifth coil 205 and the eighth coil 208 are arranged offset in the Y direction with respect to the first coil 201, the fourth coil 204, the ninth coil 209, and the twelfth coil 212. The fifth coil 205 and the eighth coil 208 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The fifth coil 205 is arranged at a position overlapping with the fourth coil 204 when viewed from the Y direction. The eighth coil 208 is arranged at a position overlapping with the ninth coil 209 when viewed from the Y direction.

[0302] 49 , the second coil 202, the third coil 203, the tenth coil 210, and the eleventh coil 211 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The third coil 203 and the tenth coil 210 are disposed between the second coil 202 and the eleventh coil 211 in the X direction. The third coil 203 is disposed closer to the second coil 202 than the tenth coil 210 in a plan view. The second coil 202 is disposed closer to the first chip side surface 70A than the third coil 203, the tenth coil 210, and the eleventh coil 211. The eleventh coil 211 is disposed closer to the second chip side surface 70B than the second coil 202, the third coil 203, and the tenth coil 210.

[0303] The sixth coil 206 and the seventh coil 207 are arranged offset in the Y direction with respect to the second coil 202, the third coil 203, the tenth coil 210, and the eleventh coil 211. The sixth coil 206 and the seventh coil 207 are arranged at the same position in the Y direction and spaced apart from each other in the X direction. The sixth coil 206 is arranged at a position overlapping with the third coil 203 when viewed from the Y direction. The seventh coil 207 is arranged at a position overlapping with the tenth coil 210 when viewed from the Y direction.

[0304] Each of the first pads 73 and each of the second pads 74 is provided at both ends of the insulating chip 70 in the X direction in a plan view. The transformer 40 (first to twelfth coils 201 to 212) is disposed between each of the first pads 73 and each of the second pads 74 in the X direction in a plan view. In a plan view, each of the first pads 73 is disposed adjacent to the second coil 202 in the X direction. In a plan view, each of the second pads 74 is disposed adjacent to the eleventh coil 211 in the X direction.

[0305] The first coil 201 is arranged opposite the second coil 202 in the Z direction. The third coil 203 is arranged opposite the fourth coil 204 in the Z direction. The fifth coil 205 is arranged opposite the sixth coil 206 in the Z direction. The seventh coil 207 is arranged opposite the eighth coil 208 in the Z direction. The ninth coil 209 is arranged opposite the tenth coil 210 in the Z direction. The eleventh coil 211 is arranged opposite the twelfth coil 212 in the Z direction.

[0306] (Coil connection configuration) 49 and 50, the insulating chip 70 includes first to seventh inner connecting wirings 271 to 277 and first to seventh outer connecting wirings 281 to 287. The first to seventh inner connecting wirings 271 to 277 and the first to seventh outer connecting wirings 281 to 287 are provided in the element insulating layer 72.

[0307] The first inner connecting wiring 271 electrically connects the inner end of the first coil 201 to the first pad 73A. The first outer connecting wiring 281 electrically connects the outer end of the first coil 201 to the first pad 73B. The configuration of the first inner connecting wiring 221 is the same as that of the first inner connecting wiring 221 of the fourth embodiment (see FIG. 38). The configuration of the first outer connecting wiring 281 is the same as that of the first outer connecting wiring 231 of the fourth embodiment (see FIG. 38).

[0308] The second inner connecting wiring 272 and the second outer connecting wiring 282 electrically connect the second coil 202 and the third coil 203. The configuration of the second inner connecting wiring 272 is the same as that of the second inner connecting wiring 222 of the fourth embodiment (see FIG. 37). The configuration of the second outer connecting wiring 282 is the same as that of the second outer connecting wiring 232 of the fourth embodiment (see FIG. 37).

[0309] The third inner connecting wiring 273 and the third outer connecting wiring 283 electrically connect the fourth coil 204 and the fifth coil 205. The third inner connecting wiring 273 and the third outer connecting wiring 283 each extend in the Y direction. The configuration of the third inner connecting wiring 273 is the same as that of the third inner connecting wiring 223 of the fourth embodiment (see FIG. 38). The configuration of the third outer connecting wiring 283 is the same as that of the third outer connecting wiring 233 of the fourth embodiment (see FIG. 38).

[0310] The fourth inner connecting wiring 274 and the fourth outer connecting wiring 284 electrically connect the sixth coil 206 and the seventh coil 207. The fourth inner connecting wiring 274 has the same configuration as the second inner connecting wiring 272, and the fourth outer connecting wiring 284 has the same configuration as the second outer connecting wiring 282.

[0311] The fifth inner connecting wiring 275 and the fifth outer connecting wiring 285 electrically connect the eighth coil 208 and the ninth coil 209. The fifth inner connecting wiring 275 has the same configuration as the third inner connecting wiring 273, and the fifth outer connecting wiring 285 has the same configuration as the third outer connecting wiring 283.

[0312] The sixth inner connecting wiring 276 and the sixth outer connecting wiring 286 electrically connect the tenth coil 210 and the eleventh coil 211. The sixth inner connecting wiring 276 has the same configuration as the second inner connecting wiring 272, and the sixth outer connecting wiring 286 has the same configuration as the second outer connecting wiring 282.

[0313] The seventh inner connecting wiring 277 electrically connects the inner end of the twelfth coil 212 to the second pad 74A. The seventh outer connecting wiring 287 electrically connects the outer end of the twelfth coil 212 to the second pad 74B. The configuration of the seventh inner connecting wiring 277 is the same as that of the fifth inner connecting wiring 225 of the fourth embodiment (see FIG. 38). The configuration of the seventh outer connecting wiring 287 is the same as that of the fifth outer connecting wiring 235 of the fourth embodiment (see FIG. 38).

[0314] (Configuration of semiconductor substrate) 49 and 50, the semiconductor substrate 71 includes first to sixth semiconductor regions 241 to 246, a peripheral region 249, and an insulating region 250. In the seventh embodiment, the insulating region 250 is a region that partitions the semiconductor substrate 71 into the first to sixth semiconductor regions 241 to 246 and the peripheral region 249. The first to sixth semiconductor regions 241 to 246 and the peripheral region 249 are insulated from each other by the insulating region 250. Note that the materials constituting the first to sixth semiconductor regions 241 to 246 and the peripheral region 249 are the same as those of, for example, the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 of the first embodiment.

[0315] The first semiconductor region 241, the second semiconductor region 242, the fifth semiconductor region 245, and the sixth semiconductor region 246 are arranged side by side in the X direction in a planar view. The second semiconductor region 242 and the fifth semiconductor region 245 are arranged between the first semiconductor region 241 and the sixth semiconductor region 246 in the X direction. The second semiconductor region 242 is arranged closer to the first semiconductor region 241 than the fifth semiconductor region 245 in a planar view. The first semiconductor region 241 is arranged closer to the first substrate side surface 71C than the second semiconductor region 242, the fifth semiconductor region 245, and the sixth semiconductor region 246. The sixth semiconductor region 246 is arranged closer to the second substrate side surface 71D than the first semiconductor region 241, the second semiconductor region 242, and the fifth semiconductor region 245.

[0316] The third semiconductor region 243 and the fourth semiconductor region 244 are arranged so as to be shifted in the Y direction with respect to the first semiconductor region 241, the second semiconductor region 242, the fifth semiconductor region 245, and the sixth semiconductor region 246. The third semiconductor region 243 and the fourth semiconductor region 244 are arranged side by side in the X direction in a planar view. The third semiconductor region 243 is arranged side by side with the second semiconductor region 242 in the Y direction. The fourth semiconductor region 244 is arranged side by side with the fifth semiconductor region 245 in the Y direction. In one example, each of the first to sixth semiconductor regions 241 to 246 is rectangular in a planar view.

[0317] The first semiconductor region 241 includes a region that overlaps with at least a portion of both the first coil 201 and the second coil 202 in a planar view. On the other hand, both the first coil 201 and the second coil 202 are disposed at positions spaced apart from the second to sixth semiconductor regions 242 to 246 in a planar view.

[0318] The second semiconductor region 242 includes a region that overlaps with at least a portion of both the third coil 203 and the fourth coil 204 in a planar view. On the other hand, both the third coil 203 and the fourth coil 204 are disposed at positions spaced apart from the first semiconductor region 241 and the third to sixth semiconductor regions 243 to 246 in a planar view.

[0319] The third semiconductor region 243 includes a region that overlaps with at least a portion of both the fifth coil 205 and the sixth coil 206 in a planar view. On the other hand, both the fifth coil 205 and the sixth coil 206 are disposed at positions spaced apart from the first semiconductor region 241, the second semiconductor region 242, and the fourth to sixth semiconductor regions 244 to 246 in a planar view.

[0320] The fourth semiconductor region 244 is a region that overlaps with at least a portion of both the seventh coil 207 and the eighth coil 208 in a planar view. On the other hand, both the seventh coil 207 and the eighth coil 208 are disposed at positions spaced apart from the first to third semiconductor regions 241 to 243, the fifth semiconductor region 245, and the sixth semiconductor region 246 in a planar view.

[0321] The fifth semiconductor region 245 is a region that overlaps with at least a portion of both the ninth coil 209 and the tenth coil 210 in a plan view. On the other hand, the ninth coil 209 and the tenth coil 210 are disposed at positions spaced apart from the first to fourth semiconductor regions 241 to 244 and the sixth semiconductor region 246.

[0322] The sixth semiconductor region 246 is a region that overlaps with at least a portion of both the eleventh coil 211 and the twelfth coil 212 in a plan view. On the other hand, the eleventh coil 211 and the twelfth coil 212 are disposed at positions spaced apart from the first to fifth semiconductor regions 241 to 245.

[0323] The outer circumferential region 249 is frame-shaped with a predetermined width and surrounds the first to sixth semiconductor regions 241 to 246 in a plan view. It can also be said that the outer circumferential region 249 surrounds the insulating region 250 in a plan view. In one example, the outer circumferential region 249 is square-shaped in a plan view. In one example, the first to twelfth coils 201 to 212 are located inward of the outer circumferential region 249 in a plan view.

[0324] The insulating region 250 includes first to sixth insulating regions 251 to 256 in a planar view. The first insulating region 251 has a frame shape surrounding the first semiconductor region 241 in a planar view. The second insulating region 252 has a frame shape surrounding the second semiconductor region 242 in a planar view. The third insulating region 253 has a frame shape surrounding the third semiconductor region 243 in a planar view. The fourth insulating region 254 has a frame shape surrounding the fourth semiconductor region 244 in a planar view. The fifth insulating region 255 has a frame shape surrounding the fifth semiconductor region 245 in a planar view. The sixth insulating region 256 has a frame shape surrounding the sixth semiconductor region 246 in a planar view. In one example, each of the first to sixth insulating regions 251 to 256 has a rectangular frame shape in a planar view. The shape of each of the first to sixth insulating regions 251 to 256 in plan view is not limited to a rectangular frame shape, and can be changed arbitrarily.

[0325] In one example, the first to sixth insulating regions 251 to 256 are integrated together, so that the insulating region 250 includes first to sixth intermediate insulating regions 261 to 266. The first intermediate insulating region 261 is a region that serves as both the first insulating region 251 and the second insulating region 252. The first intermediate insulating region 261 is provided between the first semiconductor region 241 and the second semiconductor region 242 in the X direction. The first intermediate insulating region 261 extends in the Y direction.

[0326] The second intermediate insulating region 262 is a region that serves as both the second insulating region 252 and the third insulating region 253. The second intermediate insulating region 262 is provided between the second semiconductor region 242 and the third semiconductor region 243 in the Y direction. The second intermediate insulating region 262 extends in the X direction.

[0327] The third intermediate insulating region 263 is a region that serves as both the third insulating region 253 and the fourth insulating region 254. The third intermediate insulating region 263 is provided between the third semiconductor region 243 and the fourth semiconductor region 244 in the X direction. The third intermediate insulating region 263 extends in the Y direction.

[0328] The fourth intermediate insulating region 264 is a region that serves as both the fourth insulating region 254 and the fifth insulating region 255. The fourth intermediate insulating region 264 is provided between the fourth semiconductor region 244 and the fifth semiconductor region 245 in the Y direction. The fourth intermediate insulating region 264 extends in the X direction.

[0329] The fifth intermediate insulating region 265 is a region that serves as both the second insulating region 252 and the fifth insulating region 255. The fifth intermediate insulating region 265 is provided between the second semiconductor region 242 and the fifth semiconductor region 245 in the X direction. The fifth intermediate insulating region 265 extends in the Y direction.

[0330] The sixth intermediate insulating region 266 is a region that serves as both the fifth insulating region 255 and the sixth insulating region 256. The sixth intermediate insulating region 266 is provided between the fifth semiconductor region 245 and the sixth semiconductor region 246 in the X direction. The sixth intermediate insulating region 266 extends in the Y direction.

[0331] The width and thickness dimensions of the insulating region 250 may be equal to the width dimensions WR1 to WR3 and thickness dimension HR of the insulating region 140 of the first embodiment. The material of the insulating region 250 may be the same as the material of the insulating region 140 of the first embodiment.

[0332] [Effects of the Seventh Embodiment] The insulating chip 70 and semiconductor device 10 of the seventh embodiment provide the following advantages. (7-1) The insulating chip 70 includes a ninth coil 209 and a twelfth coil 212 spaced apart from each other in the X direction, a tenth coil 210 facing the ninth coil 209 in the Z direction, and an eleventh coil 211 facing the twelfth coil 212 in the Z direction. The ninth coil 209 and the twelfth coil 212 are spaced apart from each of the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 when viewed from the Z direction. The tenth coil 210 and the eleventh coil 211 are spaced apart from each of the second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 when viewed from the Z direction. The semiconductor substrate 71 includes a fifth semiconductor region 245 arranged at a distance from the first semiconductor region 241, the second semiconductor region 242, the third semiconductor region 243, and the fourth semiconductor region 244 when viewed from the Z direction, and a sixth semiconductor region 246 arranged at a distance from the first semiconductor region 241, the second semiconductor region 242, the third semiconductor region 243, the fourth semiconductor region 244, and the fifth semiconductor region 245 when viewed from the Z direction. The insulating region 250 is configured to insulate the first semiconductor region 241, the second semiconductor region 242, the third semiconductor region 243, the fourth semiconductor region 244, the fifth semiconductor region 245, and the sixth semiconductor region 246 from one another. When viewed from the Z direction, both the ninth coil 209 and the tenth coil 210 are spaced apart from the first semiconductor region 241, the second semiconductor region 242, the third semiconductor region 243, the fourth semiconductor region 244, and the sixth semiconductor region 246, and are arranged so that at least a portion of each of them overlaps with the fifth semiconductor region 245. When viewed from the Z direction, both the eleventh coil 211 and the twelfth coil 212 are spaced apart from the first semiconductor region 241, the second semiconductor region 242, the third semiconductor region 243, the fourth semiconductor region 244, and the fifth semiconductor region 245, and are arranged so that at least a portion of each of them overlaps with the sixth semiconductor region 246.

[0333] According to this configuration, the first to twelfth coils 201 to 212 connect a plurality of insulating structures in series, thereby achieving an even higher withstand voltage for the insulating chip 70. More specifically, the first to sixth semiconductor regions 241 to 246 are insulated from one another by the insulating region 250, which makes it possible to suppress the dependence of the first to fifth semiconductor regions 241 to 245 on the potential of the second die pad 91, and to suppress the dependence of the second to sixth semiconductor regions 242 to 246 on the potential of the first die pad 81. This prevents the dielectric strength of the insulating chip 70 from decreasing due to the distance in the Z direction between the first coil 201 and the first semiconductor region 241, the distance in the Z direction between the fourth coil 204 and the second semiconductor region 242, the distance in the Z direction between the fifth coil 205 and the third semiconductor region 243, the distance in the Z direction between the eighth coil 208 and the fourth semiconductor region 244, the distance in the Z direction between the ninth coil 209 and the fifth semiconductor region 245, and the distance in the Z direction between the twelfth coil 212 and the sixth semiconductor region 246. Furthermore, the second coil 202 and the third coil 203, which are electrically connected to each other, the fourth coil 204 and the fifth coil 205, which are electrically connected to each other, the sixth coil 206 and the seventh coil 207, which are electrically connected to each other, the eighth coil 208 and the ninth coil 209, which are electrically connected to each other, and the tenth coil 210 and the eleventh coil 211, which are electrically connected to each other, each have an intermediate potential between the first coil 201 and the twelfth coil 212. In other words, the insulating chip 70 has a plurality of intermediate potentials. This allows the insulating chip 70 to withstand a higher voltage.

[0334] (7-2) The first semiconductor region 241, the second semiconductor region 242, the fifth semiconductor region 245, and the sixth semiconductor region 246 are arranged side by side in the X direction. The third semiconductor region 243 and the fourth semiconductor region 244 are arranged side by side in the X direction, and are shifted in the Y direction with respect to the first semiconductor region 241, the second semiconductor region 242, the fifth semiconductor region 245, and the sixth semiconductor region 246. The second semiconductor region 242 and the third semiconductor region 243 are arranged side by side in the Y direction. The fourth semiconductor region 244 and the fifth semiconductor region 245 are arranged side by side in the Y direction.

[0335] With this configuration, the dimension of the insulating chip 70 in the X direction is smaller than in a configuration in which the first to sixth semiconductor regions 241 to 246 are arranged in a row in the X direction, and therefore the insulating chip 70 can be made smaller in size in the X direction.

[0336] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0337] The second and third embodiments can be combined with each other. That is, in the insulating chip 70 of the second embodiment, the transformer 40 can be replaced with a capacitor 170.

[0338] The configuration of the capacitor 300 of the sixth embodiment can be applied to the fourth, fifth, and seventh embodiments. The configurations of the first unit 150 and the second unit 160 of the fifth embodiment can be applied to the seventh embodiment.

[0339] The joining manner between the first unit 150 and the second unit 160 in the second and fifth embodiments can be changed as desired. In one example, the first unit 150 and the second unit 160 may be joined to each other by an insulating bonding material. The insulating bonding material is interposed between the first unit 150 and the second unit 160 in the Z direction. The insulating bonding material is in contact with the first protective layer 153 of the first unit 150 and the second protective layer 163 of the second unit 160.

[0340] In the second and fifth embodiments, the size of the second unit 160 in a plan view can be changed arbitrarily. In one example, the dimension of the second unit 160 in the Y direction may be equal to the dimension of the first unit 150 in the Y direction.

[0341] In the second and fifth embodiments, the second semiconductor substrate 161 may be omitted from the second unit 160. In the second and fifth embodiments, the first pad 73 and the second pad 74 may be provided on the second unit 160. In this case, the first pad 73 and the second pad 74 may be provided so as to be exposed from an opening that penetrates the second semiconductor substrate 161 in the Z direction, for example. Alternatively, the first pad 73 and the second pad 74 may be provided on the second semiconductor substrate 161. Both the inner connection wiring 45A and the outer connection wiring 46A that connect the first pad 73 and the first coil 41 are provided on both the first unit 150 and the second unit 160. The inner connection wiring 45A and the outer connection wiring 46A are provided so as to electrically connect the first pad 73 and the first coil 41 when the second unit 160 is placed on the first unit 150. Furthermore, both the inner connection wiring 45B and the outer connection wiring 46B that connect the second pad 74 and the fourth coil 44 are provided on both the first unit 150 and the second unit 160. The inner connection wiring 45B and the outer connection wiring 46B are provided so that the second pad 74 and the fourth coil 44 are electrically connected when the second unit 160 is placed on the first unit 150.

[0342] In the first to third embodiments, the inter-region distance DR between the first semiconductor region 131 and the second semiconductor region 132 in the X direction can be changed arbitrarily. For example, the inter-region distance DR may be equal to or greater than the inter-pad distance PR between the first die pad 81 and the second die pad 91 in the X direction. For example, the inter-region distance DR may be equal to or greater than the distance DC between the first coil 41 and the fourth coil 44 in the X direction. For example, the inter-region distance DR may be equal to or greater than the distance DD between the second coil 42 and the third coil 43 in the X direction.

[0343] In one example, the inter-region distance DR may be equal to or less than the distance DA between the first coil 41 and the second coil 42 in the Z direction. In another example, the inter-region distance DR may be equal to or less than the distance DB between the third coil 43 and the fourth coil 44 in the Z direction.

[0344] In each embodiment, the inter-pad distance PR can be changed as desired. For example, the inter-pad distance PR may be equal to or greater than the distance DC between the first coil 41 and the fourth coil 44 in the X direction. The inter-pad distance PR may be equal to or greater than the distance DD between the second coil 42 and the third coil 43 in the X direction.

[0345] In the first to third embodiments, the configuration of the intermediate insulating region 143 of the insulating region 140 can be changed as desired. For example, Fig. 51 shows a modified example of the intermediate insulating region 143. Fig. 51 schematically shows the cross-sectional structure of the insulating chip 70 mounted on the first die pad 81 and the second die pad 91.

[0346] 51, the intermediate insulating region 143 includes a plurality of insulating portions 143A to 143C. The insulating portions 143A to 143C are arranged to be spaced apart from one another in the X direction. Each of the insulating portions 143A to 143C is made of SiO2.

[0347] Intermediate semiconductor regions 134A and 134B are defined between adjacent insulating portions in the X direction among the multiple insulating portions 143A to 143C. The intermediate semiconductor regions 134A and 134B are electrically insulated from the first semiconductor region 131, the second semiconductor region 132, and the peripheral region 133 by the intermediate insulating region 143. The intermediate semiconductor region 134A is a region between the insulating portion 143A and the insulating portion 143B in the X direction. The intermediate semiconductor region 134B is a region between the insulating portion 143B and the insulating portion 143C in the X direction. The intermediate semiconductor regions 134A and 134B are made of a material containing Si. In other words, the intermediate semiconductor regions 134A and 134B are made of the same material as the semiconductor substrate 71.

[0348] The width dimension WR3 of the intermediate insulating region 143 shown in FIG. 51 can be defined as the distance in the X direction between the edge of the insulating portion 143A closest to the first chip side surface 70A and the terminal of the insulating portion 143B closest to the second chip side surface 70B. Therefore, the width dimension WR3 of the intermediate insulating region 143 is larger than both the width dimension WR1 of the first insulating region 141 and the width dimension WR2 of the second insulating region 142. The width dimension WR3 of the intermediate insulating region 143 is also larger than the dimension HR3 of the intermediate insulating region 143 in the thickness direction. The width dimension WR3 of the intermediate insulating region 143 is also larger than the thickness TR of the semiconductor substrate 71. Furthermore, in the example shown in FIG. 51, the inter-region distance DR is equal to the width dimension WR3 of the intermediate insulating region 143. Therefore, the inter-region distance DR is larger than the inter-pad distance PR.

[0349] In the first to third embodiments, the relationship between the width dimension WR of the insulating region 140 and the dimension HR in the thickness direction of the insulating region 140 can be changed as desired. For example, as shown in Fig. 52, the width dimension WR of the insulating region 140 may be larger than the dimension HR in the thickness direction of the insulating region 140. Similarly, in the fourth to seventh embodiments, the width dimension of the insulating region 250 may be larger than the dimension in the thickness direction of the insulating region 250.

[0350] In the first to third embodiments, the configuration of the insulating region 140 in plan view can be changed arbitrarily. The insulating region 140 may be changed as in the first example shown in FIG. 53, the second example shown in FIG. 54, the third example shown in FIG. 55, and the fourth example shown in FIG. 56. FIGS. 53 to 56 schematically show the bottom structure of the insulating chip 70. Note that the insulating region 250 in the fourth to seventh embodiments may also be changed as in the first example.

[0351] 53 , in the first example insulating region 140, a first insulating region 141 and a second insulating region 142 are provided to be spaced apart in the X direction. The region of the semiconductor substrate 71 between the first insulating region 141 and the second insulating region 142 in the X direction is continuous with the peripheral region 133.

[0352] 54, in the insulating region 140 of the second example, the first insulating region 141 extends to the first substrate side surface 71C in a planar view. The second insulating region 142 extends to the second substrate side surface 71D in a planar view. That is, the first semiconductor region 131 extends to the first substrate side surface 71C in a planar view. The second semiconductor region 132 extends to the second substrate side surface 71D in a planar view. The peripheral region 133 includes two regions separated in the Y direction: a region between the third substrate side surface 71E and the insulating region 140 in the Y direction in a planar view, and a region between the fourth substrate side surface 71F and the insulating region 140 in the Y direction in a planar view.

[0353] 55, the insulating region 140 of the third example includes a first insulating region 141 and a second insulating region 142 that are spaced apart in the X direction. The first insulating region 141 extends to the first substrate side surface 71C in plan view. The second insulating region 142 extends to the second substrate side surface 71D in plan view.

[0354] 56, the insulating region 140 of the fourth example penetrates the semiconductor substrate 71 in the Y direction. The insulating region 140 extends along the Y direction. This divides the semiconductor substrate 71 into a first semiconductor region 131 and a second semiconductor region 132. In the fourth example, the semiconductor substrate 71 does not include the peripheral region 133.

[0355] In each embodiment, the first bonding material 121 may be in contact with the entire first semiconductor region 131. The second bonding material 122 may be in contact with the entire second semiconductor region 132.

[0356] In the first, third, fourth, sixth, and seventh embodiments, the relationship between the thickness TR of the semiconductor substrate 71 of the insulating chip 70 and the thickness TA of the first semiconductor substrate 51 of the first chip 50 and the thickness TB of the second semiconductor substrate 61 of the second chip 60 can be changed as desired. In one example, the thickness TR of the semiconductor substrate 71 may be equal to the thickness TA of the first semiconductor substrate 51 and the thickness TB of the second semiconductor substrate 61. In another example, the thickness TR of the semiconductor substrate 71 may be greater than the thickness TA of the first semiconductor substrate 51 and the thickness TB of the second semiconductor substrate 61.

[0357] In the second and fifth embodiments, the relationship between the thickness TR of the first semiconductor substrate 151 of the insulating chip 70 and the thickness TA of the first semiconductor substrate 51 of the first chip 50 and the thickness TB of the second semiconductor substrate 61 of the second chip 60 can be changed as desired. In one example, the thickness TS of the first semiconductor substrate 151 may be equal to the thickness TA of the first semiconductor substrate 51 and the thickness TB of the second semiconductor substrate 61. In another example, the thickness TS of the first semiconductor substrate 151 may be greater than the thickness TA of the first semiconductor substrate 51 and the thickness TB of the second semiconductor substrate 61.

[0358] In the first, third, fourth, sixth, and seventh embodiments, the configuration of the element insulating layer 72 can be changed arbitrarily. For example, as shown in FIG. 57, the element insulating layer 72 may be configured with a stacked structure of a second insulating film 75B. That is, the first insulating film 75A may be omitted from the element insulating layer 72. Note that the first element insulating layer 152 of the first unit 150 in the second and fifth embodiments may be changed in a similar manner. The second element insulating layer 162 of the second unit 160 may be changed in a similar manner.

[0359] In each embodiment, the configuration of the semiconductor device 10 can be changed as desired. In one example, the first chip 50 may be omitted from the semiconductor device 10. In one example, the second chip 60 may be omitted from the semiconductor device 10. In one example, both the first chip 50 and the second chip 60 may be omitted from the semiconductor device 10.

[0360] In the fourth embodiment, the arrangement of the first to eighth coils 201 to 208 can be changed as desired. For example, at least one of the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 may be arranged so as to be shifted in the Y direction relative to the other coils. Examples of such arrangements include a first example shown in FIGS. 58 and 59 and a second example shown in FIGS. 60 and 61.

[0361] In the first example, as shown in FIGS. 58 and 59, the fifth to eighth coils 205 to 208 may be arranged so as to be shifted in the Y direction relative to the first to fourth coils 201 to 204. The fifth coil 205 may be arranged so as to overlap with the fourth coil 204 when viewed from the Y direction. The sixth coil 206 may be arranged so as to overlap with the third coil 203 when viewed from the Y direction. Both the third inner connection wiring 223 and the third outer connection wiring 233 extend in the Y direction. Each second pad 74 is arranged so as to be shifted in the Y direction relative to each first pad 73. Each second pad 74 is arranged so as to be adjacent to the seventh coil 207 in the X direction in a plan view.

[0362] Due to this arrangement of the first to eighth coils 201 to 208, the arrangement of the first to fourth semiconductor regions 241 to 244 differs from that of the fourth embodiment. In one example, the third semiconductor region 243 and the fourth semiconductor region 244 are arranged to be shifted in the Y direction relative to the first semiconductor region 241 and the second semiconductor region 242. The third semiconductor region 243 is arranged side by side with the second semiconductor region 242 in the Y direction. The second intermediate insulating region 262 of the insulating region 250 extends in the X direction.

[0363] 58 and 59, the dimension of the insulating chip 70 in the X direction can be reduced, thereby enabling the insulating chip 70 to be made smaller in size in the X direction.

[0364] 60 and 61, the first coil 201, the fourth coil 204, the fifth coil 205, and the eighth coil 208 may be arranged in a matrix. The second coil 202, the third coil 203, the sixth coil 206, and the seventh coil 207 may be arranged in a matrix.

[0365] 61, the first coil 201 and the fourth coil 204 may be arranged side by side in the X direction, and the fifth coil 205 and the eighth coil 208 may be arranged side by side in the X direction. The fifth coil 205 and the eighth coil 208 may be arranged offset in the Y direction with respect to the first coil 201 and the fourth coil 204. The first coil 201 and the eighth coil 208 may be arranged side by side in the Y direction, and the fourth coil 204 and the fifth coil 205 may be arranged side by side in the Y direction.

[0366] 60, the second coil 202 and the third coil 203 may be arranged side by side in the X direction, and the sixth coil 206 and the seventh coil 207 may be arranged side by side in the X direction. The sixth coil 206 and the seventh coil 207 may be arranged offset in the Y direction with respect to the second coil 202 and the third coil 203. The second coil 202 and the seventh coil 207 may be arranged side by side in the Y direction, and the third coil 203 and the sixth coil 206 may be arranged side by side in the Y direction.

[0367] Due to this arrangement of the first to eighth coils 201 to 208, the arrangement of the first to fourth semiconductor regions 241 to 244 differs from that of the fourth embodiment. In one example, the third semiconductor region 243 and the fourth semiconductor region 244 are arranged so as to be shifted in the Y direction relative to the first semiconductor region 241 and the second semiconductor region 242. The third semiconductor region 243 is arranged side by side with the second semiconductor region 242 in the Y direction. The fourth semiconductor region 244 is arranged side by side with the first semiconductor region 241 in the Y direction.

[0368] The insulating region 250 includes a fourth intermediate insulating region 264. This fourth intermediate insulating region 264 is provided between the first insulating region 251 and the second insulating region 252 in the Y direction. The fourth intermediate insulating region 264 constitutes part of the first insulating region 251 and the second insulating region 252. The second intermediate insulating region 262 and the fourth intermediate insulating region 264 each extend in the X direction. The second intermediate insulating region 262 and the fourth intermediate insulating region 264 are connected to each other. The first intermediate insulating region 261 and the third intermediate insulating region 263 each extend in the Y direction. The first intermediate insulating region 261 and the third intermediate insulating region 263 are connected to each other.

[0369] 60 and 61, the dimension of the insulating chip 70 in the X direction can be reduced, thereby enabling the insulating chip 70 to be made smaller in size in the X direction.

[0370] 58 and 59, the fourth coil 204 (third coil 203) and the fifth coil 205 (sixth coil 206) are arranged at the same position in the X direction and spaced apart from each other in the Y direction, but this is not limiting. In one example, the fourth coil 204 (third coil 203) and the fifth coil 205 (sixth coil 206) may be arranged spaced apart from each other in both the X direction and the Y direction.

[0371] 60 and 61, the first coil 201 (second coil 202) and the fourth coil 204 (third coil 203) are arranged at the same position in the X direction and spaced apart from each other in the Y direction, but this is not limiting. In one example, the first coil 201 (second coil 202) and the fourth coil 204 (third coil 203) may be arranged spaced apart from each other in both the X direction and the Y direction.

[0372] Furthermore, the fifth coil 205 (sixth coil 206) and the eighth coil 208 (seventh coil 207) are arranged at the same position in the X direction and spaced apart from each other in the Y direction, but this is not limiting. In one example, the fifth coil 205 (sixth coil 206) and the eighth coil 208 (seventh coil 207) may be arranged spaced apart from each other in both the X direction and the Y direction.

[0373] In the seventh embodiment, the arrangement of the first to twelfth coils 201 to 212 can be changed as desired. In one example, the first coil 201, the fourth coil 204, the fifth coil 205, the eighth coil 208, the ninth coil 209, and the twelfth coil 212 may be arranged in a line in the X direction. The second coil 202, the third coil 203, the sixth coil 206, the seventh coil 207, the tenth coil 210, and the eleventh coil 211 may be arranged in a line in the X direction. In this case, the first to sixth semiconductor regions 241 to 246 are arranged in a line in the X direction.

[0374] In the seventh embodiment, the number of insulating elements of the insulating chip 70 can be changed arbitrarily. In one example, the number of insulating elements may be an even number of 14 or more. One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent.

[0375] The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0376] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0377] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0378] [Appendix 1] A semiconductor substrate (71); an element insulating layer (72) provided on the semiconductor substrate (71); a first insulating element (41 / 171A) and a fourth insulating element (44 / 172B) provided in the element insulating layer (72) and spaced apart from each other in a first direction (X) intersecting a thickness direction (Z) of the element insulating layer (72), a second insulating element (42 / 171B) arranged opposite the first insulating element (41 / 171A) in the thickness direction (Z), and a third insulating element (43 / 172A) arranged opposite the fourth insulating element (44 / 172B) in the thickness direction (Z); Including, The semiconductor substrate (71) a first semiconductor region (131); a second semiconductor region (132) disposed apart from the first semiconductor region (131) in the first direction (X); an insulating region (140) that insulates the first semiconductor region (131) from the second semiconductor region (132); Including, When viewed from the thickness direction (Z), both the first insulating element (41 / 171A) and the second insulating element (42 / 171B) are spaced apart from the second semiconductor region (132) and are arranged so that at least a portion of each element overlaps the first semiconductor region (131); When viewed from the thickness direction (Z), both the third insulating element (43 / 172A) and the fourth insulating element (44 / 172B) are spaced apart from the first semiconductor region (131) and are arranged so that at least a portion of each of them overlaps with the second semiconductor region (132). Insulating tip (70).

[0379] [Appendix 2] Both the first semiconductor region (131) and the second semiconductor region (132) are made of a material containing Si, The insulating region (140) is made of SiO2. 10. The insulated tip of claim 1.

[0380] [Appendix 3] The width dimension (WR) of the insulating region (140) is smaller than the dimension (HR) in the thickness direction of the insulating region (140). 10. The insulated tip of claim 1 or 2.

[0381] [Appendix 4] The width dimension (WR) of the insulating region (140) is greater than the thickness dimension (HR) of the insulating region (140). 10. The insulated tip of claim 1 or 2.

[0382] [Appendix 5] The insulating region (140) is a frame-shaped first insulating region (141) surrounding the first semiconductor region (131) when viewed from the thickness direction (Z); a frame-shaped second insulating region (142) surrounding the second semiconductor region (132) when viewed from the thickness direction (Z); Contains An insulating chip according to any one of appendices 1 to 4.

[0383] [Appendix 6] The insulating region (140) includes an intermediate insulating region (143) provided between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X), The intermediate insulating region (143) constitutes a part of the first insulating region (141) and the second insulating region (142). 10. The insulated tip of claim 5.

[0384] [Appendix 7] A connection wiring (47 / 183) is provided in the element insulating layer (72) and electrically connects the second insulating element (42 / 171B) and the third insulating element (43 / 172A). An insulating chip according to any one of appendices 1 to 6.

[0385] [Appendix 8] a first pad (73) electrically connected to the first insulating element (41 / 171A); a second pad (74) electrically connected to the fourth insulating element (44 / 172B); Including, the first pad (73) is disposed on the opposite side of the first insulating element (41 / 171A) to the fourth insulating element (44 / 172B) in the first direction (X); The second pad (74) is disposed on the opposite side of the fourth insulating element (44 / 172B) from the first insulating element (41 / 171A) in the first direction (X). An insulating chip according to any one of appendices 1 to 7.

[0386] [Appendix 9] the first insulating element (41 / 171A) is disposed closer to the semiconductor substrate (71) in the thickness direction (Z) than the second insulating element (42 / 171B); The fourth insulating element (44 / 172B) is disposed closer to the semiconductor substrate (71) in the thickness direction (Z) than the third insulating element (43 / 172A). 10. The insulated tip of claim 8.

[0387] [Appendix 10] Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is a coil (41 to 44). An insulating chip according to any one of appendices 1 to 9.

[0388] [Appendix 11] Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is an electrode plate (171A, 171B, 172A, 172B). An insulating chip according to any one of appendices 1 to 9.

[0389] [Appendix 12] The first unit (150), a second unit (160) disposed on the first unit (150); Equipped with The first unit (150) comprises: a first semiconductor substrate (151); a first element insulating layer (152) provided on the first semiconductor substrate (151); a first insulating element (41 / 171A) and a fourth insulating element (44 / 172B) embedded in the first element insulating layer (152), spaced apart from each other in a first direction (X) intersecting the thickness direction (Z) of the first element insulating layer (152), and electrically insulated from each other; Including, The first semiconductor substrate (151) a first semiconductor region (131); a second semiconductor region (132) disposed apart from the first semiconductor region (131) in the first direction (X); an insulating region (140) that insulates the first semiconductor region (131) from the second semiconductor region (132); Including, The second unit (160) comprises: a second element insulating layer (162) provided on the first element insulating layer (152); a second insulating element (42 / 171B) and a third insulating element (43 / 172A) embedded in the second element insulating layer (162), spaced apart from each other in the first direction (X), and electrically connected to each other; Including, The first insulating element (41 / 171A) and the second insulating element (42 / 171B) are disposed opposite each other in the thickness direction (Z), and the third insulating element (43 / 172A) and the fourth insulating element (44 / 172B) are disposed opposite each other in the thickness direction (Z). Insulating tip (70).

[0390] [Appendix 13] Both the first semiconductor region (131) and the second semiconductor region (132) are made of a material containing Si, The insulating region (140) is made of SiO2. 13. The insulated tip of claim 12.

[0391] [Appendix 14] The width dimension (WR) of the insulating region (140) is smaller than the dimension (HR) in the thickness direction of the insulating region (140). 14. The insulated tip of claim 12 or 13.

[0392] [Appendix 15] The width dimension (WR) of the insulating region (140) is greater than the thickness dimension (HR) of the insulating region (140). 14. The insulated tip of claim 12 or 13.

[0393] [Appendix 16] The insulating region (140) is a frame-shaped first insulating region (141) surrounding the first semiconductor region (131) when viewed from the thickness direction (Z); a frame-shaped second insulating region (142) surrounding the second semiconductor region (132) when viewed from the thickness direction (Z); Contains 16. An insulating chip according to any one of appendices 12 to 15.

[0394] [Appendix 17] The insulating region (140) includes an intermediate insulating region (143) provided between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X), The intermediate insulating region (143) constitutes a part of the first insulating region (131) and the second insulating region (132). 17. The insulated tip of claim 16.

[0395] [Appendix 18] The first unit (150) comprises: a first pad (73) electrically connected to the first insulating element (41 / 171A) and exposed from the first element insulating layer (152) in the thickness direction (Z); a second pad (74) electrically connected to the fourth insulating element (44 / 172B) and exposed from the first element insulating layer (152) in the thickness direction (Z); Contains An insulating chip according to any one of appendices 12 to 17.

[0396] [Appendix 19] The second unit (160) is smaller than the first unit (150) in a plan view seen from the thickness direction (Z), Both the first pad (73) and the second pad (74) are provided at positions different from the second unit (160) in the plan view. 19. The insulated tip of claim 18.

[0397] [Appendix 20] The first insulating element (41 / 171A) and the fourth insulating element (44 / 172B) are disposed closer to the first semiconductor substrate (151) than the center of the first element insulating layer (152) in the thickness direction (Z). 20. An insulating chip according to any one of appendices 12 to 19.

[0398] [Appendix 21] The second insulating element (42 / 171B) and the third insulating element (43 / 172A) are disposed on the opposite side of the first unit (150) from the center of the second element insulating layer (162) in the thickness direction (Z). An insulating chip according to any one of appendices 12 to 20.

[0399] [Appendix 22] The intermediate insulating region (143) is a plurality of insulating portions (143A to 143C) spaced apart from each other in the first direction (X); At least one intermediate semiconductor region (134A, 134B) provided between the plurality of insulating portions (143A to 143C); Including, The intermediate semiconductor regions (134A, 134B) are electrically insulated from the first semiconductor region (131) and the second semiconductor region (132). 18. The insulated tip of claim 6 or 17.

[0400] [Appendix 23] The insulating portions (143A to 143D) are made of SiO2, The intermediate semiconductor regions (134A, 134B) are made of a material containing Si. 23. The insulated tip of claim 22.

[0401] [Appendix 24] The insulating region (140) penetrates the semiconductor substrate (71) in a second direction (Y) perpendicular to the first direction (X) when viewed from the thickness direction (Z). An insulating chip according to any one of appendices 1 to 11.

[0402] [Appendix 25] The insulating region (140) penetrates the first semiconductor substrate (151) in a second direction (Y) perpendicular to the first direction (X) when viewed from the thickness direction (Z) of the first semiconductor substrate (151). An insulating chip according to any one of appendices 12 to 20.

[0403] [Appendix 26] A first die pad (81), a second die pad (91) disposed apart from the first die pad (81) in a first direction (X); an insulating chip (70) arranged so as to straddle the first die pad (81) and the second die pad (91) in the first direction (X); Equipped with The insulating tip (70) A semiconductor substrate (71); an element insulating layer (72) provided on the semiconductor substrate (71); a first insulating element (41 / 171A) and a fourth insulating element (44 / 172B) embedded in the element insulating layer (72) and spaced apart from each other in the first direction (X); a second insulating element (42 / 171B) arranged opposite the first insulating element (41 / 171A) in the thickness direction (Z) of the element insulating layer (72); and a third insulating element (43 / 172A) arranged opposite the fourth insulating element (44 / 172B) in the thickness direction (Z); Including, The semiconductor substrate (71) a first semiconductor region (131); a second semiconductor region (132) disposed apart from the first semiconductor region (131) in the first direction (X); an insulating region (140) that insulates the first semiconductor region (131) from the second semiconductor region (132); Including, When viewed from the thickness direction (Z), both the first insulating element (41 / 171A) and the second insulating element (42 / 171B) are spaced apart from the second semiconductor region (132) and are arranged so that at least a portion of each element overlaps the first semiconductor region (131); When viewed from the thickness direction (Z), both the third insulating element (43 / 172A) and the fourth insulating element (44 / 172B) are spaced apart from the first semiconductor region (131) and are arranged so that at least a portion of each of them overlaps with the second semiconductor region (132). A semiconductor device (10).

[0404] [Appendix 27] The first semiconductor region (131) is bonded to the first die pad (81) by a conductive first bonding material (121), The second semiconductor region (132) is bonded to the second die pad (91) by a conductive second bonding material (122). 27. The semiconductor device according to claim 26.

[0405] [Appendix 28] The insulating region (140) is a frame-shaped first insulating region (141) surrounding the first semiconductor region (131) when viewed from the thickness direction (Z); a frame-shaped second insulating region (142) surrounding the second semiconductor region (132) when viewed from the thickness direction (Z); Including, The semiconductor substrate (71) includes a peripheral region (133) surrounding the first insulating region (131) and the second insulating region (132), the first bonding material (121) is not in contact with the outer peripheral region (133) of the semiconductor substrate (71) but is in contact with the first semiconductor region (131); The second bonding material (122) does not contact the peripheral region (133) of the semiconductor substrate (71) but contacts the second semiconductor region (132). 28. The semiconductor device according to claim 27.

[0406] [Appendix 29] the first bonding material (121) includes a portion that contacts the first semiconductor region (131) and is spaced apart from the first insulating region (141) when viewed from the thickness direction (Z), The second bonding material (122) includes a portion that contacts the second semiconductor region (132) and is spaced apart from the second insulating region (142) when viewed from the thickness direction (Z). 29. The semiconductor device according to claim 28.

[0407] [Appendix 30] a first chip (50) disposed on the first die pad (81) and electrically connected to the first insulating element (41 / 171A) of the insulating chip (70); a second chip (60) disposed on the second die pad (91) and electrically connected to the fourth insulating element (44 / 172B) of the insulating chip (70); Contains 30. The semiconductor device according to any one of appendices 26 to 29.

[0408] [Appendix 31] The first chip (50) includes a first chip semiconductor substrate (51), The second chip (60) includes a second chip semiconductor substrate (61), The thickness (TR) of the semiconductor substrate (71) of the insulating chip (70) is thinner than the thickness (TA) of the semiconductor substrate (51) for the first chip and the thickness (TB) of the semiconductor substrate (61) for the second chip. 31. The semiconductor device according to claim 30.

[0409] [Appendix 32] A region-to-region distance (DR) between the first semiconductor region (131) and the second semiconductor region (12) in the first direction (X) is smaller than a pad-to-pad distance (PR) between the first die pad (81) and the second die pad (91) in the first direction (X). 32. The semiconductor device according to any one of claims 26 to 31.

[0410] [Appendix 33] The inter-region distance (DR) between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X) is greater than the distance (DA / EA) between the first insulating element (41 / 171A) and the second insulating element (42 / 171B) in the thickness direction (Z). 33. The semiconductor device according to any one of claims 26 to 32.

[0411] [Appendix 34] A region-to-region distance (DR) between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X) is equal to or greater than a pad-to-pad distance (PR) between the first die pad (81) and the second die pad (91) in the first direction (X). 32. The semiconductor device according to any one of claims 26 to 31.

[0412] [Appendix 35] The insulating region (140) includes an intermediate insulating region (143) provided between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X), The intermediate insulating region (143) constitutes a part of the first insulating region (141) and the second insulating region (142). 30. The semiconductor device according to claim 28 or 29.

[0413] [Appendix 36] A first die pad (81), a second die pad (91) disposed apart from the first die pad (81) in a first direction (X); an insulating chip (70) arranged so as to straddle the first die pad (81) and the second die pad (91) in the first direction (X); Equipped with The insulating tip (70) The first unit (150), a second unit (160) disposed on the first unit (150); Equipped with The first unit (150) comprises: a first semiconductor substrate (151); a first element insulating layer (152) provided on the first semiconductor substrate (151); a first insulating element (41 / 171A) and a fourth insulating element (44 / 172B) embedded in the first element insulating layer (152), spaced apart from each other in the first direction (X), and electrically insulated from each other; Including, The first semiconductor substrate (151) a first semiconductor region (131); a second semiconductor region (132) disposed apart from the first semiconductor region (131) in the first direction (X); an insulating region (140) that insulates the first semiconductor region (131) from the second semiconductor region (132); Including, The second unit (160) comprises: a second element insulating layer (162) provided on the first element insulating layer (152); a second insulating element (42 / 171B) and a third insulating element (43 / 172A) embedded in the second element insulating layer (162), spaced apart from each other in the first direction (X), and electrically connected to each other; Including, The first insulating element (41 / 171A) and the second insulating element (42 / 171B) are arranged opposite each other in the thickness direction (Z) of the first element insulating layer (152), and the third insulating element (43 / 172A) and the fourth insulating element (44 / 172B) are arranged opposite each other in the thickness direction (Z). A semiconductor device (10).

[0414] [Appendix 37] The first semiconductor region (131) is bonded to the first die pad (81) by a first bonding material (121), The second semiconductor region (132) is bonded to the second die pad (82) by a second bonding material (122). 37. The semiconductor device according to claim 36.

[0415] [Appendix 38] The insulating region (140) is a frame-shaped first insulating region (141) surrounding the first semiconductor region (131) when viewed from the thickness direction (Z); a frame-shaped second insulating region (142) surrounding the second semiconductor region (132) when viewed from the thickness direction (Z); Including, The first semiconductor substrate (151) includes a peripheral region surrounding the first insulating region (141) and the second insulating region (142), the first bonding material (121) is not in contact with the outer peripheral region (133) of the first semiconductor substrate (151) when viewed from the thickness direction (Z), but is in contact with the first semiconductor region (131); The second bonding material (122) is not in contact with the outer peripheral region (133) of the first semiconductor substrate (151) when viewed from the thickness direction (Z), but is in contact with the second semiconductor region (132). 38. The semiconductor device according to claim 37.

[0416] [Appendix 39] the first bonding material (121) is in partial contact with the first semiconductor region (131) and spaced apart from the first insulating region (141) when viewed from the thickness direction (Z), The second bonding material (122) is in partial contact with the second semiconductor region (132) at a distance from the second insulating region (142) when viewed from the thickness direction (Z). 39. The semiconductor device according to claim 38.

[0417] [Appendix 40] a first chip (50) disposed on the first die pad (81) and electrically connected to the first insulating element (41 / 171A) of the insulating chip (70); a second chip (60) disposed on the second die pad (91) and electrically connected to the fourth insulating element (44 / 172B) of the insulating chip (70); Contains 40. The semiconductor device according to any one of claims 36 to 39.

[0418] [Appendix 41] The first chip (50) includes a first chip semiconductor substrate (51), The second chip (60) includes a second chip semiconductor substrate (61), The thickness (TS) of the first semiconductor substrate (151) of the insulating chip (70) is thinner than the thickness (TA) of the semiconductor substrate (51) for the first chip and the thickness (TB) of the semiconductor substrate (61) for the second chip. 41. The semiconductor device according to claim 40.

[0419] [Appendix 42] A region-to-region distance (DR) between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X) is smaller than a pad-to-pad distance (PR) between the first die pad (81) and the second die pad (91) in the first direction (X). 42. The semiconductor device according to any one of claims 36 to 41.

[0420] [Appendix 43] The inter-region distance (DR) between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X) is greater than the distance (DA / EA) between the first insulating element (41 / 171A) and the second insulating element (42 / 171B) in the thickness direction (Z). 43. The semiconductor device according to any one of claims 36 to 42.

[0421] [Appendix 44] A region-to-region distance (DR) between the first semiconductor region (131) and the second semiconductor region (132) in the first direction (X) is equal to or greater than a pad-to-pad distance (PR) between the first die pad (81) and the second die pad (91) in the first direction (X). 42. The semiconductor device according to any one of claims 36 to 41.

[0422] [Appendix 45] providing a semiconductor substrate (800) having a first substrate surface (801) and a second substrate surface (802) opposite the first substrate surface (801); forming a first semiconductor region (131), a second semiconductor region (132) spaced apart from the first semiconductor region (131) in a first direction (X) on the first substrate surface (801), and an insulating layer (811) that separates the first semiconductor region (131) from the second semiconductor region (132); forming an element insulating layer (72) on the first substrate surface (801) of the semiconductor substrate (800); forming a first insulating element (41 / 171A) embedded in the element insulating layer (72) and having at least a portion overlapping the first semiconductor region (131) when viewed in a thickness direction (Z) of the element insulating layer (72); forming a fourth insulating element (44 / 172B) embedded in the element insulating layer (72) and having at least a portion overlapping the second semiconductor region (131) when viewed from the thickness direction (Z); forming a second insulating element (42 / 171B) embedded in the element insulating layer (72) and facing the first insulating element (41 / 171A) in the thickness direction (Z); forming a third insulating element (43 / 172A) embedded in the element insulating layer (72) and facing the fourth insulating element (44 / 172B) in the thickness direction (Z); grinding the second substrate surface (802) of the semiconductor substrate (800) to expose the insulating layer (811) from the second substrate surface (802) after grinding, thereby forming an insulating region (140) that insulates the first semiconductor region (131) and the second semiconductor region (132); Contains A method for manufacturing insulating chips.

[0423] [Appendix 46] Forming the insulating region (140) comprises: forming a frame-shaped first insulating region (141) surrounding the first semiconductor region (131) when viewed from the thickness direction (Z); forming a frame-shaped second insulating region (142) surrounding the second semiconductor region (132) when viewed from the thickness direction (Z); Contains 46. ​​A method for manufacturing an insulating tip according to claim 45.

[0424] [Appendix 47] The semiconductor substrate (800) is made of a material containing Si, Forming the insulating layer (811) forming a trench (810) between the first semiconductor region (131) and the second semiconductor region (132); forming the insulating layer (811) by thermally oxidizing the semiconductor substrate (800); Contains 47. A method for producing an insulating chip according to claim 45 or 46.

[0425] [Appendix 48] a fifth insulating element (205) and an eighth insulating element (208) arranged apart from each other in the first direction (X); a sixth insulating element (206) disposed opposite the fifth insulating element (205) in the thickness direction (Z); a seventh insulating element (207) disposed opposite the eighth insulating element (208) in the thickness direction (Z); Including, the fifth insulating element (205) and the eighth insulating element (208) are arranged apart from both the first insulating element (201) and the fourth insulating element (204) when viewed from the thickness direction (Z), the sixth insulating element (206) and the seventh insulating element (207) are arranged apart from both the second insulating element (202) and the third insulating element (203) when viewed from the thickness direction (Z), The semiconductor substrate (71) a third semiconductor region (243) disposed apart from the first semiconductor region (241) and the second semiconductor region (242) when viewed from the thickness direction (Z); a fourth semiconductor region (244) disposed apart from the first semiconductor region (241), the second semiconductor region (242), and the third semiconductor region (243) when viewed from the thickness direction (Z); Including, the insulating region (250) is configured to insulate the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), and the fourth semiconductor region (244) from one another; When viewed from the thickness direction (Z), both the fifth insulating element (205) and the sixth insulating element (206) are spaced apart from the first semiconductor region (241), the second semiconductor region (242), and the fourth semiconductor region (244), and are arranged so that at least a portion of each overlaps with the third semiconductor region (243); When viewed from the thickness direction (Z), both the seventh insulating element (207) and the eighth insulating element (208) are spaced apart from the first semiconductor region (241), the second semiconductor region (242), and the third semiconductor region (243), and are arranged so that at least a portion of each overlaps with the fourth semiconductor region (244). An insulating chip according to any one of appendices 1 to 4.

[0426] [Appendix 49] The first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), and the fourth semiconductor region (244) are arranged side by side in the first direction (X). 49. The insulated tip of claim 48.

[0427] [Appendix 50] A direction perpendicular to the first direction (X) when viewed from the thickness direction (Z) is defined as a second direction (Y), the third semiconductor region (243) and the fourth semiconductor region (244) are arranged to be shifted in the second direction (Y) with respect to the first semiconductor region (241) and the second semiconductor region (242), and are arranged side by side in the first direction (X); The second semiconductor region (242) and the third semiconductor region (243) are arranged side by side in the second direction (Y). 49. The insulated tip of claim 48.

[0428] [Appendix 51] The first semiconductor region (241) and the fourth semiconductor region (244) are arranged side by side in the second direction (Y). 51. The insulated tip of claim 50.

[0429] [Appendix 52] The insulating region (250) is a frame-shaped first insulating region (251) surrounding the first semiconductor region (241) when viewed from the thickness direction (Z); a frame-shaped second insulating region (252) surrounding the second semiconductor region (242) when viewed from the thickness direction (Z); a frame-shaped third insulating region (253) surrounding the third semiconductor region (243) when viewed from the thickness direction (Z); a frame-shaped fourth insulating region (254) surrounding the fourth semiconductor region (244) when viewed from the thickness direction (Z); Contains 52. An insulating chip according to any one of appendices 48 to 51.

[0430] [Appendix 53] The insulating region (250) is a first intermediate insulating region (261) provided between the first semiconductor region (241) and the second semiconductor region (242); a second intermediate insulating region (262) provided between the second semiconductor region (242) and the third semiconductor region (243); a third intermediate insulating region (263) provided between the third semiconductor region (243) and the fourth semiconductor region (244); Including, The first intermediate insulating region (261) constitutes a part of the first insulating region (251) and the second insulating region (252), the second intermediate insulating region (262) constitutes a part of the second insulating region (252) and the third insulating region (253); The third intermediate insulating region (263) constitutes a part of the third insulating region (253) and the fourth insulating region (254). 53. The insulated tip of claim 52.

[0431] [Appendix 54] a first pad (73) electrically connected to the first insulating element (201); a second pad (74) electrically connected to the eighth insulating element (208); a first connection wiring (221, 231) that electrically connects the first pad (73) and the first insulating element (201); a second connection wiring (222, 232) that electrically connects the second insulating element (202) and the third insulating element (203); a third connection wiring (223, 233) that electrically connects the fourth insulating element (204) and the fifth insulating element (205); a fourth connection wiring (224, 234) that electrically connects the sixth insulating element (206) and the seventh insulating element (207); a fifth connection wiring (225, 235) that electrically connects the eighth insulating element (208) and the second pad (74); Contains An insulating chip according to any one of appendices 48 to 53.

[0432] [Appendix 55] the first insulating element (201) is disposed closer to the semiconductor substrate (71) in the thickness direction (Z) than the second insulating element (202); the fourth insulating element (204) is disposed closer to the semiconductor substrate (71) in the thickness direction (Z) than the third insulating element (203); the fifth insulating element (205) is disposed closer to the semiconductor substrate (71) in the thickness direction (Z) than the sixth insulating element (206); the eighth insulating element (208) is disposed closer to the semiconductor substrate (71) in the thickness direction (Z) than the seventh insulating element (207); The third connection wiring (223, 233) is disposed closer to the semiconductor substrate (71) than the second connection wiring (222, 232) and the fourth connection wiring (224, 234). 55. The insulated tip of claim 54.

[0433] [Appendix 56] The first insulating element (201), the second insulating element (202), the third insulating element (203), the fourth insulating element (204), the fifth insulating element (205), the sixth insulating element (206), the seventh insulating element (207), and the eighth insulating element (208) are coils. An insulating tip according to any one of appendices 48 to 55.

[0434] [Appendix 57] The first insulating element (301A), the second insulating element (301B), the third insulating element (302A), the fourth insulating element (302B), the fifth insulating element (303A), the sixth insulating element (303B), the seventh insulating element (304A), and the eighth insulating element (304B) are electrode plates. An insulating tip according to any one of appendices 48 to 55.

[0435] [Appendix 58] the first unit (150) includes a fifth insulating element (205) and an eighth insulating element (208) embedded in the first element insulating layer (152), spaced apart from each other in the first direction (X), and electrically insulated from each other; the fifth insulating element (205) and the eighth insulating element (208) are arranged apart from the first insulating element (201) and the fourth insulating element (204); the second unit (160) includes a sixth insulating element (206) and a seventh insulating element (207) embedded in the second element insulating layer (162), spaced apart from each other in the first direction (X), and electrically insulated from each other; the sixth insulating element (206) and the seventh insulating element (207) are arranged apart from the second insulating element (202) and the third insulating element (203); The fifth insulating element (205) and the sixth insulating element (206) are arranged opposite to each other in the thickness direction (Z), and the seventh insulating element (207) and the eighth insulating element (208) are arranged opposite to each other in the thickness direction (Z). 16. An insulating chip according to any one of appendices 12 to 15.

[0436] [Appendix 59] The first semiconductor substrate (151) a third semiconductor region (243) disposed apart from the first semiconductor region (241) and the second semiconductor region (242) when viewed from the thickness direction (Z); a fourth semiconductor region (244) disposed apart from the first semiconductor region (241), the second semiconductor region (242), and the third semiconductor region (243) when viewed from the thickness direction (Z); Including, the insulating region (250) is configured to insulate the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), and the fourth semiconductor region (244) from one another; When viewed from the thickness direction (Z), the fifth insulating element (205) is spaced apart from the first semiconductor region (241), the second semiconductor region (242), and the fourth semiconductor region (244), and is arranged so that at least a portion of the fifth insulating element overlaps with the third semiconductor region (243); When viewed from the thickness direction (Z), the eighth insulating element (208) is disposed so as to be spaced apart from the first semiconductor region (241), the second semiconductor region (242), and the third semiconductor region (243) and so as to overlap at least a portion of the eighth insulating element (208) with the fourth semiconductor region (244). 59. The insulated tip of claim 58.

[0437] [Appendix 60] The insulating region (250) is a frame-shaped first insulating region (251) surrounding the first semiconductor region (241) when viewed from the thickness direction (Z); a frame-shaped second insulating region (252) surrounding the second semiconductor region (242) when viewed from the thickness direction (Z); a frame-shaped third insulating region (253) surrounding the third semiconductor region (243) when viewed from the thickness direction (Z); a frame-shaped fourth insulating region (254) surrounding the fourth semiconductor region (244) when viewed from the thickness direction (Z); Contains 59. The insulating tip of claim 59.

[0438] [Appendix 61] The insulating region (250) is a first intermediate insulating region (261) provided between the first semiconductor region (241) and the second semiconductor region (242); a second intermediate insulating region (262) provided between the second semiconductor region (242) and the third semiconductor region (243); a third intermediate insulating region (263) provided between the third semiconductor region (243) and the fourth semiconductor region (244); Including, The first intermediate insulating region (263) constitutes a part of the first insulating region (251) and the second insulating region (252), the second intermediate insulating region (262) constitutes a part of the second insulating region (252) and the third insulating region (253); The third intermediate insulating region (263) constitutes a part of the third insulating region (253) and the fourth insulating region (254). 61. The insulated tip of claim 60.

[0439] [Appendix 62] The first unit (150) comprises: a first pad (73) electrically connected to the first insulating element (201) and exposed from the first element insulating layer (152) in the thickness direction (Z); a second pad (74) electrically connected to the eighth insulating element (208) and exposed from the first element insulating layer (152) in the thickness direction (Z); Contains 62. An insulating chip according to any one of appendices 58 to 61.

[0440] [Appendix 63] The second unit (160) is smaller than the first unit (150) in a plan view seen from the thickness direction (Z), Both the first pad (73) and the second pad (74) are provided at positions different from the second unit (160) in the plan view. 63. The insulated tip of claim 62.

[0441] [Appendix 64] The first insulating element (201), the fourth insulating element (204), the fifth insulating element (205), and the eighth insulating element (208) are arranged closer to the first semiconductor substrate (151) than the center of the first element insulating layer (152) in the thickness direction (Z). 64. An insulating tip according to any one of appendices 58 to 63.

[0442] [Appendix 65] The second insulating element (202), the third insulating element (203), the sixth insulating element (206), and the seventh insulating element (207) are arranged on the opposite side of the first unit (150) with respect to the center of the second element insulating layer (162) in the thickness direction (Z). 65. An insulating tip according to any one of appendices 58 to 64.

[0443] [Appendix 66] The first unit (150) comprises: a first connection wiring (221, 231) that electrically connects the first pad (73) and the first insulating element (201); a third connection wiring (223, 233) that electrically connects the fourth insulating element (204) and the fifth insulating element (205); a fifth connection wiring (225, 235) that electrically connects the eighth insulating element (208) and the second pad (74); Including, The second unit (160) comprises: a second connection wiring (222, 232) that electrically connects the second insulating element (202) and the third insulating element (203); a fourth connection wiring (224, 234) that electrically connects the sixth insulating element (206) and the seventh insulating element (207); Contains 64. The insulated tip of claim 62 or 63.

[0444] [Appendix 67] a ninth insulating element (209) and a twelfth insulating element (212) spaced apart from each other in the first direction (X); a tenth insulating element (210) disposed opposite the ninth insulating element (209) in the thickness direction (Z); an eleventh insulating element (211) disposed opposite the twelfth insulating element (212) in the thickness direction (Z); Including, the ninth insulating element (209) and the twelfth insulating element (212) are arranged apart from each of the first insulating element (201), the fourth insulating element (204), the fifth insulating element (205), and the eighth insulating element (208) when viewed from the thickness direction (Z); the tenth insulating element (210) and the eleventh insulating element (211) are arranged apart from each of the second insulating element (202), the third insulating element (203), the sixth insulating element (206), and the seventh insulating element (207) when viewed from the thickness direction (Z); The semiconductor substrate (71) a fifth semiconductor region (245) arranged apart from the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), and the fourth semiconductor region (244) when viewed from the thickness direction (Z); a sixth semiconductor region (246) arranged apart from the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), the fourth semiconductor region (244), and the fifth semiconductor region (245) when viewed from the thickness direction (Z); Including, the insulating region (250) is configured to insulate the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), the fourth semiconductor region (244), the fifth semiconductor region (245), and the sixth semiconductor region (246) from one another; When viewed from the thickness direction (Z), both the ninth insulating element (209) and the tenth insulating element (210) are spaced apart from the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), the fourth semiconductor region (244), and the sixth semiconductor region (246), and are arranged so that at least a portion of each overlaps with the fifth semiconductor region (245); When viewed from the thickness direction (Z), both the eleventh insulating element (211) and the twelfth insulating element (212) are spaced apart from the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), the fourth semiconductor region (244), and the fifth semiconductor region (245), and are arranged so that at least a portion of each overlaps with the sixth semiconductor region (246). 49. The insulated tip of claim 48.

[0445] [Appendix 68] A direction perpendicular to the first direction (X) when viewed from the thickness direction (Z) is defined as a second direction (Y), the first semiconductor region (241), the second semiconductor region (242), the fifth semiconductor region (245), and the sixth semiconductor region (246) are arranged side by side in the first direction (X); the third semiconductor region (243) and the fourth semiconductor region (244) are arranged to be shifted in the second direction (Y) with respect to the first semiconductor region (241), the second semiconductor region (242), the fifth semiconductor region (245), and the sixth semiconductor region (246), and are arranged side by side in the first direction (X); the second semiconductor region (242) and the third semiconductor region (243) are arranged side by side in the second direction (Y), The fourth semiconductor region (244) and the fifth semiconductor region (245) are arranged side by side in the second direction (Y). 68. The insulated tip of claim 67.

[0446] [Appendix 69] The insulating region (250) is a frame-shaped first insulating region (251) surrounding the first semiconductor region (241) when viewed from the thickness direction (Z); a frame-shaped second insulating region (252) surrounding the second semiconductor region (242) when viewed from the thickness direction (Z); a frame-shaped third insulating region (253) surrounding the third semiconductor region (243) when viewed from the thickness direction (Z); a frame-shaped fourth insulating region (254) surrounding the fourth semiconductor region (244) when viewed from the thickness direction (Z); a frame-shaped fifth insulating region (255) surrounding the fifth semiconductor region (245) when viewed from the thickness direction (Z); a frame-shaped sixth insulating region (256) surrounding the sixth semiconductor region (246) when viewed from the thickness direction (Z); Contains 69. The insulated tip of claim 68.

[0447] [Appendix 70] The insulating region (250) is a first intermediate insulating region (261) provided between the first semiconductor region (241) and the second semiconductor region (242); a second intermediate insulating region (262) provided between the second semiconductor region (242) and the third semiconductor region (243); a third intermediate insulating region (263) provided between the third semiconductor region (243) and the fourth semiconductor region (244); a fourth intermediate insulating region (264) provided between the fourth semiconductor region (244) and the fifth semiconductor region (245); a fifth intermediate insulating region (265) provided between the second semiconductor region (242) and the fifth semiconductor region (245); a sixth intermediate insulating region (266) provided between the fifth semiconductor region (245) and the sixth semiconductor region (246); Including, The first intermediate insulating region (261) constitutes a part of the first insulating region (251) and the second insulating region (252), the second intermediate insulating region (262) constitutes a part of the second insulating region (252) and the third insulating region (253); the third intermediate insulating region (263) constitutes a part of the third insulating region (253) and the fourth insulating region (254); the fourth intermediate insulating region (264) constitutes a part of the fourth insulating region (254) and the fifth insulating region (255); the fifth intermediate insulating region (265) constitutes a part of the second insulating region (252) and the fifth insulating region (255); The sixth intermediate insulating region (266) constitutes a part of the fifth insulating region (255) and the sixth insulating region (266). 70. The insulated tip of claim 69.

[0448] [Appendix 71] The insulating chip (70) includes a fifth insulating element (205) and an eighth insulating element (208) that are spaced apart from each other in the first direction (X), a sixth insulating element (206) that is arranged opposite the fifth insulating element (205) in the thickness direction (Z), and a seventh insulating element (207) that is arranged opposite the eighth insulating element (208) in the thickness direction (Z), the fifth insulating element (205) and the eighth insulating element (208) are arranged apart from both the first insulating element (201) and the fourth insulating element (204) when viewed from the thickness direction (Z), the sixth insulating element (206) and the seventh insulating element (207) are arranged apart from both the second insulating element (202) and the third insulating element (203) when viewed from the thickness direction (Z), The semiconductor substrate (71) a third semiconductor region (243) disposed apart from the first semiconductor region (241) and the second semiconductor region (242) when viewed from the thickness direction (Z); a fourth semiconductor region (244) disposed apart from the first semiconductor region (241), the second semiconductor region (242), and the third semiconductor region (243) when viewed from the thickness direction (Z); Including, the insulating region (250) is configured to insulate the first semiconductor region (241), the second semiconductor region (242), the third semiconductor region (243), and the fourth semiconductor region (244) from one another; When viewed from the thickness direction (Z), both the fifth insulating element (205) and the sixth insulating element (206) are spaced apart from the first semiconductor region (241), the second semiconductor region (242), and the fourth semiconductor region (244), and are arranged so that at least a portion of each overlaps with the third semiconductor region (243); When viewed from the thickness direction (Z), both the seventh insulating element (207) and the eighth insulating element (208) are spaced apart from the first semiconductor region (241), the second semiconductor region (242), and the third semiconductor region (243), and are arranged so that at least a portion of each overlaps with the fourth semiconductor region (244). 27. The semiconductor device according to claim 26.

[0449] [Appendix 72] The first semiconductor region (241) is bonded to the first die pad (81) by a conductive first bonding material (121), The fourth semiconductor region (244) is bonded to the second die pad (91) by a conductive second bonding material (122). 72. The semiconductor device of claim 71.

[0450] [Appendix 73] The insulating region (250) is a frame-shaped first insulating region (251) surrounding the first semiconductor region (241) when viewed from the thickness direction (Z); a frame-shaped second insulating region (252) surrounding the second semiconductor region (242) when viewed from the thickness direction (Z); a frame-shaped third insulating region (253) surrounding the third semiconductor region (243) when viewed from the thickness direction (Z); a frame-shaped fourth insulating region (254) surrounding the fourth semiconductor region (244) when viewed from the thickness direction (Z); Including, the semiconductor substrate (71) includes an outer periphery region (249) surrounding the first insulating region (251), the second insulating region (252), the third insulating region (253), and the fourth insulating region (254); the first bonding material (121) is not in contact with the outer peripheral region (249) of the semiconductor substrate (71) but is in contact with the first semiconductor region (241); The second bonding material (122) is not in contact with the outer peripheral region (249) of the semiconductor substrate (71) but is in contact with the fourth semiconductor region (244). 73. The semiconductor device of claim 72.

[0451] [Appendix 74] Both the second semiconductor region (242) and the third semiconductor region (243) are disposed between the first die pad (81) and the second die pad (91). 74. The semiconductor device according to any one of appendices 71 to 73.

[0452] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0453] 10...Semiconductor device 20...1st circuit 21...Transmitting circuit 30…Second circuit 31...Receiver circuit 40...transformer 41...First coil 42...Second coil 43...Third coil 44...Fourth coil 45A, 45B...Inner connection wiring 45AA, 45BA...Coil connection part 45AB, 45BB...Connection wiring 45AC, 45BC...Pad connection part 46A, 46B...External connection wiring 46AA, 46BA...Connection wiring 46AB, 46BB...Pad connection part 47...Connection wiring 47A…1st connection wiring 47AA...First coil connection 47AB...Coil connection wiring 47AC...Second coil connection 47B...Second connection wiring 50...First chip 51...first semiconductor substrate 52...First insulating layer 53...Electrode pad 60...Second chip 61...second semiconductor substrate 62...Second insulating layer 63...Electrode pad 70...insulating tip 70S: Chip top surface 70R...Chip bottom 70A to 70D: 1st to 4th chip sides 71...Semiconductor substrate 71A...Top surface of board 71B…Bottom surface of board 71C~71F...1st~4th board side 72...Element insulating layer 73, 73A, 73B...First pad 74, 74A, 74B...Second pad 75...insulating film 75A...First insulating film 75B...Second insulating film 75U: Top insulating film 75L: Bottom insulating film 76…Protective layer 80...First lead frame 81...First die pad 82...1st lead 90...2nd lead frame 91...Second die pad 92...2nd lead 100…Sealing resin 101~104…Sealing side 111,112…Joining material 121...First bonding material 122…Second bonding material 131...first semiconductor region 132...Second semiconductor region 133...Outer area 134A, 134B...Intermediate semiconductor region 140...Isolation area 141...First insulating area 142...Second insulating area 143...Intermediate insulation area 143A~143C...Insulation section 150...1st unit 151...first semiconductor substrate 152...first element insulating layer 153...1st protective layer 160...Second unit 161...second semiconductor substrate 162...Second element insulating layer 163…Second protective layer 170...Capacitor 171...First capacitor 171A…1st electrode plate 171B…Second electrode plate 172...Second capacitor 172A…1st electrode plate 172B…Second electrode plate 181...First connection wiring 181A...Electrode connection part 181B...Pad connection part 182...Second connection wiring 182A...Electrode connection part 182B...Pad connection part 183...Third connection wiring 201...1st coil 202...Second coil 203...Third coil 204...4th coil 205...5th coil 206...6th coil 207...7th coil 208...8th coil 209...9th coil 210...10th coil 211...11th coil 212...12th coil 221~225...1st~5th inner connection wiring 231~235...1st~5th outer connection wiring 241 to 246: 1st to 6th semiconductor regions 249…Outer area 250...Isolation area 251~254...1st to 4th insulating regions 261~263...1st to 3rd intermediate insulating areas 271~277...1st~7th inner connection wiring 281~287...1st~7th inner connection wiring 300...Capacitor 301 to 304: 1st to 4th capacitors 301A~304A…1st electrode plate 301B~304B…Second electrode plate 311~315...1st to 5th connection wiring 800...Semiconductor substrate 801...Top surface of board 802…Bottom surface of board 810...Trench 811...insulating layer 910...first semiconductor wafer 920...Second semiconductor wafer 930...Dicing tape 940...Dicing blade W1~W4...Wires DA: distance between the first and second coils DB: Distance between the third and fourth coils DC: Distance between the 1st and 4th coils DD: Distance between the second and third coils DR…Distance between regions EA: Distance between the first and second electrode plates of the first capacitor EB: Distance between the first and second electrode plates of the second capacitor EC: Distance between the first electrode plate of the first capacitor and the second electrode plate of the second capacitor ED: Distance between the second electrode plate of the first capacitor and the first electrode plate of the second capacitor HR: Insulation area thickness HR1: Thickness of the first insulating region HR2: Thickness dimension of the second insulating region HR3: Thickness of intermediate insulating area PR: Pad distance TA: Thickness of the first semiconductor substrate of the first chip TB: Thickness of the second semiconductor substrate of the second chip TR: Thickness of the semiconductor substrate of the insulating chip TS: Thickness of the first semiconductor substrate of the insulating chip WR: Width of insulating area WR1: Width of the first insulating area WR2: Width of the second insulating area WR3: Width of intermediate insulation area WC1 to WC3: Width dimensions of the first to third intermediate insulating areas D1~D4: 1st to 4th distance DC1~DC3…1st~3rd distance DD1~DD3…1st~3rd distance

Claims

1. a semiconductor substrate; an element insulating layer provided on the semiconductor substrate; a first insulating element and a fourth insulating element provided in the element insulating layer and spaced apart from each other in a first direction intersecting a thickness direction of the element insulating layer, a second insulating element arranged opposite to the first insulating element in the thickness direction, and a third insulating element arranged opposite to the fourth insulating element in the thickness direction; Including, The semiconductor substrate is a first semiconductor region; a second semiconductor region disposed apart from the first semiconductor region in the first direction; an insulating region that insulates the first semiconductor region from the second semiconductor region; Including, When viewed from the thickness direction, both the first insulating element and the second insulating element are spaced apart from the second semiconductor region and are arranged so that at least a portion of each element overlaps with the first semiconductor region; When viewed from the thickness direction, both the third insulating element and the fourth insulating element are spaced apart from the first semiconductor region and are disposed so as to at least partially overlap the second semiconductor region. Insulated tip.

2. both the first semiconductor region and the second semiconductor region are made of a material containing Si, The insulating region is made of SiO ２ It is made up of The insulating tip of claim 1 .

3. The width dimension of the insulating region is smaller than the dimension of the insulating region in the thickness direction. The insulating tip of claim 1 .

4. The width dimension of the insulating region is greater than the dimension of the insulating region in the thickness direction. The insulating tip of claim 1 .

5. The insulating region is a frame-shaped first insulating region surrounding the first semiconductor region when viewed from the thickness direction; a frame-shaped second insulating region surrounding the second semiconductor region when viewed from the thickness direction; Contains The insulating tip of claim 1 .

6. the insulating region includes an intermediate insulating region provided between the first semiconductor region and the second semiconductor region in the first direction, The intermediate insulating region constitutes a part of the first insulating region and a part of the second insulating region. The insulating tip of claim 5 .

7. a connection wiring provided in the element insulating layer, the connection wiring electrically connecting the second insulating element and the third insulating element; The insulating tip of claim 1 .

8. a first pad electrically connected to the first insulating element; a second pad electrically connected to the fourth insulating element; Including, the first pad is disposed on an opposite side of the first insulating element from the fourth insulating element in the first direction; The second pad is disposed on the opposite side of the fourth insulating element from the first insulating element in the first direction. The insulating tip of claim 1 .

9. the first insulating element is disposed closer to the semiconductor substrate in the thickness direction than the second insulating element; The fourth insulating element is disposed closer to the semiconductor substrate in the thickness direction than the third insulating element. The insulating tip of claim 8.

10. Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is a coil. The insulating chip according to any one of claims 1 to 9.

11. Each of the first insulating element, the second insulating element, the third insulating element, and the fourth insulating element is an electrode plate. The insulating chip according to any one of claims 1 to 9.

12. a first die pad; a second die pad disposed apart from the first die pad in a first direction; an insulating chip disposed so as to straddle the first die pad and the second die pad in the first direction; Equipped with The insulating tip is a semiconductor substrate; an element insulating layer provided on the semiconductor substrate; a first insulating element and a fourth insulating element embedded in the element insulating layer and spaced apart from each other in the first direction, a second insulating element arranged opposite the first insulating element in a thickness direction of the element insulating layer, and a third insulating element arranged opposite the fourth insulating element in the thickness direction; Including, The semiconductor substrate is a first semiconductor region; a second semiconductor region disposed apart from the first semiconductor region in the first direction; an insulating region that insulates the first semiconductor region from the second semiconductor region; Including, When viewed from the thickness direction, both the first insulating element and the second insulating element are spaced apart from the second semiconductor region and are arranged so that at least a portion of each element overlaps with the first semiconductor region; When viewed from the thickness direction, both the third insulating element and the fourth insulating element are spaced apart from the first semiconductor region and are disposed so as to at least partially overlap the second semiconductor region. Semiconductor device.

13. the first semiconductor region is bonded to the first die pad by a conductive first bonding material; The second semiconductor region is bonded to the second die pad by a second conductive bonding material. The semiconductor device according to claim 12.

14. The insulating region is a frame-shaped first insulating region surrounding the first semiconductor region when viewed from the thickness direction; a frame-shaped second insulating region surrounding the second semiconductor region when viewed from the thickness direction; Including, the semiconductor substrate includes a peripheral region surrounding the first insulating region and the second insulating region; the first bonding material is not in contact with the outer periphery region of the semiconductor substrate but is in contact with the first semiconductor region, The second bonding material does not contact the peripheral region of the semiconductor substrate but contacts the second semiconductor region. The semiconductor device according to claim 13.

15. the first bonding material includes a portion that is in contact with the first semiconductor region and spaced apart from the first insulating region when viewed in the thickness direction, The second bonding material includes a portion that is in contact with the second semiconductor region and spaced apart from the second insulating region when viewed in the thickness direction. The semiconductor device according to claim 14.

16. a first chip disposed on the first die pad and electrically connected to the first insulating element of the insulating chip; a second chip disposed on the second die pad and electrically connected to the fourth insulating element of the insulating chip; Contains The semiconductor device according to claim 12.

17. the first chip includes a first chip semiconductor substrate; the second chip includes a second chip semiconductor substrate; The thickness of the semiconductor substrate of the insulating chip is thinner than the thickness of the semiconductor substrate for the first chip and the thickness of the semiconductor substrate for the second chip. The semiconductor device according to claim 16.

18. an inter-region distance between the first semiconductor region and the second semiconductor region in the first direction is smaller than an inter-pad distance between the first die pad and the second die pad in the first direction; The semiconductor device according to any one of claims 12 to 17.

19. The inter-region distance between the first semiconductor region and the second semiconductor region in the first direction is greater than the distance between the first insulating element and the second insulating element in the thickness direction. The semiconductor device according to claim 12.

20. an inter-region distance between the first semiconductor region and the second semiconductor region in the first direction is equal to or greater than an inter-pad distance between the first die pad and the second die pad in the first direction; The semiconductor device according to any one of claims 12 to 17.

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