Multilayer ceramic capacitor and circuit board

Abstract

To provide a multilayer ceramic capacitor that enables narrow element spacing when mounted on a circuit board, and a circuit board on which mounted elements are mounted with narrow spacing.SOLUTION: A multilayer ceramic capacitor 100 includes: a rectangular parallelepiped element assembly 10 including a laminate 20 in which ceramic layers 21 and internal electrodes 22 mainly composed of metal are alternately stacked, a protective section 30 covering the surface of the laminate 20, and a plurality of via conductors 23 each of which is disposed so as to penetrate the ceramic layers in a stacking direction of the laminate 20, has one end that at least reaches a surface of the protective section 30 and is electrically connected to the internal electrodes 22; and a plurality of terminal electrodes 40 disposed on a mounting surface 11 that, among the surfaces forming the front surface of the element assembly, faces the circuit board when mounted on the circuit board, the plurality of terminal electrodes being electrically connected to the via conductors 23. All of the terminal electrodes 40 are arranged with spacing of 10 μm or more from the outer edge of the mounting surface 11.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a circuit board. [Background technology]

[0002] In recent years, as electronic devices such as smartphones have become more sophisticated, the semiconductors they use have also become more sophisticated. The higher the performance of the semiconductor, the more susceptible it is to noise, so multilayer ceramic capacitors (MLCCs) are used as decoupling capacitors to remove this noise.

[0003] In multilayer ceramic capacitors for use as decoupling capacitors, in order to reduce equivalent series inductance (ESL), it is known that multiple conductors are provided for each polarity to electrically connect the external electrodes arranged on the main surfaces with multiple internal electrodes, and that the conductors are arranged so that the magnetic fields generated by the flowing currents cancel each other out (Patent Documents 1 and 2).

[0004] It is also known that in a multilayer ceramic capacitor, when mounted on a circuit board, external electrodes are arranged only on the mounting surface that comes into contact with the circuit board, thereby suppressing the spreading area of ​​the solder connecting the multilayer ceramic capacitor to the circuit board and reducing acoustic noise (Patent Document 3). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 7-201651 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-135333 [Patent Document 3] U.S. Patent No. 10,617,008 Summary of the Invention [Problem to be solved by the invention]

[0006] It is said that the noise reduction effect of multilayer ceramic capacitors is greater the closer they are placed to semiconductors, so recently, low-profile multilayer ceramic capacitors (low-profile MLCCs) with a small element height are sometimes mounted on the backside of circuit boards on which semiconductors are mounted.The element height of these low-profile MLCCs must be smaller than the gap between the circuit board on which the semiconductor is mounted and the motherboard on which it is mounted, and there is a demand for them to be able to accommodate gaps of 100 μm or less.

[0007] The aforementioned multilayer ceramic capacitors for noise reduction are often used in multiples to enhance the noise reduction effect. When multiple low-profile MLCCs are mounted on the backside of a circuit board on which semiconductors are mounted, they must be placed through the gaps in the ball grid array (BGA) that connects the circuit board to the motherboard, which can result in extremely narrow spaces between the low-profile MLCCs.

[0008] In a conventional multilayer ceramic capacitor 100′, as shown in FIG. 4, the terminal electrodes 40 (40a, 40b) are arranged so as to contact the outer edge of the mounting surface 11. The lands of the circuit board on which the multilayer ceramic capacitor 100′ is mounted are formed larger than the terminal electrodes 40 (40a, 40b), and therefore are arranged to protrude beyond the element in a planar view, as shown in FIG. 11 of Patent Document 3. For this reason, even when multiple elements are mounted closely together, there is a limit to how narrow the mounting spacing can be. Furthermore, when mounting on a circuit board using solder paste, solder wets and rises on each surface perpendicular to the mounting surface of the multilayer ceramic capacitor, forming fillets, which also hinders narrowing the mounting spacing between elements.

[0009] The present invention has been made to solve the above problems, and has an object to provide a multilayer ceramic capacitor that allows for narrow element spacing when mounted on a circuit board, and a circuit board in which the mounted elements are mounted with narrow spacing. [Means for solving the problem]

[0010] The inventors have conducted various studies to solve the above-mentioned problems, and have found that the above-mentioned object can be achieved by arranging multiple external electrodes of a multilayer ceramic capacitor on the mounting surface having the largest area among the surfaces forming the surface, at a predetermined interval from the outer edge of the mounting surface, and have thus completed the present invention.

[0011] That is, a first aspect of the present invention for solving the above problem is a multilayer ceramic capacitor comprising: a laminate in which ceramic layers and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and an element body having a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, at least one end of which reaches the surface of the protective portion and is electrically connected to the internal electrodes; and a plurality of terminal electrodes arranged on a mounting surface, which is the surface that faces a circuit board when mounted on the circuit board, among the surfaces forming the surface of the element body, wherein all of the plurality of terminal electrodes are electrically connected to the via conductors and are arranged at a distance of 10 μm or more from the outer edge of the mounting surface.

[0012] A second aspect of the present invention for solving the above problem is a circuit board having the multilayer ceramic capacitor according to the first aspect mounted thereon, and having lands electrically connected to the plurality of terminal electrodes entirely covered by the multilayer ceramic capacitor in a plan view.

[0013] Furthermore, a third aspect of the present invention for solving the above problem is a circuit board on which a plurality of multilayer ceramic capacitors according to the first aspect are mounted, and the interval between adjacent multilayer ceramic capacitors is 50 μm or less. [Effects of the Invention]

[0014] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can reduce the element spacing when mounted on a circuit board, and a circuit board in which the mounted elements are mounted with a narrow spacing. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 2 is a cross-sectional view taken along line AA (LT cross-sectional view) in FIG. 1. [Figure 3] 2 is a cross-sectional view taken along line BB (cross-sectional view taken along line WT) in FIG. 1. [Figure 4] FIG. 1 is a cross-sectional view (LT cross-sectional view) showing the arrangement of terminal electrodes of a conventional multilayer ceramic capacitor. [Figure 5] FIG. 4 is a schematic view (perspective view) showing the structure of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 6] FIG. 10 is a schematic view (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 7] FIG. 10 is a schematic view (WT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a fourth embodiment of the present invention. [Figure 8] FIG. 10 is a schematic diagram (LT cross-sectional view) showing the structure of a circuit board according to a fifth embodiment of the present invention. [Figure 9] FIG. 10 is a schematic diagram (LT cross-sectional view) showing the structure of a circuit board according to a sixth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] The configuration and effects of the present invention will be described below, along with the technical concept, with reference to the drawings. However, the mechanism of action includes assumptions, and the correctness of such assumptions does not limit the present invention.

[0017] [Multilayer ceramic capacitors] First Embodiment An embodiment of a multilayer ceramic capacitor according to a first aspect of the present invention is shown in FIGS. 1 to 3 as a first embodiment. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and includes a pair of faces that are perpendicular to three mutually orthogonal axes, namely, the L axis, which is the length direction, the W axis, which is the width direction, and the T axis, which is the height direction. The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, and may have any shape that is recognized as a rectangular parallelepiped when observed as a whole. Therefore, a rectangular parallelepiped in the present disclosure also includes a capacitor with rounded edges and corners, a capacitor with curved edges, and a capacitor with small curved surfaces. The length (L), width (W), and height (T) dimensions of the ceramic capacitor 100 can each independently take any value.

[0018] The dimensions of the multilayer ceramic capacitor 100 are, for example, an L-direction dimension of 200 μm to 2000 μm, a W-direction dimension of 100 μm to 2000 μm, and a T-direction dimension of 30 μm to 220 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.3 to 1.0. The dimensions are preferably an L-direction dimension of 400 μm to 1200 μm, a W-direction dimension of 400 μm to 1200 μm, and a T-direction dimension of 40 μm to 150 μm, with a value W / L (the ratio of the W-direction dimension to the L-direction dimension) of 0.4 to 1.0. It is more preferable that the T-direction dimension be 100 μm or less, since this allows for a narrower gap between the circuit board and the motherboard on which it is mounted, even when the capacitor is mounted on the back side of the circuit board (the surface opposite to the surface on which the semiconductor is mounted).

[0019] As shown in the cross-sectional views of Fig. 2 (LT cross section) and Fig. 3 (WT cross section), the multilayer ceramic capacitor 100 according to the first embodiment includes a laminate 20 in which ceramic layers 21 and internal electrodes 22 mainly composed of metal are alternately stacked in the T direction, and an element body 10 having a protective part 30 covering the surface of the laminate 20. The internal electrodes 22 include internal electrodes 22a electrically connected to each other and having one polarity, and internal electrodes 22b electrically connected to each other and having a polarity different from that of the internal electrodes 22a.

[0020] A protective portion 30 is arranged on the surface of the element body 10, covering the surface of the laminate 20. The protective portion 30 includes a cover portion 31 arranged on a plane perpendicular to the T direction, and margin portions 32 arranged on a plane perpendicular to the W direction and a plane perpendicular to the L direction, respectively.

[0021] The element body 10 has a plurality of via conductors 23 that are arranged to penetrate the ceramic layers 21 in the stacking direction of the laminate 20, with at least one end reaching the surface of the protective part 30 (cover part 31) and electrically connected to the internal electrodes 22. The via conductors 23 include a via conductor 23a electrically connected to the internal electrode 22a and a via conductor 23b electrically connected to the internal electrode 22b. Note that although the multilayer ceramic capacitor 100 shown in FIGS. 1 to 3 includes two via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0022] The multilayer ceramic capacitor 100 according to the first embodiment includes a plurality of terminal electrodes 40 arranged on a mounting surface 11, which is one of the surfaces forming the surface of the element body 10 and faces the circuit board when the element body 10 is mounted on the circuit board. The terminal electrodes 40 arranged on the mounting surface 11 include a terminal electrode 40a electrically connected to a via conductor 23a and a terminal electrode 40b electrically connected to a via conductor 23b. While the multilayer ceramic capacitor 100 shown in FIGS. 1 to 3 includes two terminal electrodes 40, the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this. Furthermore, although the multilayer ceramic capacitor 100 has terminal electrodes 40 (40a, 40b) arranged only on the mounting surface 11, the multilayer ceramic capacitor according to the first aspect of the present invention may also have terminal electrodes 40 (40a, 40b) arranged on the surface facing the mounting surface 11.

[0023] The thickness of the element body 10, obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the T-direction dimension of the multilayer ceramic capacitor 100 described above, is, for example, 20 μm to 200 μm, and preferably 30 μm to 180 μm.

[0024] Hereinafter, each component constituting the multilayer ceramic capacitor 100 according to the first embodiment will be described in detail.

[0025] (ceramic layer) The ceramic layer 21 is made of ceramic. The ceramic composition is not particularly limited as long as it forms a dense ceramic layer 21 by co-firing with the internal electrodes 22 described later, and may be appropriately selected depending on the properties required for the multilayer ceramic capacitor. Examples of ceramic compositions include those containing barium titanate (BaTiO3) as the main component, those containing strontium titanate (SrTiO3) as the main component, and those containing BaTiO3 having a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr zExamples of such ceramics include those containing O3 as a main component. The ceramic may contain an additive element in addition to the main component. Examples of the additive element include at least one selected from Mo, Nb, Ta, W, Mg, Mn, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), and Co, Ni, Li, B, Na, K, and Si. The additive element may be contained as a simple element or in the form of a compound such as an oxide, nitride, or carbide. The additive element may exist in a solid solution state in the main component, or may form a different phase from the elements constituting the main component or other additive elements.

[0026] (Internal electrode) The internal electrodes 22 (22a, 22b) are primarily composed of a metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof can be used. Among these, nickel (Ni) is preferred as the primary element because of its high heat resistance, which allows the firing temperature to be increased when co-firing with the ceramic layer 21 to form a dense ceramic layer 21, and it is relatively inexpensive. Here, the term "primary element" as used herein refers to the element with the highest content expressed in atomic percentage (atomic %).

[0027] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having the same composition as the ceramic constituting the ceramic layer 21, or a glass component.

[0028] (Protection Department) The protective part 30 has a function of protecting the ceramic layers 21 and the internal electrodes 22. The material of the protective part 30 is not limited as long as it has high electrical insulation and low permeability to deterioration factors such as moisture. From the viewpoints of making shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 uniform and alleviating internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the protective part 30 be the same as the ceramic that forms the ceramic layers 21.

[0029] (Via conductor) Like the internal electrodes 22 (22a, 22b), the via conductors 23 (23a, 23b) are primarily composed of metal. Usable metals include those similar to those of the internal electrodes 22 (22a, 22b) described above. The composition of the via conductors may be different from that of the internal electrodes 22 (22a, 22b), but is preferably the same as that of the internal electrodes 22 (22a, 22b). By making the via conductors (23a, 23b) and the internal electrodes 22 (22a, 22b) the same composition, the magnitude of shrinkage caused by firing during manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation, and the resistivity of the conductive paths of the multilayer ceramic capacitor 100 is uniform, suppressing localized heat generation during use.

[0030] The diameter of the via conductors (23a, 23b) is not particularly limited, but in order to ensure the capacity of the multilayer ceramic capacitor 100 while reducing electrical resistance and suppressing heat generation during circuit operation, it is preferable to make it 5 μm or more and 100 μm or less, and more preferably 10 μm or more and 50 μm or less.

[0031] (terminal electrode) Each of the terminal electrodes 40 (40a, 40b) arranged on the mounting surface 11 is spaced 10 μm or more from the outer edge of the mounting surface 11. By arranging the terminal electrodes 40 (40a, 40b) at a sufficient distance from the outer edge of the mounting surface, the lands of the circuit board on which the multilayer ceramic capacitor 100 is mounted can be arranged so that they are entirely covered by the multilayer ceramic capacitor 100 in a planar view, in other words, so that they do not protrude from the multilayer ceramic capacitor 100 in a planar view. This allows for a narrower mounting interval between elements. Furthermore, when the multilayer ceramic capacitor 100 is mounted on a circuit board using solder paste, the generation of fillets due to solder wetting can be suppressed, allowing for a narrower mounting interval between elements. In particular, when the multilayer ceramic capacitor 100 is a low-profile MLCC with a T-direction dimension of 100 μm or less, this significantly suppresses solder wetting that exceeds the element height, which is advantageous in that it can prevent a circuit board equipped with the capacitor from being unable to be mounted on a motherboard and prevents short circuits during operation. In order to ensure that the above-mentioned effects are significant, the distance between the terminal electrodes 40 (40a, 40b) and the outer edge of the mounting surface 11 is preferably 12 μm or more, more preferably 15 μm or more, and even more preferably 18 μm or more. There is no particular upper limit to the distance between the terminal electrodes 40 (40a, 40b) and the outer edge of the mounting surface 11, but the distance is preferably 50 μm or less, more preferably 45 μm or less, and even more preferably 40 μm or less. By keeping the distance at or below the upper limit, the area of ​​each terminal electrode 40 (40a, 40b) can be made large enough to facilitate mounting on a circuit board, while the distance between the terminal electrodes 40a and 40b of opposite polarity can be increased, thereby improving electrical insulation.

[0032] The distance between the terminal electrodes 40 (40a, 40b) is preferably 70 μm or more, more preferably 100 μm or more, and even more preferably 120 μm or more. When the distance is equal to or greater than the lower limit, the electrical insulation between the terminal electrodes 40a and 40b of opposite polarities can be improved. On the other hand, the distance between the terminal electrodes 40 (40a, 40b) is preferably 400 μm or less, more preferably 300 μm or less, and even more preferably 200 μm or less. When the distance is equal to or less than the upper limit, the area of ​​each terminal electrode 40 (40a, 40b) can be made large enough to facilitate mounting on a circuit board. Furthermore, when the height of the multilayer ceramic capacitor 100, which is the dimension perpendicular to the mounting surface 11, is 100 μm or less, the mechanical strength is significantly improved when the distance is equal to or less than the upper limit. This is presumably because the amount of deformation of the element body 10 located between the terminal electrodes 40 (40a, 40b) is reduced when stress is applied in the height direction.

[0033] The distance between the terminal electrodes 40 (40a, 40b) and the outer edge of the mounting surface 11 is determined by the following procedure. First, the mounting surface 11 of the multilayer ceramic capacitor 100 is observed using an optical microscope or a scanning electron microscope (SEM), and an image is obtained in which the outer edge of the mounting surface 11 and one of the terminal electrodes 40 (40a, 40b) adjacent to it are in the same field of view. Note that multiple terminal electrodes 40 (40a, 40b) may be present in the image, as long as the procedures described below can be performed on the obtained image. Next, a line segment formed by the outer edge of the mounting surface 11 is determined in the obtained image. Here, if the outer edge of the mounting surface 11 is curved or meandering and does not form a line segment, a line segment obtained by linearly approximating the curve formed by the outer edge is taken as the line segment formed by the outer edge. Next, a line segment that is parallel to the determined line segment and touches the outer edge side end of the terminal electrode 40 (40a, 40b) of the element body is drawn in the image, and the distance between the drawn line segment and the line segment formed by the outer edge is measured. Next, the value obtained by dividing the measured distance between the two line segments by the magnification used for the observation is taken as the distance between the terminal electrode 40 (40a, 40b) and the outer edge of the mounting surface 11.

[0034] The distance between the terminal electrodes 40 (40a, 40b) is determined by the following procedure. First, the mounting surface 11 of the multilayer ceramic capacitor 100 is observed using an optical microscope or a scanning electron microscope (SEM) to obtain an image in which multiple terminal electrodes 40 (40a, 40b) are in the same field of view. Next, in the obtained image, the distance between a point located on the outline of one arbitrarily selected terminal electrode 40 (40a, 40b) and a point located on the outline of the other terminal electrode 40 (40a, 40b) closest to the selected terminal electrode 40 (40a, 40b) is measured, and the combination of points on the outlines that provides the shortest distance is determined. Next, the distance between the two points in the combination is divided by the magnification used for the observation, and the resulting value is used as the distance between the terminal electrodes 40 (40a, 40b).

[0035] The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive, and examples of the material include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys containing any of these as a main component, and conductive resins.

[0036] The terminal electrodes 40 (40a, 40b) may have an underlying conductor 41 in contact with the element body 10 and a plated conductor 42 formed on the surface of the underlying conductor 41. The terminal electrodes 40 (40a, 40b) having such a structure can improve adhesion to the element body 10 by the underlying conductor 41, and can improve solder wettability by the plated conductor 42 when mounted on a circuit board.

[0037] An example of the material for the underlying conductor 41 is Ni. The thickness of the underlying conductor 41 can be 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less. The underlying conductor 41 is preferably disposed at a distance of 15 μm or more from the outer edge of the mounting surface 11 so that the plated conductor 42 can be formed with a sufficient thickness while maintaining the distance between the terminal electrodes 40 (40a, 40b) and the outer edge of the mounting surface 11.

[0038] The distance between the base conductor 41 and the outer edge of the mounting surface 11 is determined by the following procedure. First, the multilayer ceramic capacitor 100 is cut along a plane perpendicular to the mounting surface 11, passing through the vicinity of the center of gravity of the surface parallel to the mounting surface 11 of the terminal electrode 40 (40a, 40b) closest to the outer edge of the mounting surface 11, to prepare an observation sample. This observation sample may be prepared by polishing the surface perpendicular to the mounting surface 11 to the vicinity of the center of gravity. Next, the observation sample is embedded in resin so that the cut surface is exposed, and the cut surface is mirror-polished. Next, the mirror-polished cut surface is observed with an optical microscope, and one of the two shortest sides of the four sides that form the outer edge of the cut surface is selected as a reference line, and an image is obtained in which the reference line and the terminal electrode 40 (40a, 40b) closest to it are in the same field of view. If the outer edge of the cut surface is curved or meandering and does not form a side (line segment), a line segment obtained by linearly approximating the curve formed by the outer edge is used as the side forming the outer edge. Next, in the portion of the terminal electrode 40 (40a, 40b) in the obtained image, the base conductor 41 is determined based on the difference in hue. Next, a line segment parallel to the reference line and tangent to the base conductor 41 is drawn in the image, and the distance between the drawn line segment and the reference line is measured. Next, the measured distance between the two line segments is divided by the magnification used for the observation, and the resulting value is used as the distance between the base conductor 41 and the outer edge of the mounting surface 11.

[0039] The plated conductor 42 may be formed of a single layer or multiple layers. When the plated conductor 42 is formed of multiple layers, the number of layers is preferably two to four. An example of the material and structure of the plated conductor 42 is one formed of Cu, Ni, and Sn in this order. The thickness of the plated conductor 42 can be 1 μm to 20 μm, and preferably 3 μm to 10 μm.

[0040] The area of ​​the terminal electrodes 40 (40a, 40b), i.e., the area of ​​the terminal electrodes 40 (40a, 40b) observed when the multilayer ceramic capacitor 100 is viewed from a direction perpendicular to the mounting surface 11, is not particularly limited, as long as it is large enough to facilitate mounting on a circuit board and small enough to prevent short-circuiting between electrodes having opposite polarities. Preferably, the ratio of the total area of ​​the terminal electrodes 40 to the area of ​​the mounting surface 11 is 0.2 to 0.9, and more preferably, the ratio is 0.3 to 0.8.

[0041] <Second embodiment> In another embodiment (second embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, the number of terminal electrodes arranged on the mounting surface is four or more, and each of the terminal electrodes has a polarity opposite to that of the nearest terminal electrode on the mounting surface. An example of a multilayer ceramic capacitor 200 according to the second embodiment is shown in FIG. 5. Note that FIG. 5 shows an example in which the number of terminal electrodes 40 arranged on the mounting surface 11 is four, but the number of terminal electrodes arranged on the mounting surface is not limited to this. In the multilayer ceramic capacitor 200, the directions of currents flowing through the via conductors 23 (23a, 23b) electrically connected to each terminal electrode 40 (40a, 40b) are opposite to each other in the nearest via conductors 23 (23a, 23b). This has the advantage of reducing ESL. The above-mentioned ESL reduction effect is remarkable when the multilayer ceramic capacitor 200 has two pairs of surfaces that are parallel to the stacking direction of the laminate and face each other, and when the distance between one pair, i.e., the L-direction dimension, is L μm and the distance between the other pair, i.e., the W-direction dimension, is W μm (where L≧W), and the value of W / L, which is the ratio of W to L, is 0.8 or more and 1 or less, i.e., when the mounting surface 11 has a shape that is close to a square.

[0042] <Third embodiment> In another embodiment (third embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention, two or more of the via conductors are electrically connected to at least a portion of the internal electrodes. An example of a multilayer ceramic capacitor 300 according to the third embodiment is shown in FIG. 6. While FIG. 6 shows an example in which two via conductors 23a are electrically connected to the internal electrode 22a and one via conductor 23b is electrically connected to the internal electrode 22b, the number of via conductors (23a, 23b) connected to each internal electrode 22 (22a, 22b) is not limited to this. In the multilayer ceramic capacitor 300, the current flowing through the via conductors 23a and the internal electrode 22a is reduced, and the magnetic field generated by the current flowing through the via conductor 23a can be effectively canceled out by the magnetic field generated by the current flowing through the via conductor 23a, thereby offering the advantage of reduced ESL.

[0043] <Fourth embodiment> Another embodiment (fourth embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention is similar to the third embodiment, except that at least one of the terminal electrodes is electrically connected to two or more of the via conductors. An example of a multilayer ceramic capacitor 400 according to the fourth embodiment is shown in FIG. 7. Note that FIG. 7 shows a cross section of the multilayer ceramic capacitor 400, in which two via conductors (23a, 23b) are electrically connected to each terminal electrode 40 (40a, 40b), cut along a plane perpendicular to the L direction so as to equally divide the L-direction dimension of the terminal electrode 40a. However, the number and arrangement of the via conductors (23a, 23b) connected to each terminal electrode 40 (40a, 40b) are not limited to this. In addition to the ESL reduction effect of the ceramic capacitor according to the third embodiment, the multilayer ceramic capacitor 400 has the advantages of reducing the number of terminal electrodes, thereby reducing the number of manufacturing steps, and facilitating alignment when mounted on a circuit board.

[0044] [Manufacturing method for multilayer ceramic electronic components] The multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0045] (A) Preparation of ceramic powder First, ceramic powder is prepared. Commercially available ceramic powders can be used as appropriate. When producing ceramic powder in-house, various raw material powders containing the constituent elements are mixed in a predetermined ratio and pre-fired (calcined). When mixing the various raw material powders in a predetermined ratio, various additives such as the above-mentioned additive elements and sintering aids may be further added, or these various additives may be further added to the powder after calcination.

[0046] (B) Preparation of raw sheets Next, the ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a green sheet.

[0047] The binder used should be one that can maintain the shape of the green sheet and volatilizes without leaving behind carbon or other residues during the binder removal process prior to firing. Examples of binders that can be used include polyvinyl alcohol, polyvinyl butyral, cellulose, urethane, and vinyl acetate. There are no particular restrictions on the amount of binder used, but since it will be removed in a later process, it is preferable to use as little as possible within the range that achieves the desired formability and shape retention, in order to reduce raw material costs.

[0048] The dispersion medium used is one that does not cause aggregation of the calcined powder and binder and can be easily removed by volatilization or the like after forming into a green sheet, as described below. Examples of the dispersion medium that can be used include water and alcohol-based solvents.

[0049] Components for adjusting the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0050] The method for mixing the mixed powder with the binder and the dispersion medium is not particularly limited as long as the components are mixed uniformly while preventing the inclusion of impurities. One example is ball mill mixing.

[0051] The prepared slurry can be formed into a sheet to obtain a green sheet by a commonly used method such as a doctor blade method or a die coating method.

[0052] ((C) Formation of internal electrode pattern) Next, an internal electrode pattern containing metal is formed on the green sheet. The internal electrode pattern can be formed by printing or applying an internal electrode paste in a predetermined pattern, or by forming a metal film in a predetermined pattern by vapor deposition or sputtering. The internal electrode pattern is formed with a sufficient margin to ensure electrical insulation with the via conductor patterns that will be formed later and that will not come into contact with the via conductor patterns.

[0053] When forming an internal electrode pattern using an internal electrode paste, the internal electrode paste used is obtained by mixing metal particles and a vehicle in a triple roll mill. The internal electrode paste may contain glass frit and ceramic powder in addition to the above-mentioned components.

[0054] The type and amount of binder and solvent contained in the vehicle used are not limited, and may be selected appropriately taking into consideration the viscosity of the internal electrode paste, ease of handling, compatibility with the green sheet, and the like.

[0055] The internal electrode paste can be printed on the green sheet using, for example, a screen mask on which a predetermined internal electrode pattern is formed. When printing, a space may be left to become a margin when the multilayer ceramic capacitor is completed.

[0056] (D) Preparation of green laminate Next, a predetermined number of green sheets on which the internal electrode patterns have been formed are stacked and the green sheets are pressure-bonded together to obtain a green laminate. The stacking and pressure-bonding can be performed by a conventional method, such as pressing the stacked green sheets together in the stacking direction while heating them, and thermo-compression bonding by the action of a binder.

[0057] During lamination and compression bonding, a green sheet that will become a cover when the multilayer ceramic capacitor is completed may be added to the end portion in the lamination direction. In this case, the green sheet to be added may have the same composition as the green sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of making the shrinkage rate during firing uniform, it is preferable that the composition of the green sheet to be added is the same as or similar to the green sheet on which the above-mentioned internal electrode precursor is arranged.

[0058] ((E) Formation of via conductor pattern) Next, holes are formed in the green laminate, and the holes are filled with a conductive paste to form a via conductor pattern. Conventional methods such as drilling or lasers can be used to form the holes. Lasers are preferred because they can produce a smooth processed surface. Conventional methods such as syringe injection and metal mask printing can be used to fill the holes with the conductive paste. Metal mask printing is preferred because it has excellent filling properties for small-diameter holes. The components of the conductive paste can be the same as those of the internal electrode paste described above, and the amount of each component can be determined taking into account the hole filling properties.

[0059] ((F) Formation of terminal electrode pattern) Next, a terminal electrode pattern is formed on at least one of the surfaces (mounting surface) perpendicular to the lamination direction of the green laminate. A green sheet, which will serve as a cover when the laminate is completed, may be crimped onto the surface on which the terminal electrode pattern is not formed, so as to cover the via conductor pattern. The terminal electrode pattern can be formed by printing or applying a terminal electrode paste, or by forming a metal film by vapor deposition or sputtering. The terminal electrode pattern can be formed using a mask with a predetermined pattern. Alternatively, the terminal electrode pattern can be formed by first forming a paste film or metal film on the entire mounting surface of the green laminate and then removing the portions other than the terminal electrode pattern. Removal of the portions other than the terminal electrode pattern can be achieved by face milling, barrel polishing, laser processing, or other methods. When using a terminal electrode paste to form the terminal electrode pattern, the components can be the same as those of the internal electrode paste described above. The blending amounts of each component can be determined to obtain a uniform pattern with a predetermined thickness.

[0060] (G) Preparation of pre-fired chips Next, the green laminate is divided into individual pieces to obtain pre-fired chips. For the division, a commonly used means such as a dicing saw or a laser cutting machine can be used. After dividing the green laminate into individual pieces to form surfaces on which the internal electrode precursors are exposed, the surfaces may be coated with a material for forming margins to obtain pre-fired chips.

[0061] (H) Removal of binder Next, the resulting pre-fired chips are heated to volatilize and remove the binder. The heating conditions can be set appropriately taking into account the volatilization temperature and content of the binder. For example, the chips are held in a nitrogen (N2) atmosphere at a temperature of 200 to 500°C for 5 to 20 hours.

[0062] (I) Firing of pre-fired chips Next, the pre-fired chip from which the binder has been removed is heated to a predetermined temperature and fired. When setting the firing conditions, it is preferable to consider the sinterability of the ceramic powder, as well as the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern. An example of firing conditions is holding the chip at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours in a reducing atmosphere containing a mixture of nitrogen (N2), hydrogen (H2), and water vapor (H2O). After firing, a reoxidation treatment may be performed in which the chip is held at 600°C to 1000°C in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere.

[0063] The sintered body thus obtained may be used as a multilayer ceramic capacitor as it is, or may be used as a multilayer ceramic capacitor after forming a conductive layer on the surface of the terminal electrode pattern by plating.

[0064] [Circuit board] <Fifth embodiment> An embodiment of the circuit board according to the second aspect of the present invention will be described as a fifth embodiment with reference to FIG. 8 . A circuit board 500 according to the fifth embodiment includes a multilayer ceramic capacitor 100 according to the first aspect mounted thereon and lands 51 electrically connected to a plurality of terminal electrodes 40 (40 a, 40 b). The lands 51 are entirely covered by the multilayer ceramic capacitor 100 in a plan view, i.e., when viewed perpendicular to the circuit board 500. In FIG. 8 , the multilayer ceramic capacitor 100 is mounted on the lands 51 of the circuit board 500 via solder 52. Since the lands 51 are entirely covered by the multilayer ceramic capacitor 100 in a plan view, in other words, the lands 51 are located inside the outer edge of the mounting surface 11 of the multilayer ceramic capacitor 100, the distance between the lands (not shown) for connecting adjacent elements can be made wider than the distance between the elements themselves. This allows the distance between adjacent elements to be narrowed while ensuring electrical insulation between the elements. This makes it possible to increase the number of elements that can be mounted in a given space, and to reduce the dimensions of the circuit board when the same number of elements of the same size are mounted.

[0065] Sixth Embodiment A sixth embodiment of a circuit board according to the third aspect of the present invention will be described with reference to FIG. 9. A circuit board 600 according to the sixth embodiment includes a plurality of multilayer ceramic capacitors 100 according to the first aspect, with adjacent multilayer ceramic capacitors 100 spaced apart by 50 μm or less. As shown in FIG. 9, in the circuit board 600 according to the sixth embodiment, when the terminal electrodes 40 (40a, 40b) of the multilayer ceramic capacitors 100 are joined to the lands 61 via solder 62, fillets caused by wetting of the solder 62 are not formed. This allows the multilayer ceramic capacitors to be spaced apart from each other by 50 μm or less. This allows the number of elements that can be mounted in a given space to be increased, and the dimensions of the circuit board to be reduced when the same number of elements of the same size are mounted on the same board. [Example]

[0066] The present invention will be explained in more detail below with reference to examples, but the present invention is not limited to these examples.

[0067] [Example 1] (Production of raw sheets) Pre-fired barium titanate (BaTiO) powder was prepared as the ceramic powder. A polyvinyl butyral binder and an alcohol solvent were added to this powder and mixed in a wet ball mill. The resulting mixed slurry was formed with a doctor blade to obtain a green sheet with a thickness of 1 μm.

[0068] (Fabrication of multilayer ceramic capacitors) An internal electrode paste containing nickel powder as a metal was screen-printed onto the resulting green sheet to form an internal electrode pattern. 50 of these green sheets were then stacked. Five green sheets without the internal electrode paste printed on each of the top and bottom surfaces were then stacked on top and bottom of the green sheet to form cover sections, and the stack was then thermocompressed to obtain a green laminate. Holes were formed at predetermined positions in the green laminate using a laser, and a via conductor-forming paste containing nickel powder as a metal was squeegee-filled into the holes through a metal mask. A green sheet to form a cover section was attached to one side of the green laminate filled with the via conductor-forming paste, and a terminal electrode-forming paste containing nickel powder as a metal was screen-printed on the other side. The screen was patterned to form the base electrode and spaced a predetermined distance from the outer edge of the mounting surface. The green laminate was then singulated to form pre-fired chips. The unfired chip was heated to 300°C in a nitrogen atmosphere to remove the binder, and then heated to 1200°C in a reducing-steam atmosphere (a nitrogen-hydrogen-containing reducing gas with added water vapor), where the temperature was maintained for 2 hours for firing. The temperature was then lowered to near room temperature to obtain a sintered body. Copper, nickel, and tin layers were plated in this order on the nickel layer formed by sintering the terminal electrode-forming paste on the surface of the sintered body, yielding a multilayer ceramic capacitor according to Example 1. The resulting multilayer ceramic capacitor had a mounting surface with a rectangular shape of 1000 μm × 500 μm, and two terminal electrodes with a rectangular shape of 250 μm × 480 μm were formed 10 μm apart from the outer edge of the mounting surface. The T-direction dimension of this multilayer ceramic capacitor was 100 μm.

[0069] (Solder wetting test) A solder wetting test was performed on the multilayer ceramic capacitor of Example 1, in which the capacitor was mounted using solder on a circuit board on which 250 μm × 480 μm lands were arranged at 480 μm intervals. The test was performed on 50 elements, and if no element showed a solder fillet, it was judged to have passed. The results are shown in Table 1.

[0070] [Examples 2 and 3] Multilayer ceramic capacitors according to Examples 2 and 3 were fabricated in the same manner as in Example 1, except that the terminal electrodes were two rectangular terminal electrodes measuring 300 μm × 200 μm, spaced 15 μm apart from the outer edge of the mounting surface (Example 2), and two rectangular terminal electrodes measuring 200 μm × 150 μm, spaced 20 μm apart from the outer edge of the mounting surface (Example 3), and a solder wetting test was carried out. The results are shown in Table 1.

[0071] [Comparative Examples 1 and 2] Multilayer ceramic capacitors according to Comparative Examples 1 and 2 were fabricated in the same manner as in Example 1, except that the terminal electrodes were two rectangular terminal electrodes measuring 260 μm × 500 μm formed in contact with the outer edge of the mounting surface (Comparative Example 1), and two rectangular terminal electrodes measuring 255 μm × 490 μm formed at a distance of 5 μm from the outer edge of the mounting surface (Comparative Example 2), and a solder wetting test was carried out. The results are shown in Table 1.

[0072] [Table 1]

[0073] From the above results, it can be seen that the multilayer ceramic capacitors according to the examples, in which the multiple terminal electrodes formed on the mounting surface are all spaced 10 μm or more from the outer edge of the mounting surface, do not produce fillets due to solder wetting when mounted on a circuit board. On the other hand, the multilayer ceramic capacitors according to the comparative examples, in which the distance between the terminal electrodes formed on the mounting surface and the outer edge of the mounting surface is less than 10 μm, may produce fillets when mounted on a circuit board.

[0074] This specification also discloses the following techniques.

[0075] (Appendix 1) a laminate in which ceramic layers and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, at least one end of which reaches the surface of the protective portion and is electrically connected to the internal electrodes; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes arranged on a mounting surface that faces a circuit board when the element is mounted on the circuit board, among the surfaces that form the surface of the element; Equipped with Each of the plurality of terminal electrodes is electrically connected to the via conductor and is disposed at an interval of 10 μm or more from the outer edge of the mounting surface. Multilayer ceramic capacitor.

[0076] (Appendix 2) The multilayer ceramic capacitor according to (Appendix 1), wherein the outer edge is determined by approximating the outline appearing in an optical microscope image or a scanning electron microscope (SEM) image taken from a direction perpendicular to the mounting surface to a rectangle.

[0077] (Appendix 3) The multilayer ceramic capacitor according to (Appendix 1) or (Appendix 2), wherein the plurality of terminal electrodes have an underlying conductor in contact with the element body and a plated conductor formed on the surface of the underlying conductor, and the underlying conductor is arranged at intervals of 15 μm or more from the outer edge of the mounting surface.

[0078] (Appendix 4) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 3), wherein the height, which is the dimension in the direction perpendicular to the mounting surface, is 100 μm or less.

[0079] (Appendix 5) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 4), wherein the distance between the plurality of terminal electrodes is 400 μm or less.

[0080] (Appendix 6) The multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 5), wherein the number of the plurality of terminal electrodes is four or more, and each of the terminal electrodes has a polarity different from that of the other terminal electrode closest to it within the mounting surface.

[0081] (Appendix 7) The multilayer ceramic capacitor according to any one of (Supplementary Note 1) to (Supplementary Note 6), wherein two or more of the via conductors are electrically connected to at least a part of the internal electrode.

[0082] (Appendix 8) The multilayer ceramic capacitor according to (Supplementary Note 7), wherein at least one of the terminal electrodes is electrically connected to two or more of the via conductors.

[0083] (Appendix 9) A circuit board having the multilayer ceramic capacitor according to any one of (Appendix 1) to (Appendix 8) mounted thereon, wherein the lands electrically connected to the plurality of terminal electrodes are entirely covered by the multilayer ceramic capacitor in a plan view.

[0084] (Appendix 10) A circuit board having a plurality of multilayer ceramic capacitors according to any one of (Appendix 1) to (Appendix 8) mounted thereon, the interval between adjacently arranged multilayer ceramic capacitors being 50 μm or less. [Industrial Applicability]

[0085] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can reduce the element spacing when mounted on a circuit board, and a circuit board that allows for narrow mounting spacing between mounted elements. Such a multilayer ceramic capacitor and circuit board are useful in that they contribute to the miniaturization of electronic devices equipped with high-performance semiconductors. [Explanation of symbols]

[0086] 100, 100', 200, 300, 400 Multilayer ceramic capacitors 10 Base 11 Mounting surface 20 laminate 21 ceramic layer 22(22a, 22b) Internal electrode 23(23a, 23b) Via conductor 30 Protection Department 31 Cover 32 Margin 40(40a, 40b) terminal electrode 41 Undercoat conductor 42 Plated conductor 500, 600 circuit board 51, 61 rand 52, 62 Solder

Claims

1. a laminate in which ceramic layers and internal electrodes mainly composed of metal are alternately stacked; a protective portion covering the surface of the laminate; and a plurality of via conductors arranged to penetrate the ceramic layers in the stacking direction of the laminate, at least one end of which reaches the surface of the protective portion and is electrically connected to the internal electrodes; A rectangular parallelepiped element having the following structure: a plurality of terminal electrodes arranged on a mounting surface that faces a circuit board when the element is mounted on the circuit board, among the surfaces that form the surface of the element; Equipped with Each of the plurality of terminal electrodes is electrically connected to the via conductor and is disposed at an interval of 10 μm or more from the outer edge of the mounting surface. Multilayer ceramic capacitor.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the outer edge is determined by approximating a contour that appears in an optical microscope image or a scanning electron microscope (SEM) image taken from a direction perpendicular to the mounting surface to a rectangle.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein the plurality of terminal electrodes have an underlying conductor in contact with the element body and a plated conductor formed on a surface of the underlying conductor, and the underlying conductor is disposed at intervals of 15 μm or more from an outer edge of the mounting surface.

4. 2. The multilayer ceramic capacitor according to claim 1, wherein the height, which is the dimension in a direction perpendicular to the mounting surface, is 100 [mu]m or less.

5. 5. The multilayer ceramic capacitor according to claim 4, wherein the intervals between the plurality of terminal electrodes are 400 [mu]m or less.

6. 2. The multilayer ceramic capacitor according to claim 1, wherein the number of said plurality of terminal electrodes is four or more, and each of said terminal electrodes has a polarity different from that of the other terminal electrode closest to said terminal electrode on said mounting surface.

7. 2. The multilayer ceramic capacitor according to claim 1, wherein two or more of the via conductors are electrically connected to at least a portion of the internal electrode.

8. 8. The multilayer ceramic capacitor according to claim 7, wherein at least one of the terminal electrodes is electrically connected to two or more of the via conductors.

9. 9. A circuit board having the multilayer ceramic capacitor according to claim 1 mounted thereon, the lands electrically connected to the plurality of terminal electrodes being entirely covered by the multilayer ceramic capacitor in a plan view.

10. 9. A circuit board on which a plurality of multilayer ceramic capacitors according to claim 1 are mounted, the interval between adjacent multilayer ceramic capacitors being 50 μm or less.

Images