Regulator and power device

Abstract

To realize a regulator and a power device that can be controlled with a small current.SOLUTION: A regulator 1 comprises: a reference potential generating circuit 11 that generates a reference potential which is a reference for a midpoint potential VFGND and a midpoint potential VFGNDL which is lower than the midpoint potential VFGND; a differential amplifier 12 into which the midpoint potential VFGNDL is supplied as a low potential-sided power supply, and which amplifies a difference voltage between a feedback potential corresponding to the midpoint potential VFGND and a reference potential; and a transistor Tr1 where the amplified difference voltage is input to a gate, a drain is connected to a constant current source or to a ground potential via a resistor, and a source generates the midpoint potential VFGND.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a regulator and a power device. [Background technology]

[0002] Patent Document 1 discloses a technique for generating an intermediate potential using a Zener diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-014356 Summary of the Invention [Problem to be solved by the invention]

[0004] Patent Document 1 discloses that the current flowing through the Zener diode is set according to the maximum current of a circuit to which the intermediate potential is supplied, such as an internal circuit of a power device, which poses a problem of a large current required to generate the intermediate potential.

[0005] The present disclosure has been made to solve such problems, and aims to realize a regulator and a power device that can be controlled with a small current.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A regulator according to one embodiment includes a reference potential generating circuit that generates a reference potential that serves as a reference for a first intermediate potential and a second intermediate potential that is lower than the first intermediate potential; a differential amplifier that receives the second intermediate potential as a low-potential power supply and amplifies a difference voltage between a feedback potential corresponding to the first intermediate potential and the reference potential; and a first transistor that receives the amplified difference voltage at its gate, has a drain that is connected to a ground potential via a constant current source or a resistor, and has a source that generates the first intermediate potential.

[0008] A power device according to one embodiment includes: a reference potential generating circuit that generates a reference potential that is a reference for a first intermediate potential and a second intermediate potential that is lower than the first intermediate potential; a differential amplifier that receives the second intermediate potential as a low-potential power supply and amplifies a difference voltage between a feedback potential corresponding to the first intermediate potential and the reference potential; a first transistor that receives the amplified difference voltage at its gate, has a drain connected to a ground potential via a constant current source or a resistor, and generates the first intermediate potential at its source; and a control circuit that receives the first intermediate potential as a low-potential power supply and controls the power transistor. [Effects of the Invention]

[0009] According to the embodiment, it is possible to provide a regulator and a power device that can be controlled with a small current. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of the regulator according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a regulator according to Modification 1 of Embodiment 1. As shown in FIG. [Figure 3] FIG. 3 is a circuit diagram showing a configuration of a regulator according to Modification 2 of Embodiment 1. As shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing the configuration of the regulator according to the second embodiment. [Figure 5]FIG. 5 is a circuit diagram schematically illustrating the configuration of a power device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are denoted by the same reference numerals, and repeated explanations have been omitted as necessary.

[0012] Embodiment 1 1 is a circuit diagram showing the configuration of a regulator 1 according to a first embodiment. The regulator 1 receives a power supply voltage VCC as an input voltage and generates an intermediate potential VFGND as an output voltage. The intermediate potential VFGND is also referred to as a first intermediate potential. The intermediate potential VFGND is supplied to an internal circuit 2 as a low-potential power supply voltage. Specifically, the internal circuit 2 is an internal circuit of an IPD (Intelligent Power Device), for example, a control circuit, but may be any circuit. The intermediate potential VFGND is preferably a voltage that is approximately 5 to 8 V lower than the power supply voltage VCC so that the internal circuit 2 can be configured using low-voltage elements.

[0013] The regulator 1 includes a reference potential generating circuit 11, a differential amplifier 12, and a p-channel MOS (Metal Oxide Semiconductor) transistor Tr1. The reference potential generating circuit 11 generates a reference potential Vref and an intermediate potential VFGNDL. The reference potential Vref and the intermediate potential VFGNDL are also referred to as a first reference potential and a second reference potential, respectively. The intermediate potential VFGNDL is lower than the intermediate potential VFGND. The intermediate potential VFGNDL is also referred to as a second intermediate potential. The intermediate potentials VFGND and VFGNDL are potentials between a power supply potential VCC and a ground potential GND. Note that a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) may be used as the p-channel MOS transistor Tr1. To drive the p-channel MOS transistor Tr1, the intermediate potential VFGNDL is preferably a voltage approximately 1 V lower than the intermediate potential VFGND.

[0014] The regulator 1 further includes n-channel MOS transistors Tr2 to Tr4 and p-channel MOS transistors Tr5 to Tr6. The sources of the MOS transistors Tr2, Tr3, and Tr4 are connected to the ground potential GND. A bias voltage BIAS is supplied to the gates of the MOS transistors Tr2, Tr3, and Tr4. The MOS transistors Tr2, Tr3, and Tr4 each function as a constant current source. The MOS transistor Tr5 is connected in series to the MOS transistor Tr2, and the MOS transistor Tr4 is connected in series to the MOS transistor Tr1. The MOS transistor Tr6 is provided in a path that supplies a power supply potential VCC to the differential amplifier 12, and functions as a constant current source for stable operation of the differential amplifier 12. The gates of the MOS transistors Tr5 and Tr6 are connected to the drain of the MOS transistor Tr5.

[0015] The reference potential generating circuit 11 includes a Zener diode ZD1 and a p-channel MOS transistor Tr7. The Zener diode ZD1 is also referred to as a second Zener diode. The Zener diode ZD1 and the MOS transistor Tr7 are connected in series and are provided in a path between the power supply potential VCC and the MOS transistor Tr3. The cathode of the Zener diode ZD1 is connected to the power supply potential VCC. The gate and drain of the MOS transistor Tr7 are connected to each other, and the MOS transistor Tr7 functions as a diode. The anode of the diode is connected to the anode of the Zener diode ZD1.

[0016] A reference potential Vref, which is the reference for the midpoint potential VFGND, is generated at the anode of the Zener diode ZD1. If the Zener voltage of the Zener diode ZD1 is Vz, the reference potential Vref is VCC-Vz. An midpoint potential VFGNDL is generated at the cathode of the diode formed by the MOS transistor Tr7.

[0017] An intermediate potential VFGNDL is supplied to the differential amplifier 12 as a low-potential power supply voltage. A reference potential Vref is input to a first input terminal of the differential amplifier 12. A potential corresponding to the intermediate potential VFGND is applied as a feedback potential to a second input terminal of the differential amplifier 12. Specifically, the source voltage of the MOS transistor Tr1 is applied as a feedback potential to the second input terminal of the differential amplifier 12. The differential amplifier 12 amplifies the difference voltage between the reference potential Vref and the feedback potential and outputs the amplified difference voltage.

[0018] The gate of the MOS transistor Tr1 is connected to the output of the differential amplifier 12. That is, the amplified difference voltage is input to the gate of the MOS transistor Tr1. The drain of the MOS transistor Tr1 is connected to the ground potential GND via the MOS transistor Tr4 constituting a constant current source. Alternatively, the drain of the MOS transistor Tr1 may be connected to the ground potential GND via a resistor instead of the MOS transistor Tr4. The resistor may be a resistor for limiting the current of the internal circuit 2. The source of the MOS transistor Tr1 is the output of the regulator 1. That is, the voltage of the source of the MOS transistor Tr1 is the output voltage of the regulator 1, the intermediate potential VFGND. The MOS transistors Tr1 and Tr4 form a source follower circuit.

[0019] The current flowing through MOS transistors Tr2 and Tr5 is IR0, the current flowing through MOS transistor Tr3 is IR1, the current flowing through MOS transistor Tr6 is IR2, and the current flowing through MOS transistor Tr4 is IR3. MOS transistor Tr6 is configured so that current IR2 is a copy of current IR0 at a predetermined mirror ratio. Current IR2 flows into differential amplifier 12. MOS transistor Tr3 is configured so that current IR1 is larger than current IR2. The difference between current IR1 and current IR2 flows into reference potential generating circuit 11. Current IR3 is N times current IR1 and is set based on the maximum current flowing through internal circuit 2. In idle mode, currents IR0 and IR1 may be controlled to be reduced.

[0020] The operation of the regulator 1 according to the first embodiment will be described. As described above, the regulator 1 receives the power supply voltage VCC as an input and outputs the intermediate potential VFGND. The intermediate potential VFGND is the source voltage of the MOS transistor Tr1. The MOS transistor Tr1 is controlled by the output of the differential amplifier 12.

[0021] The differential amplifier 12 controls the MOS transistor Tr1 based on the difference between the reference voltage Vref and the voltage at the source of the MOS transistor Tr1, which is the feedback potential. That is, the differential amplifier 12 controls the MOS transistor Tr1 in response to fluctuations in the intermediate potential VFGND. For example, if the intermediate potential VFGND drops below the reference potential Vref due to a load fluctuation in the internal circuit 2, the differential amplifier 12 controls the MOS transistor Tr1 to increase its gate voltage. Because the MOS transistor Tr1 functions as a source follower, the source voltage rises in response to the gate voltage of the MOS transistor Tr1. This increases the intermediate potential VFGND. On the other hand, if the intermediate potential VFGND rises above the reference potential Vref due to a load fluctuation in the internal circuit 2, the differential amplifier 12 controls the MOS transistor Tr1 to decrease its gate voltage. As a result, the source voltage of the MOS transistor Tr1 decreases in response to the gate voltage of the MOS transistor Tr1. This operation stabilizes the intermediate potential VFGND at a value equal to the reference voltage Vref.

[0022] In the regulator 1 according to the first embodiment, an intermediate potential VFGNDL is supplied to the differential amplifier 12 as a low-potential power supply. Because the differential amplifier 12 only needs to control the MOS transistor Tr1, the intermediate potential VFGNDL as a low-potential power supply voltage only needs to be about 1 V lower than the intermediate potential VFGND (VCC-VFGNDL=6 to 9 V). This allows the differential amplifier 12 to be configured using low-voltage elements and circuits, making it possible to reduce the current flowing through the differential amplifier 12. Furthermore, the currents IR1 and IR2 for the reference potential generating circuit 11 and the differential amplifier 12 can be set regardless of the current supplied to the internal circuit 2. Therefore, the current flowing through the reference potential generating circuit 11 can also be reduced.

[0023] Therefore, the regulator 1 according to the first embodiment can be controlled with a small current. Furthermore, the differential amplifier 12 can be configured with low-voltage elements, so the circuit scale is small and it is easy to control.

[0024] The output of the differential amplifier 12 is always at about the intermediate potential VFGND-Vtp, which provides a fast response time for the MOS transistor Tr1 and reduces the risk of oscillation.Vtp represents the threshold voltage of the p-channel MOS transistor Tr1.

[0025] Modification 1 of the embodiment FIG. 2 is a circuit diagram showing the configuration of a regulator 1a according to Modification 1. Comparing FIG. 1 with FIG. 2, the regulator 1a according to Modification 1 further includes a feedback circuit F. The feedback circuit F includes a diode D1. The cathode of the diode D1 is connected to the source of the MOS transistor Tr1. The anode of the diode D1 serves as the output of the regulator 1a.

[0026] If the Zener voltage of Zener diode ZD1 is Vz and the forward voltage of diode D1 is VF, regulator 1a controls MOS transistor Tr1 so that VFGND-VF=VCC-Vz holds true. Therefore, the intermediate potential VFGND is stabilized at (VCC-Vz)+VF.

[0027] The regulator 1a according to the first modification generates an intermediate potential VFGND different from the reference voltage Vref of the differential amplifier 12 by using the feedback circuit F.

[0028] Modification 2 of Embodiment 1 FIG. 3 is a circuit diagram showing the configuration of a regulator 1b according to Modification 2. Comparing FIG. 1 with FIG. 3, the Zener diode ZD1 constituting the reference potential generating circuit 11 has been replaced with a plurality of diodes D2 connected in series. The diodes may be MOS transistors whose gates and drains are connected to each other. Alternatively, circuit elements such as resistors may be used instead of the diodes.

[0029] As in the reference potential generating circuit 11 according to the second modification, the reference potential may be generated using a diode or a resistor, instead of using a Zener diode.

[0030] Embodiment 2 Fig. 4 is a circuit diagram showing the configuration of a regulator 10 according to embodiment 2. Comparing Fig. 1 with Fig. 4, the regulator 10 further includes a Zener diode ZD2, a capacitor C, and n-channel MOS transistors Tr8 to Tr10.

[0031] The cathode of the Zener diode ZD2 is connected to the power supply potential VCC, and the anode of the Zener diode ZD2 is connected to the output of the regulator 10. The Zener diode ZD2 is also called a first Zener diode. A capacitor C is connected in parallel to the Zener diode ZD2.

[0032] The sources of the MOS transistors Tr8 and Tr9 are connected to the ground potential GND. The gates of the MOS transistors Tr8 and Tr9 are connected to the drain of the MOS transistor Tr8. The MOS transistor Tr9 copies the current flowing through the MOS transistor Tr8 and supplies the current to the Zener diode ZD2.

[0033] The MOS transistor Tr10 is provided in a path between the Zener diode ZD2 and the MOS transistor Tr9. The MOS transistor Tr10 is also referred to as a second transistor. A control signal IDLE_DIS is input to the gate of the MOS transistor Tr10. The control signal IDLE_DIS is a signal for instructing whether the internal circuit 2 is in idle mode or normal mode. In this embodiment, the control signal IDLE_DIS is at H level when the idle mode of the internal circuit 2 is disabled, that is, when the internal circuit 2 is in normal mode. In this way, the MOS transistor Tr10 functions as a switch that switches the connection state between the Zener diode ZD2 and the MOS transistor Tr9 using the control signal IDLE_DIS.

[0034] The current flowing through MOS transistor Tr9 is assumed to be IR4. MOS transistor Tr9 is configured so that current IR4 is larger than the maximum current of internal circuit 2 in normal mode. Current IR4 is set to be N times (N is an integer greater than or equal to 1) the current IR1 flowing through MOS transistor Tr3. MOS transistor Tr4 is also configured so that current IR3 flowing through MOS transistor Tr4 is larger than the maximum current of internal circuit 2 in idle mode. Current IR3 is set to be M times (M is an integer greater than or equal to 1) the current IR1. Current IR4 is larger than current IR3. In other words, N is larger than M.

[0035] As in the first embodiment, the source voltage of the MOS transistor Tr1 is the intermediate potential VFGND supplied to the internal circuit 2. When the internal circuit 2 is in the idle mode, the control signal IDLE_DIS indicates an L level, so that the MOS transistor Tr10 is controlled to be in the off state. Therefore, when the internal circuit 2 is in the idle mode, the current flowing through the internal circuit 2 flows through the path provided with the MOS transistors Tr1 and Tr4. The intermediate potential VFGND generated by the MOS transistor Tr1 is supplied to the internal circuit 2.

[0036] When the internal circuit 2 is in normal mode, the control signal IDLE_DIS indicates an H level, so that the MOS transistor Tr10 is controlled to be in an on state. Therefore, when the internal circuit 2 is in normal mode, the current flowing through the internal circuit 2 mainly flows through the path provided with the MOS transistor Tr9. The difference between the current IR4 and the current flowing through the internal circuit 2 flows through the Zener diode ZD2, and an intermediate potential VFGND is generated at the anode of the Zener diode ZD2. The intermediate potential VFGND generated by the Zener diode ZD2 is supplied to the internal circuit 2. When the internal circuit 2 is in normal mode, in order to suppress fluctuations in the intermediate potential VFGND, the current IR4 flowing through the MOS transistor Tr9 is made larger than the current flowing through the internal circuit 2 in normal mode.

[0037] The differential amplifier 12 may include a function for adjusting an offset. For example, the offset of the differential amplifier 12 may be adjusted so that the intermediate potential VFGND generated by the MOS transistor Tr1 is higher than the intermediate potential VFGND generated by the Zener diode ZD2.

[0038] Furthermore, by including a function for adjusting the offset in the differential amplifier 12, the effects of variations in the characteristics of the Zener diodes ZD1 and ZD2 can be reduced. For example, consider a case in which the characteristics of the Zener diodes ZD1 and ZD2 vary in the second embodiment. The output of the regulator 10, i.e., the source voltage of the MOS transistor Tr1, is controlled by the differential amplifier 12 to be equal to the voltage of the Zener diode ZD1. The difference between the voltage generated by the Zener diode ZD2 and the voltage generated by the Zener diode ZD1 may cause unnecessary current to flow. However, adjusting the offset of the differential amplifier 12 can reduce such unnecessary current.

[0039] When the internal circuit 2 is in the normal mode, in order to stably supply the intermediate potential VFGND, the current IR4 flowing through the MOS transistor Tr9 needs to be larger than the current flowing through the internal circuit 2 in the normal mode. On the other hand, when the internal circuit 2 is in the idle mode, the current flowing through the internal circuit 2 is also smaller than that in the normal mode. Therefore, in the second embodiment, the power consumption of the regulator 10 when the internal circuit 2 is in the idle mode is configured to be smaller than the power consumption of the regulator 10 when the internal circuit 2 is in the normal mode.

[0040] In the second embodiment, the MOS transistors Tr1 and Tr4 are configured to pass a current IR3 that is a maximum current assumed when the internal circuit 2 is in idle mode. Therefore, the MOS transistors Tr1 and Tr4 can be configured smaller than the MOS transistor Tr9. Furthermore, the differential amplifier 12 can be configured using low-voltage elements, as described in the first embodiment. Therefore, the circuit size of the differential amplifier 12 can also be reduced.

[0041] The regulator 10 according to the second embodiment can reduce the current flowing through the regulator 10 when the internal circuit 2 is in the idle mode.

[0042] Furthermore, an n-channel MOS transistor (not shown) may be further provided in the path between the MOS transistor Tr1 and the MOS transistor Tr4. An inverted signal of the control signal IDLE_DIS may be input to the gate of this MOS transistor. As a result, when the internal circuit 2 is in the normal mode, no current flows through the MOS transistors Tr1 and Tr4, and the intermediate potential VFGND may be supplied only by the Zener diode ZD2.

[0043] Embodiment 3 5 is a schematic circuit diagram showing the configuration of an IPD (Intelligent Power Device) 100 according to the third embodiment. The IPD 100 includes the regulator 10 according to the second embodiment. The IPD 100 may also include the regulator 1 according to the first embodiment.

[0044] The IPD 100 includes an n-channel power MOS transistor Tr11, a regulator 1, a level shifter 101, a control circuit 102, a charge pump 103, a level shifter 104, a driver 105, an n-channel sense MOS transistor Tr12, and a current detection circuit 106. The control circuit 102 and the charge pump 103 correspond to the internal circuit 2 described above.

[0045] The power MOS transistor Tr11 is provided in a path that supplies a power supply potential VCC to a load circuit 3 that may include an inductor, a resistor, a capacitor, etc. The power supply potential VCC may be generated by a battery. A drive signal from a driver 105 is input to the gate of the power MOS transistor Tr11. The potential of the source of the power MOS transistor Tr11 is output as an output potential OUT.

[0046] The regulator 10 has the same configuration as the regulator 10 of the second embodiment and generates an intermediate potential VFGND. The intermediate potential VFGND is supplied to a control circuit 102, a charge pump 103, and a level shifter 104. The regulator 10 also receives a detection result from a current detection circuit 106. Based on the detection result, the regulator 10 can recognize whether the control circuit 102 is set to the normal mode or the idle mode. That is, the detection result from the current detection circuit 106 corresponds to the control signal IDLE_DIS in the second embodiment.

[0047] The level shifter 101 converts a control signal, which has a predetermined amplitude with the ground potential GND at its L level, into a signal with a predetermined amplitude with the power supply potential VCC at its H level. The control circuit 102 controls the charge pump 103 based on the level-shifted control signal and transmits the control signal to the driver 105 via the level shifter 104. The charge pump 103 generates a boosted potential CPOUT higher than the power supply potential VCC under the control of the control circuit 102. The level shifter 104 converts the control signal from the control circuit 102 into a signal with a predetermined amplitude with the boosted potential CPOUT at its H level. The driver 105 generates a drive signal for driving the gate of the power MOS transistor Tr11 in accordance with the level-shifted control signal. The drive signal is also input to the gate of the sense MOS transistor Tr12. A small current flows through the sense MOS transistor Tr12, which is a copy of the current flowing through the power MOS transistor Tr11 at a small mirror ratio. The current flowing through the sense MOS transistor Tr12 is designated as current Is.

[0048] The current detection circuit 106 detects whether the minute current Is flowing through the sense MOS transistor Tr12 is equal to or less than a certain current value. The current detection circuit 106 may, for example, compare the voltage generated across a resistor through which the minute current Is flows with a threshold voltage using a comparator. Alternatively, the voltage generated across the resistor may be digitized by an ADC (Analog-to-Digital Converter), and the digitized voltage value may be compared with the threshold value.

[0049] When the current detection circuit 106 detects that the current Is is equal to or less than a certain current value, it is determined that the load circuit 3 has entered an idle state. Therefore, the detection result of the current detection circuit 106 is transmitted to the control circuit 102 via the level shifter 101, and the control circuit 102 is set to idle mode. Otherwise, the control circuit 102 is set to normal mode. For example, when the current Is is equal to or less than a certain current value, the regulator 10 may generate the intermediate potential VFGND using the differential amplifier 12 and the MOS transistor Tr1, and when the current Is is not equal to or less than a certain current value, the regulator 10 may generate the intermediate potential VFGND using the Zener diode ZD2. Specifically, the detection signal output by the current detection circuit 106 corresponds to the control signal IDLE_DIS in the second embodiment.

[0050] In the IPD 100 according to the third embodiment, the intermediate potential VFGND is supplied to the control circuit 102, etc., and therefore the control circuit 102, etc. can be configured using low-voltage elements. Furthermore, when the load circuit 3 is in an idle state, the IPD 100 can reduce the current consumption of the IPD 100 by reducing the current required to generate the intermediate potential VFGND.

[0051] Furthermore, in the third embodiment, the regulator 10 may be replaced with the regulator 1 of the first embodiment. In this case, the intermediate potential VFGND may be generated by the regulator 1 of the first embodiment regardless of the detection result of the current detection circuit 106, that is, regardless of the operating state of the load circuit 3.

[0052] Furthermore, in the third embodiment, the regulator 10 may be configured similarly to the regulator 1 of the first embodiment, and the current flowing through the regulator 1 may be switched depending on the detection result of the current detection circuit 106. For example, the MOS transistors Tr1 and Tr4 may be configured so that the amount of current flowing through the paths of the MOS transistors Tr1 and Tr4 can be switched depending on the detection result of the current detection circuit 106. That is, when the control circuit 102 is set to the idle mode depending on the detection result of the current detection circuit 106, the amount of current flowing through the paths of the MOS transistors Tr1 and Tr4 may be set smaller than the current flowing through the paths of the MOS transistors Tr1 and Tr4 when the control circuit 102 is set to the normal mode. This may allow the intermediate potential VFGND to be supplied with lower power consumption when the load circuit 3 is in the idle state. Additionally, in order to stably supply the intermediate potential VFGND, the amount of current supplied to the differential amplifier 12 may be switched depending on the detection result of the current detection circuit 106.

[0053] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0054] For example, the regulators according to the above embodiments may be configured such that the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. are reversed. Therefore, if one of the n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type. [Explanation of symbols]

[0055] 1, 1a, 1b, 10 regulators 11 Reference potential generation circuit 12 Differential Amplifier Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, Tr7, Tr8, Tr9, Tr10 MOS transistors ZD1, ZD2 Zener diodes C capacitor D1 Diode 100 IPD Tr11 Power MOS transistor Tr12 Sense MOS transistor 101, 104 Level shifter 102 control circuit 103 Charge Pump 105 Driver 106 Current detection circuit 2 Internal circuit 3 Load circuit VCC power supply potential VFGND, VFGNDL intermediate potential GND Ground potential

Claims

1. a reference potential generating circuit that generates a reference potential that is a reference for the first intermediate potential and a second intermediate potential that is lower than the first intermediate potential; a differential amplifier that receives the second intermediate potential as a low-potential power supply and amplifies a difference voltage between a feedback potential corresponding to the first intermediate potential and the reference potential; a first transistor having a gate to which the amplified differential voltage is input, a drain to which a constant current source or a resistor is connected to a ground potential, and a source to which the first intermediate potential is generated; A regulator with

2. a second transistor that is controlled to be in an off state when a circuit to which the first intermediate potential is supplied as a low potential side power supply is in an idle mode; a first Zener diode connected in series with the second transistor; Furthermore, When the circuit is in a normal mode, the first intermediate potential generated by the first Zener diode is supplied to the circuit. The regulator of claim 1 .

3. a current through the first transistor is set based on a maximum current of the circuit in the idle mode; The current flowing through the second transistor in the on state is set based on the maximum current of the circuit in the normal mode. The regulator of claim 2 .

4. A diode is provided between the source of the first transistor and a node at which the first intermediate potential is generated. The regulator of claim 1 .

5. the reference potential generating circuit includes a second Zener diode and a diode connected in series; the anode of the Zener diode and the anode of the diode are connected to each other; The reference potential is generated at the anode of the Zener diode; The second intermediate potential is generated at the cathode of the diode. The regulator of claim 1 .

6. a reference potential generating circuit that generates a reference potential that is a reference for the first intermediate potential and a second intermediate potential that is lower than the first intermediate potential; a differential amplifier that receives the second intermediate potential as a low-potential power supply and amplifies a difference voltage between a feedback potential corresponding to the first intermediate potential and the reference potential; a first transistor having a gate to which the amplified differential voltage is input, a drain to which is connected to a ground potential via a constant current source or a resistor, and a source to which the first intermediate potential is generated; a control circuit to which the first intermediate potential is supplied as a low potential side power supply and which controls a power transistor; A power device comprising:

7. a reference potential generating circuit that generates a reference potential that is an intermediate potential between a power supply potential that is an input voltage and a ground potential; a differential amplifier that uses the power supply potential as a high-potential power supply and amplifies a difference voltage between an output voltage of a regulator and the reference potential; a transistor whose gate is connected to the output of the differential amplifier, whose drain is connected to the ground potential via a constant current source or a resistor, and whose source is the output of the regulator; A regulator comprising:

8. The transistor is a P-channel MOS transistor. The regulator of claim 7.

9. the reference potential is a first reference potential, the reference potential generating circuit further generates a second reference potential that is lower than the first reference potential and higher than a ground potential; The differential amplifier is supplied with the second reference potential as a low-potential power supply. The regulator of claim 7.

10. the constant current source is a first constant current source; The reference potential generating circuit further includes a second constant current source connected between a second reference potential output node that outputs the second reference potential of the reference potential generating circuit and the ground potential. The regulator of claim 9.

11. The regulator the constant current source is a first constant current source; a Zener diode connected between a power supply voltage line to which the power supply potential is supplied and an output of the regulator; a switch and a third constant current source connected in series to the output and the ground potential; and a current flowing through the first constant current source or the resistor is smaller than a current flowing through the third constant current source; The regulator of claim 7.

12. a regulator according to claim 7; a power transistor provided to supply a power supply potential to a load circuit; a control circuit for controlling the power transistor; The control circuit is supplied with a power supply potential and operates using the output voltage of the regulator as a low-potential power supply. Power device.

13. the power device further includes a current detection unit that detects a current flowing through the power transistor; The regulator The constant current source is a first constant current source. a Zener diode connected between the input voltage and the output; a switch and a third constant current source connected in series to the output and a ground potential; and The switch is turned on and off in accordance with the detection result of the current detection unit. The power device of claim 12.

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