Semiconductor device

The semiconductor device design optimizes electrical characteristics by structuring the conductive member with a specific area ratio and resin coverage to enhance current flow and reduce unnecessary material, addressing inefficiencies in conventional devices.

JP2025127046APending Publication Date: 2025-09-01ROHM CO LTD
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Patent Information

Application Number
JP2024023528
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-02-20
Publication Date
2025-09-01

AI Technical Summary

Technical Problem

Conventional semiconductor devices have room for improvement in electrical characteristics, particularly in terms of conductive path efficiency and electrical connectivity between the semiconductor element and the leads.

Method used

A semiconductor device design featuring a first conductive member with a first wiring portion and a first terminal portion, both partially covered by a sealing resin, where the first wiring portion is exposed and overlaps the terminal portion, and a specific area ratio of the wiring portion to the terminal portion is maintained to optimize current flow.

Benefits of technology

Improves electrical characteristics by enhancing the conductive path efficiency and reducing unnecessary material, thereby optimizing current flow and reducing material waste.

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Abstract

To provide a semiconductor device which is suitable for improving electric characteristics.SOLUTION: A semiconductor device includes a first conductive member 1A, a semiconductor element 3 and a sealing resin 4. The first conductive member 1A includes a first wiring part 11 having a first main surface 11a facing a z1 side in a thickness direction z, and a first terminal part 21 which is connected to a z2 side in the thickness direction z with respect to the first wiring part 11. The semiconductor element 3 has a first electrode 31 which is positioned on a side facing the first main surface 11a in the thickness direction z, and is electrically connected to the first main surface 11a. The first wiring part 11 includes a first part 111 overlapping the first terminal part 21 when viewed in the thickness direction z, and a second part 112 which does not overlap the first terminal part 21 when viewed in the thickness direction z. A ratio of a second area which is the sum of the area of the first part 111, and the area of a first area 112A connected to the first part 111 from the part overlapping the first electrode 31 in the second part 112, to the first area of the first wiring part 11 when viewed in the thickness direction z is 60% or less.SELECTED DRAWING: Figure 15
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Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in Patent Document 1 includes leads and a semiconductor element. In the semiconductor device described in Patent Document 1, the semiconductor element is mounted on the leads by flip-chip mounting. The leads have a main surface facing one side in the thickness direction. The semiconductor element has multiple electrodes provided on the side opposite the main surface, and the multiple electrodes are joined to the main surface of the leads via a bonding layer made of, for example, solder. The leads are electrically connected to the internal circuit of the semiconductor element via at least one of the multiple electrodes. In the semiconductor device described in Patent Document 1, current can flow between the semiconductor element and the leads via the electrodes. The leads, for example, form a conductive path between the semiconductor element and a wiring board on which the semiconductor device is mounted. Semiconductor devices with such a configuration have room for improvement in electrical characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-77694

[0004] [overview] The present disclosure has been made in light of the above circumstances, and a main object of the present disclosure is to provide a semiconductor device suitable for improving electrical characteristics.

[0005] The semiconductor device provided by the present disclosure comprises a first conductive member including a first wiring portion having a first main surface facing one side in a thickness direction, and a first terminal portion connected to the other side in the thickness direction with respect to the first wiring portion and having a first back surface facing the other side in the thickness direction; a semiconductor element having at least one first electrode located on a side facing the first main surface in the thickness direction and electrically connected to the first main surface; and a sealing resin that covers at least a portion of the first wiring portion, a portion of the first terminal portion, and the semiconductor element, and has a resin back surface facing the other side in the thickness direction, The first wiring portion is exposed from the back surface, and includes a first portion that overlaps the first terminal portion when viewed in the thickness direction, and a second portion that does not overlap the first terminal portion when viewed in the thickness direction, and the second portion is located between the first main surface and the first back surface in the thickness direction and has a first intermediate surface that faces the other side in the thickness direction, and the first intermediate surface is covered with the sealing resin, and a proportion of a second area, which is the sum of an area of ​​the first portion and an area of ​​a first region that connects from a portion of the second portion that overlaps with the first electrode to the first portion, to a first area, which is the area of ​​the first wiring portion when viewed in the thickness direction, is 60% or less.

[0006] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view (through a sealing resin) showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a plan view (with a semiconductor element and a sealing resin transparent) showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5]FIG. 5 is a front view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a rear view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a right side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a left side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a partially enlarged view of FIG. [Figure 15] FIG. 15 is a partially enlarged view of FIG. [Figure 16] FIG. 16 is a plan view similar to FIG. 3, showing a semiconductor device according to a first modification of the first embodiment. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a partially enlarged view of FIG. [Figure 20] FIG. 20 is a partially enlarged view of FIG. [Figure 21] FIG. 21 is a plan view similar to FIG. 3, showing a semiconductor device according to a second modification of the first embodiment. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. [Figure 24] FIG. 24 is a partially enlarged view of FIG. [Figure 25] FIG. 25 is a partially enlarged view of FIG.

[0008] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0009] In the following, identical or similar components are denoted by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps a part of object B." Furthermore, the phrase "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." Furthermore, in this disclosure, the phrase "a surface A faces direction B (on one side or the other side of direction B)" is not limited to the case where surface A is at an angle of 90° to direction B, but also includes the case where surface A is tilted with respect to direction B.

[0011] First Embodiment A semiconductor device according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 15. The semiconductor device A10 of this embodiment includes a first conductive member 1A, a second conductive member 1B, a pair of third conductive members 1C, a plurality of conductive members 1D, 1E, and 1F, a semiconductor element 3, and a sealing resin 4. The package format of the semiconductor device A10 is a QFN (Quad For Non-Lead Package). However, the package format of the semiconductor device A10 is not limited to a QFN. The specific configuration of the semiconductor element 3 is not particularly limited, and the semiconductor element 3 is, for example, a flip-chip type LSI (Large Scale Integration).

[0012] FIG. 1 is a perspective view of the semiconductor device A10. FIG. 2 is a plan view of the semiconductor device A10, seen through the sealing resin 4. FIG. 3 is a plan view of the semiconductor device A10, seen through the semiconductor element 3 and the sealing resin 4. FIG. 4 is a bottom view of the semiconductor device A10. FIG. 5 is a front view of the semiconductor device A10. FIG. 6 is a rear view of the semiconductor device A10. FIG. 7 is a right side view of the semiconductor device A10. FIG. 8 is a left side view of the semiconductor device A10. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a cross-sectional view taken along line XX in FIG. 3. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 3. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 3. FIG. 14 is a partially enlarged view of FIG. 3. FIG. 15 is a partially enlarged view of FIG. 9. 2, the transmitted sealing resin 4 is indicated by an imaginary line (two-dot chain line). In Fig. 3, the transmitted semiconductor element 3 and sealing resin 4 are each indicated by an imaginary line (two-dot chain line).

[0013] In the description of the semiconductor device A10, the thickness direction (direction in a plan view) of the semiconductor device A10 (first conductive member 1A) is referred to as the "thickness direction z." A direction perpendicular to the thickness direction z is referred to as the "first direction x." A direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y." As shown in FIGS. 1 and 2, the semiconductor device A10 is rectangular when viewed in the thickness direction z. In the description of the semiconductor device A10, one side of the first direction x is referred to as the "x1 side of the first direction x," and the other side of the first direction x is referred to as the "x2 side of the first direction x." Furthermore, one side of the second direction y is referred to as the "y1 side of the second direction y," and the other side of the second direction y is referred to as the "y2 side of the second direction y." Furthermore, one side of the thickness direction z is referred to as the "z1 side of the thickness direction z," and the other side of the thickness direction z is referred to as the "z2 side of the thickness direction z." The z1 side in the thickness direction z is sometimes referred to as the upper side, and the z2 side in the thickness direction z is sometimes referred to as the lower side. Note that the terms "upper," "lower," "upper," "lower," "upper surface," and "lower surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0014] As shown in FIGS. 1 to 3 and 9 to 13, the sealing resin 4 covers the first conductive member 1A, the second conductive member 1B, the pair of third conductive members 1C, portions of each of the plurality of conductive members 1D, 1E, and 1F, and the semiconductor element 3. The sealing resin 4 has electrical insulation properties. An example of a material for the sealing resin 4 is black epoxy resin. When viewed in the thickness direction z, the sealing resin 4 has a rectangular shape.

[0015] As shown in FIGS. 5 to 8 , the sealing resin 4 has a resin main surface 41, a resin back surface 42, a first resin side surface 431, a second resin side surface 432, a third resin side surface 433, and a fourth resin side surface 434. The resin main surface 41 and the resin back surface 42 face opposite each other in the thickness direction z. The resin main surface 41 faces the z1 side in the thickness direction z. The resin back surface 42 faces the z2 side in the thickness direction z. The first resin side surface 431 and the second resin side surface 432 face opposite each other in the first direction x. The first resin side surface 431 faces the x1 side in the first direction x. The second resin side surface 432 faces the x2 side in the first direction x. The third resin side surface 433 and the fourth resin side surface 434 face opposite each other in the second direction y. The third resin side surface 433 faces the y1 side in the second direction y. The fourth resin side surface 434 faces the y2 side in the second direction y.

[0016] As shown in FIGS. 9 to 13, the first conductive member 1A, the second conductive member 1B, the pair of third conductive members 1C, and the plurality of conductive members 1D, 1E, and 1F each carry a semiconductor element 3. These members 1A to 1F, for example, form a conductive path between the semiconductor element 3 and a wiring board on which the semiconductor device A10 is mounted. The constituent material of these members 1A to 1F includes, for example, copper (Cu). These members 1A to 1F are formed, for example, by leads and can be obtained from the same lead frame.

[0017] As shown in FIG. 3, the first conductive member 1A is located at the center of the semiconductor device A10 in the second direction y. As shown in FIGS. 3, 4, and 9, the first conductive member 1A includes a first wiring portion 11 and a first terminal portion 21. The first wiring portion 11 extends in the first direction x as a whole. In this embodiment, the first wiring portion 11 extends from the x1 end of the semiconductor device A10 in the first direction x to the x2 end of the semiconductor device A10 in the first direction x. The first wiring portion 11 has a first main surface 11a and a first intermediate surface 11b. The first main surface 11a faces the z1 side in the thickness direction z. The first main surface 11a faces the semiconductor element 3 and supports the semiconductor element 3. The first intermediate surface 11b is located closer to the z2 side of the first main surface 11a in the thickness direction z. The first intermediate surface 11b faces the opposite side to the first main surface 11a (the z2 side in the thickness direction z). The first main surface 11a and the first intermediate surface 11b are covered with a sealing resin 4. The first main surface 11a that supports the semiconductor element 3 may be plated with, for example, silver (Ag).

[0018] The first terminal portion 21 is connected to the first wiring portion 11 on the z2 side in the thickness direction z. The first terminal portion 21 extends in the first direction x. The first terminal portion 21 extends from the x1 side end of the semiconductor device A10 in the first direction x to the x2 side end of the semiconductor device A10 in the first direction x. The first terminal portion 21 has an elongated rectangular shape with the first direction x as the longitudinal direction when viewed in the thickness direction z. The first terminal portion 21 has a first back surface 21a and a pair of end surfaces 21b. The first back surface 21a faces the side opposite to the first main surface 11a of the first wiring portion 11. The first back surface 21a faces the z2 side in the thickness direction z. The first back surface 21a is exposed from the resin back surface 42 of the sealing resin 4. The pair of end surfaces 21b are located at both ends of the first terminal portion 21 in the first direction x. One end face 21b faces the x1 side in the first direction x and is exposed from a first resin side face 431 of the sealing resin 4. The other end face 21b faces the x2 side in the first direction x and is exposed from a second resin side face 432 of the sealing resin 4. Each of the pair of end faces 21b is connected to the first back surface 21a. The first back surface 21a and the pair of end faces 21b exposed from the sealing resin 4 may be plated with, for example, tin (Sn). Note that instead of tin plating, multiple metal platings may be used, for example, in which nickel (Ni), palladium (Pd), and gold (Au) are layered in this order.

[0019] The first wiring portion 11 overlaps the entire first terminal portion 21 in the thickness direction z. Therefore, the area of ​​the first wiring portion 11 is larger than the area of ​​the first terminal portion 21 in the thickness direction z. In the semiconductor device A10, the first wiring portion 11 includes a first portion 111 and a second portion 112. The first portion 111 is a portion that overlaps with the first terminal portion 21 in the thickness direction z. The second portion 112 is a portion that does not overlap with the first terminal portion 21 in the thickness direction z. The first terminal portion 21 is connected to the z2 side of the first portion 111 in the thickness direction z. The second portion 112, which does not overlap with the first terminal portion 21 in the thickness direction z, has a first intermediate surface 11b. The first intermediate surface 11b is located between the first main surface 11a and the first back surface 21a in the thickness direction z. Details of the first wiring portion 11 will be described later.

[0020] As shown in FIG. 3, the second conductive member 1B is located on the y2 side in the second direction y of the semiconductor device A10. The second conductive member 1B is located away from the first conductive member 1A on the y2 side in the second direction y and is adjacent to the first conductive member 1A. As shown in FIGS. 3, 4, 9, 11, and 12, the second conductive member 1B includes a second wiring portion 12 and a second terminal portion 22. The second wiring portion 12 has a portion extending in the first direction x and a portion extending in the second direction y, and is substantially T-shaped when viewed in the thickness direction z. In this embodiment, the portion of the second wiring portion 12 extending in the first direction x extends from the x1 side end in the first direction x to the x2 side end in the first direction x of the semiconductor device A10. The portion of the second wiring portion 12 extending in the second direction y extends from the middle of the portion extending in the first direction x to the y2 end of the semiconductor device A10 in the second direction y. The second wiring portion 12 has a second main surface 12a and a second intermediate surface 12b. The second main surface 12a faces the z1 side in the thickness direction z. The second main surface 12a faces the semiconductor element 3 and supports the semiconductor element 3. The second intermediate surface 12b is located on the z2 side of the second main surface 12a in the thickness direction z. The second intermediate surface 12b faces the opposite side to the second main surface 12a (the z2 side in the thickness direction z). The second main surface 12a and the second intermediate surface 12b are covered with a sealing resin 4. The second main surface 12a supporting the semiconductor element 3 may be plated with silver, for example.

[0021] The second terminal portion 22 is connected to the second wiring portion 12 on the z2 side in the thickness direction z. The second terminal portion 22 extends in the second direction y. The second terminal portion 22 extends from the middle of the semiconductor device A10 in the first direction x to the y2 end in the second direction y. The second terminal portion 22 has an elongated rectangular shape with the second direction y as the longitudinal direction when viewed in the thickness direction z. The second terminal portion 22 has a second back surface 22a and an end surface 22b. The second back surface 22a faces the side opposite to the second main surface 12a of the second wiring portion 12. The second back surface 22a faces the z2 side in the thickness direction z. The second back surface 22a is exposed from the resin back surface 42 of the sealing resin 4. The end surface 22b faces the y2 side in the second direction y. The end surface 22b is connected to the second back surface 22a and is exposed from the fourth resin side surface 434 of the sealing resin 4. For example, tin plating may be applied to second rear surface 22a and end surface 22b exposed from sealing resin 4. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold laminated in this order, may be used.

[0022] When viewed in the thickness direction z, the second wiring portion 12 overlaps the entire second terminal portion 22. The second wiring portion 12 has a protruding portion 121. The protruding portion 121 protrudes from the center in the first direction x of a portion of the second wiring portion 12 extending in the first direction x toward the y1 side in the second direction y.

[0023] As shown in FIG. 3, the pair of third conductive members 1C are located on the y2 side of the semiconductor device A10 in the second direction y. The pair of third conductive members 1C are spaced apart from each other in the first direction x. The pair of third conductive members 1C are located on both sides of the second conductive member 1B (second terminal portion 22) in the first direction x. One third conductive member 1C is located on the x1 side in the first direction x, and the other third conductive member 1C is located on the x2 side in the first direction x. As shown in FIGS. 3, 4, and 12, the third conductive member 1C includes a third wiring portion 13 and a third terminal portion 23. The third wiring portion 13 has a portion extending in the first direction x and a portion extending in the second direction y, and is substantially L-shaped when viewed in the thickness direction z. The third wiring portion 13 has a third main surface 13a and a third intermediate surface 13b. The third main surface 13a faces the z1 side in the thickness direction z. The third main surface 13a faces the semiconductor element 3 and supports the semiconductor element 3. The third intermediate surface 13b is located on the z2 side of the third main surface 13a in the thickness direction z. The third intermediate surface 13b faces the opposite side to the third main surface 13a (the z2 side in the thickness direction z). The third main surface 13a and the third intermediate surface 13b are covered with a sealing resin 4. The third main surface 13a that supports the semiconductor element 3 may be plated with silver, for example.

[0024] The third terminal portion 23 is connected to the third wiring portion 13 on the z2 side in the thickness direction z. The third terminal portion 23 has a portion extending in the first direction x and a portion located on the y2 side in the second direction y, and the two portions are separated from each other. The third wiring portion 13 overlaps the entire third terminal portion 23 when viewed in the thickness direction z. The third terminal portion 23 has a third back surface 23a and end surfaces 23b and 23c. The third back surface 23a faces the side opposite to the third main surface 13a of the third wiring portion 13. The third back surface 23a faces the z2 side in the thickness direction z. The third back surface 23a is exposed from the resin back surface 42 of the sealing resin 4. The end surface 23b faces either the x1 side in the first direction x or the x2 side in the first direction x. The end face 23b is connected to the third back surface 23a and is exposed from the first resin side surface 431 or the second resin side surface 432 of the sealing resin 4. The end face 23c faces the y2 side in the second direction y. The end face 23c is connected to the third back surface 23a and is exposed from the fourth resin side surface 434 of the sealing resin 4. The third back surface 23a and the end faces 23b, 23c exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold stacked in this order, may be used.

[0025] As shown in FIG. 3, the plurality of conductive members 1D are located on the y2 side of the semiconductor device A10 in the second direction y. In the illustrated example, a pair of conductive members 1D are located apart from each other in the first direction x. The pair of conductive members 1D are located on both sides of a pair of third conductive members 1C in the first direction x. One conductive member 1D is located on the x1 side in the first direction x and near a corner on the y2 side in the second direction y, while the other conductive member 1D is located on the x2 side in the first direction x and near a corner on the y2 side in the second direction y. As shown in FIGS. 3 and 4, the conductive member 1D includes a wiring portion 14 and a terminal portion 24. The wiring portion 14 has a main surface 14a. The main surface 14a faces the z1 side in the thickness direction z. The main surface 14a faces the semiconductor element 3 and supports the semiconductor element 3. The main surface 14a is covered with a sealing resin 4. The main surface 14a supporting the semiconductor element 3 may be plated with silver, for example.

[0026] The terminal portion 24 is connected to the wiring portion 14 on the z2 side in the thickness direction z. The wiring portion 14 overlaps the entire terminal portion 24 when viewed in the thickness direction z. The terminal portion 24 has a back surface 24a and end surfaces 24b and 24c. The back surface 24a faces the opposite side to the main surface 14a of the wiring portion 14. The back surface 24a faces the z2 side in the thickness direction z. The back surface 24a is exposed from the resin back surface 42 of the sealing resin 4. The end surface 24b faces either the x1 side in the first direction x or the x2 side in the first direction x. The end surface 24b is connected to the back surface 24a and is exposed from the first resin side surface 431 or the second resin side surface 432 of the sealing resin 4. The end surface 24c faces the y2 side in the second direction y. The end surface 24c is connected to the back surface 24a and is exposed from the fourth resin side surface 434 of the sealing resin 4. For example, tin plating may be applied to the back surface 24a and the end faces 24b, 24c exposed from the sealing resin 4. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold laminated in this order, may be used.

[0027] As shown in FIG. 3, the multiple conductive members 1E are located on the y1 side of the semiconductor device A10 in the second direction y. The multiple conductive members 1E are arranged at intervals in the first direction x. As shown in FIGS. 3, 4, and 9, the conductive member 1E includes a wiring portion 15 and a terminal portion 25. The wiring portion 15 has a main surface 15a and an intermediate surface 15b. The main surface 15a faces the z1 side in the thickness direction z. The main surface 15a faces the semiconductor element 3 and supports the semiconductor element 3. The intermediate surface 15b is located on the z2 side of the main surface 15a in the thickness direction z. The intermediate surface 15b faces the opposite side to the main surface 15a (the z2 side in the thickness direction z). The main surface 15a and the intermediate surface 15b are covered with a sealing resin 4. The main surface 15a supporting the semiconductor element 3 may be silver-plated, for example.

[0028] The terminal portion 25 is connected to the wiring portion 15 on the z2 side in the thickness direction z. The wiring portion 15 overlaps the entire terminal portion 25 when viewed in the thickness direction z. The terminal portion 25 has a back surface 25a and an end surface 25b. The back surface 25a faces the opposite side to the main surface 15a of the wiring portion 15. The back surface 25a faces the z2 side in the thickness direction z. The back surface 25a is exposed from the resin back surface 42 of the sealing resin 4. The end surface 25b faces the y1 side in the second direction y. The end surface 25b is connected to the back surface 24a and is exposed from the third resin side surface 433 of the sealing resin 4. The back surface 25a and the end surface 25b exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold layered in this order, may be used.

[0029] As shown in FIG. 3, the multiple conductive members 1F are located on the y1 side of the first conductive member 1A in the second direction y. The multiple conductive members 1F are located between the first conductive member 1A and the multiple conductive members 1E in the second direction y. Some of the multiple conductive members 1F are located on the x1 side of the semiconductor device A10 in the first direction x. The remaining multiple conductive members 1F are located on the x2 side of the semiconductor device A10 in the first direction x. As shown in FIGS. 3, 4, and 13, the conductive member 1F includes a wiring portion 16 and a terminal portion 26. The wiring portion 16 has a main surface 16a and an intermediate surface 16b. The main surface 16a faces the z1 side in the thickness direction z. The main surface 16a faces the semiconductor element 3 and supports the semiconductor element 3. The intermediate surface 16b is located on the z2 side of the main surface 16a in the thickness direction z. The intermediate surface 16b faces the opposite side to the main surface 16a (the z2 side in the thickness direction z). The main surface 16a and the intermediate surface 16b are covered with a sealing resin 4. The main surface 16a that supports the semiconductor element 3 may be plated with silver, for example.

[0030] The terminal portion 26 is connected to the wiring portion 16 on the z2 side in the thickness direction z. The wiring portion 16 overlaps the entire terminal portion 26 when viewed in the thickness direction z. The terminal portion 26 has a back surface 26a and an end surface 26b. The back surface 26a faces the opposite side to the main surface 16a of the wiring portion 16. The back surface 26a faces the z2 side in the thickness direction z. The back surface 26a is exposed from the resin back surface 42 of the sealing resin 4. The end surface 26b faces either the x1 side in the first direction x or the x2 side in the first direction x. The end surface 26b is connected to the back surface 24a and is exposed from the first resin side surface 431 or the second resin side surface 432 of the sealing resin 4. The back surface 26a and the end surface 26b exposed from the sealing resin 4 may be plated with tin, for example. Note that instead of tin plating, multiple metal platings, for example, nickel, palladium, and gold stacked in this order, may be used.

[0031] As shown in FIGS. 3 and 9 to 13, the semiconductor element 3 is mounted on a first conductive member 1A, a second conductive member 1B, a pair of third conductive members 1C, and a plurality of conductive members 1D, 1E, and 1F. The semiconductor element 3 has an element body 30, a plurality of first electrodes 31, a plurality of electrodes 32, and a plurality of electrodes 33. Although detailed illustrations are omitted, the element body 30 includes, for example, a semiconductor layer having an internal circuit, and the internal circuit has a switching circuit and a control circuit that is connected to the switching circuit. The switching circuit is formed, for example, by an n-channel MOSFET, and the control circuit controls the switching circuit to operate normally.

[0032] As shown in FIGS. 9 to 13, the first electrodes 31, the electrodes 32, and the electrodes 33 are located on the side facing the first main surface 11a, the second main surface 12a, the third main surface 13a, and the main surfaces 14a to 16a in the thickness direction z. The first electrodes 31, the electrodes 32, and the electrodes 33 are provided below the element body 30 (on the z2 side in the thickness direction z). Each of the first electrodes 31 is electrically connected to the first wiring portion 11 (first main surface 11a) of the first conductive member 1A via a bonding layer 39. This establishes electrical continuity between the element body 30 (semiconductor element 3) and the first conductive member 1A. Each of the electrodes 32 is electrically connected to either the second wiring portion 12 (second main surface 12a) of the second conductive member 1B or the third wiring portion 13 (third main surface 13a) of each third conductive member 1C via the bonding layer 39. As a result, the element body 30 (semiconductor element 3) is electrically connected to the second conductive member 1B and the pair of third conductive members 1C. Each of the multiple electrodes 33 is electrically connected via a bonding layer 39 to one of the wiring portion 14 (main surface 14a) of each conductive member 1D, the wiring portion 15 (main surface 15a) of each conductive member 1E, and the wiring portion 16 (main surface 16a) of each conductive member 1F. As a result, the element body 30 (semiconductor element 3) is electrically connected to each of the multiple conductive members 1D, 1E, and 1F. The bonding layer 39 is conductive. In the example of the semiconductor device A10, the bonding layer 39 is a metal containing, for example, tin and silver, and is solder.

[0033] Each of the first conductive member 1A, the second conductive member 1B, and the pair of third conductive members 1C is electrically connected to a switching circuit of the semiconductor element 3 (element body 30). Each of the first conductive member 1A, the second conductive member 1B, and the pair of third conductive members 1C constitutes a path for a main circuit current that is switched by, for example, the semiconductor element 3 (the switching circuit). Each of the plurality of conductive members 1D, 1E, and 1F receives, for example, power (voltage) for driving the control circuit or an electrical signal for transmission to the control circuit.

[0034] The first wiring portion 11 will be described with reference to FIGS.

[0035] As described above, the first wiring portion 11 includes the first portion 111 and the second portion 112. The first portion 111 is a portion that overlaps with the first terminal portion 21 when viewed in the thickness direction z, and the second portion 112 is a portion that does not overlap with the first terminal portion 21 when viewed in the thickness direction z. The first portion 111 and the first terminal portion 21 extend in the first direction x.

[0036] In this embodiment, the second portion 112 includes a first extending portion 113 and a second extending portion 114. The first extending portion 113 extends from the first portion 111 to the y1 side in the second direction y. The second extending portion 114 extends from the first portion 111 to the y2 side in the second direction y. The length of the first extending portion 113 in the second direction y on the x1 side in the first direction x and the x2 side in the first direction x is shorter than the length of the first extending portion 113 in the second direction y at the center in the first direction x. This is to avoid interference with the conductive member 1F (wiring portion 16) adjacent to the first wiring portion 11 on the y1 side in the second direction y (see FIG. 3).

[0037] In this embodiment, the multiple first electrodes 31 are arranged along the first direction x. The multiple first electrodes 31 overlap with the first portion 111 when viewed in the thickness direction z. More specifically, when viewed in the thickness direction z, a portion of each of the multiple first electrodes 31 overlaps with the first portion 111, and the remaining portion of each of the multiple first electrodes 31 overlaps with the first extension portion 113 (second portion 112).

[0038] When viewed in the thickness direction z, the region of the first extension portion 113 (second portion 112) that extends from a portion overlapping with the plurality of first electrodes 31 to the first portion 111 is defined as the first region 112A. The first region 112A is a combination of a region in which the plurality of first electrodes 31 are arranged and whose longitudinal direction is the first direction x, and a region that connects both ends of the region in the first direction x to the furthest position on the boundary between the first extension portion 113 (second portion 112) and the first portion 111.

[0039] The first extending portion 113 has a first inner portion 113A and a first outer portion 113B. The first inner portion 113A is connected to the first portion 111 and is a portion that constitutes the first region 112A. The first outer portion 113B is connected to the first inner portion 113A and is a portion that is located on the y1 side in the second direction y relative to the first inner portion 113A.

[0040] 14 and 15, a first dimension L1, which is the length in the second direction y of the first outer portion 113B, is greater than a second dimension L2, which is the length in the second direction y of the first terminal portion 21. For example, the first dimension L1 is 1.5 to 2.5 times the second dimension L2.

[0041] The second extending portion 114 has a recess 114a. The recess 114a is located at the center of the second extending portion 114 in the first direction x and is recessed further toward the y1 side in the second direction y than other portions. The recess 114a is provided to correspond to the protruding portion 121 of the second wiring portion 12 of the second conductive member 1B. The recess 114a overlaps the entire protruding portion 121 when viewed in the second direction y.

[0042] Of the first wiring portion 11 of the first conductive member 1A, the portion necessary as a path for current flow between the semiconductor element 3 and the first terminal portion 21 (hereinafter referred to as the "necessary portion" as appropriate) is the first portion 111 that overlaps the first terminal portion 21 as viewed in the thickness direction z, and the first region 112A. In FIG. 14, the entire first wiring portion 11 is hatched downward to the right. Furthermore, the portions of the first wiring portion 11 that are necessary for the current path (the first portion 111 and the first region 112A) are hatched upward to the right. Note that in the example shown in FIG. 14, as viewed in the thickness direction z, the edge of the first region 112A on the y1 side in the second direction y corresponds to a line segment that connects, along the first direction x, the ends on the y1 side in the second direction y of each of the plurality of first electrodes 31 arranged in the first direction x.

[0043] When viewed in the thickness direction z, the ratio of the second area S2 (the sum of the area of ​​the first portion 111 and the area of ​​the first region 112A), which is the area of ​​the necessary portion of the current path (the first portion 111 and the first region 112A), to the first area S1, which is the area of ​​the entire first wiring portion 11, is, for example, 60% or less. The ratio of the second area S2 to the first area S1 is preferably 20% or more and 50% or less. In the present embodiment shown in FIG. 14, the ratio of the second area S2 to the first area S1 is 42.2%.

[0044] In this embodiment, the portion of the first wiring portion 11 that is unnecessary as a path for current to flow between the semiconductor element 3 and the first terminal portion 21 (hereinafter referred to as the "unnecessary portion" as appropriate) is other than the necessary portion (first portion 111 and first region 112A). Specifically, the unnecessary portion is the portion of the first extension portion 113 other than the first region 112A (first inner portion 113A) (mainly the first outer portion 113B), and the second extension portion 114. The area ratio of the unnecessary portion of the current path in the first wiring portion 11 is 40% or more, and preferably 50% or more and 80% or less.

[0045] Next, the operation of this embodiment will be described.

[0046] The semiconductor device A10 includes a first conductive member 1A, a semiconductor element 3, and a sealing resin 4. The first conductive member 1A includes a first wiring portion 11 and a first terminal portion 21 connected to the first wiring portion 11 on the z2 side in the thickness direction z. The first wiring portion 11 has a first main surface 11a facing the z1 side in the thickness direction z, and the first terminal portion 21 has a first back surface 21a facing the z2 side in the thickness direction z. The first back surface 21a is exposed from a resin back surface 42 of the sealing resin 4. The semiconductor element 3 has a plurality of first electrodes 31 located on a side opposite to the first main surface 11a in the thickness direction z, and the plurality of first electrodes 31 are electrically connected to the first main surface 11a. The first wiring portion 11 includes a first portion 111 overlapping the first terminal portion 21 in the thickness direction z and a second portion 112 not overlapping the first terminal portion 21 in the thickness direction z. When viewed in the thickness direction z, the ratio of the second area S2 (the sum of the area of ​​the first portion 111 and the area of ​​the first region 112A), which is the area of ​​the necessary portion of the current path, to the first area S1, which is the area of ​​the first wiring portion 11, is 60% or less. With this configuration, the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11 is 40% or more. By increasing the unnecessary portion of the current path in the first wiring portion 11 in this way, it is possible to reduce the impedance between the semiconductor element 3 and the first terminal portion 21, for example, and improve the electrical characteristics of the semiconductor device A10.

[0047] The ratio of the area of ​​the necessary portion of the current path (second area S2) to the area of ​​the first wiring portion 11 (first area S1) is 20% or more and 50% or less. In this case, the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11 is 50% or more and 80% or less. This configuration prevents the ratio of the unnecessary portion in the first wiring portion 11 from becoming excessively large, which is preferable in terms of miniaturizing the semiconductor device A10.

[0048] The first extension portion 113 has a first inner portion 113A and a first outer portion 113B. The first inner portion 113A is connected to the first portion 111 and constitutes the first region 112A. The first outer portion 113B is connected to the first inner portion 113A and is located on the y1 side of the first inner portion 113A in the second direction y. A first dimension L1, which is the length of the first outer portion 113B in the second direction y, is greater than a second dimension L2, which is the length of the first terminal portion 21 in the second direction y. This configuration efficiently reduces the ratio of the area of ​​the necessary portion of the current path (second area S2) to the area of ​​the first wiring portion 11 (first area S1). In other words, it efficiently increases the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11. Therefore, this structure is suitable for improving the electrical characteristics of the semiconductor device A10.

[0049] The first dimension L1, which is the length in the second direction y of the first outer portion 113B, is 1.5 to 2.5 times the second dimension L2, which is the length in the second direction y of the first terminal portion 21. With this configuration in which the length in the second direction y (first dimension L1) of the first extending portion 113 is increased in this manner, in addition to the effect of improving the electrical characteristics of the semiconductor device A10, the effect of preventing the sealing resin 4 from peeling off from the first conductive member 1A is enhanced.

[0050] 16 to 25 show modified examples of the semiconductor device of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as those in the above embodiment, and redundant explanations will be omitted. Furthermore, the configurations of the various parts in each of the modified examples and each of the embodiments can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0051] <First Modification of First Embodiment> 16 to 20 show a semiconductor device A11 according to a first modified example of the first embodiment. FIG. 16 is a plan view similar to FIG. 3, showing the semiconductor device A11. For ease of understanding, FIG. 16 shows the semiconductor element 3 and the sealing resin 4 in a transparent manner. In the figure, the transparent semiconductor element 3 and the sealing resin 4 are respectively indicated by imaginary lines (two-dot chain lines). FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 16. FIG. 19 is a partially enlarged view of FIG. 16. FIG. 20 is a partially enlarged view of FIG. 17.

[0052] The semiconductor device A11 of this modification differs from the semiconductor device A10 of the above embodiment in the arrangement of the multiple first electrodes 31. Accordingly, the configuration of the first extension portion 113 differs from the above embodiment. In the semiconductor device A11, the multiple first electrodes 31 are arranged along the first direction x, as in the above embodiment. On the other hand, in this modification, all of the multiple first electrodes 31 overlap with the first portion 111 when viewed in the thickness direction z. Therefore, none of the multiple first electrodes 31 overlaps with the first extension portion 113 (second portion 112) when viewed in the thickness direction z. As a result, the first extension portion 113 (second portion 112) does not have a first region 112A. Furthermore, the first extension portion 113 does not have a distinction between a first inner portion 113A and a first outer portion 113B as in the above embodiment.

[0053] 19 and 20, the dimension L3, which is the length in the second direction y of the first extending portion 113, is greater than the second dimension L2, which is the length in the second direction y of the first terminal portion 21. For example, the dimension L3 is two to three times the second dimension L2.

[0054] Of the first wiring portion 11 of the first conductive member 1A, the portion necessary for the current path between the semiconductor element 3 and the first terminal portion 21 is the first portion 111 that overlaps the first terminal portion 21 when viewed in the thickness direction z. In Fig. 19, the entire first wiring portion 11 is hatched downward to the right. Furthermore, the portion of the first wiring portion 11 necessary for the current path (first portion 111) is hatched upward to the right.

[0055] When viewed in the thickness direction z, the ratio of the second area S2 (area of ​​the first portion 111), which is the area of ​​the necessary portion of the current path (first portion 111), to the first area S1, which is the area of ​​the entire first wiring portion 11, is, for example, 60% or less. The ratio of the second area S2 to the first area S1 is preferably 20% or more and 50% or less. In this modification shown in FIG. 19, the ratio of the second area S2 to the first area S1 is 34.6%.

[0056] In this modification, the unnecessary portion of the current path between the semiconductor element 3 and the first terminal portion 21 in the first wiring portion 11 is other than the necessary portion (first portion 111). Specifically, the unnecessary portion is the second portion 112 (first extension portion 113 and second extension portion 114). The area ratio of the unnecessary portion of the current path in the first wiring portion 11 is 40% or more, and preferably 50% or more and 80% or less.

[0057] In the semiconductor device A11 of this modification, the first wiring portion 11 of the first conductive member 1A includes a first portion 111 that overlaps the first terminal portion 21 in the thickness direction z and a second portion 112 that does not overlap the first terminal portion 21 in the thickness direction z. As viewed in the thickness direction z, the ratio of the second area S2 (the area of ​​the first portion 111), which is the area of ​​the necessary portion of the current path, to the first area S1, which is the area of ​​the first wiring portion 11, is 60% or less. With this configuration, the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11 is 40% or more. By increasing the unnecessary portion of the current path in the first wiring portion 11 in this way, it is possible to reduce the impedance between the semiconductor element 3 and the first terminal portion 21, for example, and improve the electrical characteristics of the semiconductor device A11.

[0058] The ratio of the area of ​​the necessary portion of the current path (second area S2) to the area of ​​the first wiring portion 11 (first area S1) is 20% or more and 50% or less. In this case, the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11 is 50% or more and 80% or less. With this configuration, the ratio of the unnecessary portion in the first wiring portion 11 is prevented from becoming excessively large, which is preferable in terms of miniaturizing the semiconductor device A11.

[0059] The dimension L3, which is the length of the first extension portion 113 in the second direction y, is larger than the second dimension L2, which is the length of the first terminal portion 21 in the second direction y. With this configuration, it is possible to efficiently reduce the ratio of the area of ​​the necessary portion of the current path (second area S2) to the area of ​​the first wiring portion 11 (first area S1). In other words, it is possible to efficiently increase the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11. Therefore, this structure is suitable for improving the electrical characteristics of the semiconductor device A11.

[0060] The dimension L3, which is the length in the second direction y of the first extending portion 113, is between two and three times the second dimension L2, which is the length in the second direction y of the first terminal portion 21. With this configuration in which the length in the second direction y (dimension L3) of the first extending portion 113 is increased in this way, in addition to the effect of improving the electrical characteristics of the semiconductor device A11, the effect of preventing the sealing resin 4 from peeling off from the first conductive member 1A is enhanced.

[0061] <Second Modification of First Embodiment> 21 to 25 show a semiconductor device A12 according to a second modified example of the first embodiment. FIG. 21 is a plan view similar to FIG. 3, showing the semiconductor device A12. For ease of understanding, FIG. 21 shows the semiconductor element 3 and the sealing resin 4 in a transparent manner. In the figure, the transparent semiconductor element 3 and the sealing resin 4 are respectively shown by imaginary lines (two-dot chain lines). FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 21. FIG. 24 is a partially enlarged view of FIG. 21. FIG. 25 is a partially enlarged view of FIG. 22.

[0062] The semiconductor device A12 of this modification differs from the semiconductor device A10 of the above embodiment in the arrangement of the multiple first electrodes 31. In the semiconductor device A12, the multiple first electrodes 31 are arranged along the first direction x, as in the above embodiment. On the other hand, in this modification, all of the multiple first electrodes 31 overlap with the first extension portion 113 (second portion 112) when viewed in the thickness direction z. Furthermore, in this modification, the number of first electrodes 31 arranged along the first direction x is smaller than in the semiconductor device A10, and the distance between adjacent first electrodes 31 in the first direction x is larger than in the semiconductor device A10.

[0063] In this modification, similarly to the semiconductor device A10, the region from the portion of the first extension portion 113 (second portion 112) that overlaps with the plurality of first electrodes 31 to the first portion 111 when viewed in the thickness direction z is defined as the first region 112A. The first region 112A is a combination of a region in which the plurality of first electrodes 31 are arranged and whose longitudinal direction is the first direction x, and a region that connects each end of the region in the first direction x to the farthest position on the boundary between the first extension portion 113 (second portion 112) and the first portion 111.

[0064] In this modification, similar to the semiconductor device A10, the first extending portion 113 has a first inner portion 113A and a first outer portion 113B. The first inner portion 113A is connected to the first portion 111 and is a portion that constitutes the first region 112A. The first outer portion 113B is connected to the first inner portion 113A and is a portion that is located on the y1 side in the second direction y relative to the first inner portion 113A.

[0065] 24 and 25, a first dimension L1, which is the length in the second direction y of the first outer portion 113B, is greater than a second dimension L2, which is the length in the second direction y of the first terminal portion 21. For example, the first dimension L1 is 1.5 to 2.5 times the second dimension L2.

[0066] Of the first wiring portion 11 of the first conductive member 1A, the portion necessary for the current path between the semiconductor element 3 and the first terminal portion 21 is the first portion 111 overlapping the first terminal portion 21 as viewed in the thickness direction z, and the first region 112A. In FIG. 24, the entire first wiring portion 11 is hatched downward to the right. Furthermore, the portion of the first wiring portion 11 necessary for the current path (the first portion 111 and the first region 112A) is hatched upward to the right. Note that in the example shown in FIG. 24, as viewed in the thickness direction z, the edge of the first region 112A on the y1 side in the second direction y corresponds to a line segment connecting, along the first direction x, the ends on the y1 side in the second direction y of each of the plurality of first electrodes 31 arranged in the first direction x.

[0067] When viewed in the thickness direction z, the ratio of the second area S2 (the sum of the area of ​​the first portion 111 and the area of ​​the first region 112A), which is the area of ​​the necessary portion of the current path (the first portion 111 and the first region 112A), to the first area S1, which is the area of ​​the entire first wiring portion 11, is, for example, 60% or less. The ratio of the second area S2 to the first area S1 is preferably 20% or more and 50% or less. In this modification shown in FIG. 24, the ratio of the second area S2 to the first area S1 is 49.6%.

[0068] In this modification, the unnecessary portion of the current path between the semiconductor element 3 and the first terminal portion 21 in the first wiring portion 11 is other than the necessary portion (first portion 111 and first region 112A). Specifically, the unnecessary portion is the portion of the first extension portion 113 other than the first region 112A (first inner portion 113A) (mainly the first outer portion 113B), and the second extension portion 114. The area ratio of the unnecessary portion of the current path in the first wiring portion 11 is 40% or more, and preferably 50% or more and 80% or less.

[0069] In the semiconductor device A12 of this modification, the first wiring portion 11 of the first conductive member 1A includes a first portion 111 that overlaps the first terminal portion 21 in the thickness direction z and a second portion 112 that does not overlap the first terminal portion 21 in the thickness direction z. As viewed in the thickness direction z, the ratio of the second area S2 (the sum of the area of ​​the first portion 111 and the area of ​​the first region 112A), which is the area of ​​the necessary portion of the current path, to the first area S1, which is the area of ​​the first wiring portion 11, is 60% or less. With this configuration, the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11 is 40% or more. By increasing the unnecessary portion of the current path in the first wiring portion 11 in this way, it is possible to reduce the impedance between the semiconductor element 3 and the first terminal portion 21, for example, and improve the electrical characteristics of the semiconductor device A12.

[0070] The ratio of the area of ​​the necessary portion of the current path (second area S2) to the area of ​​the first wiring portion 11 (first area S1) is 20% or more and 50% or less. In this case, the ratio of the area of ​​the unnecessary portion of the current path in the first wiring portion 11 is 50% or more and 80% or less. With this configuration, the ratio of the unnecessary portion in the first wiring portion 11 is prevented from becoming excessively large, which is preferable in terms of miniaturizing the semiconductor device A12. In addition, the semiconductor device A12 has the same effects as the semiconductor device A10 of the above embodiment.

[0071] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0072] In the above embodiment, the first conductive member 1A, the second conductive member 1B, the pair of third conductive members 1C, and the plurality of conductive members 1D, 1E, and 1F are configured by leads, but the present disclosure is not limited to this. The first conductive member 1A, the second conductive member 1B, the pair of third conductive members 1C, and the plurality of conductive members 1D, 1E, and 1F may be configured by, for example, metal plating of a desired shape.

[0073] The present disclosure includes configurations related to the following notes. [Appendix 1] a first conductive member including a first wiring portion having a first main surface facing one side in a thickness direction, and a first terminal portion connected to the other side in the thickness direction of the first wiring portion and having a first back surface facing the other side in the thickness direction; a semiconductor element having at least one first electrode located on a side facing the first main surface in the thickness direction and electrically connected to the first main surface; a sealing resin that covers at least a portion of the first wiring portion, a portion of the first terminal portion, and the semiconductor element and has a resin back surface facing the other side in the thickness direction, the first rear surface is exposed from the resin rear surface, the first wiring portion includes a first portion that overlaps the first terminal portion when viewed in the thickness direction and a second portion that does not overlap the first terminal portion when viewed in the thickness direction; the second portion has a first intermediate surface located between the first main surface and the first back surface in the thickness direction and facing the other side in the thickness direction; the first intermediate surface is covered with the sealing resin, A semiconductor device in which, when viewed in the thickness direction, the ratio of a second area, which is the sum of the area of ​​the first part and the area of ​​a first region that connects from the portion of the second part that overlaps with the first electrode to a first area, which is the area of ​​the first wiring part, to a first area is 60% or less. [Appendix 2] 2. The semiconductor device according to claim 1, wherein a ratio of the second area to the first area is not less than 20% and not more than 50%. [Appendix 3] 3. The semiconductor device according to claim 1, wherein the first portion and the first terminal portion extend in a first direction perpendicular to the thickness direction. [Appendix 4] 4. The semiconductor device according to claim 3, wherein the semiconductor element has a plurality of the first electrodes arranged along the first direction. [Appendix 5] 5. The semiconductor device according to claim 4, wherein at least a portion of each of the plurality of first electrodes overlaps with the first portion when viewed in the thickness direction. [Appendix 6] 6. The semiconductor device according to claim 4, wherein the second portion has a first extension portion extending from the first portion to one side in a second direction perpendicular to the thickness direction and the first direction. [Appendix 7] 7. The semiconductor device according to claim 6, wherein at least one of the plurality of first electrodes overlaps both the first portion and the first extension portion when viewed in the thickness direction. [Appendix 8] the first extension portion has a first inner portion connected to the first portion and constituting at least a part of the first region, and a first outer portion connected to the first inner portion and located on one side of the first inner portion in the second direction, The semiconductor device according to claim 6 or 7, wherein a first dimension, which is the length in the second direction of the first outer portion, is greater than a second dimension, which is the length in the second direction of the first terminal portion. [Appendix 9] 9. The semiconductor device according to claim 8, wherein the first dimension is 1.5 to 2.5 times the second dimension. [Appendix 10] 10. The semiconductor device according to any one of claims 6 to 9, wherein the second portion has a second extension portion extending from the first portion to the other side in the second direction. [Appendix 11] a second conductive member including a second wiring portion having a second main surface facing one side in the thickness direction, and a second terminal portion connected to the other side in the thickness direction of the second wiring portion and having a second back surface facing the other side in the thickness direction, 11. The semiconductor device according to claim 10, wherein the second conductive member is located away from the first conductive member on the other side in the second direction. [Appendix 12] the second wiring portion has a protruding portion protruding to one side in the second direction, 12. The semiconductor device according to claim 11, wherein the second extension portion overlaps the entire protrusion portion when viewed in the second direction and has a recess that is recessed to one side in the second direction. [Appendix 13] 13. The semiconductor device according to any one of claims 1 to 12, wherein the first conductive member is made of a material containing copper. [Appendix 14] 14. The semiconductor device according to claim 13, wherein the first conductive member is a lead. [Explanation of symbols]

[0074] A10, A11, A12: Semiconductor device 1A: First conductive member 1B: Second conductive member 1C: Third conductive member 1D, 1E, 1F: Conductive material 11: 1st wiring section 11a: 1st main surface 11b: 1st intermediate plane 111: Part 1 112: Part 2 112A: 1st area 113: 1st extension part 113A: 1st inner part 113B: First outer part 114:Second extension part 114a: recess 12:Second wiring section 12a: Second main surface 12b: 2nd intermediate plane 121:Protrusion 13:Third wiring section 13a: Third principal surface 13b: 3rd intermediate plane 14,15,16: Wiring section 14a, 15a, 16a: Main surface 15b,16b: Intermediate surface 21: 1st terminal section 21a: 1st back side 22: 2nd terminal section 22a: Second back side 23:Third terminal section 23a: Third reverse side 24,25,26:Terminal section 24a, 25a, 26a: Back side 21b, 22b, 23b, 23c, 24b, 24c, 25b, 26b: End surface 3: Semiconductor elements 30: Element body 31: 1st electrode 32,33: Electrode 39: Bonding layer 4: Sealing resin 41: Resin main surface 42: Resin back 431: First resin side 432: Second resin side 433: Third resin side 434: 4th resin side L1: First dimension L2: Second dimension L3: Dimensions S1: 1st area S2: 2nd area x :1st direction y: second direction z: thickness direction

Claims

1. a first conductive member including a first wiring portion having a first main surface facing one side in a thickness direction, and a first terminal portion connected to the other side in the thickness direction with respect to the first wiring portion and having a first back surface facing the other side in the thickness direction; a semiconductor element having at least one first electrode located on a side facing the first main surface in the thickness direction and electrically connected to the first main surface; a sealing resin that covers at least a portion of the first wiring portion, a portion of the first terminal portion, and the semiconductor element and has a resin back surface facing the other side in the thickness direction, the first rear surface is exposed from the resin rear surface, the first wiring portion includes a first portion that overlaps with the first terminal portion when viewed in the thickness direction, and a second portion that does not overlap with the first terminal portion when viewed in the thickness direction; the second portion has a first intermediate surface located between the first main surface and the first back surface in the thickness direction and facing the other side in the thickness direction; the first intermediate surface is covered with the sealing resin, A semiconductor device, wherein, when viewed in the thickness direction, the ratio of a second area, which is the sum of the area of ​​the first part and the area of ​​a first region that connects from a portion of the second part that overlaps with the first electrode to a first area, which is the area of ​​the first wiring part, to a first area is 60% or less.

2. The semiconductor device according to claim 1 , wherein a ratio of said second area to said first area is equal to or greater than 20% and equal to or less than 50%.

3. The semiconductor device according to claim 1 , wherein the first portion and the first terminal portion extend in a first direction perpendicular to the thickness direction.

4. The semiconductor device according to claim 3 , wherein the semiconductor element has a plurality of the first electrodes arranged along the first direction.

5. The semiconductor device according to claim 4 , wherein at least a portion of each of the plurality of first electrodes overlaps with the first portion when viewed in the thickness direction.

6. 6. The semiconductor device according to claim 4, wherein the second portion has a first extending portion extending from the first portion to one side in a second direction perpendicular to the thickness direction and the first direction.

7. The semiconductor device according to claim 6 , wherein at least one of the plurality of first electrodes overlaps both the first portion and the first extension portion when viewed in the thickness direction.

8. the first extension portion has a first inner portion connected to the first portion and constituting at least a part of the first region, and a first outer portion connected to the first inner portion and located on one side of the first inner portion in the second direction, 8. The semiconductor device according to claim 7, wherein a first dimension that is a length in the second direction of said first outer portion is greater than a second dimension that is a length in the second direction of said first terminal portion.

9. 9. The semiconductor device according to claim 8, wherein the first dimension is 1.5 times or more and 2.5 times or less than the second dimension.

10. The semiconductor device according to claim 6 , wherein the second portion has a second extending portion extending from the first portion to the other side in the second direction.

11. a second conductive member including a second wiring portion having a second main surface facing one side in the thickness direction, and a second terminal portion connected to the other side in the thickness direction of the second wiring portion and having a second back surface facing the other side in the thickness direction, The semiconductor device according to claim 10 , wherein the second conductive member is located away from the first conductive member on the other side in the second direction.

12. the second wiring portion has a protruding portion protruding to one side in the second direction, The semiconductor device according to claim 11 , wherein the second extending portion overlaps the entire protruding portion when viewed in the second direction and has a recessed portion recessed to one side in the second direction.

13. 6. The semiconductor device according to claim 1, wherein the first conductive member is made of a material containing copper.

14. The semiconductor device according to claim 13 , wherein the first conductive member is a lead.

Citation Information

Patent Citations

  • Semiconductor device

    JP2020077694A