Bootstrap circuit and non-volatile memory device

Abstract

To improve accuracy of a bootstrap voltage generated by a bootstrap circuit.SOLUTION: A bootstrap circuit (3) includes a flying capacitor (FC) and an adjusting circuit (ADJ). The flying capacitor is charged according to a voltage difference between a first voltage and a second voltage if the first voltage and the second voltage are at a first level. When the first voltage and the second voltage are at the first level, the first voltage becomes a first reference value and the second voltage becomes a second reference value. When the first voltage and the second voltage are at a second level, the first voltage becomes the second reference value and the second voltage becomes a value based on the second reference value and a value of charged voltage of the flying capacitor. One of the first level or the second level is a low level and the other of the first level and the second level is a high level. The adjusting circuit adjusts the second reference value according to the second voltage at the second level.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a bootstrap circuit and a non-volatile memory device. [Background technology]

[0002] BACKGROUND ART A bootstrap circuit that generates a bootstrap voltage is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-133916

[0004] [overview] The bootstrap voltage has a value according to the voltage division of a capacitive voltage divider circuit formed by a flying capacitor and a parasitic capacitance connected to a line to which the bootstrap voltage is applied.

[0005] Therefore, ideally, the flying capacitor should be much larger than the parasitic capacitance. However, if the area of ​​the line to which the bootstrap voltage is applied becomes large and the parasitic capacitance increases, the flying capacitor must be large to achieve a large value, resulting in a significant deviation from the ideal and a deterioration in the accuracy of the bootstrap voltage.

[0006] A bootstrap circuit according to the present disclosure includes a flying capacitor and an adjustment circuit. The flying capacitor is configured to be charged according to a voltage difference between a first voltage and a second voltage when the first voltage and the second voltage are at a first level. When the first voltage and the second voltage are at the first level, the first voltage is a first reference value, and the second voltage is a second reference value. When the first voltage and the second voltage are at a second level, the first voltage is the second reference value, and the second voltage is a value based on the second reference value and a value of a charging voltage of the flying capacitor. One of the first level and the second level is a low level, and the other of the first level and the second level is a high level. The adjustment circuit is configured to adjust the second reference value according to the second voltage when the flying capacitor is at the second level.

[0007] The nonvolatile memory device according to the present disclosure includes the bootstrap circuit configured as described above. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a nonvolatile memory device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing the gate-source voltage dependence of the drain current of a data element. [Figure 3] FIG. 3 is a diagram showing an example of voltage application to a memory element during a program operation. [Figure 4] FIG. 4 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 5] FIG. 5 is a diagram showing an example of voltage application to a memory element during a read operation. [Figure 6] FIG. 6 is a cross-sectional view of the vertical structure of the memory element corresponding to FIG. [Figure 7] FIG. 7 is an external perspective view of a nonvolatile memory device according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a bootstrap circuit. [Figure 9] FIG. 9 is a timing chart showing waveforms of the bootstrap voltage and the drive voltage.

[0009] [Detailed explanation] 1 is a diagram showing the configuration of a nonvolatile memory device according to an embodiment of the present disclosure. The nonvolatile memory device 1 according to an embodiment of the present disclosure (hereinafter referred to as nonvolatile memory device 1) includes a first data element Md1, a second data element Md2, a charge pump circuit 2, a bootstrap circuit 3, a voltage application unit 4, a switch SW1, and a sense amplifier SA.

[0010] The combination of the first data element Md1 and the second data element Md2 stores data "0" or "1".

[0011] The first data element Md1 and the second data element Md2 are both configured as memory elements, and more specifically, are configured by NMOS transistors (N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors)). Memory elements are elements that can perform program operations by changing the characteristics of the transistor through hot carrier injection, and are also called OTP (One Time Programmable) elements. Note that the data elements Md1 and Md2 may be elements other than NMOS transistors as long as they are elements that can perform program operations.

[0012] Here, with respect to transistors, the concept of "structure" includes the size of the transistor. Therefore, for any plurality of transistors, "the same structure" means that the sizes of the plurality of transistors are also the same. When certain transistors have the same structure, if hot carrier injection into the plurality of transistors by a program operation has not been performed on the plurality of transistors, the electrical characteristics (including gate threshold voltage, etc.) of the plurality of transistors will also be the same. However, "the same structure and electrical characteristics of any plurality of transistors" means that they are the same in terms of design, and may actually include errors (i.e., "same" is understood to be a concept that includes errors).

[0013] The nonvolatile memory device 100 can perform a read operation for reading out data stored in the data elements Md1 and Md2, and a program operation (write operation) for rewriting the data (logical values) stored in the data elements Md1 and Md2.

[0014] During the program operation, hot carriers are injected into the data elements Md1 and Md2, changing their electrical characteristics. This change causes the gate threshold voltages of the data elements Md1 and Md2 to rise. In Figure 2, the solid waveform INI represents the gate-source voltage dependence of the drain currents of the data elements Md1 and Md2 before the program operation, and the dotted waveform PRG represents the gate-source voltage dependence of the drain currents of the data elements Md1 and Md2 after the program operation. In this way, the program operation causes the gate threshold voltage Vth to rise.

[0015] Fig. 3 is a diagram showing voltage application to a memory element MT (NMOS transistor) during a program operation. Fig. 4 is a cross-sectional view of the vertical structure of the memory element MT corresponding to Fig. 3. The memory element MT is used for the above-mentioned data elements Md1 and Md2 (Fig. 1).

[0016] As shown in FIGS. 3 and 4, during a program operation, a high voltage Vpp is applied to the gate G of the memory element MT, a high voltage Vpp is applied to the source S, and a ground potential Vss (=0V) is applied to the drain D.

[0017] Such voltage application generates hot carriers (electrons) that flow from the drain D to the source S directly below the gate G, as indicated by the arrows in Fig. 4. The hot carriers are attracted to the high voltage Vpp (positive voltage) applied to the gate G and trapped in the sidewall SSw on the source S side that is provided along the side of the gate G (trapped hot carriers E are shown in Fig. 4).

[0018] Fig. 5 is a diagram showing voltage application to memory elements MT1 and MT2 (NMOS transistors) during a read operation. Fig. 6 is a cross-sectional view of the vertical structure of memory elements MT1 and MT2 corresponding to Fig. 5. Memory elements MT1 and MT2 correspond to the above-mentioned data elements Md1 and Md2 (Fig. 1).

[0019] As shown in Figures 5 and 6, during a read operation, gate voltages Vg1 and Vg2 are applied to the gates G of memory elements MT1 and MT2, drain voltages Vd1 and Vd2 are applied to the drains D, and a ground potential Vs (=0V) is applied to the sources.

[0020] 5 and 6 show, as an example, a case where the memory device MT1 is in a state before a program operation is executed (unprogrammed state) and the memory device MT2 is in a state after a program operation is executed. That is, the memory device MT2 corresponds to the memory device MT shown in FIGS. 3 and 4.

[0021] 6, in the memory element MT2 after the program operation has been performed, hot carriers E are trapped in the sidewall SSw, so the electric field due to the gate voltage Vg2 does not reach directly below the sidewall SSw, and the channel CN2 is cut off on the side of the source S. Therefore, the gate threshold voltage becomes high, and it is difficult for the drain current to flow.

[0022] On the other hand, as shown in FIG. 6, the memory element MT1 in which the program operation is not executed is in the ON state, and a drain current flows.

[0023] The charge pump circuit 2 is driven during a program operation and is stopped during a read operation. The charge pump circuit 2 applies a voltage VP to the gates of the data elements Md1 and Md2. The voltage VP is higher than the power supply voltage VDD.

[0024] The bootstrap circuit 3 is stopped during a program operation and is driven during a read operation. The bootstrap circuit 3 applies a voltage BST to the gates of the data elements Md1 and Md2.

[0025] During a programming operation, the voltage application unit 4 applies a power supply voltage VDD between the source and drain of each of the data elements Md1 and Md2. The power supply voltage VDD is, for example, +5V. The voltage application unit 4 includes switches SW2 to SW4. The switch SW2 is provided between the drain of the second data element Md2 and a terminal to which ground potential is applied. The switch SW3 is provided between the drain of the first data element Md1 and a terminal to which ground potential is applied. The switch SW4 is provided between the sources of each of the data elements Md1 and Md2 and a terminal to which the power supply voltage VDD is applied. During a programming operation, only the switch SW2 or SW3 corresponding to the data element to be programmed is turned on, and SW4 is turned on. As a result, of the data elements Md1 or Md2 to be programmed, a high voltage VP is applied to the gate, the power supply voltage VDD is applied to the source, and the ground potential is applied to the drain.

[0026] The switch SW1 is turned off during a program operation and turned on during a read operation.

[0027] The sense amplifier SA reads out data based on the magnitude relationship between the drain currents flowing through the data elements Md1 and Md2.

[0028] The nonvolatile memory device 1 is a semiconductor integrated circuit device. FIG. 7 is an external perspective view of the nonvolatile memory device 1. The nonvolatile memory device 1 is an electronic component formed by encapsulating a semiconductor integrated circuit chip in a housing (package) made of resin. A plurality of external terminals are exposed on the housing of the nonvolatile memory device 1. Note that the number of external terminals of the nonvolatile memory device 1 and the external appearance of the nonvolatile memory device 1 shown in FIG. 7 are merely examples.

[0029] 8 is a diagram showing an example of the configuration of the bootstrap circuit 3. The bootstrap circuit 3 includes a regulator including an operational amplifier OP1, a reference voltage source VS1, and an output capacitor C1.

[0030] A reference voltage REF output from the positive terminal of a reference voltage source VS1 is supplied to the non-inverting input terminal of an operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to a first terminal of an output capacitor C1. A ground potential GND is applied to the negative terminal of the reference voltage source VS1 and a second terminal of the output capacitor C1. An internal power supply voltage VREG is output from the regulator. In the bootstrap circuit 3, the value of the ground potential GND is a first reference value, and the value of the internal power supply voltage VREG is a second reference value.

[0031] The bootstrap circuit 3 further includes buffers BUF1 to BUF3, inverters INV1 to INV2, PMOS transistors (P-channel MOSFETs) Q1 and Q2, an NMOS transistor Q3, and a flying capacitor FC.

[0032] A power supply voltage VDD is applied to the positive power supply terminals of buffers BUF1, BUF3, and inverter INV1. A bootstrap voltage BST (described later) is applied to the positive power supply terminal of buffer BUF2. An internal power supply voltage VREG is applied to the positive power supply terminal of inverter INV2. A ground potential GND is applied to the negative power supply terminals of buffers BUF1 to BUF3 and inverters INV1 to INV2.

[0033] A clock signal CLK is supplied to the input terminal of inverter INV1. The output terminal of inverter INV1 is connected to the input terminals of buffers BUF1 and BUF3. The output terminal of buffer BUF1 is connected to the input terminal of buffer BUF2. The output terminal of buffer BUF2 is connected to the gate of PMOS transistor Q1. The output terminal of buffer BUF3 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is connected to the gates of PMOS transistor Q2 and NMOS transistor Q3.

[0034] A first end of the flying capacitor FC is connected to the source and back gate of the PMOS transistor Q1. A parasitic capacitance PC is also connected to the line to which the first end of the flying capacitor FC is connected. A second end of the flying capacitor FC is connected to the drains of the PMOS transistor Q2 and the NMOS transistor Q3.

[0035] The internal power supply voltage VREG is applied to the drain of the PMOS transistor Q1 and the source of the PMOS transistor Q2. The power supply voltage VDD is applied to the back gate of the PMOS transistor Q2. The ground potential GND is applied to the source and back gate of the NMOS transistor Q3.

[0036] The voltage at the first end of the flying capacitor FC is referred to as a bootstrap voltage BST, and the voltage at the second end of the flying capacitor FC is referred to as a drive voltage DRV.

[0037] FIG. 9 is a timing chart showing the waveforms of the bootstrap voltage BST and the drive voltage DRV.

[0038] When the clock signal CLK is at a high level, the PMOS transistor Q1 is turned on, the NMOS transistor Q2 is turned off, and the PMOS transistor Q3 is turned on, thereby charging the flying capacitor FC. At this time, the drive voltage DRV and the bootstrap voltage BST are at a low level. When the drive voltage DRV is at a low level, it has a first reference value (the value of the ground potential GND). When the bootstrap voltage BST is at a low level, it has a second reference value (the value of the internal power supply voltage VREG).

[0039] When the clock signal CLK is at a low level, the PMOS transistor Q1 is turned on, the NMOS transistor Q2 is turned off, and the PMOS transistor Q3 is turned on, causing the bootstrap voltage BST and the drive voltage DRV to rise to a high level. When the drive voltage DRV is at a high level, it has a second reference value (the value of the internal power supply voltage VREG). When the bootstrap voltage BST is at a high level, it has a value based on the second reference value (the value of the internal power supply voltage VREG) and the value of the charging voltage of the flying capacitor FC.

[0040] When the parasitic capacitance PC can be considered to be zero, the bootstrap voltage BST at a high level is equal to the sum of the second reference value (the value of the internal power supply voltage VREG) and the charging voltage of the flying capacitor FC. However, if the adjustment circuit ADJ (described later) is not operated, the larger the parasitic capacitance PC, the more the bootstrap voltage BST at a high level drops from the sum of the second reference value (the value of the internal power supply voltage VREG) and the charging voltage of the flying capacitor FC. This problem becomes more pronounced when the flying capacitor FC is built into the semiconductor integrated circuit device, as in this embodiment, and the flying capacitor FC cannot be made larger.

[0041] 8, the bootstrap circuit 3 further includes an adjustment circuit ADJ. The adjustment circuit ADJ includes resistors R1 and R2, a sample-and-hold switch SHSW, a sample-and-hold capacitor SHC, and a precharge circuit PRE.

[0042] The adjustment circuit ADJ adjusts the second reference value (the value of the internal power supply voltage VREG) according to the bootstrap voltage BST when it is at a high level. This adjustment prevents the value of the bootstrap voltage BST when it is at a high level from decreasing, thereby improving the accuracy of the bootstrap voltage BST.

[0043] More specifically, in the adjustment circuit ADJ, resistors R1 and R2 generate a divided voltage of the bootstrap voltage BST, and a sample-and-hold circuit formed by the sample-and-hold switch SHSW and the sample-and-hold capacitor SHC samples and holds the divided voltage of the bootstrap voltage BST when the voltage is at a high level. The second reference value (the value of the internal power supply voltage VREG) is adjusted according to the output of the sample-and-hold circuit. The output of the sample-and-hold circuit is supplied to the inverting input terminal of the operational amplifier OP1. The sample-and-hold switch SHSW is controlled so that the timing at which the sample-and-hold switch SHSW is turned on is determined, for example, based on the falling edge of the clock signal CLK. Therefore, the bootstrap circuit 3 includes a logic circuit (not shown) that generates a control signal for the sample-and-hold switch SHSW based on, for example, the clock signal CLK.

[0044] Unlike the present embodiment, the sample-and-hold circuit may sample and hold the bootstrap voltage BST itself. In this case, for example, the output of the sample-and-hold circuit may be divided and used as the output of the adjustment circuit ADJ.

[0045] The precharge circuit PRE precharges the sample-and-hold capacitor SHC when the bootstrap circuit 3 is started up. The precharge circuit PRE precharges the sample-and-hold capacitor SHC to a voltage higher than the feedback voltage corresponding to the target value of the second reference value (the value of the internal power supply voltage VREG). In the configuration example shown in FIG. 8, the value of the feedback voltage corresponding to the target value of the second reference value (the value of the internal power supply voltage VREG) matches the value of the reference voltage REF.

[0046] By precharging the sample-and-hold capacitor SHC to a voltage higher than the feedback voltage corresponding to the target value of the second reference value (the value of the internal power supply voltage VREG), the second reference value (the value of the internal power supply voltage VREG) is gradually adjusted (over multiple times) and converges, thereby suppressing oscillation of the internal power supply voltage VREG.

[0047] The time constant of the operational amplifier OP1 is set to be sufficiently slow compared to the sampling period of the sample-and-hold circuit formed by the sample-and-hold switch SHSW and the sample-and-hold capacitor SHC. This setting also makes it possible to suppress oscillation of the internal power supply voltage VREG.

[0048] The adjustment circuit ADJ adjusts the second reference value (the value of the internal power supply voltage VREG) in accordance with the bootstrap voltage BST at a timing (timing TM2 in FIG. 9) when a predetermined period has elapsed since the bootstrap voltage BST started to switch from low to high (timing TM1 in FIG. 9). The period is set to be longer than the time required from the start of the bootstrap voltage BST switching from low to high to the completion of boosting the bootstrap voltage BST, which is determined by simulation, experiment, etc.

[0049] By adjusting the timing described above, the second reference value (the value of the internal power supply voltage VREG) is adjusted according to the bootstrap voltage BST after the boost is completed, rather than during the boost process, thereby further improving the accuracy of the bootstrap voltage BST.

[0050] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0051] For example, in the above embodiment, the bootstrap circuit is configured to generate a bootstrap voltage that is boosted to the positive side. However, the bootstrap circuit may be configured to generate a bootstrap voltage that is inverted and boosted, i.e., a bootstrap voltage that is boosted to the negative side.

[0052] When the bootstrap circuit is configured to generate an inverted boosted bootstrap voltage, the first level is a high level and the other of the second levels is a low level. Also, when the bootstrap circuit is configured to generate an inverted boosted bootstrap voltage, it is preferable that the precharge circuit be configured to precharge the sample-and-hold capacitor to a voltage lower than the feedback voltage corresponding to the target value of the second reference value.

[0053] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0054] A bootstrap circuit (3) of the present disclosure includes a flying capacitor (PC) and an adjustment circuit (ADJ), and is configured to be charged according to a voltage difference between a first voltage (DRV) and a second voltage (BST) when the first voltage and the second voltage are at a first level, and when the first voltage and the second voltage are at the first level, the first voltage becomes a first reference value (GND) and the second voltage becomes a second reference value (VREG), and when the first voltage and the second voltage are at a second level, the first voltage becomes the second reference value and the second voltage becomes a value based on the second reference value and a value of a charging voltage of the flying capacitor, one of the first level and the second level is a low level and the other of the first level and the second level is a high level, and the adjustment circuit is configured to adjust the second reference value according to the second voltage when the second voltage is at the second level (first configuration).

[0055] According to the bootstrap circuit of the first configuration, the adjustment circuit can adjust the second reference value, and therefore, even if the flying capacitor cannot be made larger when the area of ​​the line to which the second voltage (bootstrap voltage) is applied becomes large and the parasitic capacitance becomes large, the accuracy of the second voltage (bootstrap voltage) can be improved.

[0056] In the bootstrap circuit of the first configuration, the adjustment circuit may be configured (second configuration) to include a sample-and-hold circuit (SHSW, SHC) configured to sample and hold a voltage based on the second voltage, and to adjust the second reference value in accordance with an output of the sample-and-hold circuit.

[0057] In the bootstrap circuit of the second configuration, the sample and hold circuit may include a sample and hold capacitor (SHC), and the adjustment circuit may include a precharge circuit (PRE) configured to precharge the sample and hold capacitor (Third configuration).

[0058] In the bootstrap circuit of the third configuration, the first level may be a low level, and the precharge circuit may be configured to precharge the sample and hold capacitor to a voltage higher than a feedback voltage corresponding to a target value of the second reference value (fourth configuration).

[0059] In the bootstrap circuit of the third configuration, the first level may be a high level, and the precharge circuit may be configured to precharge the sample and hold capacitor to a voltage lower than a feedback voltage corresponding to a target value of the second reference value (fifth configuration).

[0060] In the bootstrap circuits of the first to fifth configurations, the adjustment circuit may be configured to adjust the second reference value in accordance with the second voltage at a timing when a predetermined period has elapsed since the second voltage started to switch from the first level to the second level (sixth configuration).

[0061] The nonvolatile memory device (1) according to the present disclosure has a configuration (seventh configuration) including a bootstrap circuit having any one of the first to sixth configurations.

[0062] The nonvolatile memory device of the seventh configuration may be configured as a semiconductor integrated circuit device (eighth configuration). [Explanation of symbols]

[0063] 1 Nonvolatile memory device according to an embodiment of the present disclosure 2. Charge pump circuit 3 Bootstrap Circuit 4. Voltage application section ADJ adjustment circuit BUF1~BUF3 buffers C1 Output capacitor FC Flying Capacitor INV1, INV2 inverters Md1 First data element Md2 Second data element OP1 operational amplifier PC parasitic capacitance PRE Precharge circuit Q1, Q2 PMOS transistors Q3 NMOS transistor R1, R2 resistance VS1 Reference voltage source SA Sense Amplifier SW1 to SW4 switches SHC Sample and Hold Capacitor SHSW Sample and hold switch

Claims

1. A flying capacitor and an adjustment circuit are provided, the flying capacitor is configured to be charged according to a voltage difference between the first voltage and the second voltage when the first voltage and the second voltage are at a first level; When the first voltage and the second voltage are at the first level, the first voltage is a first reference value and the second voltage is a second reference value; when the first voltage and the second voltage are at a second level, the first voltage is the second reference value, and the second voltage is a value based on the second reference value and a value of the charging voltage of the flying capacitor; one of the first level and the second level is a low level, and the other of the first level and the second level is a high level; The adjustment circuit is configured to adjust the second reference value in response to the second voltage when at the second level.

2. 2. The bootstrap circuit of claim 1, wherein the adjustment circuit includes a sample-and-hold circuit configured to sample and hold a voltage based on the second voltage, and is configured to adjust the second reference value in response to an output of the sample-and-hold circuit.

3. the sample-and-hold circuit includes a sample-and-hold capacitor; 3. The bootstrap circuit of claim 2, wherein the adjustment circuit comprises a precharge circuit configured to precharge the sample and hold capacitor.

4. the first level is a low level, 4. The bootstrap circuit of claim 3, wherein the precharge circuit is configured to precharge the sample and hold capacitor to a voltage higher than a feedback voltage corresponding to a target value of the second reference value.

5. the first level is a high level, 4. The bootstrap circuit of claim 3, wherein the precharge circuit is configured to precharge the sample and hold capacitor to a voltage lower than a feedback voltage corresponding to a target value of the second reference value.

6. 2. The bootstrap circuit according to claim 1, wherein the adjustment circuit is configured to adjust the second reference value in accordance with the second voltage at a timing when a predetermined period has elapsed since the second voltage started to switch from the first level to the second level.

7. A non-volatile memory device comprising a bootstrap circuit according to any one of claims 1 to 6.

8. 8. The nonvolatile memory device according to claim 7, which is a semiconductor integrated circuit device.

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