Semiconductor memory device

Abstract

To suppress bending and distortion of a laminated structure.SOLUTION: A semiconductor memory device 1 according to an embodiment includes: a first stacked body LM in which a plurality of conductive layers WL are stacked so as to be separated from each other; a plate-like part LI that extends in the first stacked body LM in the stacking direction of the first stacked body LM and a first direction intersecting the stacking direction and divides the first stacked body LM in a second direction intersecting the stacking direction and the first direction; and a pillar PL that extends in the first stacked body LM in the stacking direction and in which memory cells MC are formed at intersections with at least a part of the plurality of conductive layers WL. A first layer OLc including at least one of Si-C bonds and Si-Si bonds and a first insulating layer OLx including Si-O bonds and covering upper and lower surfaces of the first layer OLc in the stacking direction and an end surface of the first layer OLc facing the side wall of the plate-like part LI are disposed between the plurality of conductive layers WL. The first layer OLc includes more Si-C bonds or Si-Si bonds than the first insulating layer OLx, and the first insulating layer OLx includes more Si-O bonds than the first layer OLc.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] When manufacturing a semiconductor memory device such as a three-dimensional nonvolatile memory, a process may be included in which multiple sacrificial layers and multiple insulating layers are alternately stacked one by one, and multiple conductive layers are formed in the gaps between the insulating layers after removing the sacrificial layers. However, after removing the sacrificial layers, the remaining insulating layers may bend or the entire structure may become distorted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2017 / 077134 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device that can suppress warping and distortion of a stacked structure. [Means for solving the problem]

[0005] a first insulating layer that includes Si-O bonds and / or Si-C bonds and covers upper and lower surfaces of the first layer in the stacking direction and an end surface of the first layer facing a sidewall of the plate-shaped portion of the first layer; a first stacked body in which a plurality of conductive layers are stacked and spaced apart from one another; a plate-shaped portion that extends within the first stacked body in a stacking direction of the first stacked body and a first direction intersecting the stacking direction and divides the first stacked body in a second direction intersecting the stacking direction and the first direction; and a pillar that extends within the first stacked body in the stacking direction and has a memory cell formed at each intersection with at least a portion of the plurality of conductive layers. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to a first embodiment. [Figure 2] 1 is a cross-sectional view taken along the Y direction showing an example of the configuration of a semiconductor memory device according to a first embodiment. [Figure 3] FIG. 2 is a schematic diagram illustrating a stacked body included in the semiconductor memory device according to the first embodiment. [Figure 4] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 6] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 7] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 8] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 9]2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 2A to 2C are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] FIG. 10 is a diagram showing an example of the schematic configuration of a semiconductor memory device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] [Embodiment 1] Hereinafter, the first embodiment will be described in detail with reference to the drawings.

[0009] (Configuration example of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to embodiment 1. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0010] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0011] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0012] As shown in FIG. 1(a), the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0013] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical conduction is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A stacked body LM is disposed on the source line SL, in which a select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order.

[0014] 1(a) and 1(b), a memory region MR is arranged in the center of the laminate LM in the X direction, and staircase regions SR are arranged at both ends of the laminate LM in the X direction. The memory region MR and staircase region SR are divided into multiple regions by multiple plate-like contacts LI that penetrate the laminate LM and extend in the X direction.

[0015] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as a unit for erasing this data.

[0016] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0017] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction thereof. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0018] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0019] In this specification, the direction in which the terrace surfaces of the plurality of word lines WL and select gate lines SGD and SGS face is defined as the upper side of the semiconductor memory device 1.

[0020] The above-mentioned isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0021] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0022] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0023] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0024] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0025] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0026] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around the stacked body LM. A peripheral region PR is arranged around the stacked body LM so as to surround the stacked body LM, and a kerf region KR is arranged further outside the peripheral region PR so as to surround the stacked body LM and the peripheral region PR.

[0027] The kerf region KR corresponds to a dicing line used when cutting out and singulating the individual semiconductor memory devices 1. The kerf region KR may include alignment marks and laminated bodies LMs (not shown). As will be described later, the laminated bodies LMs are portions that are cut off from the laminated body LM during the manufacturing process of the semiconductor memory device 1, and have a structure in which multiple insulating layers NL are stacked in place of the word lines WL and the like.

[0028] The semiconductor substrate SB above the insulating layer 50 covering the laminate LM is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0029] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor memory device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0030] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view taken along the Y direction showing an example of the configuration of the semiconductor memory device 1 according to the first embodiment.

[0031] More specifically, Figure 2(a) is a cross-sectional view of the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53, which will be described later, is omitted.

[0032] Fig. 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS. Fig. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL. Fig. 2(d) is an enlarged cross-sectional view of a plate-like contact LI at the height of the word line WL or the select gate lines SGD and SGS.

[0033] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers. Of these, at least the intermediate source line BSL may be, for example, a conductive polysilicon layer into which impurities are diffused.

[0034] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA within the insulating layer 50 outside the laminated body LM.

[0035] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0036] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0037] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer containing a carbon-doped silicon oxide layer as a core material. The detailed layer structure of the insulating layer OL will be described later.

[0038] The upper surface of the laminated body LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53 each constitute a part of the insulating layer 50 in FIG.

[0039] As described above, the multilayer body LM is divided in the Y direction by the plurality of plate-shaped contacts LI. That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the multilayer body LM.

[0040] In this way, the plate-shaped contact LI extends continuously within the laminate LM from one end to the other end in the X direction of the laminate LM. The plate-shaped contact LI also penetrates the laminate LM and the upper source line DSLb to reach the intermediate source line BSL.

[0041] The plate-shaped contact LI has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0042] Each of the plate-shaped contacts LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0043] The insulating layer 54 covers side walls of the plate-shaped contacts LI facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the intermediate source lines BSL. However, instead of the plate-shaped contacts LI, a plate-shaped member filled with an insulating layer may penetrate the laminated body LM and extend in the X direction, thereby dividing the laminated body LM in the Y direction.

[0044] Furthermore, a plurality of isolation layers SHE are disposed between the plate contacts LI adjacent in the Y direction, extending in the X direction and penetrating the upper layer portion of the stacked body LMb. These isolation layers SHE are insulating layers 56 such as silicon oxide layers that penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0045] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped contacts LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0046] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0047] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0048] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0049] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0050] 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0051] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillar PL together with the outermost memory layer ME. However, a portion of the channel layer CN is exposed to the outermost periphery of the pillar PL at the depth of the intermediate source line BSL, and its side surface is in contact with the intermediate source line BSL, thereby electrically connecting to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0052] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0053] 2(a), plugs CH are connected only to three of the six pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 2(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a) via plugs CH not shown in Fig. 2(a).

[0054] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0055] As shown in Figure 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0056] 2(b), select gates STD are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGD0 and SGD1 above the word lines WL, and select gates STS are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGS0 and SGS1 below the word lines WL.

[0057] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0058] Hereinafter, the detailed structure of each layer of the laminate LM of the semiconductor memory device 1 of the first embodiment will be further described with reference to FIGS. 2(b) to 2(d).

[0059] As shown in Figures 2(b) to 2(d), in each of the multiple word lines WL and select gate lines SGD, SGS included in the laminate LM, a barrier metal layer BM and a metal element-containing layer MO are arranged in this order on the upper and lower surfaces in the stacking direction.

[0060] The barrier metal layer BM includes at least one of a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, and a molybdenum nitride layer. This prevents metal atoms, such as tungsten or molybdenum, constituting the word lines WL from diffusing into adjacent layers. The metal-element-containing layer MO is, for example, an aluminum oxide (Al2O3) layer, and functions as a block insulating layer in the memory cells MC.

[0061] 2(b) and 2(c), the end faces of the word lines WL, etc., facing the side walls of the pillars PL are also covered with the barrier metal layer BM and the metal-element-containing layer MO in this order. On the other hand, as shown in FIG. 2(d), the end faces of the word lines WL, etc., facing the side walls of the plate contacts LI are not covered with the barrier metal layer BM and the metal-element-containing layer MO, but are in direct contact with the side walls of the plate contacts LI.

[0062] The barrier metal layer BM covering the end faces of the word lines WL and select gate lines SGD, SGS facing the side walls of the plate contacts LI, as well as their upper and lower surfaces, is slightly recessed in a direction away from the plate contact LI from the end faces of the insulating layer OL adjacent to them in the stacking direction. Accordingly, the insulating layer 54 covering the side walls of the plate contacts LI protrudes toward the recessed end faces of the word lines WL, etc. In other words, the insulating layer 54 on the side walls of the plate contacts LI protrudes to both sides in the Y direction at the height of each word line WL and select gate line SGD, SGS.

[0063] As shown in Figures 2(b) to 2(d), each of the insulating layers OL included in the laminate LM includes a core layer OLc and insulating layers OLx that sandwich the core layer OLc from above and below in the stacking direction. The core layer OLc is, for example, a carbon-doped silicon oxide layer, i.e., a silicon carbonate layer. The insulating layer OLx is, for example, a silicon oxide layer, and is formed by oxidizing the surface of the core layer OLc, as described below.

[0064] Here, the core layer OLc, which is a carbon-doped silicon oxide layer or the like, and the insulating layer OLx formed by oxidizing the core layer OLc may both contain Si-C bonds and Si-O bonds. However, due to the oxidation of the core layer OLc, the Si-C bonds in the insulating layer OLx are broken or replaced with Si-O bonds. Therefore, the core layer OLc contains more Si-C bonds than the insulating layer OLx, and the insulating layer OLx contains more Si-O bonds than the core layer OLc.

[0065] The contents of Si-C bonds and Si-O bonds in the core layer OLc and the insulating layer OLx can be measured, for example, by TEM-EELS, which is a combination of transmission electron microscopy (TEM) and electron energy-loss spectroscopy (EELS).

[0066] It is preferable that the insulating layer OLx is oxidized to such an extent that a spectrum due to Si—C bonds is not detected in the TEM-EESL measurement.

[0067] Furthermore, the carbon content of the core layer OLc is preferably 1 atomic % or more. This allows the Young's modulus of the core layer OLc to be, for example, 100 GPa or more, which is higher than that of the insulating layer OLx. The carbon content in the core layer OLc can be measured, for example, by Auger Electron Spectroscopy (AES).

[0068] As shown in FIG. 2(d), the end face of the core layer OLc facing the side wall of the plate-shaped contact LI is covered with an insulating layer OLx. The insulating layer OLx covering the end face of the core layer OLc is further covered with the metal-element-containing layer MO. That is, the metal-element-containing layer MO extends along the interface between the insulating layer OL and the barrier metal layer BM covering the word line WL, and continuously extends to the interface between the side wall of the plate-shaped contact LI and the end face of the insulating layer OL. As a result, the core layer OLc of the insulating layer OL faces the side wall of the plate-shaped contact LI via the insulating layer OLx and the metal-element-containing layer MO.

[0069] On the other hand, as shown in Figures 2(b) and 2(c), the end face of the core layer OLc facing the side wall of the pillar PL is not covered by the insulating layer OLx or the metal element-containing layer MO, etc., but is in direct contact with the side wall of the pillar PL.

[0070] In each insulating layer OL, the insulating layer OLx has a substantially uniform thickness on both the top and bottom surfaces of the core layer OLc and on the end surface of the core layer OLc facing the sidewall of the plate contact LI. That is, the thickness in the stacking direction of the insulating layer OLx on the top surface of the core layer OLc, the thickness in the stacking direction of the insulating layer OLx on the bottom surface of the core layer OLc, and the thickness in the Y direction of the insulating layer OLx covering the end surface of the core layer OLc facing the sidewall of the plate contact LI are all substantially equal. It is preferable that the thickness of these insulating layers OLx be equal to or greater than the thickness of the core layer OLc.

[0071] In this specification, when the layer thickness of a specified layer is said to be substantially uniform or equal, it means at least one of the following: that the layer thickness of the specified layer is set to be uniform or equal by design, and that the layer thickness of the specified layer is uniform or equal within the range of an allowable manufacturing error.

[0072] The core layer OLc has a high Young's modulus but a lower breakdown voltage than the insulating layer OLx. The insulating layer OLx contains more Si-O bonds than the core layer OLc and is formed to a thickness equal to or greater than that of the core layer OLc, thereby increasing the breakdown voltage of the insulating layer OL as a whole and suppressing leakage current between layers such as the word lines WL.

[0073] As described above, the semiconductor memory device 1 of Embodiment 1 has a stacked body LM having the layer structure described above. The semiconductor memory device 1 of Embodiment 1 may also have a stacked body having a layer structure different from the above. Such stacked bodies LMs are described with reference to FIG. 3.

[0074] 3A and 3B are schematic diagrams illustrating the stacked bodies LM and LMs included in the semiconductor memory device 1 according to the embodiment 1. More specifically, FIG. 3A is a schematic plan view showing the layout of the semiconductor memory device 1, and FIGS. 3B and 3C are cross-sectional views showing the layer structures of the stacked bodies LMs and LM included in the semiconductor memory device 1.

[0075] As shown in FIG. 3(a), the semiconductor memory device 1 is diced into individual chips. A plane PLN including various components such as a stacked body LM, pillars PL, plate-like contacts LI, and contacts CC is disposed in the center of the diced semiconductor memory device 1. Although only one plane PLN is shown in the example of FIG. 3, the semiconductor memory device 1 may have multiple plane PLNs. A plane PLN is an element of the semiconductor memory device 1 that can operate independently of other plane PLNs.

[0076] As described above, the laminate LM included in the plane PLN is divided by a plurality of plate-shaped contacts LI, and block regions BLK are arranged between adjacent plate-shaped contacts LI. However, dummy block regions BLKd that do not function as block regions BLK are arranged at both ends in the Y direction, that is, further outside the plate-shaped contacts LI that are closest to both ends of the laminate LM in the Y direction.

[0077] A peripheral region PR is disposed around the plane PLN so as to surround the plane PLN. A kerf region KR is disposed further outside the peripheral region PR so as to surround the plane PLN via the peripheral region PR.

[0078] As shown in Figure 3(c), the laminate LM included in the plane PLN includes, as described above, a plurality of insulating layers OL arranged between a plurality of word lines WL and having a three-layer structure of insulating layer OLx / core layer OLc / insulating layer OLx.

[0079] 3(b), laminates LMs having a layer structure different from that of the laminate LM may be arranged at both ends in the Y direction of the laminate LM included in the plane PLN, i.e., in at least a portion of the dummy block region BLKd. The laminates LMs have a configuration in which multiple insulating layers NL and multiple core layers OLc are alternately stacked one by one.

[0080] The insulating layers NL are, for example, silicon nitride layers, and are arranged at height positions corresponding to the word lines WL and select gate lines SGD, SGS of the laminate LM. Each insulating layer NL has a thickness in the stacking direction that is equal to or greater than the thickness of each word line WL in the laminate LM, as well as the thickness of the barrier metal layers BM and metal element-containing layers MO arranged above and below the word lines WL.

[0081] The multiple core layers OLc contain the same material as the core layer OLc of the laminate LM, such as a carbon-doped silicon oxide layer, and are arranged at a height corresponding to that of the core layer OLc of the laminate LM. Each core layer OLc included in the laminate LMs has a thickness in the stacking direction that exceeds the thickness of each core layer OLc included in the laminate LM. However, the thickness of the core layer OLc in the stacking direction in the laminate LMs is equal to or less than the total thickness of the core layer OLc in the laminate LM and the insulating layers OLx arranged above and below the core layer OLc.

[0082] Furthermore, the laminate LMs as described above can also be disposed in at least a portion of the kerf region KR. As described above, the kerf region KR is used as a dicing line when singulating the semiconductor memory device 1. Therefore, although part or all of the kerf region KR disappears from the semiconductor memory device 1 after singulation, the laminate LMs in the kerf region KR that were cut off from the laminate LM during the manufacturing process of the semiconductor memory device 1 may remain even after singulation.

[0083] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 of the first embodiment will be described with reference to Figures 4 to 14. Figures 4 to 14 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0084] 4 to 8 are cross-sectional views along the Y direction of a region that will later become the memory region MR.

[0085] As shown in FIG. 4(a), a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are formed in this order on a support substrate SS.

[0086] The support substrate SS may be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate. The insulating layer 60 (see FIG. 2, etc.) may be formed on the upper surface of the support substrate SS. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL.

[0087] A stacked body LMsa is formed on the upper source line DSLb, in which multiple insulating layers NL and multiple core layers OLc are alternately stacked one by one. The insulating layer NL is, for example, a silicon nitride layer, and functions as a sacrificial layer that will later be replaced with a conductive material to become the word line WL or the select gate line SGS. The core layer OLc can be formed by depositing a silicon oxide layer using a method such as chemical vapor deposition (CVD) while doping it with carbon. In this case, it is preferable to adjust the amount of carbon doping so that the carbon content in the core layer OLc is 1 atomic % or more.

[0088] After that, although not shown, the insulating layer NL and the core layer OLc are processed into a stepped shape in a partial region of the laminate LMsa. This processing can be performed by repeatedly slimming a mask pattern such as a photoresist layer and etching the insulating layer NL and the core layer OLc of the laminate LMsa.

[0089] Specifically, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layer NL and core layer OLc are etched away one layer at a time. Then, using oxygen plasma or other treatment, the edges of the mask pattern are recessed to expose the top surface of the laminate LMsa, and the insulating layer NL and core layer OLc are further etched away one layer at a time. By repeating this process multiple times, the laminate LMsa is formed with a stepped shape at both ends in the X direction and both ends in the Y direction.

[0090] This also separates the laminate LMsa into a central portion of the laminate LMsa, which will later become the laminate LMa when pillars PL and contacts CC, etc. are formed, and an outer edge portion of the laminate LMsa, which is cut off from this central portion and is positioned in the kerf region KR (see Figure 3, etc.) so as to surround the central portion of the laminate LMsa.

[0091] As shown in FIG. 4(b), multiple memory holes MHa are formed in the stack LMsa, extending in the stacking direction. The multiple memory holes MHa penetrate the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN, and reach the lower source line DSLa. These memory holes MHa will later become the lower structure of the pillar PL.

[0092] 4(c), these memory holes MHa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer, thereby forming pillars PLc in which the sacrificial layer 26 is filled in the multiple memory holes MHa.

[0093] As shown in Fig. 4(d), a laminate LMsb is formed by covering the laminate LMsa with multiple insulating layers NL and multiple core layers OLc stacked alternately. The insulating layers NL of the laminate LMsb function as sacrificial layers that will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0094] After this, although not shown, the insulating layer NL and the core layer OLc are processed into a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layer NL and the core layer OLc of the laminate LMsb multiple times, similar to the processing performed on the laminate LMsa described above.

[0095] At this time, the uppermost step of the staircase portion already formed in the laminate LMsa and the lowermost step of the staircase portion formed in the laminate LMsb are brought close to each other to form a staircase shape that is continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. As a result, the laminates LMsa and LMsb are formed with staircase regions SR having a staircase shape extending from the laminate LMsa to the laminate LMsb, at both ends in the X direction and both ends in the Y direction.

[0096] This also separates the laminate LMsb into a central laminate LMsb, which will later become the laminate LMb when pillars PL and contacts CC, etc. are formed, and an outer edge laminate LMsb which is cut off from this central portion and is positioned in the kerf region KR (see Figure 3, etc.) so as to surround the central laminate LMsb.

[0097] As shown in Fig. 5(a), multiple memory holes MHb are formed through the stack LMsb and connected to the multiple pillars PLc already formed in the stack LMsa. The memory holes MHb are the portions that will later become the upper structure of the pillars PL.

[0098] 5(b), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb, thereby opening a memory hole MHa at the bottom of each of the memory holes MHb, and forming a plurality of memory holes MH that penetrate the stacks LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN and reach the lower source line DSLa.

[0099] In addition, if the sacrificial layer 26 filled in the pillars PLc is a CVD-carbon layer or the like, when the mask pattern or the like used in forming the memory holes MHb in Figure 5(a) above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed all at once from these pillars PLc.

[0100] 5(c), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order in the memory hole MH, whereby the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0101] The multilayer insulating layer MEb is an insulating layer with a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0102] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminated body LMsb.

[0103] 5(d), the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the top surface of the stack LMsb, and a recess DN is formed at the top end of the memory hole MH, thereby forming, in order from the outer periphery, the memory layer ME, the channel layer CN, and the core layer CR in the memory hole MH.

[0104] 6(a), a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the stacked body LMsb.

[0105] As shown in FIG. 6(b), the semiconductor layer CPb on the upper surface of the stacked body LMsb is removed by CMP or the like, and a cap layer CP is formed on the upper end of the memory hole MH.

[0106] As shown in Figure 6(c), a core layer OLc is stacked on the top layer of the laminate LMsb, which has been thinned by CMP or the like. This forms a pillar PL in which the cap layer CP is buried in the top core layer OLc. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and only a portion of the side of the channel layer CN is exposed from the memory layer ME.

[0107] 7(a), a slit ST is formed that penetrates the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. Insulating layers 54s are formed on side walls of the slit ST that face each other in the Y direction. The slit ST also extends in the X direction within the stacked bodies LMsa, LMsb.

[0108] As shown in FIG. 7(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0109] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs. At this time, since the sidewalls of the slits ST are protected by the insulating layer 54s, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well.

[0110] 7(c), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 2(b) and 2(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0111] 7(d), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0112] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0113] As shown in FIG. 8(a), the insulating layer 54s on the sidewall of the slit ST is temporarily removed.

[0114] 8(b), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having multiple gap layers GP from which the insulating layers NL between the core layers OLc have been removed.

[0115] The laminates LMga and LMgb, which include multiple gap layers GP, have a fragile structure. The multiple pillars PL support these fragile laminates LMga and LMgb. Furthermore, the core layers OLc remaining in the laminates LMga and LMgb are made of a material with a higher Young's modulus than, for example, a silicon oxide layer that is not doped with carbon.

[0116] Such a support structure for the pillars PL and the core layer OLc having a high Young's modulus prevent the core layer OLc remaining in the laminates LMga and LMgb from bending and the laminates LMga and LMgb from being distorted or collapsed.

[0117] After removing the insulating layer NL from the laminates LMsa and LMsb, the surface of the core layer OLc is oxidized to form an insulating layer OLx that covers the top and bottom surfaces of the core layer OLc and the end surface facing the slit ST, thereby forming a plurality of insulating layers OL each having a three-layer structure of the core layer OLc and the insulating layer OLx in the laminates LMga and LMgb.

[0118] 8(c), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0119] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0120] In the above-described replacement process of the laminated body LM, the laminated bodies LMsa and LMsb before replacement may remain in some regions.

[0121] For example, the insulating layer NL remover injected through the slit ST may not penetrate into the outer regions of the slits ST that are closest to both ends of the stacked bodies LMsa and LMsb in the Y direction and are close to the end positions of the stacked bodies LMsa and LMsb in the Y direction. In this case, the insulating layer NL is not removed in this region, and the word lines WL and the like are not formed, so the stacked bodies LMsa and LMsb remain with their layer structure intact.

[0122] However, as described above, the outer region of the slit ST closest to both ends of the stacks LMsa and LMsb in the Y direction is made into a dummy block region BLKd, so even if the stacks LMsa and LMsb remain, it will not affect the characteristics of the semiconductor memory device 1.

[0123] Furthermore, for example, when both ends in the X direction and both ends in the Y direction of the laminates LMsa and LMsb are processed into a stepped shape, the outer edge portion remaining in the kerf region KR is also separated from the part of the laminates LMsa and LMsb in which the slit ST is formed, and therefore remains as is without being subjected to replacement processing.

[0124] Thereafter, an insulating layer 54 is formed on the sidewall of the slit ST, and the insulating layer 54 is filled with the conductive layer 24 to form the plate-like contact LI. However, the slit ST may be filled with the insulating layer 54 or the like without forming the conductive layer 24, to form a plate-like member.

[0125] Here, FIGS. 9 to 14 show details of the replacement process for forming the word lines WL from the insulating layer NL.

[0126] 9 to 14(a) are enlarged cross-sectional views of a pillar PL at the height of the word line WL. 9 to 14(b) are enlarged cross-sectional views of the stacked bodies LMga and LMgb or the stacked bodies LMa and LMb at the height of the word line WL. 9 to 14(c) are enlarged cross-sectional views of the slit ST or the plate-like contact LI at the height of the word line WL.

[0127] The following replacement process is also performed in the area including the select gate lines SGD and SGS.

[0128] 9 shows the state of the laminated bodies LMga and LMgb after the insulating layers NL have been removed through the slits ST. Gap layers GP are formed between the core layers OLc by removing the insulating layers NL. In removing the insulating layers NL, a remover such as hot phosphoric acid is used as described above, and the laminated bodies LMga and LMgb after the insulating layers NL have been removed are also cleaned using a predetermined cleaning solution.

[0129] The surface tension of the remover or cleaning solution acts on the core layers OLc in the laminates LMga and LMgb, which raises concerns that adjacent core layers OLc in the stacking direction may adhere to each other. However, as described above, the core layers OLc contain a material with a high Young's modulus, which prevents such adhesion between the core layers OLc. Similarly, the high Young's modulus of the core layers OLc also prevents bending and distortion of the laminates LMga and LMgb.

[0130] On the other hand, the core layer OLc has a lower breakdown voltage than, for example, a silicon oxide layer that is not doped with carbon. Therefore, before forming the word lines WL and the like in the gap layer GP of the laminated bodies LMga and LMgb, a process is performed in which the surface of the core layer OLc is oxidized to increase the breakdown voltage.

[0131] As shown in Figure 10, the core layer OLc is oxidized to form an insulating layer OLx on the surface of the core layer OLc. The surface of the core layer OLc can be oxidized by, for example, oxygen radical oxidation treatment or thermal oxidation treatment. The oxygen radical oxidation treatment is performed using oxygen plasma generated by, for example, a remote plasma method or a direct plasma method. The thermal oxidation treatment can be performed by, for example, a dry treatment in which the object to be oxidized is heated in an oxygen atmosphere or an ozone atmosphere, or a wet treatment in which the object to be oxidized is heated in water vapor.

[0132] By oxidizing the core layer OLc in this manner, almost the entire exposed surface of the core layer OLc is oxidized to form an insulating layer OLx, and an insulating layer OL having a three-layer structure of insulating layer OLx / core layer OLc / insulating layer OLx in the layer thickness direction is formed.

[0133] 10(a) and 10(b), in the vicinity of the pillars PL and in the portions of the laminates LMga and LMgb where the pillars PL and the slits ST are not present, the upper and lower surfaces of the core layer OLc in the stacking direction are oxidized and covered with the insulating layer OLx. On the other hand, as shown in FIG. 10(c), in the vicinity of the slit ST, not only the upper and lower surfaces but also the end surface of the core layer OLc facing the slit ST are exposed. Therefore, in addition to the upper and lower surfaces of the core layer OLc, the end surface on the slit ST side is also covered with the insulating layer OLx.

[0134] This oxidation process usually proceeds at a substantially uniform rate across the entire exposed surface of the core layer OLc. Therefore, the insulating layer OLx covering the exposed surface of the core layer OLc is formed to a substantially uniform thickness everywhere. At this time, the surface of the core layer OLc is sufficiently oxidized so that the amount of Si-O bonds in the insulating layer OLx is greater than the amount of Si-O bonds in the core layer OLc. It is also preferable to perform the oxidation process until the remaining core layer OLc that has not been oxidized has a thickness equal to or less than that of the insulating layer OLx on the surface of the core layer OLc.

[0135] This allows the insulating layer OL as a whole to obtain a sufficient breakdown voltage.

[0136] The insulating layer OLx formed by the oxidation treatment may expand in volume more than the original core layer OLc, which is why the overall thickness of the insulating layer OL in the three-layer structure of insulating layer OLx / core layer OLc / insulating layer OLx after the oxidation treatment may be greater than the thickness of the core layer OLc before the oxidation treatment.

[0137] 11 , a metal element-containing layer MO and a barrier metal layer BM are formed in this order in the gap layer GP of the laminated bodies LMga and LMgb via a slit ST. The metal element-containing layer MO and barrier metal layer BM are formed on the upper and lower surfaces of the insulating layer OL exposed in the gap layer GP, the end faces of the insulating layer OL facing the slit ST, and the side walls of the pillars PL exposed in the gap layer GP. That is, the metal element-containing layer MO and barrier metal layer BM are formed on the side walls of the pillars PL at the height of the gap layer GP where the word lines WL and the like will be formed later, and on the side walls of the slits ST at the height of the insulating layer OL.

[0138] 12, a conductive material such as tungsten or molybdenum is filled into the gap layer GP of the stacked bodies LMga and LMgb, in which the metal element-containing layer MO and the barrier metal layer BM are formed, through the slits ST to form the word lines WL, etc. At this time, the conductive material is also formed in part of the slits ST.

[0139] As shown in FIG. 13, the conductive material formed in the slit ST is removed. The barrier metal layer BM covering the end surface of the insulating layer OL facing the slit ST is also removed. At this time, in order to completely remove the barrier metal layer BM from the end surface of the insulating layer OL, part or all of the metal-element-containing layer MO on the end surface of the insulating layer OL may be removed. At this time, the end surface of the word line WL exposed in the slit ST may recede away from the side wall of the slit ST together with the barrier metal layer BM covering the top and bottom surfaces of the word line WL.

[0140] By removing the barrier metal layer BM from the end face of the insulating layer OL, conduction through the barrier metal layer BM between the word lines WL adjacent in the stacking direction can be suppressed.

[0141] 14, an insulating layer 54 is formed on the sidewall of the slit ST, and the slit ST is further filled with a conductive layer 24. This forms the plate contact LI. Note that, when the barrier metal layer BM is removed from the end face of the insulating layer OL, the word lines WL and the like recede, and therefore the insulating layer 54 on the sidewall of the plate contact LI may have a shape that protrudes in the direction of the word lines WL at the height position of the word lines WL and the like.

[0142] Thereafter, a trench is formed through one or more conductive layers, including the top conductive layer of the laminated body LMb, and an insulating layer 56 is filled into the trench to form a separation layer SHE that divides these conductive layers into the pattern of the select gate line SGD.

[0143] Furthermore, a plurality of contacts CC are formed from the upper side of the staircase region SR, reaching the word lines WL and select gate lines SGD, SGS that constitute each step of the staircase structure of the staircase region SR.

[0144] An insulating layer 52 is formed on the upper surface of the laminate LM, and plugs CH connected to the pillars PL and plugs connected to the contacts CC are formed through the insulating layer 52. An insulating layer 53 is further formed on the insulating layer 52, and bit lines BL connected to the plugs CH and upper layer wiring connected to the contacts CC via the plugs are formed. Electrode pads and the like for electrical conduction with the peripheral circuit CBA are also formed on the upper surface of the insulating layer 53.

[0145] The plugs CH and the bit lines BL may be formed collectively by using, for example, a dual damascene method.

[0146] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0147] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0148] In this manner, the semiconductor memory device 1 of the first embodiment is manufactured.

[0149] In the manufacturing process of semiconductor memory devices such as 3D nonvolatile memories, a sacrificial layer in a stack may be replaced with a conductive layer to form a stack of conductive and insulating layers. In this case, the fragile stack containing multiple gap layers may bend or distort during the replacement process.

[0150] To prevent this, it is conceivable to achieve both sufficient strength and voltage resistance by using a three-layer structure for the insulator placed between the sacrificial layers, in which an undoped silicon oxide layer is sandwiched between carbon-doped silicon oxide layers with a high Young's modulus. However, to form an insulating layer with a three-layer structure, for example, the layers must be deposited in the order of a carbon-doped silicon oxide layer, an undoped silicon oxide layer, and a carbon-doped silicon oxide layer, and the gas type must be switched multiple times for each insulator between the sacrificial layers, which raises concerns about reduced throughput.

[0151] According to the semiconductor memory device 1 of embodiment 1, a core layer OLc containing Si-C bonds and an insulating layer OLx containing Si-O bonds are arranged as insulators between each of the multiple word lines WL, and the insulating layer OLx covers the upper and lower surfaces of the core layer OLc in the stacking direction and the end surfaces of the core layer OLc facing the side walls of the plate-shaped contacts LI.

[0152] This increases the Young's modulus of the core layer OLc compared to the insulating layer OLx, thereby suppressing deflection and distortion of the laminated bodies LMga and LMgb during replacement processing. Furthermore, the insulating layer OLx covering the core layer OLc increases the breakdown voltage of the insulating layer OL as a whole, thereby suppressing leakage current between the word lines WL. By sandwiching the word lines WL between the insulating layers OL, which have an increased breakdown voltage overall, leakage current between the word lines WL and the plate-like contacts LI can also be suppressed.

[0153] According to the semiconductor memory device 1 of embodiment 1, the thickness of the insulating layer OLx in the stacking direction is preferably equal to or greater than the thickness of the core layer OLc in the stacking direction, which allows the insulating layer OL as a whole to have a more sufficient breakdown voltage.

[0154] According to the semiconductor memory device 1 of embodiment 1, the insulating layer OLx is an oxidized layer of the core layer OLc. In this way, when a remover or cleaning solution is used in the replacement process of the laminated body LMs, the core layer OLc before the oxidation process can suppress bending and distortion of the laminated body LMs, and by subsequently oxidizing the surface of the core layer OLc before forming the word lines WL, etc., an insulating layer OL with sufficient withstand voltage can be obtained without reducing throughput.

[0155] [Embodiment 2] Hereinafter, the second embodiment will be described in detail with reference to the drawings. The semiconductor memory device 2 of the second embodiment differs from the first embodiment in the memory region MR and the staircase region SR in the stacked body LM, and the position of the peripheral circuit CUA relative to the stacked body LM.

[0156] In the following drawings, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0157] Fig. 15 is a diagram showing a schematic configuration example of a semiconductor memory device 2 according to embodiment 2. More specifically, Fig. 15(a) is a cross-sectional view of the semiconductor memory device 2 taken along the X direction, and Figs. 15(b) and 15(c) are cross-sectional views showing the layer structures of the laminated bodies LMs and LM included in the semiconductor memory device 2, respectively.

[0158] As shown in FIG. 15(a), the semiconductor memory device 2 of the second embodiment includes a peripheral circuit CUA and a stacked body LM having a plurality of word lines WL and the like, in this order, on a substrate SB.

[0159] The substrate SB is a semiconductor substrate such as a silicon substrate, etc. On the substrate SB, a peripheral circuit CUA including transistors TR, wiring, etc., which controls the electrical operation of the memory cells MC of the semiconductor memory device 2 is arranged.

[0160] The peripheral circuit CUA is covered with an insulating layer 40 such as a silicon oxide film. Source lines SL are arranged on the insulating layer 40. Above the source lines SL, a stacked body LM is arranged in which a plurality of word lines WL and select gate lines SGD, SGS are stacked.

[0161] The laminate LM has a plurality of memory regions MR, staircase regions SR, SRs, and via contact regions TP arranged in the central part of the laminate LM, and the memory regions MR are arranged on both sides of the staircase regions SR, SRs, and via contact regions TP in the X direction.

[0162] In the memory region MR, a plurality of pillars PL are arranged, penetrating a plurality of word lines WL in the stacking direction. A plurality of memory cells MC (see FIG. 2) are formed at the intersections of the pillars PL and the word lines WL. As a result, the semiconductor memory device 2 of the second embodiment is also configured as a three-dimensional nonvolatile memory in which a plurality of memory cells MC are arranged three-dimensionally.

[0163] The staircase region SR includes multiple staircase portions formed by digging down multiple word lines WL and other elements in a canyon-like manner in the stacking direction. The word lines WL and select gate lines SGD and SGS of each layer maintain electrical continuity on both sides of the staircase region SR in the X direction via the Y-direction ends of the staircase region SRc.

[0164] Of the word lines WL and select gate lines SGD, SGS processed in a stepped shape, the contacts CC connected to the word lines WL and select gate lines SGS are arranged in the stepped portion near the through contact region TP on one side in the X direction, and the contacts CC connected to the select gate line SGD are arranged near the memory region MR on the other side in the X direction.

[0165] Furthermore, a staircase region SRs is further provided between the through-contact region TP and the memory region MR, and has a contact CC connected to the select gate line SGD.

[0166] These contacts CC, which are connected to the word lines WL and select gate lines SGD, SGS in the staircase regions SR, SRs, are electrically connected to the peripheral circuit CUA via upper layer wiring further above the select gate line SGD and via through contacts C4, etc., which will be described below.

[0167] In the via contact region TP, via contacts C4 are arranged, which penetrate the via contact region TP in the laminate LM. The via contacts C4 connect the peripheral circuit CUA arranged on the underlying substrate SB with contacts CC provided on the multiple word lines WL. Various voltages applied to the memory cells MC from the contacts CC are controlled by the peripheral circuit CUA via the via contacts C4 and the like.

[0168] The laminated body LM having the above-described configuration is covered with an insulating layer 50. The insulating layer 50 also extends around the multiple laminated bodies LM. A peripheral region PR is arranged around the laminated body LM, and a kerf region KR is arranged further outside the peripheral region PR at the end of each individual semiconductor memory device 2.

[0169] As shown in FIG. 15(c), the stacked body LM included in the semiconductor memory device 2 has the same layer structure as the stacked body LM in the above-described embodiment.

[0170] 15(b), in the through contact region TP, a laminate LMs is arranged in place of the laminate LM, in which a plurality of insulating layers NL and a plurality of core layers OLc are alternately stacked one by one. That is, the laminate LMs is arranged in the through contact region TP, sandwiched on both sides by the laminate LM or surrounded on the periphery by the laminate LM. Such a laminate LMs is formed by providing a barrier between both ends of the through contact region TP in the Y direction and the slits on the outside thereof to block the insulating layer NL remover injected through the slits, thereby providing an area that is not subjected to the replacement process.

[0171] The through contact C4 penetrates the laminated body LMs that does not have the word line WL, etc., and is electrically connected to the peripheral circuit CUA below the laminated body LM. This prevents, for example, the through contact C4 from becoming electrically connected to the word line WL, etc. in the laminated body LM.

[0172] The laminate LMs can also be disposed in at least a part of the kerf region KR, as in the above-described embodiment 1. The laminate LMs in the kerf region KR is also separated from the laminate LMs in the central part where the pillars PL and the like are disposed in the manufacturing process of the semiconductor memory device 2, and is a part that is maintained with its layer structure intact without being subjected to a replacement process.

[0173] Furthermore, similarly to the first embodiment, the laminated body LMs may be disposed at both ends of the laminated body LM in the Y direction.

[0174] In the above-described first and second embodiments, the core layer OLc included in the laminate LM of the semiconductor memory device 1 or 2 is a carbon-doped silicon oxide layer, and the insulating layer OLx is a layer obtained by oxidizing the core layer OLc. However, the core layer having a higher Young's modulus than a silicon oxide layer or the like is not limited to the above and may be, for example, a silicon carbide layer or a silicon layer. Such a core layer OLc with a high Young's modulus can also suppress bending and distortion of the laminate LM.

[0175] When the core layer is a silicon carbide layer, as in the above-described first and second embodiments, these layers can be configured so that the content of Si-C bonds in the core layer is greater than the content of Si-C bonds in the insulating layer obtained by oxidizing the core layer, and the content of Si-O bonds in the insulating layer is greater than the content of Si-O bonds in the core layer.

[0176] When the core layer is a silicon layer, these layers can be configured so that the content of Si-Si bonds in the core layer is greater than the content of Si-Si bonds in the insulating layer obtained by oxidizing the core layer, and the content of Si-O bonds in the insulating layer is greater than the content of Si-O bonds in the core layer.

[0177] In the above-described first and second embodiments, the semiconductor memory devices 1 and 2 are provided with a stack LM having a two-tier structure in which two stacks LMa and LMb are stacked one above the other. However, the configuration of the stack is not limited to two tiers, and may be one tier, or three or more tiers.

[0178] In the above-described first and second embodiments, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0179] In the above-described first and second embodiments, the peripheral circuits CBA and CUA are arranged above or below the laminate LM. However, the peripheral circuits may be arranged on the same layer as the laminate. In this case, the laminate can be formed at a different position from the peripheral circuits on the semiconductor substrate on which the peripheral circuits are formed.

[0180] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0181] 1,2...semiconductor memory device, BK...block insulating layer, CC...contact, CN...channel layer, CT...charge storage layer, LI...plate-shaped contact, LM, LMa, LMb, LMga, LMgb, LMs, LMsa, LMsb...stacked body, MC...memory cell, MR...memory region, NL, OL, OLx...insulating layer, OLc...core layer, PL...pillar, SR...staircase region, SGD, SGS...select gate line, ST...slit, TN...tunnel insulating layer, WL...word line.

Claims

1. a first laminate in which a plurality of conductive layers are laminated and spaced apart from one another; a plate-like portion extending within the first laminate in a stacking direction of the first laminate and a first direction intersecting the stacking direction, and dividing the first laminate in a second direction intersecting the stacking direction and the first direction; pillars extending in the stacking direction within the first stacked body, and at intersections with at least some of the plurality of conductive layers, memory cells are formed in the pillars, Between each of the plurality of conductive layers, a first layer including at least one of a Si—C bond and a Si—Si bond; a first insulating layer including a Si—O bond, covering upper and lower surfaces of the first layer in the stacking direction and an end surface of the first layer facing the side wall of the plate-shaped portion; The first layer comprises: the first insulating layer contains more Si—C bonds or more Si—Si bonds than the first insulating layer; The first insulating layer comprises: the first layer contains more Si—O bonds than the first layer; Semiconductor memory device.

2. The first layer comprises: the first insulating layer is in contact with the sidewall of the pillar without being interposed therebetween; 2. The semiconductor memory device according to claim 1.

3. a metal element-containing layer covering each of the opposing surfaces of the first insulating layer facing the plurality of conductive layers and a surface of the first insulating layer facing the plate-shaped portion and covering the end surface of the first layer; 2. The semiconductor memory device according to claim 1.

4. a first laminate including a plurality of conductive layers laminated with an insulator therebetween; a plate-like portion extending within the first laminate in a stacking direction of the first laminate and a first direction intersecting the stacking direction, and dividing the first laminate in a second direction intersecting the stacking direction and the first direction; pillars extending in the stacking direction within the first stacked body, and at intersections with at least some of the plurality of conductive layers, memory cells are formed in the pillars, the insulator between each of the plurality of conductive layers includes a first layer, located in the first insulating layer at an intermediate position in the stacking direction, the first layer having a higher Young's modulus than the first insulating layer; an end surface of the first layer facing the side wall of the plate-shaped portion is covered with the first insulating layer; an end surface of the first layer facing the side wall of the pillar is in contact with the side wall of the pillar without the first insulating layer therebetween; Semiconductor memory device.

5. The first insulating layer comprises: the first layer covers the upper and lower surfaces and the end surface facing the side wall of the plate-like portion with a substantially uniform thickness; 5. The semiconductor memory device according to claim 4.

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