Semiconductor device

Abstract

To provide a transistor using an oxide semiconductor layer and having electrical characteristics required for a particular application, and a semiconductor device including the transistor.SOLUTION: A transistor 440a includes a semiconductor layer, source or drain electrode layers 405a and 405b, a gate insulating film 402, and a gate electrode layer 401 stacked in this order over an oxide insulating film 436. The transistor 440a uses an oxide semiconductor stack including at least two oxide semiconductor layers 101 and 102 having different band gaps as the semiconductor layers. Oxygen or a dopant may be introduced into the oxide semiconductor stack.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A technique for constructing transistors (also called thin film transistors (TFTs)) using semiconductor thin films. This technology is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices such as: Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. It is being done.

[0004] As for transistors using oxide semiconductors, there are many In transistors using oxide semiconductors, higher electrical characteristics are required. For the purpose of achieving good electrical characteristics, low-resistance source and drain regions are fabricated using an aluminum reaction method. Techniques for forming regions have been reported (see, for example, Non-Patent Document 1).

[0005] For example, indium (In), gallium (Ga), and nickel are used as the active layer of a transistor. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 [Non-patent literature]

[0007] [Non-Patent Document 1] N.Morosawa, Yoshihiro Ohshima, Mitsuo Morooka, Toshiaki Arai, Tatsuya Sasaoka, “A Novel Self-Aligned Top-Gate Oxide TFT for AM-OLED Displays”, SID 11 DIGEST pp479-482 Summary of the Invention [Problem to be solved by the invention]

[0008] If the on-characteristics of a transistor (for example, on-current and field-effect mobility) are improved, the semiconductor device This enables high-speed response and high-speed driving in devices, resulting in higher performance semiconductor devices. On the other hand, in order to reduce the power consumption of a semiconductor device, the off-state current of a transistor must be sufficiently low. In this way, the electrical properties required for a transistor depend on the application and purpose. These electrical properties vary depending on the material and therefore it is beneficial to have more precise control over these properties.

[0009] The threshold voltage of the transistor using an oxide semiconductor for the channel formation region is plotted. This transistor structure can be used to realize a so-called normally-off switching element. One of the objectives of the present invention is to provide a structure and a method for manufacturing the same.

[0010] The transistor has a gate voltage that is as close to 0V as possible to form a positive threshold voltage. If the threshold voltage of the transistor is negative, the gate voltage Even at 0V, current flows between the source and drain electrodes, making it a so-called normally-on state. In LSIs, CPUs, and memories, the electrical characteristics of the transistors that make up the circuits are important. These electrical characteristics determine the power consumption of a semiconductor device. Among the properties, the threshold voltage (Vth) is important. If the voltage is negative, it is difficult to control the circuit. A transistor in which a channel is formed and a drain current flows is used in an integrated circuit of a semiconductor device. It is not suitable for use as a transistor.

[0011] In addition, depending on the material and manufacturing conditions, the manufactured transistor may not be normally off. Even in this case, it is important to approach the normally-off characteristics, and the threshold voltage is Even if the transistor is normally on, the threshold voltage is reduced to zero. It is also an object of the present invention to provide a structure and a manufacturing method thereof.

[0012] Furthermore, in order to realize a semiconductor device with higher performance, it is necessary to improve the on-characteristics of the transistor (for example, This configuration improves the current and field-effect mobility, enabling high-speed response and high-speed operation of semiconductor devices. It is also an object of the present invention to provide a method for manufacturing the same.

[0013] As described above, a transistor using an oxide semiconductor layer having electrical properties required for a particular application can be fabricated. An object of the present invention is to provide a transistor and a semiconductor device including the transistor. [Means for solving the problem]

[0014] A semiconductor layer, a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order. In the layered transistor, the semiconductor layers are at least At least one oxide semiconductor stack including two oxide semiconductor layers is used.

[0015] When the oxide semiconductor stack has a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer, In this case, the first oxide semiconductor layer and the second oxide semiconductor layer have their own energy The stacking order is not limited as long as the caps are different. The layer may have a large gap or a small energy gap.

[0016] Specifically, in the stack of oxide semiconductor layers, the energy gap of one of the oxide semiconductor layers is The energy gap of the other oxide semiconductor layer is set to be 3 eV or more, and the energy gap of the other oxide semiconductor layer is set to be less than 3 eV. In this specification, the term "energy gap" refers to "band gap" or " It is used in the same sense as "forbidden band width."

[0017] When the oxide semiconductor stack has a stack structure of three or more layers, all the oxide semiconductor layers are different from each other. The structure may have the same energy gap as the material, or may have approximately the same energy gap as the material. The oxide semiconductor layer may be used in a stack of a plurality of oxide semiconductor layers.

[0018] For example, the oxide semiconductor stack may be formed by stacking a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer. In the stacked structure of oxide semiconductor layers, the energy gap of the second oxide semiconductor layer is set to be larger than that of the first oxide semiconductor layer. The energy gap of the first oxide semiconductor layer is set to be smaller than that of the second oxide semiconductor layer and the third oxide semiconductor layer. The electron affinity of the second oxide semiconductor layer is calculated by comparing the electron affinity of the first oxide semiconductor layer and the electron affinity of the third oxide semiconductor layer. In this case, the electron affinity of the first oxide semiconductor layer and the third oxide semiconductor layer is set to be larger than that of the second oxide semiconductor layer. The energy gap and electron affinity of the semiconductor layer can be made equal. The second oxide semiconductor layer having a small energy gap is formed on the first oxide semiconductor layer having a large energy gap. By using a structure in which the second oxide semiconductor layer is sandwiched between the first oxide semiconductor layer and the second oxide semiconductor layer, the transistor This has the effect of reducing the off-state current (leak current). Here, the electron affinity is the relationship between the vacuum level and This represents the energy difference with the conduction band of an oxide semiconductor.

[0019] In a transistor including an oxide semiconductor layer, the energy gap of the oxide semiconductor layer For example, in a transistor using an oxide semiconductor layer, In a transistor, if the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, On the other hand, the energy gap of the oxide semiconductor layer is large. If the gate insulating film is thin, the off-state current can be reduced.

[0020] In the case of a single oxide semiconductor layer, the size of the energy gap of the oxide semiconductor layer determines the transistor Since the electrical characteristics of the transistor are almost determined, it is necessary to give the transistor the desired electrical characteristics. It's difficult.

[0021] A stack of oxide semiconductor layers with different energy gaps was used. This allows for more precise control of the electrical characteristics of the transistor, resulting in a desired It is possible to impart electrical properties to the transistor.

[0022] Therefore, it is possible to provide semiconductor devices that meet various purposes, such as high functionality, high reliability, or low power consumption. It is possible.

[0023] One embodiment of the configuration of the present invention disclosed in this specification is a first oxide semiconductor having a different energy gap. an oxide semiconductor stack including a conductor layer and a second oxide semiconductor layer; a source electrode layer and a drain electrode layer; a gate insulating film on the source electrode layer and the drain electrode layer; The semiconductor device includes a gate electrode layer over a gate insulating film, the gate electrode layer overlapping with an oxide semiconductor stack.

[0024] One embodiment of the invention disclosed in this specification is a semiconductor device including a first oxide semiconductor layer, a second oxide semiconductor layer, a a stack of oxide semiconductor layers including a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer in this order; a source electrode layer and a drain electrode layer, and a gate insulating film on the source electrode layer and the drain electrode layer. a gate electrode layer over the gate insulating film, the gate electrode layer overlapping the oxide semiconductor stack; The oxide semiconductor layer has an energy gap smaller than that of the first oxide semiconductor layer and the third oxide semiconductor layer. This is a semiconductor device with a wide energy gap.

[0025] In the above structure, the oxide semiconductor stack has an island shape, and the source electrode layer and the drain electrode layer The oxide semiconductor layer can be formed in contact with the side surface (edge ​​portion) of the oxide semiconductor stack. The side (end) of the layer is provided with a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer. Since the side surfaces (ends) of the semiconductor layers are exposed, the first oxide semiconductor layer and the second oxide semiconductor layer The first oxide semiconductor layer and the third oxide semiconductor layer are in contact with the source electrode layer and the drain electrode layer.

[0026] One embodiment of the invention disclosed in this specification is a semiconductor device having a structure in which a semiconductor layer having a different energy gap is formed on an oxide insulating film. and forming a stack of oxide semiconductor layers including two oxide semiconductor layers, A gate insulating film is formed on the source electrode layer and the drain electrode layer, and the gate insulating film covers the source electrode layer and the drain electrode layer. This is a method for manufacturing a semiconductor device, in which a film is formed, and a gate electrode layer is formed on the gate insulating film.

[0027] One embodiment of the invention disclosed in this specification is a semiconductor device having a structure in which a semiconductor layer having a different energy gap is formed on an oxide insulating film. a mask is formed over the stack of oxide semiconductor films, and The stack of oxide semiconductor films is etched to form a stack of oxide semiconductor films. a source electrode layer and a drain electrode layer are formed on the insulating layer, and the source electrode layer and the drain electrode layer are covered with the insulating layer; A method for manufacturing a semiconductor device in which a gate insulating film is formed and a gate electrode layer is formed on the gate insulating film. It is the law.

[0028] In addition, a dopant is introduced into the oxide semiconductor stack using the gate electrode layer as a mask, and a self-aligned The channel formation region is sandwiched between the low-resistance The dopant is an impurity that changes the electrical conductivity of the oxide semiconductor stack. The dopant introduction method includes ion implantation, ion doping, plasma ion implantation, and the like. A method such as ion implantation can be used.

[0029] The semiconductor device has a stack of oxide semiconductor layers including a low-resistance region sandwiching a channel formation region in the channel length direction. As a result, the transistor has high on-state characteristics (for example, on-state current and field-effect mobility). This enables high-speed operation and high-speed response.

[0030] Further, a heat treatment (desorption treatment) for releasing hydrogen or moisture from an oxide semiconductor layer (oxide semiconductor film) is performed. For example, in the above configuration, before forming the mask, Then, heat treatment is performed to release hydrogen or moisture contained in the stacked oxide semiconductor film. It is preferable to do so.

[0031] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. In the oxide semiconductor film, oxygen is released and the amount of oxygen is reduced. Oxygen vacancies exist in the areas where the oxide has been removed, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. This results in the creation of donor levels.

[0032] Therefore, when oxygen is added to the oxide semiconductor layer (oxide semiconductor film) that has been subjected to dehydration or dehydrogenation treatment, It is preferable to supply oxygen to the oxide semiconductor layer (oxide semiconductor film). This makes it possible to compensate for oxygen vacancies in the film.

[0033] For example, an oxide insulating film containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed on an oxide semiconductor layer ( By providing the insulating film in contact with the oxide semiconductor layer (oxide semiconductor film), In the above structure, oxygen can be supplied to the dehydration or dehydrogenation semiconductor film. The oxide semiconductor layer (oxide semiconductor film) and the oxide insulating film that were subjected to heat treatment were thinned. By performing heat treatment in a state where the oxide semiconductor layer (oxide semiconductor film ) may be supplied with oxygen.

[0034] In addition, the oxide semiconductor layer (oxide semiconductor film) that has been subjected to dehydration or dehydrogenation treatment may be treated with oxygen (a small amount of oxygen). At least one of oxygen radicals, oxygen atoms, and oxygen ions is introduced into the film. Oxygen may be supplied. The oxygen introduction method may be an ion implantation method, an ion doping method, or Plasma immersion ion implantation, plasma treatment, etc. can be used. can.

[0035] Furthermore, the oxide semiconductor layer (oxide semiconductor film) provided in the transistor is preferably an oxide semiconductor layer. The oxide semiconductor contains a region where the oxygen content is excessive compared to the stoichiometric composition ratio in the crystalline state. In this case, the oxygen content is preferably in the range of stoichiometric composition of the oxide semiconductor. Alternatively, the oxygen content should be such that it exceeds the amount of oxygen in the case of a single crystal. Oxygen may exist between the lattices of an oxide semiconductor.

[0036] Hydrogen or moisture is removed from the oxide semiconductor, and the semiconductor is highly purified to minimize the amount of impurities. By supplying oxygen to compensate for oxygen vacancies, an I-type (intrinsic) oxide semiconductor or an I-type By doing so, it is possible to obtain an oxide semiconductor that is as close to intrinsic as possible. Bringing the Fermi level (Ef) of a semiconductor to the same level as the intrinsic Fermi level (Ei) Therefore, by using the oxide semiconductor film in a transistor, the oxide semiconductor film can be effectively prevented from being generated due to oxygen vacancies. The variation in threshold voltage Vth of the transistor and the threshold voltage shift ΔVth are reduced. It is possible.

[0037] One embodiment of the present invention is a transistor or a circuit including a transistor. For example, the present invention relates to a semiconductor device, a transistor in which a channel formation region is formed of an oxide semiconductor, The present invention relates to a semiconductor device having a circuit including a transistor. , LSI, CPU, power devices mounted on power supply circuits, memory, thyristors, converters, semiconductor integrated circuits including image sensors, and electronic devices such as liquid crystal display panels. The present invention relates to electronic equipment that incorporates, as a component, a light-emitting display device having an electro-optical device or a light-emitting element. [Effects of the Invention]

[0038] A stack of oxide semiconductor layers with different energy gaps was used. This allows for more precise control of the electrical characteristics of the transistor, resulting in a desired It is possible to impart electrical properties to the transistor.

[0039] Therefore, it is possible to provide semiconductor devices that meet various purposes, such as high functionality, high reliability, or low power consumption. It is possible. [Brief explanation of the drawings]

[0040] [Figure 1] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 2] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Figure 3] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 4] 1A and 1B are a diagram illustrating one embodiment of a semiconductor device and an energy band diagram; [Figure 5] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Figure 6] 1A to 1C illustrate one embodiment of a semiconductor device and a manufacturing method thereof; [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 9] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 10] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 11] 1A and 1B are diagrams illustrating electronic devices. [Figure 12] FIG. 1 is a diagram showing ionization potential. [Figure 13] FIG. 1 is a diagram showing an energy band diagram. [Figure 14] TEM photographs and schematic diagrams of samples of the examples. DETAILED DESCRIPTION OF THE INVENTION

[0041] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the accompanying drawings. However, the invention disclosed in this specification is not limited to the following description, and various forms and details may be used. It will be readily understood by those skilled in the art that the invention disclosed in this specification can be modified in any manner. The present invention is not limited to the following embodiments. The ordinal numbers such as 2 are used for convenience and do not indicate the order of processes or stacking. Furthermore, the present specification does not indicate specific names as matters for identifying the invention. do not have.

[0042] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor having an oxide semiconductor film will be described as an example of a semiconductor device. This indicates a transistor.

[0043] The transistor may have a single gate structure in which one channel formation region is formed, or two gate structures in which two channel formation regions are formed. The gate structure may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. , and has two gate electrode layers arranged above and below the channel region with a gate insulating film interposed therebetween; A dual gate type may also be used.

[0044] The transistor 440a and the transistor 440b shown in FIGS. 1A and 1B are top-gate 1 is an example of a planar transistor having a structure.

[0045] As shown in FIGS. 1A and 1B, the transistors 440a and 440b are oxidized. A first oxide film having a different energy gap is formed on a substrate 400 on which an insulating film 436 is provided. an oxide semiconductor stack 403 including a semiconductor layer 101 and a second oxide semiconductor layer 102; The electrode layer 405a, the drain electrode layer 405b, the gate insulating film 402, and the gate electrode layer 401 are An insulating film 407 is formed over the transistor 440a and the transistor 440b. are.

[0046] In FIG. 1, the interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is shown by a dotted line, which is a schematic representation of the oxide semiconductor stack 403. Depending on the material, film formation conditions, and heat treatment, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 may be separated. In some cases, the interface between the oxide layer 102 and the oxide layer 102 may become unclear. A mixed region or layer of the semiconductor layer may be formed. The same applies to the other drawings in this specification.

[0047] In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor The layers 102 may be stacked in any order as long as they have different energy gaps. I can't.

[0048] Specifically, in the oxide semiconductor stack 403, the energy gap between one of the oxide semiconductor layers is the energy gap of the other oxide semiconductor layer is set to 3 eV or more, and the energy gap of the other oxide semiconductor layer is set to less than 3 eV. .

[0049] The transistor 440a illustrated in FIG. 1A has a second oxide semiconductor layer formed on the first oxide semiconductor layer 101. In this example, the compound semiconductor layer 102 has a larger energy gap than the compound semiconductor layer 101. The first oxide semiconductor layer 101 in the transistor 440a is an In—Sn—Zn-based oxide. A second oxide film (energy gap 2.6 eV to 2.9 eV, typically 2.8 eV) The compound semiconductor layer 102 is an In-Ga-Zn oxide (also written as IGZO) film ( An energy gap of 3.0 eV to 3.4 eV, typically 3.2 eV, is used.

[0050] On the other hand, the transistor 440b illustrated in FIG. 1B has a second oxide semiconductor layer 101 and a second oxide semiconductor layer 102. In this example, the oxide semiconductor layer 102 has a smaller energy gap than the oxide semiconductor layer 102 in this embodiment. In the transistor 440b, the first oxide semiconductor layer 101 is made of In-Ga-Z The second oxide semiconductor layer 102 is an n-type oxide film (energy gap 3.2 eV). An In-Sn-Zn oxide film (energy gap 2.8 eV) is used.

[0051] In this manner, in the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are The oxide semiconductor layer 102 has a larger energy gap on the side in contact with the gate insulating film 402. It may be a layer having a small energy gap.

[0052] In FIG. 4A, the oxide semiconductor stack 403 includes a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102. A transistor using a stack of three layers of a semiconductor layer 102, a third oxide semiconductor layer 103, and a third oxide semiconductor layer 104. 480a is shown.

[0053] The transistor 480a is formed by forming a first oxide film over the substrate 400 on which the oxide insulating film 436 is provided. The semiconductor device includes a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103. a source electrode layer 405a, a drain electrode layer 405b, a gate insulating film 406, a gate insulating film 408, a gate insulating film 409, a gate insulating film 410, a gate insulating film 411, a gate insulating film 412, a gate insulating film 413, a gate insulating film 414, a gate insulating film 415, a gate insulating film 416, a gate insulating film 417, a gate insulating film 418 The transistor 480a includes an insulating film 402 and a gate electrode layer 401. is formed.

[0054] In FIG. 4, the boundary between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 The dotted lines indicate the surface of the oxide semiconductor stack 403. Depending on the material, film formation conditions, and heat treatment, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 may be formed. In some cases, the interface with the semiconductor layer 102 may become unclear. In some cases, a region that can be called a mixed region or mixed layer of the compound semiconductor layer is formed. The same applies to the interface between the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103.

[0055] In the oxide semiconductor stack 403 of the transistor 480a, the first oxide semiconductor layer 101 , the energy gaps of the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are not all the same and contain at least two different energy gaps.

[0056] When the oxide semiconductor stack 403 has a stacked structure of three or more layers, all of the oxide semiconductor layers The energy gaps may be different, or may be approximately the same. The oxide semiconductor stack 403 may include an oxide semiconductor layer having a groove.

[0057] The oxide semiconductor stack 403 (the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, The oxide semiconductor used for the third oxide semiconductor layer 103) is at least indium ( It is preferable that the material contains In (In) or zinc (Zn). It is particularly preferable that the material contains In and Zn. In addition, a stabilizer for reducing variations in the electrical characteristics of a transistor using the oxide is also provided. It is preferable to have gallium (Ga) as an additive in addition to these. It is preferable to have tin (Sn) as a riser. It is preferable that the alloy contains aluminum (A) as a stabilizer. It is preferred to have l).

[0058] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0059] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides Oxides such as In-Ga-Zn oxides, In-Al-Zn oxides, and In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides Oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxides and In-Hf-Ga-Zn oxides, which are oxides of the base metals oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn In-Hf-Zn based oxides and In-Hf-Al-Zn based oxides can be used.

[0060] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0061] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0062] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide with a molecular ratio or an oxide with a composition close to that.

[0063] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the following appropriate.

[0064] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0065] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The above condition is satisfied, and r can be set to 0.05, for example. The same is true for monsters.

[0066] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0067] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0068] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface of 0.1 nm or less.

[0069] Ra is defined in JIS B 0601:2001 (ISO4287:1997). It is a three-dimensional extension of the arithmetic mean roughness that is currently used to measure curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviations from the specified surface to the target surface" and is defined by formula (1).

[0070]

number

[0071] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 ) (the rectangular area defined by the four points (x2, y2)), and Z0 is the average height of the measurement surface. Ra is the strength of the AFM (Atomic Force Microscope). It can be evaluated using the OPE.

[0072] The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 of the oxide semiconductor stack 403 The third oxide semiconductor layer 103 is an oxide semiconductor layer containing crystals and having crystallinity (crystal The crystals in the crystalline oxide semiconductor layer can be aligned along the crystal axis. The orientation may be random or may have a certain orientation.

[0073] For example, the crystalline oxide semiconductor layer may be formed of an oxide semiconductor containing crystals having a c-axis approximately perpendicular to the surface. A nitride semiconductor layer can be used.

[0074] The oxide semiconductor layer including crystals having a c-axis approximately perpendicular to the surface does not have a single-crystal structure, but has a It is not an amorphous structure, but a crystalline oxide semiconductor with c-axis orientation (C Axis Aligned Crystalline Oxide Semiconductor; It is a membrane (also called CAAC-OS).

[0075] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure in which the amorphous phase contains crystalline and amorphous parts. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the amorphous part contained in the CAAC-OS film were The boundary between the crystal and the CAAC-OS film is not clear. Therefore, the CAAC-OS film has no grain boundary. The resulting decrease in electron mobility is suppressed.

[0076] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 10° to 5°.

[0077] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0078] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0079] Transistors using CAAC-OS films show fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0080] There are three methods for obtaining CAAC-OS films. The oxide semiconductor layer is formed at a temperature of 500°C or higher and the c-axis is oriented approximately perpendicular to the surface. The second method is to deposit a thin film and then heat it at a temperature between 200°C and 700°C. The third method is to form a thin film with the first layer, and then align the c-axis approximately perpendicular to the surface. After that, heat treatment is performed at 200°C to 700°C, and the second layer is formed on the surface. This is a method for vertically orienting the c-axis.

[0081] A first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 10 The thickness of the film 3 is 1 nm or more and 100 nm or less (preferably 5 nm or more and 30 nm or less). Sputtering method, MBE (Molecular Beam Epitaxy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition) The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 can be formed by a method such as a method for forming a thin film of a SiO 2 film. The oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are formed on the surface of the sputtering target. In contrast, a sputtering device is used to deposit films on multiple substrate surfaces set approximately perpendicular to the substrate. A film may be formed.

[0082] In a transistor including an oxide semiconductor layer, the energy gap of the oxide semiconductor layer For example, in a transistor using an oxide semiconductor layer, In a transistor, if the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, On the other hand, the energy gap of the oxide semiconductor layer is large. If the gate insulating film is thin, the off-state current can be reduced.

[0083] Oxide semiconductor stack 40 using multiple oxide semiconductor layers having different energy gaps 3, transistor 440a, transistor 440b, transistor The electrical characteristics of 480a can be controlled more precisely, and the desired electrical characteristics can be obtained by 440a, transistor 440b, and transistor 480a.

[0084] For example, in the oxide semiconductor stack 403 of the transistor 480a in FIG. The energy gap of the second oxide semiconductor layer 102 is set to be equal to that of the first oxide semiconductor layer 101 and the third oxide semiconductor layer 102. The energy gap of the first oxide semiconductor layer 103 is set to be smaller than that of the second oxide semiconductor layer 103. The energy gaps of the semiconductor layer 101 and the third oxide semiconductor layer 103 are approximately the same. It is possible.

[0085] Figure 4(C) shows the energy band diagram in the film thickness direction (between E1 and E2) in Figure 4(A). The transistor 480a has an energy band shown in FIG. The first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 1 However, if a buried channel is formed in the conduction band, it is preferable to select a material of Therefore, it is not necessary to have depressions in both the conduction band and the valence band as shown in Figure 4(C). For example, the energy band diagram may have a depression only in the conduction band. A configuration that allows obtaining an energy band diagram may also be used.

[0086] For example, the first oxide semiconductor layer 101 in the transistor 480a may be formed of In-Ga- Zn-based oxide film (energy gap 3.2 eV) as the second oxide semiconductor layer 102 is an In-Sn-Zn oxide film (energy gap 2.8 eV), and the third oxide semiconductor The layer 103 is an In-Ga-Zn oxide film (energy gap 3.2 eV). .

[0087] The three-layer oxide semiconductor stack 403 includes the first oxide semiconductor layer in the transistor 480a. The oxide semiconductor layer 101 is an In-Ga-Zn oxide film, and the second oxide semiconductor layer 10 The second oxide semiconductor layer 2 is an In-Zn oxide film, and the third oxide semiconductor layer 103 is an In-Ga-Zn a Ga—Zn-based oxide film as the first oxide semiconductor layer 101; The oxide semiconductor layer 102 is an In—Sn—Zn-based oxide film, and the third oxide semiconductor layer 103 is an In—Sn—Zn-based oxide film. The first oxide semiconductor layer 101 may be a stack of Ga—Zn-based oxide films. a Zn-based oxide film as the second oxide semiconductor layer 102; an In—Zn-based oxide film as the third oxide semiconductor layer 103; The semiconductor layer 103 may be a stack of Ga—Zn-based oxide films.

[0088] The second oxide semiconductor layer 102 having a small energy gap is The first oxide semiconductor layer 101 and the third oxide semiconductor layer 103 sandwich the insulating film. This can further reduce the off-state current (leakage current) of the transistor 480a. can be.

[0089] An example of a manufacturing method using the transistor 440a is shown in FIGS.

[0090] First, an oxide insulating film 436 is formed over a substrate 400 .

[0091] There is no significant limitation on the substrate that can be used for the substrate 400, but at least the substrate that can be used for the subsequent heat treatment For example, barium borosilicate glass Glass substrates such as glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, and surface treatment substrates. A single crystal semiconductor such as silicon or silicon carbide can also be used. Substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. Any of these substrates on which semiconductor elements are provided is called a substrate 400. It may also be used as.

[0092] Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device, a transistor including an oxide semiconductor stack 403 is formed over a flexible substrate. The gate 440a may be directly formed, or a gate including the oxide semiconductor stack 403 may be formed on another substrate. The transistor 440a may be fabricated, and then peeled off and transferred to a flexible substrate. In order to peel and transfer the transistor from the substrate to a flexible substrate, A release layer may be provided between the substrate 440a and the base 440b.

[0093] The oxide insulating film 436 is formed by a plasma CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide , gallium oxide, or a mixture of these materials.

[0094] The oxide insulating film 436 may have a single layer structure or a stacked layer structure. A silicon oxide film formed by sputtering is used.

[0095] Alternatively, a nitride insulating film may be provided between the oxide insulating film 436 and the substrate 400. The insulating film is made of silicon nitride or silicon oxynitride by plasma CVD or sputtering. It is formed using aluminum nitride, aluminum oxide nitride, or a mixture of these materials. It is possible.

[0096] Next, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 were formed over the oxide insulating film 436. A stack 493 of oxide semiconductor films made of oxide semiconductor films 92 is formed (see FIG. 2A).

[0097] The oxide insulating film 436 is in contact with the stack of oxide semiconductor films 493 (the stack of oxide semiconductor films 403). Therefore, there is oxygen in the film (bulk) in an amount exceeding the stoichiometric composition ratio. For example, when a silicon oxide film is used as the oxide insulating film 436, , SiO 2+α (where α>0). As a result, oxygen can be supplied to the oxide semiconductor film stack 493 (the oxide semiconductor stack 403). The oxide semiconductor film stack 493 (oxide semiconductor stack 4 03), oxygen vacancies in the film can be compensated for.

[0098] For example, the oxide insulating film 436 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed as an oxide semiconductor. By providing the insulating film 493 in contact with the oxide semiconductor stack 403, the oxide insulating film 493 Oxygen is supplied from the insulating film 436 to the stacked oxide semiconductor film 493 (the stacked oxide semiconductor film 403). The oxide semiconductor film stack 493 (oxide semiconductor stack 403) and the oxide insulating film The insulating film 436 is at least partially in contact with the oxide semiconductor film. Oxygen may be supplied to the stack 493 (the oxide semiconductor stack 403).

[0099] The stack of oxide semiconductor films 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 1 In the step of forming the oxide semiconductor film stack 493 (first oxide semiconductor film 191 and the second oxide semiconductor film 192) to prevent hydrogen or water from being contained in the second oxide semiconductor film 193. 4, a stack of oxide semiconductor films 493 (a first oxide semiconductor film 191 and a second oxide semiconductor film As a pretreatment for forming the oxide insulating film 43 in the preheating chamber of the sputtering equipment, The substrate on which the oxide insulating film 436 is formed is preheated to remove hydrogen, moisture, etc. adsorbed on the substrate and the oxide insulating film 436. It is preferable to desorb and exhaust the impurities. Iopumps are preferred.

[0100] The oxide insulating film 436 includes the stack of oxide semiconductor films 493 (the stack of oxide semiconductor films 403). The contact region may be subjected to a planarization treatment. However, polishing processes (e.g., chemical mechanical polishing) Polishing (CMP), dry etching, and plasma treatment are used. It is possible.

[0101] The plasma treatment may be, for example, a reverse plasma treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma near the substrate, thereby modifying the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the oxide insulating film 436 is subjected to the etching, powdery substances (particles, dust, etc.) attached to the surface of the oxide insulating film 436 are removed. (also called) can be removed.

[0102] As a planarization process, polishing, dry etching, and plasma treatment may be performed multiple times. In addition, when the steps are combined, there is no particular limitation on the order of the steps. The thickness is not limited to a specific value and may be set appropriately depending on the unevenness of the surface of the oxide insulating film 436.

[0103] Note that the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed using oxygen. It is formed by sputtering under conditions where a large amount of oxygen is contained (for example, in an atmosphere of 100% oxygen). The oxide semiconductor is preferably formed in a crystalline state. The film contains a region in which the oxygen content is excessive relative to the stoichiometric composition ratio. preferable.

[0104] In this embodiment, the first oxide semiconductor film 191 is formed by a sputtering method. For example, the target for this purpose is a target having a composition ratio of In:Sn:Zn in atomic ratio. , 1:2:2, 2:1:3, 1:1:1, or 20:45:35, etc. Using the get, an In—Sn—Zn—O film is formed.

[0105] In this embodiment, the second oxide semiconductor film 192 is formed by a sputtering method. For example, the target for this purpose is a composition ratio of In2O3:Ga2O3:Zn. Using an oxide target with a molar ratio of 0 = 1:1:2, an In-Ga-Zn oxide film was formed. The material and composition of the target are not limited to those mentioned above, and examples thereof include In2O3:G A metal oxide target of a2O3:ZnO=1:1:1 [molar ratio] may also be used.

[0106] The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. By using a metal oxide target with a high filling rate, the film is formed. In addition, the oxide semiconductor film can be a dense film.

[0107] The first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed by a sintering furnace. The sputtering gas is a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It is preferable to use

[0108] The substrate is held in a film-forming chamber that is kept in a reduced pressure state, and the remaining moisture in the film-forming chamber is removed. The sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the target. 0, a stack of oxide semiconductor films 493 (first oxide semiconductor film 191 and second oxide semiconductor film To remove residual moisture in the deposition chamber, an adsorption type vacuum pump is used. For example, cryopumps, ion pumps, and titanium sublimation pumps are used. As the exhaust means, a turbo molecular pump with a cold trap added is preferable. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms, water ( Compounds containing hydrogen atoms (and more preferably compounds containing carbon atoms) such as HO are exhausted. Therefore, the stack 493 of oxide semiconductor films formed in the film formation chamber (first oxide semiconductor film The concentration of impurities contained in the oxide semiconductor film 191 and the second oxide semiconductor film 192 can be reduced.

[0109] In addition, a stack 493 of the oxide insulating film 436 and the oxide semiconductor film (first oxide semiconductor film 191 and the second oxide semiconductor film 192) are preferably formed successively without being exposed to the air. The stack 493 of the oxide insulating film 436 and the oxide semiconductor film (the first oxide semiconductor film 191 and When the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed in succession without exposure to the air, an oxide insulating film is formed. This can prevent impurities such as hydrogen and moisture from being adsorbed onto the surface of the film 436 .

[0110] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions contained in the sputtering target cleave from the ab plane, forming a -b Peels off as flat or pellet-shaped sputtered particles with surfaces parallel to the plane In this case, the plate-like sputtered particles may be transferred to the substrate while maintaining their crystalline state. By reaching the plate, a CAAC-OS film can be formed.

[0111] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0112] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0113] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0114] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0115] As an example of a sputtering target, an In-Ga-Zn-O compound target is The following are the results:

[0116] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. After that, it is heat-treated at a temperature between 1000℃ and 1500℃ to form polycrystalline In-G The target is a-Zn-O compound, where X, Y, and Z are any positive numbers. The predetermined mole ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2 mo The powder type and mixing ratio depend on the sputtering process to be produced. The value may be changed as appropriate depending on the target.

[0117] The stack of oxide semiconductor films 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 1 92) by a photolithography process to form an island-shaped oxide semiconductor stack 403 (first oxide semiconductor The resulting semiconductor layer is processed into a conductor layer 101 and a second oxide semiconductor layer 102 (see FIG. 2B).

[0118] In addition, a resist mask for forming an island-shaped oxide semiconductor stack 403 was formed by inkjet printing. If the resist mask is formed by the ink-jet method, a photomask can be used. Since no external wiring is used, manufacturing costs can be reduced.

[0119] Note that the etching of the oxide semiconductor film may be dry etching or wet etching. For example, an etching method used for wet etching of an oxide semiconductor film may be used. The cleaning solution can be a mixture of phosphoric acid, acetic acid, and nitric acid. O07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0120] In this embodiment, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed of the same Since the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are formed by etching using a mask, The oxide semiconductor layer 102 has the same shape as the oxide semiconductor layer 102, with the end portions of the side surfaces aligned. In the conductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 The sides (ends) of the are exposed.

[0121] In addition, excessive hydrogen (water or hydrogen) is added to the oxide semiconductor stack 403 (the oxide semiconductor film stack 493). Heat treatment may be carried out to remove (dehydrate or dehydrogenate) the acid groups (including the acid groups). The treatment temperature is between 300°C and 700°C, or below the distortion point of the substrate. This can be done under reduced pressure or a nitrogen atmosphere. The substrate is placed in a furnace, and the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) is Heat treatment is carried out at 450°C for 1 hour in a nitrogen atmosphere.

[0122] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0123] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 to 700°C. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0124] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not contained. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than 1 ppm.

[0125] In addition, after the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) is heated by heat treatment, In the same furnace, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS ( The moisture content measured using a cavity ring-down laser spectroscopy (CDR) dew point meter is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably 10 It is also possible to introduce oxygen gas or nitrous oxide gas containing water, hydrogen, etc. It is preferable that the oxygen gas or the dioxide gas introduced into the heat treatment device is not contained. The purity of the nitrogen gas is 6N or more, preferably 7N or more (i.e., oxygen gas or nitrous oxide gas). It is preferable to keep the impurity concentration in the gas to 1 ppm or less, preferably 0.1 ppm or less. Impurities due to dehydration or dehydrogenation treatment by the action of oxygen gas or nitrous oxide gas The oxide, which is the main component material of the oxide semiconductor, was also reduced during the removal process. By supplying the element, the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) is formed. It can be highly purified and electrically made into type I (intrinsic).

[0126] Note that the heat treatment for dehydration or dehydrogenation is performed after the stack 493 of oxide semiconductor films (first oxide film) is removed. After the formation of the first oxide semiconductor film 191 and the second oxide semiconductor film 192, and before the formation of the insulating film 407 In this case, the step may be performed at any timing in the manufacturing process of the transistor 440a. For example, a stack of oxide semiconductor films 493 (a first oxide semiconductor film 191 and a second oxide semiconductor film 192) After the formation of the oxide semiconductor layer 192, or after the formation of the island-shaped oxide semiconductor stack 403 (first oxide semiconductor layer 10 This can be performed after the first and second oxide semiconductor layers 102) are formed.

[0127] The heat treatment for dehydration or dehydrogenation may be carried out multiple times, or may be carried out in combination with other heat treatments. For example, after the first oxide semiconductor film 191 is formed and after the second oxide semiconductor film 19 2 After formation, heat treatment may be carried out twice.

[0128] The heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor stack 403 (first oxide semiconductor Before being processed into islands as the oxide semiconductor layer 101 and the second oxide semiconductor layer 102, The stack 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 192) is an oxide semiconductor film. If the heat treatment is performed while the insulating film 436 is covering the oxide insulating film 436, oxygen contained in the oxide insulating film 436 is removed by the heat treatment. This is preferable because it can prevent the release of the hydroxybenzoates.

[0129] Next, a source electrode layer and a drain electrode layer (the same layer as this) are formed on the oxide semiconductor stack 403. The conductive film is formed to be a conductive layer (including wirings formed by the method described above). As a conductive film used for the source electrode layer and the drain electrode layer, for example, A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements In addition, a metal film such as Al or Cu may be used as the upper or lower side. Both are made of high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film , a molybdenum nitride film, or a tungsten nitride film) may be laminated. The conductive film used for the source electrode layer and the drain electrode layer is formed of a conductive metal oxide. Conductive metal oxides such as indium oxide (In2O3) and tin oxide (SnO 2), zinc oxide (ZnO), indium oxide tin oxide (In2O3-SnO2), indium oxide Indium zinc oxide (In2O3-ZnO) or silicon oxide on these metal oxide materials can be used.

[0130] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed. After forming the source electrode layer 405a and the drain electrode layer 405b by this method, a resist mask In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are A tungsten film having a thickness of 10 nm is formed. In this way, the source electrode layer 405a and the drain electrode layer 405b are formed. If the electrode layer 405b is thin, the coverage of the gate insulating film 402 formed thereon is good. In addition, when a dopant is introduced into the oxide semiconductor stack 403 to form a low-resistance region, , passing through the source electrode layer 405a and the drain electrode layer 405b. Dopants can also be introduced into the oxide semiconductor stack 403 below the drain electrode layer 405b. do.

[0131] In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor Since the side surfaces (ends) of the layer 102 are exposed, the source electrode layer 405a and the drain electrode layer 4 05b is formed on part of the side surfaces of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. It is formed so as to be in contact with the

[0132] Next, the oxide semiconductor stack 403, the source electrode layer 405a, and the drain electrode layer 405b A gate insulating film 402 is formed to cover the gate insulating film 402 (see FIG. 2C).

[0133] In order to improve the coverage of the gate insulating film 402, the oxide semiconductor stack 403 and the The above-described planarization treatment may also be performed on the surfaces of the source electrode layer 405a and the drain electrode layer 405b. In particular, when a thin insulating film is used as the gate insulating film 402, the oxide semiconductor stack 40 3. The surfaces of the source electrode layer 405a and the drain electrode layer 405b have good flatness. is preferred.

[0134] The thickness of the gate insulating film 402 is set to 1 nm or more and 20 nm or less, and is formed by sputtering or MBE. The method, CVD method, pulsed laser deposition method, ALD method, etc. can be used as appropriate. The insulating film 402 is formed by forming a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. The film may be formed using a sputtering device that performs film formation in a set state.

[0135] The gate insulating film 402 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, Silicon nitride film, silicon oxynitride film, aluminum oxynitride film, or silicon nitride oxide film The gate insulating film 402 can be formed using an oxide semiconductor film. It is preferable that the contact portion contains oxygen. Preferably, there is at least a stoichiometric amount of oxygen present in the solution (in the solution), For example, when a silicon oxide film is used as the gate insulating film 402, SiO 2+α ( In this embodiment, the gate insulating film 402 is made of SiO 2+α (where α>0) is used. This silicon oxide film is used as the gate insulating film. By using the oxide semiconductor layer 402, oxygen can be supplied to the oxide semiconductor stack 403, and the characteristics can be improved. Furthermore, the gate insulating film 402 can improve the characteristics of the transistor to be manufactured. It is preferable to form the gate insulating film 402 taking into consideration the size and step coverage of the gate insulating film 402 .

[0136] The gate insulating film 402 may be made of hafnium oxide, yttrium oxide, or hafnium. Silicate (HfSi x O y x>0, y>0), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and high-k materials such as lanthanum oxide are used to Furthermore, the gate insulating film 402 may have a single layer structure or a multilayer structure. It can also be made as a structure.

[0137] Then, the gate electrode layer 401 is formed by plasma CVD or sputtering. The gate electrode layer 401 is formed on the insulating film 402. The gate electrode layer 401 is made of molybdenum, titanium, tantalum, or tantalum. Metallic materials such as tungsten, aluminum, copper, chromium, neodymium, scandium, etc. The gate electrode layer 401 can be formed using an alloy material containing these as main components. semiconductor films, such as polycrystalline silicon films doped with impurity elements such as phosphorus; A silicide film such as nickel silicide may be used. The gate electrode layer 401 has a single layer structure. Alternatively, a laminated structure may be used.

[0138] The gate electrode layer 401 is made of an indium tin oxide or an indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon oxide Conductive materials such as indium tin oxide doped with the above-mentioned conductive material can also be used. It is also possible to use a laminated structure of an electrically conductive material and the above-mentioned metal material.

[0139] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 402 is made of a metal oxide containing nitrogen. oxides, specifically, nitrogen-containing In-Ga-Zn-O films and nitrogen-containing In-Sn-O films , In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, and Sn- O film, In-O film containing nitrogen, and metal nitride film (InN, SnN, etc.) can be used. These films have a work function of 5 electron volts or more, preferably 5.5 electron volts or more, When used as a gate electrode layer, the threshold voltage of the transistor is increased. This makes it possible to realize a so-called normally-off switching element.

[0140] Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 2D). A plurality of oxide semiconductor layers having different energy gaps (first oxide semiconductor layer 101 The oxide semiconductor stack 403 using the first oxide semiconductor layer 102 and the second oxide semiconductor layer 103 is used. This allows for more precise control of the electrical characteristics of the transistors 440a and 440b. This allows the transistors 440a and 440b to have desired electrical characteristics.

[0141] Next, the oxide semiconductor stack 403, the source electrode layer 405a, the drain electrode layer 405b, and the gate electrode layer 405c are An insulating film 407 is formed on the gate insulating film 402 and the gate electrode layer 401 (see FIG. 2(E)). .

[0142] The insulating film 407 is formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. The insulating film 407 is typically a silicon oxide film, a silicon oxynitride film, or a silicon oxynitride film. For example, an inorganic insulating film such as an aluminum oxide film or a gallium oxide film can be used.

[0143] The insulating film 407 may be an aluminum oxide film, a hafnium oxide film, or a magnesium oxide film. film, zirconium oxide film, lanthanum oxide film, barium oxide film, or metal nitride film (e.g. , aluminum nitride film) can also be used.

[0144] The insulating film 407 may be a single layer or a laminated layer, and may be, for example, a silicon oxide film and an aluminum oxide film. A stack of the above can be used.

[0145] The insulating film 407 is formed by mixing impurities such as water and hydrogen into the insulating film 407 by a method such as sputtering. It is preferable to form the insulating film 407 by using a method other than the above. If the insulating film in contact with the conductive stack 403 is a film containing excess oxygen, the oxide semiconductor stack 40 This is preferred because it provides a source of oxygen to 3.

[0146] In this embodiment, a silicon oxide film having a thickness of 100 nm is deposited as the insulating film 407 by sputtering. The silicon oxide film is formed by sputtering. Typically, under an atmosphere of argon, oxygen, or a mixture of rare gases and oxygen. This can be done.

[0147] In order to remove residual moisture in the deposition chamber of the insulating film 407, similarly to the deposition of the oxide semiconductor film, It is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating film 407 formed in the film formation chamber evacuated using a pump can be reduced. In addition, as an exhaust means for removing residual moisture in the film forming chamber of the insulating film 407, a turbo A molecular pump with a cold trap added may also be used.

[0148] The insulating film 407 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or hydrogen. It is preferable to use a high-purity gas from which impurities such as oxides have been removed.

[0149] As shown in FIG. 3B, an insulating film provided as an interlayer insulating film over the transistor 440d As a film, an insulating film 416 is formed between the transistor 440d and the insulating film 407, and an interlayer insulating film The insulating film 416 may be formed using a material and a method similar to those of the insulating film 407. For example, an aluminum oxide film can be used as the insulating film 416. By using a silicon oxide film as 407, the insulating film provided on the transistor 440d can be A laminate of an aluminum oxide film and a silicon oxide film can be used. The transistor 440d is formed by etching the gate insulating film 402 using the gate electrode layer 401 as a mask. The oxide semiconductor stack 403 is partially exposed by etching. In this example, the insulating film 416 is provided so as to be in contact with the insulating film 416 .

[0150] The insulating film 407 and the insulating film 416 can be formed over the oxide semiconductor stack 403. The aluminum oxide film that can be formed is permeable to both impurities such as hydrogen and moisture, and oxygen. It has a high blocking effect that prevents light from passing through.

[0151] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The inclusion of impurities such as moisture in the oxide semiconductor stack 403 and the inclusion of the main component constituting the oxide semiconductor It functions as a protective film that prevents oxygen, which is a decomposition material, from being released from the oxide semiconductor stack 403. .

[0152] In addition, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistor. The planarized insulating film may be made of organic materials such as polyimide, acrylic, or benzocyclobutene resin. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. By laminating multiple insulating films made of these materials, A planarizing insulating film may be formed.

[0153] In addition, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating film 407. and a wiring layer electrically connected to the source electrode layer 405a and the drain electrode layer 405b in the openings. The wiring layer may be used to connect to other transistors to form various circuits. It is possible.

[0154] The source electrode layer 405a and the drain electrode layer 405b are The etching process for forming the opening reaching the layer 405b results in partial over-etching. The source electrode layer and the drain electrode layer may have a stacked structure, and the etching process may be performed when forming an opening. A conductive film that also functions as a gate electrode layer is provided as a source electrode layer and a drain electrode layer. It is possible.

[0155] As shown in FIG. 3A, the transistor 440c has a source electrode layer and a drain electrode layer stacked thereon. This is an example of a layer structure, and the source electrode layer is a source electrode layer 404a and a source electrode layer 40 5a, the drain electrode layer 404b and the drain electrode layer 405b are stacked as the drain electrode layer. As in the transistor 440c, the gate insulating film 402, the insulating film 407, and The source electrode layer 405a and the drain electrode layer 405b are connected to the source electrode layer 404a and the drain electrode layer 404b. An opening is formed to reach the source electrode layer 404a and the drain electrode layer 404b. Alternatively, wiring layers 465a and 465b may be formed to electrically connect to the wiring layers 465a and 465b.

[0156] In the transistor 440c, the source electrode layer 404a and the drain electrode layer 404b are formed as openings. The source electrode layer 404a and the drain electrode layer 404b also function as an etching stopper during the formation of the source electrode layer 404a. The source electrode layer 405a is a tungsten film or a tantalum nitride film. The drain electrode layer 405b can be formed using a copper film, an aluminum film, or the like. The source electrode layer 404a, the source electrode layer 405a, the drain electrode layer 404b, and the drain electrode layer 405c can be formed. When the thickness of the layered layer of the drain electrode layer 405b is set to about 5 nm or more and 15 nm or less, This can improve the coverage of the gate insulating film 402.

[0157] The wiring layer 465a and the wiring layer 465b are connected to the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b. The wiring layer 405b can be formed using the same material and method as the wiring layer 405b. 465a, and a wiring layer 465b, which is a laminate of a tantalum nitride film and a copper film, or a tantalum nitride film and A lamination with a tungsten film can be used.

[0158] A sidewall insulating layer may be provided on the side surface of the gate electrode layer 401. After forming an insulating film to cover the electrode layer 401, this is subjected to RIE (Reactive Ion Etching). The insulating film is processed by anisotropic etching using reactive ion etching (RIE). Then, a sidewall insulating layer may be formed in a self-aligned manner on the sidewall of the gate electrode layer 401. The insulating film is not particularly limited, but for example, TEOS (Tetraethylorthosilicate) o-Silicate) or silane, etc., and oxygen or nitrous oxide, etc. The insulating film can be formed by thermal CVD or by using silicon oxide, which has good step coverage. Formed by methods such as Zuma CVD, atmospheric pressure CVD, bias ECRCVD, and sputtering In addition, low temperature oxidation (LTO) Silicon oxide formed by a deposition method may also be used.

[0159] The oxide semiconductor stack 403, which is highly purified and has oxygen vacancies filled, is free from impurities such as hydrogen and water. The hydrogen concentration in the oxide semiconductor stack 403 was 5×10 19 atom s / cm 3 Less than or equal to 5 x 10 18 atoms / cm 3 The oxides are as follows: The hydrogen concentration in the semiconductor stack 403 was measured by secondary ion mass spectroscopy (SIMS). It is measured by ion mass spectrometry (Ion Mass Spectrometry).

[0160] The oxide film produced by this embodiment is highly purified and contains excess oxygen to compensate for the oxygen deficiency. The transistor 440a using the compound semiconductor stack 403 has a current value in an off state (off voltage The current value was set at 100 zA / μm (1 zA (zeptoampere)) per μm of channel width at room temperature. ) is 1×10 -21 A) or less, preferably 10 zA / μm or less, more preferably 1 zA / It is possible to reduce the intensity to a level of 100 yA / μm or less, more preferably to a level of 100 yA / μm or less.

[0161] As described above, semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption can be provided. can be provided.

[0162] (Embodiment 2) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts as those in the above embodiment or parts and steps having similar functions are the same as those in the above embodiment. The same operations can be performed as in the first embodiment, and the repeated explanation will be omitted. The literal meaning is omitted.

[0163] In this embodiment, in a manufacturing method of a semiconductor device according to the disclosed invention, The oxide semiconductor stack that has been subjected to the oxidation treatment is subjected to oxidation treatment with oxygen (at least oxygen radicals, oxygen atoms, and oxygen atoms). An example of supplying oxygen into the film by introducing oxygen ions (including either ions or non-ions) will be shown.

[0164] By the dehydration or dehydrogenation treatment, oxygen, which is the main component material of the oxide semiconductor, is simultaneously In the oxide semiconductor stack, oxygen may be released from the region where oxygen is released, resulting in a decrease in the amount of oxygen. Oxygen vacancies exist in the donor region, which cause fluctuations in the electrical characteristics of the transistor. -level occurs.

[0165] Therefore, it is preferable to supply oxygen to the oxide semiconductor stack that has been subjected to dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor stack, oxygen vacancies in the film can be compensated for. By using the oxide semiconductor stack in a transistor, a transistor caused by oxygen vacancies can be prevented. By reducing the variation in the threshold voltage Vth of the transistor and the threshold voltage shift ΔVth, In addition, the threshold voltage can be shifted in the positive direction to make the transistor normally off. You can also do this.

[0166] FIG. 5A corresponds to FIG. 2C, and shows a substrate 400 provided with an oxide insulating film 436. A first oxide semiconductor layer 101 and a second oxide semiconductor layer 102 having different energy gaps are formed on the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. The oxide semiconductor stack 403 including the layer 102, the source electrode layer 405a, and the drain electrode layer 405 b, a gate insulating film 402 is formed.

[0167] Next, oxygen 431 (at least oxygen radicals, oxygen atoms, and oxygen atoms) is added to the oxide semiconductor stack 403. ions) to form a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102. The oxygen-excess regions 111 and 112 are formed in the oxide semiconductor stack 403 including the oxide semiconductor layer 102. (See FIG. 5(B)).

[0168] The oxygen-excess regions 111 and 112 have a stoichiometric composition when the oxide semiconductor is in a crystalline state. The region includes at least a portion where the oxygen content is in excess of the ratio. The oxygen 431 supplied to the excess regions 111 and 112 causes the first oxide semiconductor layer 101 and oxygen vacancies present in the oxide semiconductor stack 403 including the second oxide semiconductor layer 102. It can be compensated.

[0169] On the oxide semiconductor stack 403 having the oxygen excess regions 111 and 112 and the gate insulating film 402 A gate electrode layer 401 is formed, and a transistor 430 is manufactured (see FIG. 5C).

[0170] Oxygen is introduced into the oxide semiconductor stack 403 that has been subjected to dehydration or dehydrogenation treatment. By supplying the oxide semiconductor layer 403, the oxide semiconductor layer 403 is highly purified and becomes an i-type (intrinsic) layer. A transistor having a highly purified and i-type (intrinsic) oxide semiconductor stack 403 can be obtained. The change in electrical characteristics of the star 430 is suppressed, and the star 430 is electrically stable.

[0171] The oxygen introduction method includes ion implantation, ion doping, and plasma immersion. On-implantation methods, plasma treatment, etc. can be used.

[0172] In the oxygen introduction step, when oxygen is introduced into the oxide semiconductor stack 403, 3 or through other films such as the gate insulating film 402 and the insulating film 407. Oxygen may be introduced into the oxide semiconductor stack 403. When oxygen is introduced through another film, Ion implantation method, ion doping method, plasma immersion ion implantation method However, when oxygen is directly introduced into the exposed oxide semiconductor stack 403, Alternatively, plasma treatment or the like can be used.

[0173] Oxygen can be introduced into the oxide semiconductor stack 403 after dehydration or dehydrogenation treatment. The oxide semiconductor stack that has been subjected to the dehydration or dehydrogenation treatment may be a stack of oxide semiconductor layers. Oxygen may be introduced into 403 multiple times.

[0174] For example, in Embodiment 1, oxygen is introduced into the oxide semiconductor stack 403 by The source electrode layer 405 is formed on the stack of the oxide semiconductor films 493 or the stack of the oxide semiconductor films 403. a) After forming the drain electrode layer 405b, after forming the gate insulating film 402, This can be performed after the formation of the insulating film 416 or after the formation of the insulating film 407.

[0175] In addition, oxygen is introduced into the oxygen-excess regions 111 and 112 in the oxide semiconductor stack 403. The oxygen concentration introduced by the process is 1×10 18 atoms / cm 3 5x10 or more 21 at oms / cm 3 It is preferable that:

[0176] In an oxide semiconductor, oxygen is one of the main components. The oxygen concentration in the conductor laminate 403 was measured by SIMS (Secondary Ion Mass Spectroscopy). It is difficult to accurately estimate the radiation intensity using methods such as spectroscopic methods. It is difficult to determine whether oxygen has been intentionally added to the oxide semiconductor stack 403. It can be said that.

[0177] By the way, oxygen has 17 O and 18 There are isotopes such as O, and their existence in nature The respective proportions of oxygen atoms are known to be approximately 0.037% and 0.204% of the total oxygen atoms. That is, when these isotopes are intentionally added to the oxide semiconductor stack 403, The concentrations of these isotopes can be estimated by methods such as SIMS. By measuring the oxygen concentration in the oxide semiconductor stack 403, it is possible to estimate the oxygen concentration more accurately. Therefore, by measuring the concentrations of these elements, it is possible to determine whether the oxide semiconductor stack 403 is intentionally formed. Alternatively, it may be determined whether oxygen has been added intentionally.

[0178] After oxygen is introduced into the oxide semiconductor film, heat treatment is preferably performed.

[0179] As in the transistor 430 of this embodiment, oxygen is directly introduced into the oxide semiconductor stack 403. In this case, the oxide insulating film 436 in contact with the oxide semiconductor stack 403 and the gate insulating film 402 The film does not necessarily contain a large amount of oxygen. In order to prevent desorption from the layer 403 and to prevent impurities containing hydrogen such as hydrogen and water from being released from the oxide semiconductor The layer 403 is shielded from impurities containing hydrogen, such as oxygen, hydrogen, and water, so that they do not re-enter the layer 403. It is preferable to provide a film with a high blocking effect as the insulating film 407. For example, Oxidation with a high blocking effect against both impurities such as hydrogen and water, and oxygen. It is preferable to use an aluminum film or the like.

[0180] Of course, the oxide insulating film 436 and the gate insulating film 402 in contact with the oxide semiconductor film are formed by Furthermore, oxygen is directly introduced into the oxide semiconductor stack 403, and oxygen is supplied by multiple oxygen supply methods. You may also practice law.

[0181] In this embodiment, oxygen is introduced into the oxide semiconductor stack 403 as an example. The introduction of the element was performed on the gate insulating film 402, the oxide insulating film 436, and the oxide semiconductor stack 403. The insulating film 416, the insulating film 407, or the like may be formed. Oxygen is introduced into the insulating film 402, the oxide insulating film 436, the insulating film 416, and the insulating film 407. By providing an excess of oxygen, oxygen can be supplied to the oxide semiconductor stack 403. Cut.

[0182] As described above, a semiconductor device using an oxide semiconductor stack having stable electrical characteristics is provided. Therefore, a highly reliable semiconductor device can be provided.

[0183] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0184] (Embodiment 3) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts as those in the above embodiment or parts and steps having similar functions are the same as those in the above embodiment. The same operations can be performed as in the first embodiment, and the repeated explanation will be omitted. The literal meaning is omitted.

[0185] In this embodiment, in a method for manufacturing a semiconductor device according to the disclosed invention, This is an example of forming a low-resistance region in a layer. The low-resistance region is formed by changing the conductivity of the oxide semiconductor stack. The layer can be formed by introducing an impurity (also called a dopant) that causes the layer to be in a non-transparent state.

[0186] FIG. 6A corresponds to FIG. 2D and shows a substrate 400 provided with an oxide insulating film 436. A first oxide semiconductor layer 101 and a second oxide semiconductor layer 102 having different energy gaps are formed on the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. The oxide semiconductor stack 403 including the layer 102, the source electrode layer 405a, and the drain electrode layer 405 b, a gate insulating film 402 and a gate electrode layer 401 are formed.

[0187] Next, a gate insulating film 4 is formed on the oxide semiconductor stack 403 using the gate electrode layer 401 as a mask. 02, the dopant 421 passes through the source electrode layer 405a and the drain electrode layer 405b. is selectively introduced to form low resistance regions 121a, 121b, 122a, and 122b.

[0188] In this embodiment, the source electrode layer 405a and the drain electrode layer 405b are formed as thin films. Therefore, the oxide semiconductor stack 403 under the source electrode layer 405a and the drain electrode layer 405b The dopant 421 is introduced into the low resistance regions 121a, 121b, 122a, and 122b. An example of the generated data is shown below.

[0189] The thicknesses of the source electrode layer 405a and the drain electrode layer 405b and the introduction of the dopant 421 are Depending on the conditions, the oxide semiconductor under the source electrode layer 405a and the drain electrode layer 405b If the dopant 421 is not introduced into the stack 403, even if it is introduced, the concentration is low and the source voltage A region with a higher resistance than the low-resistance region other than the region under the electrode layer 405a or the drain electrode layer 405b In addition, depending on the conditions for introducing the dopant 421, the first oxide semiconductor The dopant 421 is introduced only into the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102. When a region is formed, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 There may be a dopant concentration distribution.

[0190] The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor stack 403. Panto 421 includes group 15 elements (typically phosphorus (P), arsenic (As), and ammonium). Sb), boron (B), aluminum (Al), nitrogen (N), argon (Ar ), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (C l), titanium (Ti), and zinc (Zn) are used. can be done.

[0191] The dopant 421 is implanted into the insulating film 407, the source electrode layer 405a, and the drain electrode layer 405b. The dopant 421 passes through the oxide electrode layer 405b and is introduced into the oxide semiconductor stack 403. The introduction methods include ion implantation, ion doping, and plasma immersion ion implantation. In this case, the dopant 421 is It is preferable to use ions of fluoride or chloride.

[0192] The dopant 421 introduction process is performed by adjusting the implantation conditions such as the acceleration voltage and the dose amount, and the insulating layer through which the dopant 421 passes. The thickness of the insulating film 407 may be appropriately set and controlled. Boron is used as the dopant, and boron ions are implanted by ion implantation. The dose of 21 is 1×10 13 ions / cm 2 5x10 or more 16 ions / cm 2 below This can be done as follows.

[0193] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0194] The dopant 421 may be introduced while the substrate 400 is heated.

[0195] Note that the process of introducing the dopant 421 into the oxide semiconductor stack 403 may be performed multiple times. In addition, a plurality of types of dopants may be used.

[0196] After the introduction of the dopant 421, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be performed.

[0197] When the oxide semiconductor stack 403 is a crystalline oxide semiconductor film, the dopant 421 is introduced. In this case, the dopant 421 may be partially amorphous. By performing this treatment, the crystallinity of the oxide semiconductor stack 403 can be restored.

[0198] Therefore, in the oxide semiconductor stack 403, the low-resistance regions 121c are sandwiched between the channel formation region 121c. The first oxide semiconductor layer 101 provided with the first and second oxide semiconductor layers 121a and 121b and the channel formation region 12 a second oxide semiconductor layer 102 in which low-resistance regions 122a and 122b are provided with a second oxide semiconductor layer 102 and a second oxide semiconductor layer 102c sandwiched therebetween; is formed.

[0199] Through the above steps, the transistor 420 of this embodiment is manufactured (see FIG. 6B).

[0200] In addition, like the transistor 440d described in Embodiment 1, the gate insulating film 402 The oxide semiconductor stack 403 is partially exposed by etching using the electrode layer 401 as a mask. In the transistor contacting the insulating film 416, a dopant is introduced to form a low resistance region. A transistor 425 having the above structure is shown in FIG.

[0201] The transistor 425 is formed by introducing dopants using the gate electrode layer 401 as a mask. The low resistance regions 121a, 121b, 122a, and 122c are disposed on either side of the hole formation regions 121c and 122c. 22b. Also, a source electrode layer through which dopants are introduced, The drain electrode layer may also contain dopants. The dopant is also introduced into the source electrode layer and the drain electrode layer, and the source electrode layer 4 containing the dopant 15a, which is an example of a drain electrode layer 415b containing a dopant.

[0202] Low resistance regions 121a and 121b are provided on either side of a channel formation region 121c in the channel length direction. The first oxide semiconductor layer 101 and the low-resistance region 122c are sandwiched between the first oxide semiconductor layer 101 and the low-resistance region 122b. and a second oxide semiconductor layer 102 on which the oxide semiconductor layers 122a and 122b are provided. 403, transistor 420 and transistor 425 have on-characteristics (e.g., For example, the on-state current and field effect mobility are high, enabling high-speed operation and high-speed response.

[0203] In addition, a dopant is introduced into the transistor 430 having the oxygen excess region described in Embodiment 2. FIG. 6C shows a transistor 423 in which a low-resistance region is formed by inserting a gate insulating film.

[0204] The transistor 423 has an oxygen excess region 111, similar to the transistor 430 in FIG. a first oxide semiconductor layer 101 including an oxygen-excess region 112; In the transistor provided with the oxide semiconductor stack having the layer 102, the gate electrode layer 4 A dopant is introduced using O1 as a mask to form a channel forming region 121c containing excess oxygen. Low resistance regions 121d, 121e, and 122c containing dopants and excess oxygen are provided between the low resistance regions 121d, 121e, and 122c. 22d, 122e, and low resistance regions 121a, 121b, 122a, 122b, 122c, 122d, 122e containing dopants. It is produced by forming 2b.

[0205] The channel forming region 121c is sandwiched between low resistance regions 121d, 121e, and 121f in the channel length direction. The first oxide semiconductor layer 101 provided with the gate insulating film 21a and the gate insulating film 121b, and the channel formation region 122 The second oxide film is provided with low resistance regions 122d, 122e, 122a, and 122b on both sides of the oxide film. The oxide semiconductor stack 403 including the oxide semiconductor layer 102 423 has high on-state characteristics (e.g., on-state current and field-effect mobility), high-speed operation, and high-speed response. This becomes possible.

[0206] Furthermore, as in the transistor 480a described in Embodiment 1, the oxide semiconductor stack 403 In a three-layer transistor, oxygen and dopants are introduced to form an oxygen-excess region and a low-resistance region. A transistor 480b with a resistor region formed therein is shown in FIG.

[0207] The transistor 480b includes a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, Oxygen is introduced into the oxide semiconductor stack 403 including the third oxide semiconductor layer 103 to form an oxygen permeation layer. After forming the gate electrode layer 401, the dopant is applied using the gate electrode layer 401 as a mask. The oxygen-excess channel forming regions 121c, 122c, and 123c are sandwiched between the channels. The low resistance regions 121d, 121e, 122d, and 122e containing dopants and excess oxygen are e, 123d, and 123e, and low resistance regions 121a, 121b, and 122a containing dopants. , 122b, 123a, and 123b.

[0208] The channel forming region 121c is sandwiched between low resistance regions 121d, 121e, and 121f in the channel length direction. The first oxide semiconductor layer 101 provided with the gate insulating film 21a and the gate insulating film 121b, and the channel formation region 122 The second oxide film is provided with low resistance regions 122d, 122e, 122a, and 122b on both sides of the oxide film. The compound semiconductor layer 102 and the low resistance regions 123d and 123e sandwiching the channel forming region 123c. and a third oxide semiconductor layer 103 on which the oxide semiconductor layers 123a and 123b are provided. By including layer 403, the transistor 480b has on-characteristics (e.g., on-current and The high field-effect mobility (and field-effect mobility) enables high-speed operation and high-speed response.

[0209] Transistor 420, transistor 423, transistor 425, transistor 480b In the figure, the low resistance regions 121a, 121b, 122a, and 122b are source regions or drain regions. The low resistance regions 121a, 121b, 122a, and 123a can function as an insulating region. By providing 22b, the low resistance regions 121a, 121b, 122a, and 122b Therefore, the electric field applied to the channel forming regions 121c and 122c formed in the semiconductor layer can be reduced. In addition, the low resistance regions 121a, 121b, 122a, and 122b are formed of oxide semiconductor layers. The layer 403 is electrically connected to the source electrode layer 405a and the drain electrode layer 405b. As a result, the oxide semiconductor stack 403, the source electrode layer 405a, and the drain electrode layer 405 Therefore, the contact resistance between the transistor 420 and the transistor 4b can be reduced. The electrical properties of 23 can be improved.

[0210] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0211] (Fourth embodiment) A semiconductor device having a display function using the transistor as an example described in any of Embodiments 1 to 3 A semiconductor device (also called a display device) can be manufactured. Part or all of the circuitry is integrated onto the same substrate as the pixel section to form a system-on-panel. It is possible.

[0212] In FIG. 7A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided and the substrate is sealed with a second substrate 4006. In A), the area surrounded by the sealant 4005 on the first substrate 4001 and are formed in different regions using a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted on the substrate. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a signal line driver circuit 4005 are connected to the pixel portion 4002. Various signals and potentials are transmitted through the FPC (Flexible Printed Circuit )4018a, 4018b are supplied.

[0213] 7B and 7C, a pixel portion 4002 provided on a first substrate 4001 and a scanning A sealing material 4005 is provided so as to surround the line driver circuit 4004. A second substrate 4006 is provided on the substrate 4002 and the scanning line driver circuit 4004. The pixel portion 4002 and the scanning line driver circuit 4004 are formed by the first substrate 4001 and the sealing material 4004. The display element is sealed by the second substrate 4005 and the second substrate 4006. In C), the area surrounded by the sealant 4005 on the first substrate 4001 and are formed in different regions using a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. In FIG. 7(B) and (C), a signal line driver circuit 4003 is mounted. A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a signal line driver circuit 4005 are connected to the pixel portion 4002. The various signals and potentials are supplied from the FPC4018.

[0214] 7B and 7C, the signal line driver circuit 4003 is formed separately, and the first substrate 4 001, but the present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0215] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A The C This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 7(B) shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 7(C) shows an example in which a signal line driver circuit 4003 is mounted by the COG method. ) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0216] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0217] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with a printed wiring board attached The IC (integrated circuit) is directly mounted on the module or display element using the COG method. All such modules are also included in the display device.

[0218] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described as an example in any of Embodiments 1 to 3 can be used. do.

[0219] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0220] One mode of a semiconductor device will be described with reference to FIGS. 7 and 8. FIG. 8 shows the M Equivalent to the cross-sectional view at -N.

[0221] As shown in FIGS. 7 and 8, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are terminals of the FPC 4018. and are electrically connected to each other via an anisotropic conductive film 4019 .

[0222] The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030. 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. It is formed of a conductive film.

[0223] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 7 and 8, the transistors included in the pixel portion 4002 are 4004 and a transistor 4010 included in the scanning line driver circuit 4004. In FIG. 8A, an insulating film 4020 is provided over the transistors 4010 and 4011. 8B, an insulating film 4021 is further provided. It is an insulating film that functions as a base film.

[0224] The transistors 4010 and 4011 are the transistors according to any one of Embodiments 1 to 3. In this embodiment, the transistor shown in Embodiment 1 can be applied. 10. An example in which a transistor having a structure similar to that of the transistor 440a is used will be described.

[0225] The transistors 4010 and 4011 have semiconductor layers each having an energy gap Transistor having an oxide semiconductor stack including at least two oxide semiconductor layers with different properties An oxide semiconductor using a plurality of oxide semiconductor layers having different energy gaps By using stacked layers, the electrical characteristics of transistors can be controlled with greater precision. The transistors 4010 and 4011 can have desired electrical characteristics. It becomes Noh.

[0226] Therefore, the semiconductor device of this embodiment shown in FIGS. 7 and 8 has high functionality, high reliability, or It is possible to provide semiconductor devices that meet various objectives, such as low power consumption.

[0227] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. can be used.

[0228] FIG. 8(A) shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer 403 1 and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between two layers that function as alignment films. The second electrode layer 4031 is formed on the second substrate. The first electrode layer 4030 and the second electrode layer 4031 are disposed on the liquid crystal layer 400 side. 8 are stacked together.

[0229] 4035 is a columnar spacer obtained by selectively etching the insulating film. It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. A pacer may be used.

[0230] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. The liquid crystal material (liquid crystal composition) can be in a cholesteric phase, a smectic phase, or a cubic phase depending on the conditions. The phases shown are nematic, chiral, isotropic, etc.

[0231] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase is a phase that appears just before the transition from the black phase to the isotropic phase. The blue phase can be expressed by using a liquid crystal composition in which the above-mentioned compounds are mixed. In order to widen the temperature range, a polymerizable monomer and a polymerization initiator are added to the liquid crystal composition that exhibits the blue phase. The liquid crystal layer can be formed by adding a polymer stabilizer. The liquid crystal composition that exhibits this phase has a short response time and is optically isotropic, so alignment treatment is not required. It has little viewing angle dependency. Also, since there is no need to provide an alignment film, rubbing treatment is not required. Therefore, electrostatic breakdown caused by the rubbing process can be prevented, and the manufacturing process This reduces defects and damage to the liquid crystal display device during the manufacturing process, thereby improving the productivity of the liquid crystal display device. A transistor including an oxide semiconductor film can be easily affected by static electricity. This can cause the electrical characteristics of the transistor to fluctuate significantly, potentially causing it to deviate from the design range. Therefore, a liquid crystal display device having a transistor including an oxide semiconductor film exhibits a blue phase. It is more effective to use a crystalline composition.

[0232] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0233] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the oxide film may be set in consideration of the off-state current of the transistor. By using a transistor with a semiconductor film, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0234] The transistor including the oxide semiconductor film disclosed in this specification has a current value ( Therefore, the retention time of electrical signals such as image signals can be controlled to be low. The write interval can be set to a long value when the power is on. This reduces the frequency of flash operations, thereby reducing power consumption.

[0235] In addition, the transistor including the oxide semiconductor film disclosed in this specification has high field-effect mobility. For example, such high-speed driving is possible. By using such a transistor in a liquid crystal display device, it is possible to The driver transistors used in the driver circuit section can be formed on the same substrate. That is, a semiconductor device formed from a silicon wafer or the like is used as a separate driving circuit. Since there is no need for a pixel portion, the number of components in the semiconductor device can be reduced. However, by using transistors that can be driven at high speed, high-quality images can be provided. Therefore, high reliability can be achieved as a semiconductor device.

[0236] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS(Fringe Field Switching) mode, ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0237] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. In addition, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0238] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0239] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. is not limited to color display devices, but also applies to monochrome display devices. It is also possible.

[0240] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0241] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0242] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0243] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0244] FIG. 8B shows an example of a light-emitting device using a light-emitting element as a display element. The element 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, a second electrode layer 4032, a third electrode layer 4033, a fourth electrode layer 4034, a fourth electrode layer 4035, a fourth electrode layer 4036, a fourth electrode layer 4037, a fifth electrode layer 4038, a sixth electrode layer 4039 ... The light-emitting element 4513 has a stacked structure of two electrode layers 4031, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed appropriately according to the direction of the light to be extracted from the do.

[0245] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening has a continuous curved surface. It is preferable to form the inclined surface so as to have a constant slope.

[0246] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0247] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective film may be formed on the insulating film 4031 and the partition wall 4510. The protective film may be made of silicon nitride. A silicon nitride film, a silicon oxide film, a DLC film, etc. can be formed on the first substrate 400. The space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005 is filled with a filler 45. 14 is provided and sealed. In this way, it is highly airtight and degassed so as not to be exposed to the outside air. Protective films with low wear (laminating films, UV-curing resin films, etc.) and covering materials It is preferable to package (enclose) the

[0248] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide Mido, epoxy resin, silicone resin, PVB (Polyvinyl Butyral) or EVA (Elastomer) For example, nitrogen may be used as a filler. stomach.

[0249] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0250] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display (electrophoretic display), and is similar to paper. It is possible to have the same readability, lower power consumption than other display devices, and a thinner, lighter form factor. This has the advantage of

[0251] The electrophoretic display device may have various forms, but it has a structure in which first particles having a positive charge and and a second particle having a negative charge. By applying an electric field to the microcapsules, The particles in the cell are moved in opposite directions to each other, and only the color of the particles that gather on one side is displayed. The first particles or the second particles contain a dye, and when there is no electric field, they move. The color of the first particle and the color of the second particle are different (including colorless). )

[0252] In this way, the electrophoretic display device moves materials with high dielectric constants to areas with high electric fields, so-called This is a display that utilizes the dielectrophoretic effect.

[0253] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0254] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0255] In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method uses spherical particles painted in black and white as the display element. The first electrode layer and the second electrode layer are disposed between the first electrode layer and the second electrode layer. This is a display method that controls the orientation of spherical particles by creating a potential difference between the electrode layers. be.

[0256] In addition, in FIG. 7 and FIG. 8, the first substrate 4001 and the second substrate 4006 are made of glass. In addition to a glass substrate, a flexible substrate can also be used. For example, a light-transmitting plastic substrate can be used. As for plastic, FRP (Fibreglass) s-Reinforced Plastics) plate, PVF (Polyvinyl Fluoride) A film, a polyester film or an acrylic resin film can be used. If transparency is not required, metal substrates such as aluminum and stainless steel (metal film For example, aluminum foil can be covered with PVF film or polyester film. It is also possible to use a sheet sandwiched between two sheets.

[0257] In this embodiment, an aluminum oxide film is used as the insulating film 4020.

[0258] The aluminum oxide film provided as the insulating film 4020 over the oxide semiconductor film is resistant to hydrogen, moisture, and It has a high blocking effect that prevents impurities such as urea and oxygen from passing through the membrane. stomach.

[0259] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The intrusion of impurities such as moisture into the oxide semiconductor film and the intrusion of the main component material of the oxide semiconductor The oxide semiconductor film functions as a protective film that prevents oxygen from being released from the oxide semiconductor film.

[0260] The insulating film 4021 functioning as a planarizing insulating film can be formed of a material such as acrylic, polyimide, or benzosilane. Heat-resistant organic materials such as clobutene resin, polyamide, and epoxy can be used. In addition to the above organic materials, low-k materials and siloxane resins can also be used. , PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. The insulating film may be formed by stacking a plurality of insulating films made of these materials.

[0261] The method for forming the insulating film 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, etc.), Printing methods (screen printing, offset printing, etc.), doctor knife, roll coater, car A ten coater, knife coater, or the like can be used.

[0262] A display device transmits light from a light source or a display element to display an image. All thin films such as the substrate, insulating film, and conductive film provided in the part are resistant to light in the visible light wavelength range. It shall be translucent.

[0263] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) that apply a voltage to the display element In the case of a light-emitting element (also called a counter electrode layer), the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0264] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide , silicon oxide-doped indium tin oxide, graphene, and other transparent conductive materials Fees can be used.

[0265] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0266] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or a derivative thereof Conductors, etc.

[0267] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0268] As described above, by using the transistor described in any of Embodiments 1 to 3, various It is possible to provide semiconductor devices having various functions.

[0269] (Embodiment 5) The transistor exemplified in any one of the first to third embodiments is used to read information on an object. Therefore, a semiconductor device having an image sensor function for detecting a pixel can be manufactured.

[0270] FIG. 9A shows an example of a semiconductor device having an image sensor function. 9(A) is an equivalent circuit of the photosensor, and FIG. 9(B) is a cross-sectional view showing a part of the photosensor.

[0271] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode is electrically connected to the gate of transistor 640. One of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other terminal is electrically connected to one of the source and drain terminals of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The signal line 671 is electrically connected to the sensor output signal line 671.

[0272] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor film is not clearly shown. To make it easy to identify, the symbol for a transistor using an oxide semiconductor film is written as “OS.” In FIG. 9A, a transistor 640 and a transistor 656 are the same as those in the first embodiment. The transistors shown in the above to 3 can be applied, and the transistor is a transistor using an oxide semiconductor film. In this embodiment, a transistor having a structure similar to that of the transistor 440a shown in the first embodiment is used. An example of applying a transistor is shown below.

[0273] FIG. 9B shows the photodiode 602 and the transistor 640 in the photosensor. 6 is a cross-sectional view showing a photodiode functioning as a sensor on a substrate 601 (TFT substrate). A photodiode 602 and a transistor 640 are provided. A substrate 613 is provided on top of the resistor 640 using an adhesive layer 608 .

[0274] On the transistor 640, an insulating film 631, an insulating film 632, an interlayer insulating film 633, and an interlayer insulating film The photodiode 602 is provided on the interlayer insulating film 633. An electrode layer 641 formed on the interlayer insulating film 633 and an electrode layer provided on the interlayer insulating film 634 642, a first semiconductor film 606a and a second semiconductor film 606b are formed between the first semiconductor film 606a and the second semiconductor film 606b in this order from the interlayer insulating film 633 side. 6b and a third semiconductor film 606c are stacked.

[0275] The electrode layer 641 is electrically connected to a conductive layer 643 formed on the interlayer insulating film 634. 642 is electrically connected to the conductive layer 645 via the electrode layer 641. The conductive layer 645 is The photodiode 602 is electrically connected to the gate electrode layer of the transistor 640. It is electrically connected to the transistor 640 .

[0276] Here, the first semiconductor film 606a is a semiconductor film having a p-type conductivity, and the second semiconductor film 606b is a high resistance semiconductor film (I-type semiconductor film), and the third semiconductor film 606c is an n-type A pin-type photodiode in which semiconductor films having different conductivity types are stacked is shown as an example.

[0277] The first semiconductor film 606a is a p-type semiconductor film, and is an amorphous film containing an impurity element that imparts p-type. The first semiconductor film 606a can be formed from a group 13 silicon film. Using semiconductor material gas containing impurity elements (e.g., boron (B)), plasma CVD is used. Silane (SiH4) can be used as the semiconductor material gas. Alternatively, i2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may be used. In addition, after forming an amorphous silicon film that does not contain impurity elements, the film is formed by diffusion or ion implantation. Impurity elements may be introduced into the amorphous silicon film by using a method such as ion implantation. It is preferable to diffuse the impurity element by heating or the like after introducing the impurity element. In this case, the amorphous silicon film can be formed by LPCVD, vapor phase growth, Alternatively, sputtering or the like may be used. The thickness of the first semiconductor film 606a is 10 nm or more and 5 nm or less. It is preferable to form it so that the thickness is 0 nm or less.

[0278] The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film) and is made of amorphous silicon. The second semiconductor film 606b is formed by amorphous silicon using a semiconductor material gas. A thick silicon film is formed by plasma CVD. The semiconductor material gas is silane. (SiH4) can be used. Alternatively, Si2H6, SiH2Cl2, SiHCl3, S The second semiconductor film 606b may be formed by LPCVD. The second semiconductor film 606b may be formed by vapor deposition, sputtering, or the like. It is preferable to form the film so that the thickness is 00 nm or more and 1000 nm or less.

[0279] The third semiconductor film 606c is an n-type semiconductor film and is an amorphous film containing an impurity element that imparts n-type. The third semiconductor film 606c is formed of a thick silicon film. It is formed by the plasma CVD method using a semiconductor material gas containing silicon (e.g., phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming an amorphous silicon film that does not contain elements, the film is then doped with silicon using diffusion or ion implantation. An impurity element may be introduced into the amorphous silicon film by ion implantation or the like. After the element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon film can be formed by LPCVD, vapor phase growth, or sputtering. The thickness of the third semiconductor film 606c is 20 nm or more and 200 nm or less. It is preferable to form it so that it faces downward.

[0280] The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are Instead of an amorphous semiconductor, it may be formed using a polycrystalline semiconductor, or a microcrystalline (semi-amorphous) semiconductor. Semi Amorphous Semiconductor (SAS) )) It may be formed using a semiconductor.

[0281] Considering the Gibbs free energy, microcrystalline semiconductors are metastable, intermediate between amorphous and single crystal. In other words, a semiconductor with a third state that is stable in terms of free energy It has a short-range order and lattice distortion. Microcrystalline silicon, a typical example of a microcrystalline semiconductor, is characterized by its Raman scattering. The spectrum shows single-crystal silicon at 520 cm -1 It is shifted to the lower wavenumber side. That is, 520 cm, which indicates single crystal silicon -1 and 480 cm, which indicates amorphous silicon - 1 The Raman spectrum of microcrystalline silicon has a peak between these two. Contains at least 1 atomic % or more of hydrogen or halogen to terminate the bonding bonds. It also contains rare gas elements such as helium, argon, krypton, and neon. By increasing the lattice distortion, the stability is increased and a good microcrystalline semiconductor film can be obtained. .

[0282] This microcrystalline semiconductor film is formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or Alternatively, it can be formed by a microwave plasma CVD device with a frequency of 1 GHz or more. Representative examples include SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, and S It can be formed by diluting silicon-containing compounds such as iF4 with hydrogen. In addition to compounds containing hydrogen (e.g., silicon hydride) and hydrogen, helium, argon, krypton, neon forming a microcrystalline semiconductor film by diluting the semiconductor film with one or more rare gas elements selected from the group consisting of fluorine and fluorine; In these cases, the flow rate ratio of hydrogen to silicon-containing compounds (e.g., silicon hydride) is 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, and more preferably 100 times Furthermore, in the gas containing silicon, carbide gases such as CH4, C2H6, GeH 4. Germanium gas such as GeF4, F2, etc. may be mixed.

[0283] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type The photodiode exhibits better characteristics when the p-type semiconductor film side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed to the photodiode 602 This shows an example of converting the light received by the semiconductor film into an electrical signal. Since light from the semiconductor film side having a pattern becomes disturbance light, a conductive film with light blocking properties is used for the electrode layer. It is also possible to use the n-type semiconductor film side as the light-receiving surface.

[0284] The insulating film 632, the interlayer insulating film 633, and the interlayer insulating film 634 are made of insulating materials. Depending on the material, sputtering, plasma CVD, SOG, spin coating, Spray coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater It can be formed using a material such as a silicon dioxide particle.

[0285] In this embodiment, an aluminum oxide film is used as the insulating film 631. It can be formed by sputtering or plasma CVD.

[0286] The aluminum oxide film provided as the insulating film 631 over the oxide semiconductor film is resistant to hydrogen, moisture, and the like. High blocking effect that prevents both impurities and oxygen from passing through the membrane .

[0287] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The intrusion of impurities such as moisture into the oxide semiconductor film and the intrusion of the main component material of the oxide semiconductor The oxide semiconductor film functions as a protective film that prevents oxygen from being released from the oxide semiconductor film.

[0288] The insulating film 632 may be made of an inorganic insulating material such as a silicon oxide layer, a silicon oxynitride layer, An oxide insulating film such as an aluminum oxide layer or an aluminum oxynitride layer, or a silicon nitride layer , a nitride such as a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer A single layer or a stacked layer of insulating films can be used.

[0289] The interlayer insulating films 633 and 634 function as planarizing insulating films to reduce surface irregularities. The interlayer insulating films 633 and 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic resins such as resins, benzocyclobutene-based resins, polyamides, and epoxy resins In addition to the organic insulating materials, low-dielectric-constant materials (low- k material), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass), etc. A single layer or a laminated layer can be used.

[0290] By detecting the light incident on the photodiode 602, information on the detected object is read. It is possible to read the information of the detected object using a light source such as a backlight. It is possible.

[0291] As described above, a plurality of oxide semiconductor layers having different energy gaps as semiconductor layers By using a stack of oxide semiconductor layers using This allows for precise control, making it possible to impart desired electrical characteristics to the transistor. By using such a transistor, various advantages such as high functionality, high reliability, and low power consumption can be achieved. A semiconductor device suited to the purpose can be provided.

[0292] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0293] (Sixth embodiment) The transistor exemplified in any one of the first to third embodiments is a transistor stacked in a plurality of layers. The present invention can be suitably applied to a semiconductor device having an integrated circuit. As an example of a semiconductor device, a storage medium (memory element) will be shown.

[0294] In the embodiment, a transistor that is a first transistor manufactured on a single crystal semiconductor substrate A second transistor 140 is formed using a semiconductor film above the transistor 140 via an insulating film. A semiconductor device including the transistor 162 is manufactured. The transistor 162 may be suitably used as any of the transistors exemplified in any of the above. In this embodiment, the transistor 162 may be the same as that shown in Embodiment 1. 4 shows an example in which a transistor having a structure similar to that of the transistor 440a is used.

[0295] The semiconductor materials and structures of the stacked transistors 140 and 162 may be the same. This embodiment is directed to a material suitable for a circuit of a storage medium (memory element). These are examples using transistors of different materials and structures.

[0296] 10A and 10B show an example of the configuration of a semiconductor device. 10(B) shows a plan view of the semiconductor device. This corresponds to the cross section taken along lines C1-C2 and D1-D2 in FIG. 10(B). An example of a circuit diagram in which the semiconductor device is used as a memory element is shown in FIG. The semiconductor device shown in FIG. 10(B) has a transistor using a first semiconductor material in the lower part. The second semiconductor material is used as the second transistor 162. In the embodiment, the first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is The oxide semiconductor is a semiconductor material other than the oxide semiconductor. Use of ruthenium, silicon germanium, silicon carbide, or gallium arsenide It is preferable to use a single crystal semiconductor, since it is possible to achieve the above. Alternatively, an organic semiconductor material may be used. Transistors using such semiconductor materials are easy to operate at high speeds. The characteristics of transistors using semiconductors enable them to retain charge for long periods of time.

[0297] The semiconductor device in FIG. 10 will be described with reference to FIGS.

[0298] The transistor 140 is disposed on a substrate 185 that includes a semiconductor material (e.g., silicon). The channel forming region 116 is formed by doping the impurity ions 116. The region 120, the metal compound region 124 in contact with the impurity region 120, and the channel forming region 1 A gate insulating film 108 is provided on the gate electrode 16, and a gate electrode 109 is provided on the gate insulating film 108. The electrode 110 is a ferroelectric material.

[0299] The substrate 185 containing the semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, or a The substrates used include crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates. Generally, an "SOI substrate" is a substrate in which a silicon semiconductor film is provided on an insulating surface. However, in this specification, it refers to a substrate having a structure in which a material other than silicon is formed on an insulating surface. In other words, the semiconductor film of the "SOI substrate" The film is not limited to a silicon semiconductor film. In addition, the SOI substrate can be made of an insulating material such as a glass substrate. The term "semiconductor film" includes a structure in which a semiconductor film is provided on a substrate via an insulating film.

[0300] The SOI substrate is fabricated by implanting oxygen ions into a mirror-polished wafer and then heating it at high temperature. By doing so, an oxide layer is formed at a certain depth from the surface, and the cracks that have occurred in the surface layer are removed. a method for eliminating microvoids formed by hydrogen ion irradiation and a method for forming microvoids by heat treatment A method of cleaving a semiconductor substrate by using a length, or a method of forming a single crystal semiconductor film by crystal growth on an insulating surface. A method for forming the above-mentioned film or the like can be used.

[0301] For example, ions are added from one surface of a single crystal semiconductor substrate to form a single crystal semiconductor substrate. A weakened layer is formed at a certain depth from the surface of the single crystal semiconductor substrate, and the single crystal semiconductor substrate is An insulating film is formed on either one of the single crystal semiconductor substrate and the element substrate. While the substrates are stacked together, a crack is generated in the weakened layer, and the single crystal semiconductor substrate is separated at the weakened layer. A heat treatment is performed to form a single crystal semiconductor film on the element substrate as a semiconductor film from the single crystal semiconductor substrate. The SOI substrate manufactured by the above method can also be suitably used.

[0302] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 140. In order to achieve high integration, the transistor 140 may be It is desirable to have a structure that does not have a sidewall insulating layer that becomes a sidewall. When the characteristics of the gate electrode 140 are important, a side wall is formed on the side surface of the gate electrode 110. A wall insulating layer may be provided to provide impurity regions 120 including regions with different impurity concentrations.

[0303] The transistor 140 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a readout transistor, it is possible to read out information at high speed. Two insulating films are formed to cover the transistor 140. As a process before forming the capacitor 162 and the capacitor element 164, the two insulating film layers are subjected to CMP. Then, the planarized insulating film 128 and the insulating film 130 are formed, and at the same time, the upper surface of the gate electrode 110 is Expose.

[0304] The insulating film 128 and the insulating film 130 are typically made of a silicon oxide film, a silicon oxynitride film, or an oxide Aluminum film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, nitride An inorganic insulating film such as a silicon oxide film or an aluminum nitride oxide film can be used. The film 128 and the insulating film 130 are formed by using a plasma CVD method, a sputtering method, or the like. It is possible.

[0305] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric-constant materials (low-k materials) can also be used. When organic materials are used, insulating films can be formed by wet methods such as spin coating and printing. 128 and an insulating film 130 may be formed.

[0306] Note that the insulating film 130 that is in contact with the semiconductor film is a silicon oxide film.

[0307] In this embodiment, the insulating film 128 is formed by sputtering an oxynitride film having a thickness of 50 nm. A silicon film is formed, and an oxide film having a thickness of 550 nm is formed by a sputtering method as the insulating film 130. A silicon film is formed.

[0308] On the insulating film 130 that has been sufficiently planarized by CMP processing, oxide semiconductors with different energy gaps are formed. In this embodiment, a conductive film is stacked on the oxide semiconductor film by a sputtering method. In this way, an In—Sn—Zn oxide layer and an In—Ga—Zn oxide layer are formed in this order on the insulating film 130. Layer on top of each other.

[0309] Next, the stack of oxide semiconductor films is selectively etched to form an island-shaped stack of oxide semiconductor films 144. A source electrode or drain electrode 142 a and a source electrode 142 b are formed on the oxide semiconductor stack 144. A gate electrode or drain electrode 142b is formed.

[0310] A gate insulating film 146 and a gate electrode layer 148 are formed over the oxide semiconductor film. 148 is formed by forming a conductive layer and then selectively etching the conductive layer. It can be achieved.

[0311] The gate insulating film 146 is formed by depositing an oxide film using a plasma CVD method, a sputtering method, or the like. Silicon film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide Aluminum film, aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film, aluminum oxide film A gallium oxide film, a gallium oxide film, or an aluminum oxide film can be formed.

[0312] A gate electrode layer 148, a source electrode or a drain electrode 142a, a source electrode or a drain electrode The conductive layer that can be used for the electrode 142b can be formed by PVD such as sputtering. The conductive layer can be formed by a CVD method such as a plasma CVD method. The material may be an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned Alloys containing elements such as Mn, Mg, Zr, Be, Nd, and Sc can be used. Any one of these materials or a combination of two or more of these materials may be used.

[0313] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0314] Next, an insulating film is formed on the oxide semiconductor stack 144, the gate insulating film 146, and the gate electrode layer 148. In this embodiment, an aluminum oxide film is formed as the insulating film 150. do.

[0315] The aluminum oxide film provided as the insulating film 150 on the oxide semiconductor stack 144 is , a blocking effect that prevents impurities such as water and oxygen from passing through the membrane (blocking effect) ) is high.

[0316] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The inclusion of impurities such as moisture in the oxide semiconductor stack 144 and the inclusion of the main components constituting the oxide semiconductor It functions as a protective film that prevents oxygen, a component material, from being released from the oxide semiconductor stack 144. .

[0317] Alternatively, a separate insulating film may be formed on the insulating film 150 .

[0318] The insulating film is a silicon oxide film formed by plasma CVD or sputtering. Silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum nitride film, oxide Aluminum film, aluminum oxynitride film, aluminum nitride oxide film, hafnium oxide film Alternatively, a gallium oxide film can be used.

[0319] On the insulating film 150, an electrode is formed in a region overlapping with the source electrode or the drain electrode 142a. A layer 153 is formed.

[0320] Next, the insulating film 152 is formed over the transistor 162 and the electrode layer 153. The layer 2 can be formed by sputtering or CVD. Inorganic insulators such as silicon oxide nitride, silicon nitride, hafnium oxide, and aluminum oxide The material may be polyimide, acrylic, benzophenone, or the like. Organic materials such as cyclobutene resins can be used. The organic materials can be applied by coating or printing. A wet method such as a printing method or an ink jet method can be used.

[0321] Next, a source electrode or a drain electrode is formed on the gate insulating film 146, the insulating film 150, and the insulating film 152. An opening is formed that reaches the inner electrode 142b. The opening is formed using a mask or the like. This is done by selective etching.

[0322] Thereafter, a wiring 156 that contacts the source electrode or drain electrode 142b is formed in the opening. 10A shows the connection between the source electrode or drain electrode 142b and the wiring 156. The connecting portion is not shown.

[0323] The wiring 156 is formed by a PVD method such as a sputtering method, or a C method such as a plasma CVD method. After forming a conductive layer using the VD method, the conductive layer is etched to form The material of the conductive layer is selected from Al, Cr, Cu, Ta, Ti, Mo, and W. The elements mentioned above and alloys containing the elements mentioned above can be used. Any one of R, Be, Nd, and Sc, or a combination of these materials may be used. The details are similar to those of the source electrode or drain electrode 142a.

[0324] Through the above steps, the transistor 162 and the capacitor 164 are formed. The transistor 162 has at least two oxide semiconductor layers with different energy gaps. The transistor has an oxide semiconductor stack 144 including different energy layers. The oxide semiconductor stack 144 is made up of a plurality of oxide semiconductor layers having a gap. This allows for more precise control of the electrical characteristics of the transistor 162, It is possible to impart electrical characteristics to the transistor 162. In this case, the oxide semiconductor stack 144 is highly purified and an oxide semiconductor layer containing excess oxygen is formed to compensate for oxygen vacancies. Therefore, the off-state current of the transistor 162 is reduced and the electrical characteristics are changed. The capacitance element 164 is electrically stable because the capacitance is suppressed by the source electrode or the drain electrode. a gate electrode 142a, an oxide semiconductor stack 144, a gate insulating film 146, and an electrode layer 153; It consists of:

[0325] In the capacitor element 164 of FIG. 10, the gate insulating film 146 and the insulating film 150 are stacked. As a result, the insulation between the source electrode or drain electrode 142a and the electrode layer 153 is sufficiently ensured. Of course, in order to ensure a sufficient capacitance, the insulating film 150 is effectively used. Alternatively, a capacitor 164 having an insulating film may be used. Furthermore, if capacitance is not required, the capacitance element 164 may be omitted. It is also possible to do this.

[0326] FIG. 10C shows an example of a circuit diagram in the case where the semiconductor device is used as a memory element. In FIG. 10C, one of the source electrode and the drain electrode of the transistor 162 is One of the electrodes of the capacitor 164 and the gate electrode of the transistor 140 are electrically connected. In addition, the first wiring (also called the source line) and the transistor The source electrode of 140 is electrically connected to the second wiring (2nd Line: bit line The drain electrode of the transistor 140 is electrically connected to the drain electrode of the transistor 140. The third wiring (also called the first signal line) and the source of the transistor 162 The other of the drain electrode and the drain electrode is electrically connected to a fourth wiring (4th Line The second signal line (also referred to as a second signal line) and the gate electrode of the transistor 162 are electrically connected to each other. The fifth line (also called a word line) and the capacitor element 16 The other of the four electrodes is electrically connected.

[0327] The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 162, the source of the transistor 162 One of the electrodes or drain electrodes of the capacitor 164 and the transistor 140 The potential of the node (hereinafter referred to as node FG) electrically connected to the gate electrode of Furthermore, by having the capacitance element 164, This makes it easier to retain the charge given to the gate FG and to read out the retained information. becomes.

[0328] When storing (writing) information in the semiconductor device, first, the potential of the fourth wiring is set to This sets the potential at which the transistor 162 is turned on, turning the transistor 162 on. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, the charges that give two different potential levels (hereinafter referred to as low level Either a charge or a high level charge is given. The potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off 162, node FG is in a floating state, so As described above, a predetermined amount of charge is stored in the node FG. By storing and holding information, the memory cell can store information.

[0329] Since the off-state current of the transistor 162 is controlled to be extremely small, the The charge stored in the memory is retained for a long time, so that no refresh operation is required. Alternatively, the frequency of refresh operations can be reduced significantly, and power consumption can be reduced sufficiently. In addition, even if there is no power supply, the memory can be stored for a long period of time. The content can be preserved.

[0330] When reading out the stored information (reading), a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the potential is held at the node FG. Depending on the amount of charge transferred, transistor 140 assumes different states. If 40 is an n-channel type, when a high level charge is held at node FG, The apparent threshold voltage V of transistor 140 th_H A low-level charge is applied to node FG. The apparent threshold voltage V of transistor 140 when held th_L It became lower Here, the apparent threshold is the voltage at which the transistor 140 is turned on. Therefore, the potential of the fifth wiring is V th _H and V th_L By setting the potential V0 to the intermediate potential between For example, if a high level charge is applied during writing, The potential of the fifth wire is V0 (>V th_H ), transistor 140 is in the "on state" When a low level charge is applied, the potential of the fifth wire becomes V0( <V t h_L ), transistor 140 remains in the "off state." The potential of the wiring is controlled to read out the on / off state of the transistor 140 (the The stored information can be read out by reading out the potential of the wiring 2.

[0331] When the stored information is rewritten, a predetermined amount of electricity is consumed by the rewriting. By supplying a new potential to node FG, which holds the load, node FG is connected to the new information. Specifically, the potential of the fourth wiring is set to a value corresponding to the potential of the fourth wiring when the transistor 162 is turned on. This turns on the transistor 162. A potential (potential related to new information) is supplied to node FG, and a predetermined amount of charge is accumulated in node FG. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the node FG receives the new information. That is, a predetermined amount of charge is stored in the node FG by the first write. While the charge is held, the same operation as the first write (second write) is performed. , it is possible to overwrite the stored information.

[0332] The transistor 162 described in this embodiment has at least two layers with different energy gaps. and the off-state current is controlled to be sufficiently low. By using such a transistor, it is possible to A semiconductor device capable of retaining memory contents is obtained.

[0333] As described above, an oxide semiconductor layer using a plurality of oxide semiconductor layers having different energy gaps can be fabricated. By using semiconductor stacks, the electrical characteristics of transistors can be controlled more precisely. This makes it possible to impart desired electrical characteristics to the transistor. It is possible to provide semiconductor devices that meet various objectives, such as high reliability or low power consumption. .

[0334] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0335] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), ), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines, etc. Examples of electronic devices including the semiconductor device described in the above embodiment will be described. By providing the semiconductor device described in the above embodiment, high performance and high reliability can be achieved. To provide electronic devices that are endowed with qualities suited to various purposes, such as high performance or low power consumption. can be done.

[0336] FIG. 11A shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. By applying the semiconductor device shown in any one of the above to 6 to the display portion 3003, high performance and A highly reliable notebook-type personal computer can be obtained.

[0337] FIG. 11B shows a personal digital assistant (PDA), which has a main body 3021 including a display unit 3023 and a An external interface 3025 and operation buttons 3024 are provided. The semiconductor device shown in any of the first to sixth embodiments has a stylus 3022 as an accessory. By applying the body device to the display unit 3023, a more high-performance and highly reliable mobile information terminal can be obtained. (PDA).

[0338] FIG. 11C shows an example of an electronic book. For example, the electronic book has a housing 2701 and The housing 2701 and the housing 2703 are made up of two housings. The opening and closing operation can be performed with the shaft portion 2711 as an axis. This configuration allows the device to function like a paper book.

[0339] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 11C), and An image can be displayed on the display portion (the display portion 2707 in FIG. 11C). The semiconductor device shown in any one of 1 to 6 can be applied to the display portion 2705 and the display portion 2707. As a result, a high performance and highly reliable e-book can be obtained. When using a transmissive or reflective LCD device, it is expected that it will be used in relatively bright conditions. Therefore, solar panels will be installed to generate electricity and charge the battery. It is also possible to use a lithium-ion battery as the battery, which can be made smaller. This has the advantage of being able to

[0340] FIG. 11C shows an example in which an operation unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The back of the housing may be provided with a keyboard, a pointing device, etc. On the front and sides, there are external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion port, etc. Furthermore, the electronic book may be configured to have a function as an electronic dictionary. You may do so.

[0341] The electronic book may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to purchase and download desired book data from the server. be.

[0342] FIG. 11(D) shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 contains a display panel 2802, a speaker 2803, a microphone, and 2804, pointing device 2806, camera lens 2807, external connection terminal 2808. The housing 2800 also includes a solar cell for charging the mobile phone. The antenna is mounted on the housing 28 The semiconductor device according to any one of the first to sixth embodiments is incorporated in the display panel. By applying this to the Nel 2802, a high performance and highly reliable mobile phone can be achieved. .

[0343] The display panel 2802 is equipped with a touch panel, and the image displayed in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0344] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera lens 2802, so video calls are possible. The speaker 2803 and microphone 2804 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 2800 and the housing 2801 can be slid apart. As shown in 11(D), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0345] The external connection terminal 2808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 2811, it is possible to store and transfer a larger amount of data. do.

[0346] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0347] FIG. 11(E) shows a digital video camera, which includes a main body 3051, a display unit (A) 3057, Eyepiece 3053, operation switch 3054, display unit (B) 3055, battery 3056, etc. The semiconductor device according to any one of the first to sixth embodiments is configured as a display device. By applying this to (A) 3057 and display (B) 3055, high performance and high reliability can be achieved. The image capturing apparatus may be a digital video camera.

[0348] 11(F) shows an example of a television device. The television device has a housing 96 The display unit 9603 is incorporated in the camera body 9601. The display unit 9603 can display images. In this example, the housing 9601 is supported by a stand 9605. The semiconductor device described in any of Embodiments 1 to 6 is applied to the display portion 9603. This makes it possible to provide a television device with high performance and reliability.

[0349] The television set can be operated using an operation switch on the housing 9601 or a separate remote control. In addition, the remote control device can be configured to output the A display unit for displaying information may be provided.

[0350] The television device is assumed to be equipped with a receiver, modem, etc. It can receive television broadcasts and can also communicate by wire or wireless via a modem. By connecting to a network, you can send and receive data in one direction (sender to receiver) or two directions (sender to receiver). It is also possible to communicate information between the recipient and the receiver, or between receivers themselves.

[0351] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Example]

[0352] In this example, a layer having an energy gap of 1.0 μm or less is formed on the first oxide semiconductor layer. a second oxide semiconductor layer having a thickness smaller than that of the first oxide semiconductor layer, and a third oxide semiconductor layer is formed on the second oxide semiconductor layer. A sample with a quartz-oxide semiconductor layer is prepared, and the ionization potential of the sample is measured. The energy band diagram was calculated based on the results. The potential value is the sum of the band gap and the electron affinity. The value of is obtained by measuring a single film of the material with an ellipsometer.

[0353] The sample is a single-crystal silicon substrate with a 5-nm thick IGZO film and a 5-nm thick In-Sn The deposition conditions for each layer were as follows: The film was formed using the sputtering method at a substrate temperature of 300°C in an oxygen atmosphere (100% oxygen). The target was an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. The In-Sn-Zn oxide film is formed by In:Sn:Zn= An oxide target with an atomic ratio of 2:1:3 is used.

[0354] In addition, a quartz substrate was used as the substrate, and the cross section of the sample obtained by laminating films under the same film-forming conditions was photographed. The TEM photograph is shown in Figure 14(A). A schematic diagram is shown in Figure 14(B). In B), the interface of the oxide semiconductor layer is shown by a dotted line, but this is only a schematic illustration. Depending on the material, film formation conditions, and heat treatment, the interface between each oxide semiconductor layer may become unclear. The sample photographed in FIG. 14(A) is a first film having a thickness of 5 nm on a quartz substrate 1000. IGZO film 1001, 5 nm thick In-Sn-Zn oxide film 1002, 5 nm thick The second IGZO film 1003 is laminated on the In-Sn-Zn oxide film. The interface of the IGZO film can be seen. In addition, in FIG. 14(A), the second IGZO film 1003 and The In-Sn-Zn oxide film 1002 contains crystals and has a crystalline structure with a c-axis orientation. It can be seen that the first layer is an oxide semiconductor (CAAC). The IGZO film 1001 has an amorphous structure. In FIG. 14(A), two of the three layers are The second IGZO film is an oxide semiconductor film having a crystalline structure, but is not particularly limited thereto. Only 1003 may have a crystalline structure, or all three layers may have a crystalline structure, or The entire structure may be amorphous.

[0355] Ultraviolet photoelectron spectroscopy (UPS) was performed while sputtering from the sample surface. Ionization by Violet Photoelectron Spectroscopy The results of measuring the potential are shown in FIG.

[0356] In FIG. 12, the horizontal axis represents the sputtering time from the sample surface, and the vertical axis represents the ionization time. The potential is shown in Fig. 1. The sputtering of the IGZO film and the In-Sn-Zn oxide film The boundary of the sample is shown assuming that the rates are equal. It can be seen that the ionization potential decreases in the In-Sn-Zn oxide film containing the The ionization potential represents the energy difference from the vacuum level to the valence band.

[0357] The conduction band is calculated by subtracting the band gap measured by ellipsometry from the ionization potential value. The energy was calculated and the band structure of this laminated film was created. The band gaps of the Sn-Zn oxide films were set to 3.2 eV and 2.8 eV, respectively. The result is shown in Figure 13. In Figure 13, the energy band diagram is filled in like the one shown in Figure 4(C). It can be seen that an in-between channel is formed.

[0358] In this example, IGZO films are used as the first oxide semiconductor layer and the third oxide semiconductor layer. , which has a higher ionization potential than the first oxide semiconductor layer and the third oxide semiconductor layer. and the second oxide semiconductor layer has a small energy gap and is made of In—Sn The stacked layer using the Zn-based oxide film has the energy band diagram shown in Figure 13 or Figure 4(C). It was confirmed that the first oxide semiconductor layer, the second oxide semiconductor layer, and The combination of materials for the third oxide semiconductor layer is not particularly limited, and may be any of the materials shown in FIG. 13 or FIG. Consider the energy gap of the material used by the implementer so that the energy band diagram shown in For example, the first oxide semiconductor layer and the third oxide semiconductor layer may be made of a material selected and combined appropriately in consideration of the above. The first oxide semiconductor layer is an IGZO film, and the second oxide semiconductor layer is an indium zinc oxide film. A stacked layer using an oxide film may also be used. [Explanation of symbols]

[0359] 101 Oxide semiconductor layer 102 Oxide semiconductor layer 103 Oxide semiconductor layer 106 Element isolation insulating layer 108 Gate insulating film 110 gate electrode 111 Oxygen excess region 112 Oxygen excess region 116 Channel formation region 120 Impurity region 121a Low resistance area 121b Low resistance region 121c Channel formation region 121d Low resistance region 121e Low resistance region 122a Low resistance area 122b Low resistance region 122c Channel formation region 122d Low resistance region 122e low resistance area 123a Low resistance area 123b Low resistance region 123c Channel formation region 123d low resistance region 123e Low resistance region 124 Metal compound area 128 insulating film 130 insulating film 140 transistors 142a Drain electrode 142b Drain electrode 144 Oxide Semiconductor Stack 146 Gate insulating film 148 gate electrode layer 150 insulating film 152 insulating film 153 Electrode layer 156 Wiring 162 transistors 164 Capacitor 185 PCB 191 Oxide semiconductor film 192 Oxide semiconductor film 400 boards 401 Gate electrode layer 402 Gate insulating film 403 Oxide Semiconductor Stack 404a Source electrode layer 404b Drain electrode layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating Film 415a Source electrode layer 415b Drain electrode layer 416 Insulating film 420 transistors 421 Dopant 423 Transistor 425 transistor 430 transistors 431 Oxygen 436 Oxide insulating film 440a transistor 440b transistor 440c transistor 440d transistor 465a Wiring layer 465b wiring layer 480a transistor 480b transistor 493 Lamination 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Insulating film 632 insulating film 633 Interlayer insulating film 634 Interlayer insulating film 640 transistors 641 Electrode layer 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 1000 quartz substrate 1001 IGZO membrane 1002 In-Sn-Zn oxide film 1003 IGZO membrane 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 2800 chassis 2801 Case 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation Key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 solar cell 2811 external memory slot 3001 main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main Unit 3022 stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main Unit 3053 Eyepiece 3054 Operation switch 3056 Battery 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 insulating film 4021 Insulating film 4023 Insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9601 Housing 9603 Display section 9605 Stand

Claims

1. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer having a region located above the first insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer with the third insulating layer interposed therebetween and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region overlapping with the second conductive layer via the fourth insulating layer and the third insulating layer and having a function as the other electrode of the capacitor element; a channel formation region of the first transistor and a channel formation region of the second transistor that do not overlap each other in a plan view;

2. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer having a region located above the first insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer with the third insulating layer interposed therebetween and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer; a fourth conductive layer having a region overlapping with the second conductive layer via the fourth insulating layer and the third insulating layer and having a function as the other electrode of the capacitor element; the first insulating layer comprises nitrogen and silicon; the second insulating layer comprises oxygen and silicon; the third insulating layer comprises oxygen and silicon; a channel formation region of the first transistor and a channel formation region of the second transistor that do not overlap each other in a plan view;

3. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer having a region located above the first insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer with the third insulating layer interposed therebetween and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer; a fifth insulating layer having a region in contact with an upper surface of the fourth insulating layer; a fourth conductive layer having a region overlapping with the second conductive layer via the fourth insulating layer and the third insulating layer and having a function as the other electrode of the capacitor element; a channel formation region of the first transistor and a channel formation region of the second transistor do not overlap each other in a plan view; The semiconductor device, wherein the fifth insulating layer comprises an organic material.

4. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitance element; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second insulating layer having a region located above the first insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the second insulating layer and including a channel formation region of the second transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a top surface of the first conductive layer and functioning as one of a source electrode and a drain electrode of the second transistor; a third insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; a third conductive layer having a region located above the oxide semiconductor layer with the third insulating layer interposed therebetween and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer; a fifth insulating layer having a region in contact with an upper surface of the fourth insulating layer; a fourth conductive layer having a region overlapping with the second conductive layer via the fourth insulating layer and the third insulating layer and having a function as the other electrode of the capacitor element; the first insulating layer comprises nitrogen and silicon; the second insulating layer comprises oxygen and silicon; the third insulating layer comprises oxygen and silicon; a channel formation region of the first transistor and a channel formation region of the second transistor do not overlap each other in a plan view; The semiconductor device, wherein the fifth insulating layer comprises an organic material.

5. In any one of claims 1 to 4, At least one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer has a stacked structure.

Images