Structure, quantum bit, quantum arithmetic device, method for manufacturing structure, and method for manufacturing quantum bit

Abstract

To provide a structure capable of stably developing a hinge helical channel, a quantum bit, a quantum operation device, a manufacturing method of the structure, and a manufacturing method of the quantum bit.SOLUTION: A method of manufacturing a structure includes a step of preparing a hexagonal crystal substrate in which a protrusion having an edge whose longitudinal direction is a [-12-10] direction is formed on a main surface whose plane orientation is a (0001) plane, a step of forming an s-wave superconductor layer containing a first van der Waals layered substance on the substrate by epitaxial growth, and a step of forming a transition metal dichalcogenide layer containing a second van der Waals layered substance on the s-wave superconductor layer by epitaxial growth. The structures can be used, for example, in quantum computing.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a structure, a quantum bit, a quantum processing device, a method for manufacturing a structure, and a method for manufacturing a quantum bit. [Background technology]

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure for generating Majorana particles. A single layer of WTe2, a layered material of transition metal dichalcogenide, is used as the two-dimensional topological insulator. Research is also being conducted on higher-order topological insulator layers consisting of multilayers of WTe2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 9-74232 [Patent Document 2] International Publication No. 2022 / 137421 [Patent Document 3] U.S. Patent Application Publication No. 2021 / 0388488 [Patent Document 4] US Patent Application Publication No. 2020 / 0098990 [Non-patent literature]

[0004] [Non-Patent Document 1] N. Read and D. Green, Phys. Rev. B 61, 10267 (2000) [Non-patent document 2] V. Mourik et al., Science 336, 25 (2012) [Non-patent document 3] J. Alicea, Rep. Prog. Phys. 75, 076501 (2012) [Non-patent document 4] S. Wu et al., Science 359, 76 (2018) [Non-Patent Document 5] Y.-B. Choi et al., Nat. Mater 19, 974 (2020) [Non-patent document 6] LA Walsh et al., 2D Mater. 4, 025044 (2017) Summary of the Invention [Problem to be solved by the invention]

[0005] Although theoretical proposals have been made so far, it is desirable to stably express the hinged helical channel required for generating Majorana particles.

[0006] An object of the present disclosure is to provide a structure, a quantum bit, a quantum processing device, a method for manufacturing a structure, and a method for manufacturing a quantum bit that are capable of stably expressing a hinge helical channel. [Means for solving the problem]

[0007] According to one embodiment of the present disclosure, there is provided a method for manufacturing a structure, the method comprising the steps of: preparing a hexagonal substrate having a (0001)-oriented main surface on which protrusions with edges extending in the [-12-10] direction are formed; epitaxially growing an s-wave superconductor layer including a first van der Waals layer material on the substrate; and epitaxially growing a transition metal dichalcogenide layer including a second van der Waals layer material on the s-wave superconductor layer. [Effects of the Invention]

[0008] According to the present disclosure, hinge helical channels can be stably expressed. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a structure according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the structure according to the first embodiment. [Figure 3] FIG. 3 is a perspective view showing a substrate included in the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view showing a substrate included in the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a method for manufacturing the structure according to the first embodiment. [Figure 6] FIG. 6 shows the results of RHEED observation (part 1). [Figure 7] FIG. 7 shows the results of RHEED observation (part 2). [Figure 8] FIG. 8 shows the results of RHEED observation (part 3). [Figure 9] FIG. 9 shows the results of RHEED observation (part 4). [Figure 10] FIG. 10 shows the results of RHEED observation (part 5). [Figure 11] FIG. 11 shows the results of RHEED observation (part 6). [Figure 12] FIG. 12 is a schematic diagram (part 1) showing the atomic arrangements of the substrate, the s-wave superconductor layer, and the transition metal dichalcogenide layer. [Figure 13] FIG. 13 is a schematic diagram (part 2) showing the atomic arrangements of the substrate, the s-wave superconductor layer, and the transition metal dichalcogenide layer. [Figure 14] FIG. 14 is a top view showing a quantum bit according to the second embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 1) showing a quantum bit according to the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 2) showing a quantum bit according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 3) showing the quantum bit according to the second embodiment. [Figure 18] FIG. 18 is a top view (part 1) showing a method for manufacturing a quantum bit according to the second embodiment. [Figure 19] FIG. 19 is a top view (part 2) showing the method for manufacturing a quantum bit according to the second embodiment. [Figure 20] FIG. 20 is a top view (part 3) illustrating the method for manufacturing a quantum bit according to the second embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 1) showing a method for manufacturing a quantum bit according to the second embodiment. [Figure 22] FIG. 22 is a cross-sectional view (part 2) showing the method for manufacturing a quantum bit according to the second embodiment. [Figure 23] FIG. 23 is a cross-sectional view (part 3) showing the method for manufacturing a quantum bit according to the second embodiment. [Figure 24] FIG. 24 is a cross-sectional view (part 4) illustrating the method for manufacturing a quantum bit according to the second embodiment. [Figure 25] FIG. 25 is a cross-sectional view (part 5) illustrating the method for manufacturing a quantum bit according to the second embodiment. [Figure 26] FIG. 26 is a cross-sectional view (part 6) illustrating the method for manufacturing a quantum bit according to the second embodiment. [Figure 27] FIG. 27 is a cross-sectional view (part 7) illustrating a method for manufacturing a quantum bit according to the second embodiment. [Figure 28] FIG. 28 is a diagram illustrating a quantum processing device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. In the crystallographic descriptions in this disclosure, individual orientations are indicated by brackets [ ] and individual planes by parentheses ( ). Furthermore, while a negative crystallographic index is typically represented by placing a "-" (bar) above a number, in this disclosure, a negative sign is placed before the number. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is referred to as an XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is referred to as a YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is referred to as a ZX plane. For convenience, the Z1-Z2 direction is defined as the up-down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0011] (First embodiment) First, the first embodiment will be described. The first embodiment relates to a structure. FIG. 1 is a perspective view showing the structure according to the first embodiment. FIG. 2 is a cross-sectional view showing the structure according to the first embodiment. FIG. 3 is a perspective view showing a substrate included in the first embodiment. FIG. 4 is a cross-sectional view showing a substrate included in the first embodiment. The crystal orientations in FIGS. 1 to 4 are the crystal orientations of the substrate 110.

[0012] As shown in FIGS. 1 and 2, the structure 100 according to the first embodiment includes a substrate 110, an s-wave superconductor layer 120, and a transition metal dichalcogenide layer .

[0013] The substrate 110 is a hexagonal substrate. The substrate 110 is, for example, a sapphire (α-Al2O3) substrate, a silicon carbide substrate, or a gallium nitride substrate. As shown in FIGS. 1 to 4, the substrate 110 has a primary surface 112 whose plane orientation is (0001). Protrusions 114 having edges 116 with their longitudinal direction in the [-12-10] direction are formed on the primary surface 112. A plurality of protrusions 114 may be formed on the primary surface 112. For example, the height h of the protrusions 114 is 1.42 nm to 3.55 nm, the width (dimension in the short side direction ([10-10] direction)) W is 30 nm to 70 nm, and the period t in the width direction is 50 nm to 200 nm.

[0014] An s-wave superconductor layer 120 is formed on the primary surface 112 of the substrate 110. The s-wave superconductor layer 120 includes a plurality of first van der Waals layered materials, which are two-dimensional materials. The first van der Waals layered material is, for example, NbSe2. The crystal structure of the NbSe2 multilayer film is 2H-type, its space group is P63mmc, and the lattice constant in the a-axis direction is 0.35 nm, the lattice constant in the b-axis direction is 0.35 nm, and the lattice constant in the c-axis direction is 1.38 nm. The s-wave superconductor layer 120 has a plurality of NbSe2 layers, for example, 150 layers. The thickness of the transition metal dichalcogenide layer 130 is, for example, 50 nm to 200 nm. The thickness of one NbSe2 layer is approximately 0.69 nm. The first van der Waals layered material may be NbS2, TaSe2, or TaS2, and in any of these cases, the crystal structure of the multilayer film is 2H-type. The s-wave superconductor layer 120 has a main surface 122 with a (001) plane orientation. On the main surface 122, protrusions 124 are formed, each having an edge 126 with the longitudinal direction in the

[0010] direction (b-axis direction) and the lateral direction in the

[0210] direction. The protrusions 124 are formed following the protrusions 114. For example, the height of the protrusions 124 is 1.42 nm to 3.55 nm, the width is 30 nm to 70 nm, and the period in the width direction is 50 nm to 200 nm. The superconducting critical temperature T c decreases with the number of layers. The superconducting critical temperature T c is about 7.2 K, and the superconducting critical temperature T cIt is about the same as

[0015] A transition metal dichalcogenide layer 130 is formed on the primary surface 122 of the s-wave superconductor layer 120. The transition metal dichalcogenide layer 130 includes a second van der Waals layered material, which is a two-dimensional material. The second van der Waals layered material is, for example, WTe2 (tungsten ditelluride). The WTe2 multilayer film has a Td-type crystal structure, a space group Pmm21, and a lattice constant in the a-axis direction of 0.63 nm, a lattice constant in the b-axis direction of 0.35 nm, and a lattice constant in the c-axis direction of 1.41 nm. The transition metal dichalcogenide layer 130 has multiple layers of WTe2, for example, five layers. The thickness of the transition metal dichalcogenide layer 130 is, for example, 1 nm to 5 nm. The thickness of one layer of WTe2 is approximately 0.71 nm. The second van der Waals layered material may contain Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt as a transition metal, or any combination thereof. The transition metal dichalcogenide layer 130 has a primary surface 132 with a (001) plane orientation. On the primary surface 132, protrusions 134 are formed, each having an edge 136 with a longitudinal direction in the

[0010] direction (b-axis direction) and a lateral direction in the

[0100] direction (a-axis direction). The protrusions 134 are formed following the protrusions 124. For example, the height of the protrusions 134 is 1.42 nm to 3.55 nm, the width is 30 nm to 70 nm, and the period in the width direction is 50 nm to 200 nm.

[0016] Next, a method for manufacturing the structure 100 according to the first embodiment will be described. Fig. 5 is a cross-sectional view showing the method for manufacturing the structure 100 according to the first embodiment. Here, a sapphire substrate is used as the substrate 110, a multilayer film of NbSe2 is formed as the s-wave superconductor layer 120, and a multilayer film of WTe2 is formed as the transition metal dichalcogenide layer 130. The crystal orientation in Fig. 5 is the crystal orientation of the substrate 110.

[0017] First, the substrate 110 (see FIGS. 3 and 4) is formed. In forming the substrate 110, for example, a flat sapphire substrate having a main surface 112 that is a c-plane (with a (0001) plane orientation) is etched to form a plurality of protrusions 114 on the main surface 112, each having edges 116 with their longitudinal directions aligned in the [-12-10] direction.

[0018] To form the protrusions 114, first, a first electron beam resist is spin-coated on the main surface 112. Next, a first mask pattern is formed from the first electron beam resist by electron beam lithography. The first mask pattern covers the portions of the substrate 110 where the protrusions 114 are to be formed and exposes the other portions. For example, the first electron beam resist may be a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1. After forming the first mask pattern, the substrate 110 is processed by Ar ion milling. In the Ar ion milling, for example, a beam acceleration voltage is 280 V and a beam current is 150 mA. As a dry etching process, reactive ion etching (RIE) using Cl-based gases such as Cl2 and BCl3 or F-based gases such as SF6 and CF4 may be performed instead of Ar ion milling.

[0019] After the substrate 110 is formed, the substrate 110 is cleaned. In the cleaning, the substrate 110 is first annealed at approximately 1200°C for 3 to 5 hours in the air or in an oxygen atmosphere at atmospheric pressure. Next, the substrate 110 is immersed in methanol for 20 to 30 minutes and then rinsed with ultrapure water. These processes can improve the flatness of the surface of the substrate 110. For example, the surface of the substrate 110 has atomic-level flatness. In this way, a hexagonal substrate 110 can be prepared, in which protrusions 114 having edges 116 with their longitudinal directions in the [-12-10] direction are formed on the main surface 112.

[0020] 5, an s-wave superconductor layer 120 is formed by epitaxial growth on the primary surface 112 of the substrate 110. The s-wave superconductor layer 120 can be heteroepitaxially grown by, for example, molecular beam epitaxy (MBE). This heteroepitaxial growth is sometimes called van der Waals heteroepitaxial growth.

[0021] When the s-wave superconductor layer 120 is formed by the MBE method, the basic vacuum level is 10 -8 The temperature of the substrate 110 is maintained at approximately 600°C in an ultra-high vacuum chamber in the Pa range, and Nb and Se are co-evaporated. For example, Nb is evaporated onto the substrate 110 by electron beam evaporation at a deposition rate of 0.01 nm / min, and Se is evaporated onto the substrate 110 at a deposition rate of 1 nm / min using a K-cell evaporator heated to 180°C. The s-wave superconductor layer 120 includes, for example, 150 layers of 2H—NbSe2 multilayer film.

[0022] After the s-wave superconductor layer 120 is formed, the deposition of Nb is stopped, but the deposition of Se is continued while post-annealing is performed at 950° C. for 30 minutes. As a result, the crystallinity and surface roughness inside the s-wave superconductor layer 120 can be improved at the atomic level.

[0023] Next, a transition metal dichalcogenide layer 130 is formed by epitaxial growth on the primary surface 122 of the s-wave superconductor layer 120 (see FIGS. 1 and 2). The transition metal dichalcogenide layer 130 can be heteroepitaxially grown by, for example, the MBE method. This heteroepitaxial growth is also sometimes called van der Waals heteroepitaxial growth.

[0024] When the transition metal dichalcogenide layer 130 is formed by the MBE method, the basic vacuum level is 10 -8In an ultra-high vacuum chamber in the Pa range, the temperatures of the substrate 110 and the s-wave superconductor layer 120 are maintained at approximately 210°C, and co-evaporation of W and Te is performed. For example, W is evaporated onto the s-wave superconductor layer 120 by electron beam evaporation at a deposition rate of 0.005 nm / min, and Te is evaporated onto the s-wave superconductor layer 120 at a deposition rate of 1 nm / min using a K-cell evaporator heated to 300°C. The transition metal dichalcogenide layer 130 includes, for example, a five-layer Td-WTe2 multilayer film.

[0025] After the formation of the transition metal dichalcogenide layer 130, the deposition of W is stopped, but the deposition of Te is continued while post-annealing is performed at 250° C. for 30 minutes. As a result, the crystallinity and surface roughness inside the transition metal dichalcogenide layer 130 can be improved at the atomic level.

[0026] The s-wave superconductor layer 120 and the transition metal dichalcogenide layer 130 can be grown in situ by heteroepitaxial growth, for example, in the same vacuum chamber. The s-wave superconductor layer 120 and the transition metal dichalcogenide layer 130 can be formed by physical vapor deposition in a vacuum integrated process. The method for forming the s-wave superconductor layer 120 and the transition metal dichalcogenide layer 130 is not limited to MBE. For example, they may be formed by pulsed laser deposition (PLD) or sputtering.

[0027] In this manner, the structure 100 according to the first embodiment can be manufactured.

[0028] In the structure 100, the crystal orientation of the substrate 110 is inherited by the crystal orientation of the s-wave superconductor layer 120, and the crystal orientation of the s-wave superconductor layer 120 is inherited by the crystal orientation of the transition metal dichalcogenide layer 130. Therefore, the transition metal dichalcogenide layer 130 with good crystallinity can be grown heteroepitaxially.

[0029] Furthermore, convex portions 134 having edges 136 are formed on the primary surface 132 of the transition metal dichalcogenide layer 130, and the edges 136 extend in accordance with the edges 116 of the convex portions 114 of the substrate 110. That is, the edges 136 extend along the <0010> direction (b-axis direction) of Td-WTe2. In the transition metal dichalcogenide layer 130, as shown in FIG. 2 , for each convex portion 134, a hinge helical channel 141 appears at the intersection line between the top surface and one side surface and at the intersection line between the other side surface and the bottom surface of the recess adjacent to the convex portion 134. Between the side surfaces of opposing convex portions 134, a hinge helical channel 141 appears on one side surface at the intersection line with the top surface, and a hinge helical channel 141 appears on the other side surface at the intersection line with the bottom surface of the recess.

[0030] Thus, according to the first embodiment, the hinge helical channel 141 can be stably generated by forming the edge of the transition metal dichalcogenide layer while controlling the longitudinal direction of the edge in the <0010> direction (b-axis direction). In particular, when the height of the protrusion 134 is approximately the same as the thickness of two to five WTe layers (1.42 nm to 3.55 nm), the hinge helical channel 141 can be easily generated without being affected by bulk conductivity.

[0031] Next, the results of in situ reflection high-energy electron diffraction (RHEED) observations of the first embodiment conducted by the present inventors will be described. In these observations, a sample was prepared in accordance with the first embodiment, and this sample was observed by RHEED. The substrate 110 used was a sapphire substrate with protrusions 114 having a height h of 2 nm, a width W of 50 nm, and a period t of 100 nm. The s-wave superconductor layer 120 was formed of a 150-layer NbSe2 multilayer film, and the transition metal dichalcogenide layer 130 was formed of a 5-layer WTe2 multilayer film.

[0032] 6 to 11 show the results of RHEED observation. Fig. 6 shows a diffraction image obtained when the main surface 112 of the substrate 110 is irradiated with an electron beam in a direction substantially parallel to the [10-10] direction of α-Al2O3, and Fig. 7 shows a diffraction image obtained when the main surface 112 of the substrate 110 is irradiated with an electron beam in a direction substantially parallel to the [-12-10] direction of α-Al2O3. Fig. 8 shows a diffraction image obtained when the main surface 122 of the s-wave superconductor layer 120 is irradiated with an electron beam in a direction substantially parallel to the

[0210] direction of NbSe2, and Fig. 9 shows a diffraction image obtained when the main surface 122 of the s-wave superconductor layer 120 is irradiated with an electron beam in a direction substantially parallel to the

[0010] direction of NbSe2. FIG. 10 shows a diffraction image obtained when an electron beam is irradiated onto the primary surface 132 of the transition metal dichalcogenide layer 130 in a direction approximately parallel to the

[0100] direction of WTe2, and FIG. 11 shows a diffraction image obtained when an electron beam is irradiated onto the primary surface 132 of the transition metal dichalcogenide layer 130 in a direction approximately parallel to the

[0010] direction of WTe2.

[0033] 6 and 7, the Kikuchi line appeared in the diffraction image of the substrate 110, confirming good crystallinity on the primary surface 112 of the substrate 110. Furthermore, as shown in FIGS. 8 to 11, streak patterns reflecting the uniformity of the crystals were observed in both the s-wave superconductor layer 120 and the transition metal dichalcogenide layer 130. That is, a streak pattern 151 indicating 2H—NbSe2 and a streak pattern 152 indicating Td—WTe2 were observed.

[0034] 6 to 11, it can be concluded that the crystalline orientation relationships shown in Fig. 12 and Fig. 13 are established among the substrate 110, the s-wave superconductor layer 120, and the transition metal dichalcogenide layer 130 by van der Waals heteroepitaxial growth. Fig. 12 and Fig. 13 are schematic diagrams showing the atomic arrangements of the substrate 110, the s-wave superconductor layer 120, and the transition metal dichalcogenide layer 130. Fig. 12 shows the atomic arrangement when the structure 100 is viewed from the Z2 side, and Fig. 13 shows the atomic arrangement when the structure 100 is viewed from the Y2 side.

[0035] 12 and 13, the

[0210] direction of the 2H-NbSe2 multilayer film and the

[0100] direction (a-axis direction) of the Td-WTe2 multilayer film are aligned with the [10-10] direction of the sapphire substrate, and the

[0010] direction (b-axis direction) of the 2H-NbSe2 multilayer film and the

[0010] direction (b-axis direction) of the Td-WTe2 multilayer film are aligned with the [-12-10] direction of the sapphire substrate. That is, the [10-10] direction of α-Al2O3, the

[0210] direction of 2H-NbSe2, and the

[0100] direction of Td-WTe2 are parallel to one another, and the [-12-10] direction of α-Al2O3, the

[0010] direction of 2H-NbSe2, and the

[0010] direction of Td-WTe2 are parallel to one another.

[0036] (Second embodiment) Next, a second embodiment will be described. The second embodiment relates to a quantum bit. The quantum bit according to the second embodiment is used in a quantum operation device such as a quantum computer. FIG. 14 is a top view showing the quantum bit according to the second embodiment. FIGS. 15, 16, and 17 are cross-sectional views showing the quantum bit according to the second embodiment. FIG. 15 corresponds to a cross-sectional view taken along line XV-XV in FIG. 14. FIG. 16 corresponds to a cross-sectional view taken along line XVI-XVI in FIG. 14. FIG. 17 corresponds to a cross-sectional view taken along line XVII-XVII in FIG. 14.

[0037] The quantum bit 1 according to the second embodiment includes a substrate 210, an s-wave superconductor layer 220, a transition metal dichalcogenide layer 230, and an insulating layer 80. The quantum bit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, a third ferromagnetic insulator layer 33, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63.

[0038] The substrate 210 is a hexagonal substrate. The substrate 210 is, for example, a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate. As shown in FIGS. 14 to 17, the substrate 210 has a primary surface 212 whose plane orientation is a (0001) plane. Protrusions 214A and 214B are formed on the primary surface 212, each having an edge 216 with its longitudinal direction aligned in the [-12-10] direction. The protrusion 214B is on the X1 side of the protrusion 214A. The Y1-Y2 direction is parallel to the [-12-10] direction, and the protrusions 214A and 214B extend along the Y1-Y2 direction. For example, the height of the protrusions 214A and 214B is 1.42 nm to 3.55 nm, the width (dimension in the X1-X direction) is 30 nm to 70 nm, and the distance between the side surface on the X1 side of the protrusion 214A and the side surface on the X1 side of the protrusion 214B is 50 nm to 200 nm. The protrusion 214A is an example of a first protrusion, and the protrusion 214B is an example of a second protrusion. Of the edges 216 of the protrusion 214A, the edge 216 on the protrusion 214B side is an example of a first edge, and of the edges 216 of the protrusion 214B, the edge 216 on the protrusion 214A side is an example of a second edge. The main surface 212 is an example of a first main surface.

[0039] An s-wave superconductor layer 220 is formed on a primary surface 212 of a substrate 210. The s-wave superconductor layer 220 includes a plurality of first van der Waals layered materials, which are two-dimensional materials. The first van der Waals layered material is, for example, NbSe2. The s-wave superconductor layer 220 has a plurality of NbSe2 layers, for example, 150 layers. The transition metal dichalcogenide layer 230 has a thickness of, for example, 50 nm to 200 nm. The first van der Waals layered material may be NbS2, TaSe2, or TaS2. The s-wave superconductor layer 220 has a primary surface 222 whose plane orientation is the (001) plane. Protrusions 224A and 224B are formed on the primary surface 222, each having an edge 226 with its longitudinal direction aligned in the

[0010] direction (b-axis direction) and its lateral direction aligned in the

[0210] direction. The protrusion 224A is formed following the protrusion 214A, and the protrusion 224B is formed following the protrusion 214B. For example, the height of the protrusions 224A and 224B is 1 nm to 5 nm, the width is 30 nm to 70 nm, and the distance between the X1-side side surface of the protrusion 224A and the X1-side side surface of the protrusion 224B is 50 nm to 200 nm. The main surface 222 is an example of a second main surface. The edge 226 is an example of a third edge.

[0040] A transition metal dichalcogenide layer 230 is formed on a primary surface 222 of the s-wave superconductor layer 220. The transition metal dichalcogenide layer 230 includes a second van der Waals layered material, which is a two-dimensional material. The second van der Waals layered material is, for example, WTe2. The transition metal dichalcogenide layer 230 has multiple layers, for example, five layers, of WTe2. The thickness of the transition metal dichalcogenide layer 230 is, for example, 1 nm to 5 nm. The second van der Waals layered material may include, as a transition metal, Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt, or any combination thereof. The transition metal dichalcogenide layer 230 has a primary surface 232 whose plane orientation is a (001) plane. Convex portions 234A and 234B are formed on the main surface 232, each having an edge 236 with its longitudinal direction in the

[0010] direction (b-axis direction) and its lateral direction in the

[0100] direction (a-axis direction). The convex portion 234A is formed following the convex portion 224A, and the convex portion 234B is formed following the convex portion 224B. For example, the height of the convex portions 234A and 234B is 1 nm to 5 nm, the width is 30 nm to 70 nm, and the distance between the X1-side side surface of the convex portion 234A and the X1-side side surface of the convex portion 234B is 50 nm to 200 nm. The main surface 232 is an example of a third main surface. The edge 236 is an example of a fourth edge.

[0041] 15 and 16, in transition metal dichalcogenide layer 230, hinge helical channel 241 appears at the intersection between the top surface of convex portion 234A and the side surface on the X2 side, and hinge helical channel 242 appears at the intersection between the bottom surface of the recess on the X1 side of convex portion 234A and the side surface on the X1 side of convex portion 234A. Furthermore, hinge helical channel 243 appears at the intersection between the top surface of convex portion 234B and the side surface on the X2 side, and hinge helical channel 244 appears at the intersection between the bottom surface of the recess on the X1 side of convex portion 234B and the side surface on the X1 side of convex portion 234B.

[0042] The first ferromagnetic insulator layer 31 is provided on a portion of the protrusion 234A, a portion of the protrusion 234B, and the recess between the protrusions 234A and 234B, and covers a portion of the hinge helical channel 242 and a portion of the hinge helical channel 243. The third ferromagnetic insulator layer 33 is provided on a portion of the protrusion 234A, a portion of the protrusion 234B, and the recess between the protrusions 234A and 234B, and covers a portion of the hinge helical channel 242 and a portion of the hinge helical channel 243. The third ferromagnetic insulator layer 33 is on the Y2 side of the first ferromagnetic insulator layer 31. The second ferromagnetic insulator layer 32 is provided on a portion of the protrusion 234A and a portion of the recess between the protrusions 234A and 234B, and covers a portion of the hinge helical channel 242. The second ferromagnetic insulator layer 32 is located between the first ferromagnetic insulator layer 31 and the third ferromagnetic insulator layer 33 in the Y1-Y2 direction. The distance between the first ferromagnetic insulator layer 31 and the second ferromagnetic insulator layer 32 in the Y1-Y2 direction is large enough to allow one Majorana grain to appear between them, and the distance between the third ferromagnetic insulator layer 33 and the second ferromagnetic insulator layer 32 is also large enough to allow one Majorana grain to appear between them. Examples of materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 include Cr2Ga2Te6. The materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may also be other diluted magnetic semiconductors. The thicknesses of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 are, for example, approximately 50 nm. The first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 are examples of ferromagnetic layers. The portion of the edge 216 of the convex portion 214A on the convex portion 214B side that is covered by the first ferromagnetic insulator layer 31 is an example of a first portion, the portion covered by the second ferromagnetic insulator layer 32 is an example of a third portion, and the portion covered by the third ferromagnetic insulator layer 33 is an example of a fourth portion. The portion of the edge 216 of the convex portion 214B on the convex portion 214A side that is covered by the first ferromagnetic insulator layer 31 is an example of a second portion, and the portion covered by the third ferromagnetic insulator layer 33 is an example of a fifth portion.

[0043] Four Majorana particles γ1, γ2, γ3, and γ4 are generated in quantum bit 1. For example, Majorana particle γ1 is generated stably near the Y2 side of first ferromagnetic insulator layer 31 in hinge helical channel 243, and Majorana particle γ2 is generated stably between first ferromagnetic insulator layer 31 and second ferromagnetic insulator layer 32 in hinge helical channel 242. Furthermore, Majorana particle γ4 is generated stably near the Y1 side of third ferromagnetic insulator layer 33 in hinge helical channel 243, and Majorana particle γ3 is generated stably between the third ferromagnetic insulator layer 33 and second ferromagnetic insulator layer 32 in hinge helical channel 242.

[0044] The first gate electrode 41 is provided on the first ferromagnetic insulator layer 31. The second gate electrode 42 is provided on the second ferromagnetic insulator layer 32. The third gate electrode 43 is provided on the third ferromagnetic insulator layer 33. The first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 may be made of Au. The first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 each have a thickness of, for example, about 30 nm.

[0045] The insulating layer 80 is formed on the primary surface 232 of the transition metal dichalcogenide layer 230. The upper surface of the insulating layer 80 is located higher (on the Z2 side) than the upper surfaces of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. Examples of materials for the insulating layer 80 include HfO2, Al2O3, Si3N4, HfSiO, HfAlON, YO3, SrTiO3, PbZrTiO3, and BaTiO3. The thickness of the insulating layer 80 is, for example, approximately 100 nm. A first contact hole 81, a second contact hole 82, and a third contact hole 83 are formed in the insulating layer 80. The first gate electrode 41 is exposed through the first contact hole 81, the second gate electrode 42 is exposed through the second contact hole 82, and the third gate electrode 43 is exposed through the third contact hole 83.

[0046] The quantum bit 1 includes a lower superconductor layer 50, a first upper superconductor layer 61A, a second upper superconductor layer 62A, and a third upper superconductor layer 63A.

[0047] The lower superconductor layer 50 is provided on the insulating layer 80 and has a first region 51, a second region 52, and a third region 53. The lower superconductor layer 50 is made of, for example, Al. The lower superconductor layer 50 has a thickness of, for example, about 50 nm. The first region 51 has a U-shaped planar shape and is located near the first gate electrode 41. The first region 51 has an X1-side portion, an X2-side portion, and a Y2-side portion of the first gate electrode 41. The second region 52 has a U-shaped planar shape and is located near the second gate electrode 42. The second region 52 has a Y1-side portion, a Y2-side portion, and an X1-side portion of the second gate electrode 42. The third region 53 has a U-shaped planar shape and is located near the third gate electrode 43. The third region 53 has a portion on the X1 side of the third gate electrode 43, a portion on the X2 side, and a portion on the Y1 side.

[0048] A part of the first region 51 may overlap with a part of the second region 52, and a part of the second region 52 may overlap with a part of the third region 53. For example, a part of the first region 51 may overlap with a part of the second region 52 above the Majorana particles γ1 and γ2, and a part of the second region 52 may overlap with a part of the third region 53 above the Majorana particles γ3 and γ4.

[0049] The first SQUID 61 has a first region 51 of the lower superconductor layer 50, a pair of first tunnel barrier layers (not shown), and a first upper superconductor layer 61A. The first tunnel barrier layers are provided on two ends of the first region 51 of the lower superconductor layer 50 on the Y1 side. The material of the first tunnel barrier layer is AlO xThe first upper superconductor layer 61A has a U-shaped planar shape, with one end on one of the first tunnel barrier layers and the other end on the other first tunnel barrier layer. The first upper superconductor layer 61A is made of Al, for example. The first upper superconductor layer 61A has a thickness of, for example, about 50 nm. Thus, the first SQUID 61 includes a pair of Josephson junctions. The first SQUID 61 also includes a loop surrounding the first ferromagnetic insulator layer 31 in plan view.

[0050] The second SQUID 62 has the second region 52 of the lower superconductor layer 50, a pair of second tunnel barrier layers 62B, and a second upper superconductor layer 62A. The second tunnel barrier layer 62B is provided on two ends of the second region 52 of the lower superconductor layer 50 on the X2 side. The material of the second tunnel barrier layer 62B is AlO x The second upper superconductor layer 62A has a U-shaped planar shape, with one end on one of the second tunnel barrier layers 62B and the other end on the other second tunnel barrier layer 62B. The second upper superconductor layer 62A is made of Al, for example. The second upper superconductor layer 62A has a thickness of, for example, about 50 nm. Thus, the second SQUID 62 includes a pair of Josephson junctions. The second SQUID 62 also includes a loop surrounding the second ferromagnetic insulator layer 32 in plan view.

[0051] The third SQUID 63 has a third region 53 of the lower superconductor layer 50, a pair of third tunnel barrier layers (not shown), and a third upper superconductor layer 63A. The third tunnel barrier layers are provided on the two ends of the third region 53 of the lower superconductor layer 50 on the Y2 side. The material of the third tunnel barrier layer is AlO xThe third upper superconductor layer 63A has a U-shaped planar shape, with one end on one of the third tunnel barrier layers and the other end on the other third tunnel barrier layer. The third upper superconductor layer 63A can be made of Al, for example. The third upper superconductor layer 63A has a thickness of, for example, about 50 nm. Thus, the third SQUID 63 includes a pair of Josephson junctions. The third SQUID 63 also includes a loop surrounding the third ferromagnetic insulator layer 33 in plan view.

[0052] In the quantum bit 1 configured in this manner, the Majorana particles γ1 to γ4 are exchanged by a change in electrostatic potential caused by application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.

[0053] For example, in the exchange between Majorana fermions γ1 and γ2, an electric field is applied from the first gate electrode 41, and a minute change in magnetic flux during the exchange between Majorana fermions γ1 and γ2 is detected by the first SQUID 61 as a minute change in voltage signal. In the exchange between Majorana fermions γ2 and γ3, an electric field is applied from the second gate electrode 42, and a minute change in magnetic flux during the exchange between Majorana fermions γ2 and γ3 is detected by the second SQUID 62 as a minute change in voltage signal. In addition, in the exchange between Majorana fermions γ3 and γ4, an electric field is applied from the third gate electrode 43, and a minute change in magnetic flux during the exchange between Majorana fermions γ3 and γ4 is detected by the third SQUID 63 as a minute change in voltage signal.

[0054] Next, a method for manufacturing the quantum bit 1 according to the second embodiment will be described. Figures 18 to 20 are top views showing the method for manufacturing the quantum bit 1 according to the second embodiment. Figures 21 to 27 are cross-sectional views showing the method for manufacturing the quantum bit 1 according to the second embodiment.

[0055] 18 and 21, following the first embodiment, processes from the formation of a substrate 210 to the formation of a transition metal dichalcogenide layer 230 are performed. As a result, hinge helical channels 241, 242, 243, and 244 extending along the <0010> direction (b-axis direction) of WTe2 appear in the transition metal dichalcogenide layer 230. FIG. 21 corresponds to a cross-sectional view taken along line XXI-XXI in FIG. 18.

[0056] Next, as shown in Figures 19, 22, 24, and 26, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, a third ferromagnetic insulator layer 33, a first gate electrode 41, a second gate electrode 42, and a third gate electrode 43 are formed. Figure 22 corresponds to a cross-sectional view taken along line XXII-XXII in Figure 19. Figure 24 corresponds to a cross-sectional view taken along line XXIV-XXIV in Figure 19. Figure 26 corresponds to a cross-sectional view taken along line XXVI-XXVI in Figure 19.

[0057] When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, a second electron beam resist is first spin-coated onto the transition metal dichalcogenide layer 230. Next, a second mask pattern is formed from the second electron beam resist by electron beam lithography. The second mask pattern exposes the portions where the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 will be formed, and covers the other portions. For example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used as the second electron beam resist. After forming the second mask pattern, a Cr2Ga2Te6 layer and an Au layer are formed by PLD.

[0058] When forming the Cr2Ga2Te6 layer by the PLD method, for example, the temperature of the substrate 210 is kept at 200°C, and the laser energy density is set to 1.0 J / cm 2 ~2.0J / cm 2The irradiation frequency is set to 1 Hz, the distance between the substrate 210 and the target is set to about 5 cm, and the film formation rate is set to 1.0 nm / min to 2.0 nm / min.

[0059] When the Au layer is formed by the PLD method, for example, the temperature of the substrate 210 is kept at room temperature, and the laser energy density is set to 1.0 J / cm 2 2 ~2.0J / cm 2 The irradiation frequency is set to 5 Hz, the distance between the substrate 210 and the target is set to about 5 cm, and the film formation rate is set to 5.0 nm / min to 10.0 nm / min.

[0060] After the Cr2Ga2Te6 layer and the Au layer are formed, the second mask pattern is removed together with the Cr2Ga2Te6 layer and the Au layer deposited thereon. This is called lift-off. As a result, the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained. Furthermore, four Majorana particles γ1, γ2, γ3, and γ4 are generated.

[0061] 20, 23, 25, and 27, an insulating layer 80 is formed, and a first contact hole 81, a second contact hole 82, and a third contact hole 83 are formed in the insulating layer 80. FIG. 23 corresponds to a cross-sectional view taken along line XXIII-XXIII in FIG. 20. FIG. 25 corresponds to a cross-sectional view taken along line XXV-XXV in FIG. 20. FIG. 27 corresponds to a cross-sectional view taken along line XXVII-XXVII in FIG. 20.

[0062] When forming the insulating layer 80, for example, a HfO2 layer is formed by atomic layer deposition (ALD). When forming the HfO2 layer by ALD, for example, tetrakis(dimethylamino)hafnium and H2O are used as precursors, and the deposition temperature is set to 250°C. The insulating layer 80 may be formed of an Al2O3 layer, Si3N4 layer, HfSiO layer, HfAlON layer, YO3 layer, SrTiO3 layer, PbZrTiO3 layer, BaTiO3 layer, or the like. The method for forming the insulating layer 80 can be selected appropriately depending on the material.

[0063] When forming the first contact hole 81, the second contact hole 82, and the third contact hole 83, first, a third electron beam resist is spin-coated onto the upper surface of the insulating layer 80. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern covers the portions of the insulating layer 80 where the first contact hole 81, the second contact hole 82, and the third contact hole 83 are to be formed, and leaves the other portions exposed. As the third electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used. After forming the third mask pattern, the insulating layer 80 is processed by Ar ion milling.

[0064] Next, the first SQUID 61, the second SQUID 62, and the third SQUID 63 are formed on the insulating layer 80 (see FIGS. 14 to 17).

[0065] When forming the first SQUID 61, the second SQUID 62, and the third SQUID 63, first, a fourth electron beam resist is spin-coated on the upper surface of the insulating layer 80. Next, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography. The fourth mask pattern exposes the portion where the lower superconductor layer 50 is to be formed and covers the other portions. For example, a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1 can be used as the fourth electron beam resist. After forming the fourth mask pattern, an Al layer is formed by evaporation. When forming the Al layer by evaporation, for example, the temperature of the substrate 210 is maintained at room temperature and the film formation rate is set to 5.0 nm / min. After forming the Al layer, the fourth mask pattern is removed together with the Al layer deposited thereon. In other words, lift-off is performed. As a result, the lower superconductor layer 50 is obtained.

[0066] After the formation of the lower superconductor layer 50, a fifth electron beam resist is spin-coated onto the upper surfaces of the insulating layer 80 and the lower superconductor layer 50. Next, a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography. The fifth mask pattern exposes the portions where the first tunnel barrier layer, the second tunnel barrier layer 62B, and the third tunnel barrier layer are to be formed, and covers the other portions. As the fifth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) at a ratio of 1:1 can be used. After the formation of the fifth mask pattern, AlO x Forms a layer of AlO x When forming the layer by vapor deposition, for example, the temperature of the substrate 210 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is set to about 50 Pa, and Al is vapor-deposited. x After the formation of the layer, a fifth mask pattern is formed on the AlO x As a result, the first tunnel barrier layer, the second tunnel barrier layer 62B, and the third tunnel barrier layer are obtained.

[0067] After the first tunnel barrier layer, the second tunnel barrier layer 62B, and the third tunnel barrier layer are formed, a sixth electron beam resist is spin-coated on the upper surfaces of the insulating layer 80, the lower superconductor layer 50, the first tunnel barrier layer, the second tunnel barrier layer 62B, and the third tunnel barrier layer. Next, a sixth mask pattern is formed from the sixth electron beam resist by electron beam lithography. The sixth mask pattern exposes the areas where the first upper superconductor layer 61A, the second upper superconductor layer 62A, and the third upper superconductor layer 63A are to be formed, and covers the other areas. For example, the sixth electron beam resist may be a resist obtained by diluting ZEP 520A (manufactured by Zeon Corporation) with ZEP-A (manufactured by Zeon Corporation) at a ratio of 1:1. After the sixth mask pattern is formed, an Al layer is formed by evaporation. When forming the Al layer by evaporation, the temperature of the substrate 210 is maintained at room temperature, and the deposition rate is set to 5.0 nm / min. After the Al layer is formed, the sixth mask pattern is removed together with the Al layer deposited thereon. That is, lift-off is performed. As a result, a portion where the first upper superconductor layer 61A is to be formed, a portion where the second upper superconductor layer 62A is to be formed, and a third upper superconductor layer 63A are to be obtained.

[0068] In this way, the quantum bit 1 according to the second embodiment can be manufactured.

[0069] In the quantum bit 1, the crystal orientation of the substrate 210 is inherited by the crystal orientation of the s-wave superconductor layer 220, and the crystal orientation of the s-wave superconductor layer 220 is inherited by the crystal orientation of the transition metal dichalcogenide layer 230. Therefore, the transition metal dichalcogenide layer 230 with good crystallinity can be grown heteroepitaxially.

[0070] Furthermore, hinge helical channels 241, 242, 243, and 244 extending parallel to the b-axis direction of the Td-WTe multilayer film are stably generated in the transition metal dichalcogenide layer 230. Therefore, Majorana particles γ1, γ2, γ3, and γ4 can be stably generated at desired positions.

[0071] It is also possible to provide multiple quantum bits 1 on the substrate 210 to achieve a multi-qubit configuration, or to mount a semiconductor integrated circuit on the substrate 210. Therefore, according to this embodiment, it is possible to accelerate research and development toward realizing a practical error-tolerant quantum computer.

[0072] In the second embodiment, Nb or Pb may be used as the material for the lower superconductor layer 50, the first upper superconductor layer 61A, the second upper superconductor layer 62A, and the third upper superconductor layer 63A, and an oxide thereof, i.e., NbO x or PbO x may also be used.

[0073] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a quantum processing device including the quantum bit 1 according to the second embodiment. Fig. 28 is a diagram showing the quantum processing device according to the third embodiment.

[0074] As shown in FIG. 28 , the quantum processing device 2 according to the third embodiment includes a quantum bit chip 381, a signal generator 382, ​​a signal demodulator 383, and a cryogenic dilution refrigerator 384. The quantum bit chip 381 includes a plurality of quantum bits 1 according to the second embodiment. The quantum bit chip 381 is housed in the cryogenic dilution refrigerator 384 and cooled to a temperature of 10 mK or less. The signal generator 382 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 381. The quantum bit chip 381 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 383 demodulates the signal output from the quantum bit chip 381. The signal generator 382 and the signal demodulator 383 are used at a temperature around room temperature, for example.

[0075] Since the quantum processing device 2 according to the third embodiment includes the quantum bit 1 according to the second embodiment, it is possible to stably generate Majorana particles and perform stable operations.

[0076] The structures, qubits and quantum processing devices of the present disclosure can be used, for example, in quantum computing.

[0077] Although the preferred embodiments have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0078] Various aspects of the present disclosure are summarized below as appendices.

[0079] (Appendix 1) preparing a hexagonal substrate having a main surface with a (0001) plane orientation, on which protrusions with edges extending in the [-12-10] direction are formed; forming an s-wave superconductor layer including a first van der Waals layered material on the substrate by epitaxial growth; forming a transition metal dichalcogenide layer including a second van der Waals layer material on the s-wave superconductor layer by epitaxial growth; A method for manufacturing a structure, comprising: (Appendix 2) 2. A method for producing a structure according to claim 1, wherein the transition metal dichalcogenide layer is a higher-order topological insulator layer containing a plurality of transition metal dichalcogenides stacked on the s-wave superconductor layer. (Appendix 3) 3. The method for producing a structure according to claim 1, wherein the second van der Waals layered material contains WTe2. (Appendix 4) 4. The method for producing a structure according to claim 3, wherein the height of the protrusions is equal to the thickness of two to five layers of WTe2. (Appendix 5) 4. A method for producing a structure according to any one of claims 1 to 3, wherein the first van der Waals layered material contains NbSe2, NbS2, TaSe2 or TaS2. (Appendix 6) preparing a hexagonal substrate having a main surface with a (0001) plane orientation, on which a first protrusion having a first edge with a longitudinal direction in the [-12-10] direction is formed; forming an s-wave superconductor layer including a first van der Waals layered material on the substrate by epitaxial growth; forming a transition metal dichalcogenide layer including a second van der Waals layer material on the s-wave superconductor layer by epitaxial growth; forming a first ferromagnetic layer on the transition metal dichalcogenide layer to cover a first portion of the first edge; 1. A method for manufacturing a quantum bit, comprising: (Appendix 7) 7. The method for manufacturing a quantum bit according to claim 6, wherein the transition metal dichalcogenide layer is a higher-order topological insulator layer including a plurality of transition metal dichalcogenides stacked on the s-wave superconductor layer. (Appendix 8) 8. The method for producing a quantum bit according to claim 6 or 7, wherein the second van der Waals layered material contains WTe2. (Appendix 9) 9. The method for producing a quantum bit according to claim 8, wherein the height of the first convex portion is equal to the thickness of two to five layers of WTe2. (Appendix 10) 10. The method for producing a quantum bit according to any one of claims 6 to 9, wherein the first van der Waals layered material comprises NbSe2, NbS2, TaSe2, or TaS2. (Appendix 11) a second protrusion having a second edge with a longitudinal direction in the [-12-10] direction is formed on the substrate, the second protrusion being spaced apart from the first protrusion; the first ferromagnetic layer is formed to further cover a second portion of the second edge; forming a second ferromagnetic layer on the transition metal dichalcogenide layer, the second ferromagnetic layer covering a third portion of the first edge spaced from the first portion; forming a third ferromagnetic layer on the transition metal dichalcogenide layer, the third ferromagnetic layer covering a fourth portion of the first edge spaced apart from the first and third portions and a fifth portion of the second edge spaced apart from the second portion; and 12. The method for manufacturing a quantum bit according to claim 6, wherein the second ferromagnetic layer is located between the first ferromagnetic layer and the third ferromagnetic layer in a direction along the first edge. (Appendix 12) a hexagonal substrate having a first main surface with a (0001) plane orientation and a first protrusion having a first edge with a longitudinal direction in the [-12-10] direction; an s-wave superconductor layer provided on the substrate, the s-wave superconductor layer including a first van der Waals layered material having a third edge with a longitudinal direction in the

[0010] direction on a second main surface having a (001) plane orientation; a transition metal dichalcogenide layer including a second van der Waals layered material, the transition metal dichalcogenide layer being provided on the s-wave superconductor layer, the transition metal dichalcogenide layer having a third main surface with a (001) plane orientation and a fourth edge with a longitudinal direction in the

[0010] direction; a first ferromagnetic layer disposed on the transition metal dichalcogenide layer and covering a first portion of the first edge; A quantum bit comprising: (Appendix 13) 13. The quantum bit of claim 12, wherein the transition metal dichalcogenide layer is a higher-order topological insulator layer including a plurality of transition metal dichalcogenides stacked on the s-wave superconductor layer. (Appendix 14) 14. The quantum bit of claim 12 or 13, wherein the second van der Waals layered material comprises WTe2. (Appendix 15) 15. The quantum bit according to claim 14, wherein the height of the first protrusion is equal to the thickness of two to five layers of WTe2. (Appendix 16) 16. The quantum bit of any one of claims 12 to 15, wherein the first van der Waals layered material comprises NbSe2, NbS2, TaSe2, or TaS2. (Appendix 17) a second protrusion having a second edge with a longitudinal direction in the [-12-10] direction is formed on the substrate, the second protrusion being spaced apart from the first protrusion; the first ferromagnetic layer further covers a second portion of the second edge; a second ferromagnetic layer disposed on the transition metal dichalcogenide layer and covering a third portion of the first edge spaced apart from the first portion; a third ferromagnetic layer provided on the transition metal dichalcogenide layer, covering a fourth portion of the first edge spaced apart from the first and third portions, and a fifth portion of the second edge spaced apart from the second portion; and 17. The quantum bit according to any one of claims 12 to 16, wherein the second ferromagnetic layer is located between the first ferromagnetic layer and the third ferromagnetic layer in a direction along the first edge. (Appendix 18) a first superconducting quantum interference meter having a loop surrounding the first ferromagnetic layer in a plan view; a second superconducting quantum interference meter having a loop surrounding the second ferromagnetic layer in a plan view; a third superconducting quantum interference device having a loop surrounding the third ferromagnetic layer in a plan view; 18. The quantum bit of claim 17, comprising: (Appendix 19) a first gate electrode provided on the first ferromagnetic layer; a second gate electrode provided on the second ferromagnetic layer; a third gate electrode provided on the third ferromagnetic layer; 18. The quantum bit of claim 17, comprising: (Appendix 20) 20. A quantum computing device comprising the quantum bit according to any one of appendices 12 to 19. [Explanation of symbols]

[0080] 1: Quantum bit 2: Quantum computing device 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate electrode 42: Second gate electrode 43: Third gate electrode 50: Lower superconductor layer 61: First SQUID 62:2nd SQUID 63: The Third SQUID 100: Structure 110, 210: Substrate 112, 122, 132, 212, 222, 232: Main surfaces 114, 124, 134, 214A, 214B, 224A, 224B, 234A, 234B: Convex parts 116, 126, 136, 216, 226, 236: Edge 120, 220: s-wave superconductor layer 130, 230: Transition metal dichalcogenide layer 141, 241, 242, 243, 244: hinged helical channel

Claims

1. preparing a hexagonal substrate having a main surface with a (0001) plane orientation, on which protrusions with edges extending in the [-12-10] direction are formed; forming an s-wave superconductor layer comprising a first van der Waals layer material on the substrate by epitaxial growth; forming a transition metal dichalcogenide layer including a second van der Waals layer material on the s-wave superconductor layer by epitaxial growth; A method for manufacturing a structure, comprising:

2. 2. The method for manufacturing a structure according to claim 1, wherein the transition metal dichalcogenide layer is a high-order topological insulator layer containing a plurality of transition metal dichalcogenides stacked on the s-wave superconductor layer.

3. The second van der Waals layered material is WTe ２ 3. The method for manufacturing a structure according to claim 1, further comprising:

4. The first van der Waals layered material is NbSe ２ , NbS ２ , TaSe ２ or TaS ２ 3. The method for manufacturing a structure according to claim 1, further comprising:

5. preparing a hexagonal substrate having a main surface with a (0001) plane orientation, on which first protrusions each having a first edge with a longitudinal direction in the [-12-10] direction are formed; forming an s-wave superconductor layer comprising a first van der Waals layer material on the substrate by epitaxial growth; forming a transition metal dichalcogenide layer including a second van der Waals layer material on the s-wave superconductor layer by epitaxial growth; forming a first ferromagnetic layer on the transition metal dichalcogenide layer, the first ferromagnetic layer covering a first portion of the first edge; 1. A method for manufacturing a quantum bit, comprising:

6. 6. The method for manufacturing a quantum bit according to claim 5, wherein the transition metal dichalcogenide layer is a higher-order topological insulator layer including a plurality of transition metal dichalcogenides stacked on the s-wave superconductor layer.

7. The second van der Waals layered material is WTe ２ 7. The method for producing a quantum bit according to claim 5, further comprising:

8. The first van der Waals layered material is NbSe ２ , NbS ２ , TaSe ２ or TaS ２ 7. The method for producing a quantum bit according to claim 5, further comprising:

9. a second protrusion having a second edge with a longitudinal direction in the [-12-10] direction is formed on the substrate, the second protrusion being spaced apart from the first protrusion; the first ferromagnetic layer is formed to further cover a second portion of the second edge; forming a second ferromagnetic layer on the transition metal dichalcogenide layer, the second ferromagnetic layer covering a third portion of the first edge remote from the first portion; forming a third ferromagnetic layer on the transition metal dichalcogenide layer, the third ferromagnetic layer covering a fourth portion of the first edge spaced apart from the first and third portions and a fifth portion of the second edge spaced apart from the second portion; and 7. The method for manufacturing a quantum bit according to claim 5, wherein the second ferromagnetic layer is located between the first ferromagnetic layer and the third ferromagnetic layer in a direction along the first edge.

10. a hexagonal substrate having a first main surface with a (0001) plane orientation and a first protrusion formed thereon, the first protrusion having a first edge with a longitudinal direction in the [-12-10] direction; an s-wave superconductor layer provided on the substrate, the s-wave superconductor layer including a first van der Waals layered material having a second main surface with a (001) plane orientation and a third edge with a longitudinal direction in the [010] direction; a transition metal dichalcogenide layer including a second van der Waals layer material, the second van der Waals layer material having a third main surface with a (001) plane orientation and a fourth edge with a longitudinal direction in a [010] direction, the second van der Waals layer material being provided on the s-wave superconductor layer; a first ferromagnetic layer disposed on the transition metal dichalcogenide layer and covering a first portion of the first edge; A quantum bit comprising:

11. 11. The quantum bit of claim 10, wherein the transition metal dichalcogenide layer is a higher-order topological insulator layer including a plurality of transition metal dichalcogenides stacked on the s-wave superconductor layer.

12. The second van der Waals layered material is WTe ２ 12. A quantum bit according to claim 10 or 11, comprising:

13. The first van der Waals layered material is NbSe ２ , NbS ２ , TaSe ２ or TaS ２ 12. A quantum bit according to claim 10 or 11, comprising:

14. a second protrusion having a second edge with a longitudinal direction in the [-12-10] direction is formed on the substrate, the second protrusion being spaced apart from the first protrusion; the first ferromagnetic layer further covers a second portion of the second edge; a second ferromagnetic layer disposed on the transition metal dichalcogenide layer and covering a third portion of the first edge spaced apart from the first portion; a third ferromagnetic layer provided on the transition metal dichalcogenide layer and covering a fourth portion of the first edge spaced apart from the first and third portions and a fifth portion of the second edge spaced apart from the second portion; and The quantum bit according to claim 10 or 11, wherein the second ferromagnetic layer is located between the first ferromagnetic layer and the third ferromagnetic layer in the direction along the first edge.

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