Electro-optic device and electronic appliance

Abstract

To avoid the overlap of noise, which is caused due to potential variation of a selection signal, with a data signal.SOLUTION: Three selection signal lines 180 and three inversion selection signal lines 181 are provided along an X direction. A data line 14 and data signal lines 13_1 to 13_3 are provided along a Y direction. A transistor N1 has an input end connected to any of the data signal lines 13_1 to 13_3 and an output end connected to the data line 14. The conduction state between the input end and the output end is defined based on a selection signal and an inversion selection signal. A capacitance Sc1a parasitic between the data signal line 13_1 and the selection signal line 180 and a capacitance Sc1b parasitic between the data signal line 13_1 and the inversion signal line 181 which constitutes a pair with the selection signal line 180 are in substantially the same relation.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In a demultiplexer-type electro-optical device, data lines are grouped into groups of several lines. Data signals are supplied to data signal lines provided corresponding to each group. The data signals are distributed to each data line by switching elements whose on or off state is determined by a selection signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-240830 Summary of the Invention [Problem to be solved by the invention]

[0004] However, such a demultiplexer has a problem in that noise caused by potential fluctuations in the selection signal is superimposed on the data signal, degrading the display quality. [Means for solving the problem]

[0005] In order to solve the above-described problems, an electro-optical device according to an embodiment of the present disclosure includes a plurality of data lines including k (k is an integer of 2 or more) data lines that are grouped together, data signal lines that output data signals corresponding to the k data lines according to gradations of pixels, k selection signal lines to which selection signals are respectively supplied, k inverted selection signal lines that form pairs with the k selection signal lines and are respectively supplied with inverted signals of the selection signals, and switching elements provided in one-to-one correspondence with the plurality of data lines, wherein the k selection signal lines and the k inverted selection signal lines are provided along a first direction, the data signal lines and the data signal lines are arranged along a second direction intersecting the first direction, the switching element has an input terminal connected to the data signal line and an output terminal connected to one of the k data lines, the conduction state between the input terminal and the output terminal is determined based on the selection signal and the inverted selection signal line, and a first coupling capacitance between the data signal line and one of the k selection signal lines and a second coupling capacitance between the data signal line and one of the k inverted selection signal lines that forms a pair with the one selection signal line have approximately the same relationship. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view showing an electro-optical device according to a first embodiment. [Figure 2] FIG. 1 is a block diagram showing a configuration of an electro-optical device. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a pixel circuit in an electro-optical device. [Figure 4] FIG. 2 is a diagram showing the arrangement of each part in the electro-optical device. [Figure 5] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 6] FIG. 10 is a diagram illustrating a configuration of a demultiplexer of an electro-optical device according to a comparative example. [Figure 7] FIG. 10 is a diagram for explaining a problem in the comparative example. [Figure 8]FIG. 2 is a diagram showing the configuration of a demultiplexer of the electro-optical device according to the first embodiment. [Figure 9] FIG. 2 is a diagram illustrating noise cancellation in the first embodiment. [Figure 10] FIG. 10 is a diagram showing the configuration of a demultiplexer of an electro-optical device according to a second embodiment. [Figure 11] FIG. 10 is a diagram showing the configuration of a demultiplexer of an electro-optical device according to a third embodiment. [Figure 12] FIG. 2 is a cross-sectional view of a main part for explaining a wiring layer of the electro-optical device. [Figure 13] FIG. 10 is a plan view showing a main part of an electro-optical device according to a third embodiment. [Figure 14] 1 is a diagram showing a projection display device to which an electro-optical device according to an embodiment is applied; DETAILED DESCRIPTION OF THE INVENTION

[0007] Projection display devices according to embodiments will be described below with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from those of the actual device. The embodiments described below are preferred examples, and therefore various technically preferable limitations are applied. However, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0008] FIG. 1 is a perspective view showing the configuration of a module 1 including an electro-optical device 100 according to an embodiment. The electro-optical device 100 is a transmissive liquid crystal panel used, for example, as a light valve in a projection display device. The electro-optical device 100 is housed in a frame-shaped case 72 that opens to a rectangular display area 10. One end of an FPC board 74 is connected to the electro-optical device 100. FPC is an abbreviation for Flexible Printed Circuits. A plurality of terminals 76 are provided on the other end of the FPC board 74, and are connected to a higher-level circuit (not shown).

[0009] The display control circuit 30, which is a semiconductor chip, is mounted on the FPC board 74 by face-down bonding, and video data is supplied from a higher-level circuit in synchronization with a synchronization signal via multiple terminals 76. The video data defines the gradation of pixels in the image to be displayed, for example, in 8 bits.

[0010] In the drawing, the X direction is the longitudinal direction of the display area 10, that is, the direction in which the scanning lines extend, and the Y direction is the lateral direction of the display area 10, that is, the direction in which the data lines extend. When the electro-optical device 100 is used as a light valve in a projection display device, transmitted images from three electro-optical devices 100 corresponding to the primary colors R (red), G (green), and B (blue) are synthesized to display a color image, as will be described later. Therefore, a pixel, which is the smallest unit of a color image, is expressed by additive color mixing of a red subpixel formed by an electro-optical device corresponding to R, a green subpixel formed by an electro-optical device corresponding to G, and a blue subpixel formed by an electro-optical device corresponding to B. However, when it is not necessary to specify the color of the red, green, and blue subpixels or when only brightness is an issue, there is no need to refer to them as subpixels. Therefore, in this explanation, the red, green, and blue subpixels will also be referred to simply as "pixels."

[0011] The synchronization signals include a vertical synchronization signal that instructs the pixels arranged in the display area 10 to start vertical scanning, a horizontal synchronization signal that instructs the pixels to start horizontal scanning, and a clock signal that indicates the timing of one pixel of video data. The display control circuit 30 processes the video data and synchronization signals, and outputs data signals and control signals necessary for driving the electro-optical device 100. The data signals are analog signals obtained by converting the video data, and the control signals are signals for controlling vertical scanning and horizontal scanning in the electro-optical device 100. The display control circuit 30 may be provided in a higher-level circuit, rather than being mounted on the FPC board 74, and may receive video signals and control signals via terminals .

[0012] 2 is a block diagram showing the electrical configuration of the module 1. The module 1 includes the above-described electro-optical device 100 and a display control circuit 30. A scanning line driving circuit 130 and a peripheral circuit 150 are provided on the periphery of the display area 10 of the electro-optical device 100. The electro-optical device 100 is configured by sealing liquid crystal between an element substrate on which thin film transistors and the like are formed and an opposing substrate on which a common electrode is formed, and a scanning line driving circuit 130 and a peripheral circuit 150 are formed on the element substrate.

[0013] In the display region 10 of the electro-optical device 100, pixel circuits 110 corresponding to the pixels of the image to be displayed are arranged in a matrix. More specifically, in the display region 10, m scanning lines 12 are provided extending horizontally in the figure, and a total of (3n) columns of data lines 14, grouped into groups of three columns, extend vertically in the figure and are provided electrically insulated from the scanning lines 12. The pixel circuits 110 are provided at intersections of the m scanning lines 12 and the (3n) data lines 14. Therefore, in this embodiment, the pixel circuits 110 are arranged in a matrix of m rows and (3n) columns.

[0014] Here, m is an integer equal to or greater than 2. n is an integer equal to or greater than 2. In this embodiment, m<(3n). An integer i between 1 and m is used to generally describe the rows of the scanning lines 12 and the rows in the matrix-arranged pixel circuits 110. For example, the scanning lines 12 may be referred to as rows 1, 2, 3, ..., (i-1), i, ..., (m-1), and m from top to bottom in the figure. Similarly, an integer j between 1 and n is used to generalize and describe the columns of data lines 14 and the columns of matrix-arranged pixel circuits 110. For example, to distinguish the data lines 14, they may be referred to as columns 1, 2, 3, ..., (3j-2), (3j-1), (3j), ..., (3n-2), (3n-1), and (3n) from left to right in the drawing. For convenience of explanation, the configuration of the pixel circuit 110 will be described with reference to FIG.

[0015] FIG. 3 is a diagram showing an equivalent circuit of four pixel circuits 110 (2×2) corresponding to the intersections of two adjacent scanning lines 12 and two adjacent data lines 14. As shown in the figure, the pixel circuit 110 includes a transistor 116 and a liquid crystal element 120. The transistor 116 is, for example, an N-channel thin film transistor. In the pixel circuit 110, the gate node of the transistor 116 is connected to the scan line 12, the source node is connected to the data line 14, and the drain node is connected to the pixel electrode 118.

[0016] In this description, "connection" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes, even if the elements are not directly connected to each other.

[0017] A common electrode 108 is provided on the opposing substrate in common to all pixels so as to face the pixel electrode 118. The common electrode 108 is maintained at a substantially constant potential LCcom over time. A liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108. Therefore, for each pixel circuit 110, a liquid crystal element 120 is formed by the pixel electrode 118, the common electrode 108, and the liquid crystal 105. Furthermore, a storage capacitor 109 is provided electrically in parallel with the liquid crystal element 120. One end of the storage capacitor 109 is connected to the pixel electrode 118, and the other end is connected to a capacitance line 107. The capacitance line 107 is maintained at a constant potential over time, for example, the same potential LCcom as the common electrode 108.

[0018] 2, in this embodiment, the (3n) data lines 14 are grouped into groups of 3. The j-th group counting from the left corresponds to the three data lines 14 in the (3j-2)th, (3j-2)th, and (3j)th columns. Furthermore, in the j-th group, the data lines 14 may be described as the first series in the (3j-2)th column, the second series in the (3j-1)th column, and the third series in the (3j)th column. In other words, in the j-th group, the first series of data lines 14 is the (3j-2)th column, the second series of data lines 14 is the (3j-1)th column, and the third series of data lines 14 is the (3j)th column.

[0019] The display control circuit 30 processes the video data and synchronization signals supplied from the higher-level circuit, and outputs control signals to the scanning line driving circuit 130 as well as data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) and selection signals Sel(1) to Sel(3). Data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) are supplied to the electro-optical device 100 via n data signal lines 13. The data signals Vid(1), Vid(2), Vid(3), ..., Vid(n) will be generally described below. Data signal Vid(j) is a signal whose potential corresponds to the grayscale levels of three pixels corresponding to the intersections of three data lines 14 belonging to the j-th group and horizontally scanned scanning lines 12. In detail, the potential of data signal Vid(j) changes in a time-division manner during the horizontal scanning period according to the grayscale levels of the three pixels.

[0020] The selection signal Sel(1) is a signal for selecting the first series of data lines 14. Similarly, the selection signal Sel(2) is a signal for selecting the second series of data lines 14, and the selection signal Sel(3) is a signal for selecting the third series of data lines 14. The logic levels of the selection signals Sel(1) to Sel(3) are each inverted by a NOT circuit Iv11 and output as an inverted selection signal. The selection signals Sel(1) to Sel(3) are individually supplied to selection signal lines extending in the X direction, and inverted signals of the selection signals Sel(1) to Sel(3) are individually supplied to inverted selection signal lines also extending in the X direction. Although omitted in FIG. 2, the inverted signals of the selection signals Sel(1) to Sel(3) are represented in order as / Sel(1) to / Sel(3).

[0021] The scanning line driving circuit 130 supplies scanning signals individually to m rows of scanning lines 12 under the control of the display control circuit 30. Here, the scanning signal supplied to the first scanning line 12 is denoted as Gwr(1), and similarly, the scanning signals supplied to the second, third, ..., (i-1), i, ..., (m-1), and m-th scanning lines 12 are denoted as Gwr(2), Gwr(3), ..., Gwr(i-1), Gwr(i), ..., Gwr(m-1), and Gwr(m), respectively.

[0022] The display control circuit 30 outputs various control signals for controlling the scanning line driving circuit 130, but since the control signals to the scanning line driving circuit 130 are not important in this case, only the signal paths are illustrated and detailed descriptions of the control signals are omitted.

[0023] The peripheral circuit 150 is a circuit (demultiplexer) that distributes data signals supplied to the data signal lines 13 to each data line 14 in accordance with selection signals Sel(1) to Sel(3) and inverted selection signals / Sel(1) to / Sel(3). In detail, the peripheral circuit 150 has a transistor N1 and a NOT circuit Iv1 for each column of data lines 14.

[0024] The transistor N1 is an N-channel thin film transistor similar to the transistor 116 in the pixel circuit 110. The transistor N1 and the NOT circuit Iv1 will be described with a focus on the j-th group.

[0025] The data signal line 13, to which the data signal Vid(j) corresponding to the jth group is supplied, branches into three, and each branch line intersects with three selection signal lines and three inverted selection signal lines and is connected to the source node, which is the input terminal of transistor N1. In the jth group, the input terminal of the first series transistor N1 is connected to the data signal line 13 to which the data signal Vid(j) corresponding to the jth group is supplied, and the output terminal is connected to the first series data line 14 in the jth group. In the j-th group, the NOT circuit Iv1 of the first series re-inverts the logic level of the inverted selection signal / Sel(1) and outputs it. The selection signal Sel(1) and the inverted signal of the inverted selection signal / Sel(1) are joined and supplied to the gate node of the j-th transistor N1 of the first series.

[0026] In the jth group, the input terminal of the second-series transistor N1 is connected to the data signal line 13 corresponding to the jth group, and the output terminal is connected to the jth second-series data line 14. In the jth group, the second-series NOT circuit Iv1 re-inverts the logic level of the inverted selection signal / Sel(2) and outputs it. The selection signal Sel(2) and the inverted signal of the inverted selection signal / Sel(2) are joined and supplied to the gate node of the jth second-series transistor N1. Similarly, in the jth group, the input terminal of the third series transistor N1 is connected to the data signal line 13 corresponding to the jth group, and the output terminal is connected to the jth third series data line 14. In the jth group, the third series NOT circuit Iv1 re-inverts the logic level of the inverted selection signal / Sel(3) and outputs it. The selection signal Sel(3) and the inverted signal of the inverted selection signal / Sel(3) are joined and supplied to the gate node of the jth third series transistor N1.

[0027] 2 is a diagram showing the electrical configuration of the electro-optical device 100, and in reality, the elements of the electro-optical device 100 are arranged as shown in FIG. If m<3n, the display area 10 has a rectangular shape with the X direction longer than the Y direction. As described above, one end of the FPC board 74 is connected to one longitudinal side of the electro-optical device 100. Between the one end of the FPC board 74 and the display area 10, the peripheral circuit 150 is provided.

[0028] A scanning line driving circuit 130 is provided on each of the two sides of the display area 10 along the Y direction. That is, two scanning line driving circuits 130 are provided, and scanning signals are supplied to the scanning lines 12 from both ends. The reason for this configuration is that the effect of delay in the scanning signal on the display can be reduced compared to when the scanning signal is supplied from only one end. The two scanning line driving circuits 130 are supplied with the same control signal from the display control circuit 30. Although the selection signals Sel(1) to Sel(3) are supplied from the left end in FIG. 2, they are supplied from both the left and right ends, as shown in FIG. 4, in the same way as the scanning signals, in order to suppress the effects of delay. The NOT circuit Iv11 is also provided at both the left and right ends. Therefore, the inverted selection signals / Sel(1) to / Sel(3) are also supplied from both the left and right ends.

[0029] FIG. 5 is a timing chart showing the operation of the electro-optical device 100. As shown in FIG. In the electro-optical device 100, m scanning lines 12 are scanned one by one during a frame (V) period in the order of 1st, 2nd, 3rd, ..., mth rows. In detail, as shown in the figure, the scanning signals Gwr(1), Gwr(2), ..., Gwr(i-1), Gwr(i), ..., Gwr(m-1), Gwr(m) are sequentially and exclusively set to H level by the scanning line driving circuit 130 for each horizontal scanning period (H). In this embodiment, the periods during which adjacent scanning signals Gwr(1) to Gwr(m) are at H level are separated in time. Specifically, after scanning signal Gwr(i-1) changes from H level to L level, the next scanning signal Gwr(i) becomes H level after a period. This period corresponds to the horizontal blanking period.

[0030] In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by video data supplied from a higher-level circuit. If the length of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Furthermore, the horizontal scanning period (H) is the time interval during which the scanning signals Gwr(1) to Gwr(m) sequentially go to H level, but for convenience in the figure, the start timing of the horizontal scanning period (H) is shown approximately in the center of the horizontal blanking period.

[0031] When one of the scanning signals Gwr(1) to Gwr(m), for example the scanning signal Gwr(i) for the ith row, goes high, the transistor 121 of the pixel circuit 110 located in the ith row is turned on. As a result, in the pixel circuit 110, one end of the liquid crystal element 120 and one end of the storage capacitor 109 are electrically connected to the corresponding data line 14. In the case of the pixel circuit 110 in the ith row and (3j-2)th column, one end of the liquid crystal element 120 and one end of the storage capacitor 109 in the pixel circuit 110 are electrically connected to the (3j-2)th column data line 14.

[0032] In this description, the "on state" of a transistor means that the source node and drain node of the transistor are electrically closed, resulting in a low impedance state, and the "off state" of a transistor means that the source node and drain node are electrically open, resulting in a high impedance state.

[0033] During the period in which the scanning signal Gwr(i) is at H level, the selection signals Sel(1), Sel(2), and Sel(3) successively and exclusively become H level. When the selection signal Sel(1) goes high, the inverted selection signal / Sel(1) goes low, and the output of the NOT circuit Iv1 in the first series goes high, turning on the transistor N1 in the first series. The display control circuit 30 outputs the potentials of the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order according to the gradation of the pixels in the i-th row and the 1st, 4th, ..., (3j-2), ..., (3n-2)th columns, and according to the write polarity.

[0034] Therefore, the data signal Vid(j) is applied to one end of the liquid crystal element 120 and one end of the storage capacitor 109 in the pixel circuit 110 in the i-th row and (3j-2)th column via the data line 14 in the (3j-2)th column. The potential of the data signal Vid(j) applied to one end of the liquid crystal element 120 is maintained by the capacitive nature of the liquid crystal element 120 and the storage capacitance 109 even when the transistor N1 in the (3j-2) column is turned off and the horizontal scanning period for the i-th row ends and the scanning signal Gwr(i) becomes L level.

[0035] As is well known, in the liquid crystal element 120, the orientation of the liquid crystal molecules changes in response to the electric field generated by the pixel electrode 118 and the common electrode 108. Therefore, the liquid crystal element 120 has a transmittance that corresponds to the effective value of the applied voltage. In this embodiment, the transmittance is minimum when the voltage applied to the liquid crystal element 120 is zero, and the transmittance increases as the applied voltage increases, in a normally black mode.

[0036] The data signal Vid(j) is a potential corresponding to the gradation of the pixel in the i-th row (3j-2) column, and is a potential corresponding to the write polarity. When driving the liquid crystal element 120, AC driving is required to prevent deterioration of the liquid crystal 105. For this reason, a positive potential on the higher side and a negative potential on the lower side relative to the amplitude center potential Vcen are alternately applied to the pixel electrode 118, for example, every one frame (V). The potential Vcen can be considered to be approximately the same potential as the potential LCcom applied to the common electrode 108.

[0037] The range that the positive polarity potential can take is indicated by Rng(+). The range Rng(+) is, for example, from the potential Vwt(+) when the gradation is at its highest value to the potential Vbk(+) when the gradation is at its lowest value. The range that the negative polarity potential can take is indicated by Rng(-). The range Rng(-) is, for example, from the potential Vwt(-) when the gradation is at its highest value to the potential Vbk(-) when the gradation is at its lowest value. Here, the (3j-2)th column of the horizontal scanning of the ith row has been described, but the same operation is similarly performed in the first series of 1st, 4th, 7th, . . . , (3n-2)th columns. The selection signal Sel(1) goes to L level, and then the selection signal Sel(2) goes to H level.

[0038] When the selection signal Sel(2) goes high, the second-series transistor N1 is turned on. The display control circuit 30 outputs the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order at potentials corresponding to the grayscales and write polarities of the pixels in the i-th row and the 2nd, 5th, ..., (3j-1), ..., (3n-1)th columns. As a result, the liquid crystal element 120 of the pixel circuit 110 corresponding to the intersection of the i-th row scanning line and the second-series data line 14 exhibits a transmittance corresponding to the grayscale. The selection signal Sel(2) goes to L level, and then the selection signal Sel(3) goes to H level.

[0039] When the selection signal Sel(3) goes high, the third-series transistor N1 is turned on. The display control circuit 30 outputs the data signals Vid(1), Vid(2), ..., Vid(j), ..., Vid(n) in order at potentials corresponding to the grayscales of the pixels in the i-th row and the 3rd, 6th, ..., (3j), ..., (3n) columns, and at potentials corresponding to the write polarity. As a result, the liquid crystal element 120 of the pixel circuit 110 corresponding to the intersection of the i-th row scanning line and the third-series data line 14 exhibits a transmittance corresponding to the grayscale. After this, the selection signal Sel(3) goes low, and horizontal scanning of the i-th row ends.

[0040] Here, horizontal scanning of the i-th row has been described, but similar operations are performed sequentially for horizontal scanning of the 1st, 2nd, 3rd, . . . , mth rows. When horizontal scanning of the mth row is completed, the next frame period begins, and horizontal scanning resumes from row 1. During the next frame period, the display control circuit 30 inverts the potential polarity of the data signal.

[0041] Before describing the advantages of the electro-optical device 100 according to this embodiment, an electro-optical device according to a comparative example will be described.

[0042] 6 is a diagram showing the configuration of the j-th group of peripheral circuits 150 in an electro-optical device according to a comparative example. As shown in this diagram, in the comparative example, inverted selection signals / Sel(1) to / Sel(3) are not supplied, and a NOT circuit Iv1 is not provided for each data line 14. For this reason, in the j-th group, the data signal line 13 to which the data signal Vd(j) is supplied intersects with three selection signal lines 180 to which the selection signals Sel(1) to Sel(3) are respectively supplied. The data signal line 13 and the selection signal line 180 are electrically insulated from each other via an insulating layer, but a parasitic capacitance occurs between them using the insulating layer as a dielectric.

[0043] In detail, among the branched data signal lines 13, the data signal line 13_1 corresponding to the first series has a parasitic capacitance Sc1a between it and the selection signal line 180 to which the selection signal Sel(1) is supplied, as indicated by a dashed circle. Similarly, the data signal line 13_1 has a parasitic capacitance Sc2a between it and the selection signal line 180 to which the selection signal Sel(2) is supplied, and a parasitic capacitance Sc3a between it and the selection signal line 180 to which the selection signal Sel(3) is supplied. Of the branched data signal lines 13, the data signal line 13.2 corresponding to the second series and the data signal line 13_3 corresponding to the third series also have parasitic capacitance due to intersections with the three selection signal lines 180, similar to the data signal line 13_1 corresponding to the first series.

[0044] FIG. 7 is a diagram for explaining noise superimposed on a data signal line in the comparative example. The selection signals Sel(1), Sel(2), and Sel(3) become H level exclusively in this order during the horizontal scanning period (H). When the logic level of the selection signal Sel(1) changes, noise Ns1a corresponding to the change in logic level is superimposed on the data signal Vid(j) supplied to the data signal line 13_1 via the capacitance Sc1a. The same applies to the selection signals Sel(2) and Sel(3). In detail, when the logic level of the selection signal Sel(2) changes, noise Ns2a corresponding to the change in logic level is superimposed on the data signal Vid(j) supplied to the data signal line 13_1 via the capacitance Sc2a, and when the logic level of the selection signal Sel(3) changes, noise Ns3a corresponding to the change in logic level is superimposed on the data signal Vid(j) supplied to the data signal line 13_1 via the capacitance Sc3a.

[0045] When noise is superimposed on the data signal line 13_1, the data signal Vid(j), which should have a potential corresponding to the gradation level, deviates from the potential corresponding to the gradation level. When a potential that deviates from the potential corresponding to the gradation level is applied to the pixel electrode 118 via the data line 14, it causes a decrease in display quality, such as display unevenness. Note that, although the first series has been described here, noise is also superimposed in the second and third series in the same way.

[0046] FIG. 8 is a diagram showing the configuration of the j-th group of the peripheral circuits 150 in the electro-optical device 100 according to the first embodiment. As described above, in the embodiment, not only are the selection signals Sel(1) to Sel(3) supplied individually via the selection signal line 180, but the inverted selection signals / Sel(1) to / Sel(3) are also supplied individually via the inverted selection signal line 181. In the j-th group, among the branched data signal lines 13, for example, the first series data signal line 13_1 intersects with three selection signal lines 180 to which the selection signals Sel(1) to Sel(3) are respectively supplied and three selection signal lines 180 to which the inverted selection signals / Sel(1) to / Sel(3) are respectively supplied.

[0047] The inverted selection signals / Sel(1) to / Sel(3) are signals obtained by inverting the logic levels of the selection signals Sel(1) to Sel(3), respectively. Therefore, the change in the logic level of the selection signal Sel(1) and the change in the logic level of the inverted selection signal / Sel(1) are in opposite directions to each other, but the magnitudes of the changes are approximately the same. Similarly, the change in the logic level of the selection signal Sel(2) and the logic level of the inverted selection signal / Sel(2), and the change in the logic level of the selection signal Sel(3) and the logic level of the inverted selection signal / Sel(3) are in opposite directions to each other, but the magnitudes of the changes are approximately the same.

[0048] The data signal line 13_1 corresponding to the first series is parasitic with capacitances Sc1b, Sc2b, and Sc3b in addition to capacitances Sc1a, Sc2a, and Sc3a. In detail, the data signal line 13_1 is parasitic with capacitance Sc1b between it and the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied, with capacitance Sc2b between it and the inverted selection signal line 181 to which the inverted selection signal / Sel(2), and with capacitance Sc3b between it and the inverted selection signal line 181 to which the inverted selection signal / Sel(3) is supplied.

[0049] FIG. 9 is a diagram for explaining cancellation of noise superimposed on a data signal line in the first embodiment. When the logic level of the selection signal Sel(1) changes, noise Ns1a corresponding to the change in logic level is superimposed on the data signal line 13_1 via the capacitance Sc1a. However, at the same time, noise Ns1b of approximately the same magnitude and in the opposite direction to the noise Ns1a, specifically noise Ns1b corresponding to the change in logic level of the inverted selection signal / Sel(1), is superimposed on the data signal line 13_1 via the capacitance Scb1.

[0050] Therefore, noise Ns1a superimposed on the data signal line 13_1 as the logic level of the selection signal Sel(1) changes is cancelled out by noise Ns1b superimposed as the logic level of the inverted selection signal / Sel(1) changes. Similarly, noise Ns2a superimposed on the data signal line 13_1 as the logic level of the selection signal Sel(2) changes is cancelled out by noise Ns2b superimposed on the data signal line 13_1 as the logic level of the inverted selection signal / Sel(2) changes. Noise Ns3a superimposed on the data signal line 13_1 as the logic level of the selection signal Sel(3) changes is cancelled out by noise Ns3b superimposed on the data signal line 13_1 as the logic level of the inverted selection signal / Sel(3) changes. Although the first sequence has been described above, noise is similarly cancelled out in the second and third sequences.

[0051] In this way, in the first embodiment, noises Ns1a to Ns3a that occur in association with changes in the logic levels of the selection signals Sel(1) to Sel(3) are cancelled out by noises Ns1b to Ns3b that occur in association with changes in the logic levels of the inverted selection signals / Sel(1) to / Sel(3). Therefore, in the first embodiment, noise fluctuations in the data signal Vid(j) are suppressed, making it possible to avoid degradation of display quality such as display unevenness.

[0052] In the first embodiment, the switching element that distributes the data signal supplied to the data signal line 13 to each data line 14 is configured as an N-channel transistor N1, but it may also be configured as a P-channel transistor. However, one channel type transistor has a problem in that its resistance in the on state is relatively high. Therefore, as resolution increases and the period during which the transistor is in the on state becomes shorter, there is a possibility that the data signal supplied to the data signal line 13 will not be able to be written (propagated) sufficiently to each data line 14. Therefore, a second embodiment will be described, which reduces such a possibility. Note that the electro-optical device 100 according to the second embodiment differs from the first embodiment only in the demultiplexer and its periphery, and is otherwise the same as the first embodiment. Therefore, the differences from the second embodiment will be mainly described.

[0053] FIG. 10 is a diagram showing the configuration of the j-th group of the peripheral circuits 150 in the electro-optical device 100 according to the second embodiment. In the second embodiment, each data line 14 has a transmission gate Trs and a NOT circuit Iv2. The transmission gate Trs is an analog switch in which a P-channel transistor P1 and an N-channel transistor N1 are connected in parallel. The transistors P1 and N1 are both thin-film transistors similar to the transistor 116 in the pixel circuit 110.

[0054] In the j-th group, the input terminal of the first series transmission gate Trs is connected to the data signal line 13_1 branched in the j-th group corresponding to the first series, and the output terminal is connected to the first series data line 14 in the j-th group. In the j-th group, transistors P1 and N1 constituting the first-series transmission gate Trs will be described. A selection signal Sel(1) is supplied to the gate node of the transistor N1. A signal obtained by inverting the logic level of the selection signal Sel(1) by a NOT circuit Iv2 is supplied to the gate node of the transistor P1. In the second embodiment, three inverted selection signal lines 181 are provided extending in the same X direction as the selection signal line 180. The signal inverted by the first NOT circuit Iv2 is connected to one of the three inverted selection signal lines 181 via a signal line extending along the Y direction.

[0055] In the j-th group, the transmission gate Trs and the NOT circuit Iv2 of the second series are the same as those of the first series. That is, in the j-th group, the input terminal of the second-system transmission gate Trs is connected to the data signal line 13_2 branched off corresponding to the second system in the j-th group, and the output terminal is connected to the second-system data line 14 in the j-th group. In the j-th group, the selection signal Sel(2) is supplied to the gate node of the transistor N1 constituting the second-system transmission gate Trs, and a signal obtained by inverting the logic level of the selection signal Sel(2) by the NOT circuit Iv2 is supplied to the gate node of the transistor P. The signal inverted by the second-system NOT circuit Iv2 is connected to another one of the three inverted selection signal lines 181 via a signal line extending along the Y direction.

[0056] In the j-th group, the transmission gate Trs and the NOT circuit Iv2 of the third system are similar to those of the first and second systems. That is, in the j-th group, the input terminal of the third-system transmission gate Trs is connected to the data signal line 13_3 branched off corresponding to the third system in the j-th group, and the output terminal is connected to the third-system data line 14 in the j-th group. In the j-th group, the selection signal Sel(3) is supplied to the gate node of the transistor N1 constituting the third-system transmission gate Trs, and a signal obtained by inverting the logic level of the selection signal Sel(3) by the NOT circuit Iv2 is supplied to the gate node of the transistor P1. The signal inverted by the third-system NOT circuit Iv2 is connected to the remaining one of the three inverted selection signal lines 181 via a signal line extending along the Y direction.

[0057] The three inverted selection signal lines 181 are individually supplied with the inverted selection signals / Sel(1) to / Sel(3) in the first embodiment. Therefore, each of the data signal lines 13_1 to 13_3 intersects with three selection signal lines 180 to which selection signals Sel(1) to Sel(3) are supplied and three inverted selection signal lines 181 to which inverted selection signals / Sel(1) to / Sel(3) are supplied.

[0058] Also in the second embodiment, noises Ns1a to Ns3a generated in accordance with changes in the logic levels of the selection signals Sel(1) to Sel(3) are cancelled out by noises Ns1b to Ns3b generated in accordance with changes in the logic levels of the inverted selection signals / Sel(1) to / Sel(3). Therefore, also in the second embodiment, noise fluctuations in the data signal Vid(j) supplied via any of the data signal lines 13_1 to 13_3 are suppressed, thereby making it possible to avoid degradation of display quality such as display unevenness.

[0059] In the second embodiment, the ON state of the transmission gate Trs means that the transistors N1 and P1 are simultaneously turned ON in parallel, and the resistance value is approximately half of that when only one of the channel type transistors is turned ON. When the potential of the data signal is high in positive write, the P-channel transistor compensates for the insufficient write of the N-channel transistor. Conversely, when the potential of the data signal is low in negative write, the N-channel transistor compensates for the insufficient write of the P-channel transistor. Therefore, according to the second embodiment, even if resolution continues to increase, the data signals supplied to the data signal lines 13 can be sufficiently written to each data line 14, and display unevenness caused by differences in write polarity can be suppressed.

[0060] In the first embodiment, three NOT circuits Iv11 that sequentially invert the selection signals Sel(1) to Sel(3) are provided, one for each side when driving from one side, or two for each side when driving from both sides. The NOT circuits Iv11 are shared by the data lines 14 of each column, so although there are only a few of them, each is required to have high driving capability. In contrast to this, in the second embodiment, a NOT circuit Iv2 is provided for each data line 14, and therefore the NOT circuit Iv2 is not required to have high driving capability.

[0061] If the capacitances Sc1a and Sc1b parasitic on the data signal lines 13 (13_1 to 13_3) are not approximately the same, noise cancellation cannot be expected. Similarly, if the capacitances Sc2a and Sc2b and the capacitances Sc3a and Sc3b are not approximately the same, noise cancellation cannot be expected. Therefore, a third embodiment will be described, which makes it easy to equalize such parasitic capacitances. Note that the electro-optical device 100 according to the third embodiment differs from the first embodiment only in the demultiplexer and its periphery, and is otherwise the same as the first embodiment. Therefore, the differences from the third embodiment will be mainly described.

[0062] FIG. 11 is a diagram showing the configuration of the j-th group of the peripheral circuits 150 in the electro-optical device 100 according to the third embodiment. In the third embodiment, a transmission gate Trs similar to that in the second embodiment is provided for each data line 14. In other words, the transistor N1 and the NOT circuit Iv1 provided for each data line 14 in the first embodiment are replaced with a transmission gate Trs in the third embodiment.

[0063] Therefore, also in the second embodiment, noises Ns1a to Ns3a superimposed on the data signal lines 13_1 to 13_3 in accordance with changes in the logic levels of the selection signals Sel(1) to Sel(3) are cancelled out by noises Ns1b to Ns1b generated in accordance with changes in the logic levels of the inverted selection signals / Sel(1) to / Sel(3). Therefore, also in the third embodiment, noise fluctuations in the data signal Vid(j) supplied via any of the data signal lines 13_1 to 13_3 are suppressed, making it possible to avoid degradation of display quality such as display unevenness.

[0064] FIG. 12 is a cross-sectional view showing a main part of the electro-optical device 100 according to the third embodiment, specifically, a part of the transistor N1, cut in the X direction. As shown in this figure, in the electro-optical device 100, a semiconductor layer Sm_N, a gate electrode Pol_N, a first insulating layer Is1, a first wiring layer Mt1, a second insulating layer Is2, a second wiring layer Mt2, a third insulating layer Is3 and a third wiring layer Mt3 are provided in this order on an insulating substrate Su such as quartz.

[0065] In reality, an insulating layer or the like is provided to cover the third wiring layer Mt3, but these elements are omitted. The source node of transistor N1 is connected to wiring Mw19 patterned from the first wiring layer Mt1 via a contact hole Ct11 opening in the first insulating layer Is1, and the wiring Mw19 is connected to a data signal line 13_1 patterned from the second wiring layer Mt2 via a contact hole Ct21 opening in the second insulating layer Is2.

[0066] On the side of the transistor N1, a wiring Mw11 formed by patterning the first wiring layer Mt1 is provided below the data signal line 13_1, and a wiring Mw31 formed by patterning the third wiring layer Mt3 is provided above the data signal line 13_1. Therefore, the data signal line 13_1 is sandwiched between the wirings Mw11 and Mw31 in a cross-sectional view. The data signal line 13_1 is provided with a protrusion Mw21_N that protrudes from the wirings Mw11 and Mw31 in plan view in order to connect to the source node of the transistor N1. Although the transistor N1 has been described here, the transistor P1 has almost the same configuration and is therefore not shown.

[0067] 13 is a plan view showing the wiring of the demultiplexer and transmission gate Trs in the jth group in the electro-optical device 100 according to the third embodiment. Note that in FIG. 13, the wiring is shifted to make the layer structure easier to understand, but in reality, the wiring overlaps in plan view.

[0068] In the figure, Sm_P is the semiconductor layer of the transistor P1 that constitutes the transmission gate Trs, and Sm_N is the semiconductor layer of the transistor N1 that constitutes the transmission gate Trs as described above.

[0069] The selection signal lines 180 to which the selection signals Sel(1) to Sel(3) are supplied are wirings patterned on the first wiring layer Mt1. The data signal lines 13_1 to 13_3 are wirings patterned on the second wiring layer Mt2. The inverted selection signal lines 181 to which the inverted selection signals / Sel(1) to / Sel(3) are supplied are wirings patterned on the third wiring layer Mt3.

[0070] In the first group, the data signal line 13_1 extends to the transmission gate Trs in the opposite Y direction, sandwiched between the line Mw11 in the lower layer and the line M31 in the upper layer. The line Mw11 is a line branched from the selection signal line 180 to which the selection signal Sel(1) is supplied, and the line Mw31 is a line branched from the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied.

[0071] The wiring Mw11 has a protrusion Mw15 in the X direction in the figure, and the protrusion Mw15 is connected to the gate electrode Pol_N of the transistor N1 that constitutes the transmission gate Trs via a contact hole not shown. The wiring Mw31 has a protrusion Mw35 in the X direction in the figure, and the protrusion Mw35 is connected to the gate electrode Pol_P of the transistor P1 that constitutes the transmission gate Trs via a contact hole not shown.

[0072] The data signal line 13_1 sandwiched between the wirings Mw11 and Mw31 has protrusions Mw21_N and Mw21_P in the X direction in the figure. The protrusion Mw21_N is connected to the wiring Mw19 in Figure 12 via a contact hole Ct21. Therefore, the data signal line 13_1 is connected to the source node of the transistor N1 via the wiring Mw19. Although not specifically shown, the protrusion Mw21_P is connected to the source node of the transistor P1 via an electrode in the same manner as the protrusion Mw21_N. The data line 14 is commonly connected to the drain node of the transistor Pt1 and the drain node of the transistor Nt1.

[0073] In the second series, the wiring Mw14 is a wiring that branches off in the opposite Y direction from the selection signal line 180 to which the selection signal Sel(2) is supplied, passes through the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied, and bends in the opposite X direction just before the selection signal line 180 to which the selection signal Sel(1) is supplied. The wiring Mw14 and the selection signal line 180 are patterned from the same first wiring layer Mt1, and therefore cannot intersect in a planar view. Therefore, the wiring Mw14 is connected to the wiring Mw12 via the relay wiring Mw27, straddling the selection signal line 180 to which the selection signal Sel(1) is supplied. Note that the relay wiring Mw27 is patterned from a wiring layer other than the first wiring layer Mt1, for example, the second wiring layer Mt2, and is connected to the wiring Mw14 via a contact hole (not shown) and to the wiring Mw12 via a contact hole (also not shown). That is, the selection signal line 180 to which the selection signal Sel(2) is supplied is connected to the wiring Mw12 via the wiring Mw14 and the relay wiring Mw27 in this order. The wiring Mw12 is a wiring that overlaps the data signal line 13_2 in a lower layer and extends in the opposite Y direction to the transmission gate Trs.

[0074] The wiring Mw34 is a wiring that branches off in the opposite Y direction from the inverted selection signal line 181 to which the inverted selection signal / Sel(2) is supplied, crosses the selection signal line 180 to which the selection signal Sel(2) is supplied, and bends in the X direction just before the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied. The wiring Mw34 and the inverted selection signal line 181 are patterned from the same third wiring layer Mt3, and therefore cannot intersect in a planar view. Therefore, the wiring Mw34 passes through the inverted selection signal line 181, to which the inverted selection signal / Sel(1) is supplied, via the relay wiring Mw28 and is connected to the wiring Mw32. The relay wiring Mw28 is patterned from a wiring layer other than the third wiring layer Mt3, for example, the second wiring layer Mt2, and is connected to the wiring Mw34 via a contact hole (not shown) and to the wiring Mw32 via a contact hole (also not shown). That is, the inverted selection signal line 181 to which the inverted selection signal / Sel(2) is supplied is connected to the wiring Mw32 via the wiring Mw34 and the relay wiring Mw28 in this order. The wiring Mw32 is a wiring that overlaps the data signal line 13_2 in an upper layer and extends in the opposite Y direction to the transmission gate Trs.

[0075] Therefore, in the second series, the data signal line 13_2 extends to the transmission gate Trs in the opposite direction to the Y direction while being sandwiched between the wiring Mw12 in the lower layer and the wiring M32 in the upper layer.

[0076] The third series has a similar wiring configuration. That is, the selection signal line 180 to which the selection signal Sel(3) is supplied is connected to the wiring Mw13 via the wiring Mw14, the relay wiring Mw27, the wiring Mw19, and the relay wiring Mw27 in this order. The wiring Mw19 is formed by patterning the first wiring layer Mt1. The wiring Mw13 is a wiring that overlaps the data signal line 13_3 in a lower layer and extends in the opposite Y direction to the transmission gate Trs. Furthermore, the inverted selection signal line 181, to which the inverted selection signal / Sel(3) is supplied, is connected to the wiring Mw33 via the wiring Mw34, the relay wiring Mw28, the wiring Mw39, and the relay wiring Mw28 in this order. The wiring Mw39 is formed by patterning the third wiring layer Mt3. The wiring Mw33 is a wiring that overlaps the data signal line 13_3 in an upper layer and extends in the opposite Y direction to the transmission gate Trs.

[0077] In the third embodiment, the first series data signal line 13_1 is sandwiched, in a cross-sectional view, between a wiring Mw11 to which the selection signal Sel(1) is supplied and a wiring Mw31 to which the inverted selection signal / Sel(1) is supplied, from the point where it intersects with the selection signal line 180 to which the selection signal Sel(1) is supplied to the transmission gate Trs. Therefore, in the third embodiment, the capacitance Sc1a parasitic on the data signal line 13_1 and the selection signal line 180 to which the selection signal Sel(1) is supplied is larger than in a configuration in which a capacitance is simply created at the intersection of both signal lines. Similarly, the capacitance Sc1b parasitic on the data signal line 13_1 and the inverted selection signal line 181 to which the inverted selection signal / Sel(1) is supplied is larger than in a configuration in which a capacitance is simply created at the intersection of both signal lines.

[0078] Similarly, the second-system data signal line 13_2 is sandwiched between the wiring Mw12 supplied with the selection signal Sel(2) and the wiring Mw32 supplied with the inverted selection signal / Sel(2) in a cross-sectional view from the point where it intersects with the selection signal line 180 supplied with the selection signal Sel(2) to the transmission gate Trs. For this reason, the capacitance Sc2a parasitic on the data signal line 13_2 and the selection signal line 180 supplied with the selection signal Sel(2) and the capacitance Sc2b parasitic on the data signal line 13_2 and the inverted selection signal line 181 supplied with the inverted selection signal / Sel(2) are also larger than in a configuration in which capacitance is created simply at the intersection of both signal lines.

[0079] Similarly, the third-system data signal line 13_3 is sandwiched between the wiring Mw13 supplied with the selection signal Sel(3) and the wiring Mw33 supplied with the inverted selection signal / Sel(3) in a cross-sectional view from the point where it intersects with the selection signal line 180 supplied with the selection signal Sel(3) to the transmission gate Trs. For this reason, the capacitance Sc3a parasitic on the data signal line 13_3 and the selection signal line 180 supplied with the selection signal Sel(3) and the capacitance Sc3b parasitic on the data signal line 13_3 and the inverted selection signal line 181 supplied with the inverted selection signal / Sel(3) are also larger than in a configuration in which capacitance is created simply at the intersection of both signal lines.

[0080] The second and third transmission gates Trs have the same configuration as the first transmission gate Trs.

[0081] It is desirable that the capacitance values ​​of the capacitors Sc1a and Sc1b are approximately the same, the capacitance values ​​of the capacitors Sc2a and Sc2b are also approximately the same, and the capacitance values ​​of the capacitors Sc3a and Sc3b are also approximately the same. Here, if the capacitance value is small, even a slight difference in capacitance value will result in a significant difference. For example, if the capacitance value ratio is "1.0" and "1.2", even if the difference is "0.2", the difference will be 20%. In contrast, in the third embodiment, since the capacitance values ​​of the capacitors Sc1a and Sc1b are both large, a small difference is unlikely to become a significant difference. For example, if the ratio of the capacitance values ​​is "10.0" and "10.2," even if the difference is the same "0.2," the difference is only 2%. As described above, in the third embodiment, the capacitance values ​​of the capacitors Sc1a and Sc1b, the capacitance values ​​of the capacitors Sc2a and Sc2b, and the capacitance values ​​of the capacitors Sc3a and Sc3b are all large, so even if there is a difference in the capacitance values, the effect of the difference can be reduced.

[0082] In the third embodiment, the wiring Mw16 branches off in the Y direction from the selection signal line 180 and extends to the adjacent inverted selection signal line 181. With the wiring Mw16, for example, in the case of the data signal line 13_1, the length of the lower layer to which the selection signal Sel(1) of the lower layer is supplied is approximately equal to the length of the upper layer to which the inverted selection signal / Sel(1) of the upper layer is supplied, and therefore the capacitance values ​​of the capacitors Sc1a and Sc1b can be more uniform than in a configuration without the wiring Mw16. The same applies to the second-system wiring Mw16 and the third-system wiring Mw16.

[0083] In the third embodiment, three NOT circuits Iv11 are configured to generate inverted selection signals in common across the first to nth groups, but it is also possible to configure the NOT circuits Iv2 provided for each data line 14 to generate inverted selection signals individually, as in the second embodiment shown in Figure 10.

[0084] Furthermore, the X direction is an example of a “first direction,” the Y direction is an example of a “second direction,” the capacitance Sc1a is an example of a “first coupling capacitance,” and the capacitance Sc1b is an example of a “second coupling capacitance.” The NOT circuit Iv2 is an example of a “NOT circuit,” the wiring Mw11 is an example of a “first wiring,” and the wiring Mw31 is an example of a “second wiring.”

[0085] In the embodiment, the number k of data lines 14 constituting one group is described as "3", but it may be "2" or an integer equal to or greater than "4".

[0086] In the embodiment, the data signal lines 13_1 to 13_3 after branching from the data signal line 13 intersect with the selection signal line 180 and the inverted selection signal line 181. However, the present invention is not limited to this, and the data signal line 13 may be branched after crossing with the selection signal line 180 and the inverted selection signal line 181.

[0087] Next, a projection display device will be described as an example of an electronic device to which the electro-optical device 100 according to the embodiment is applied.

[0088] 14 is a diagram showing the optical configuration of a projection display device 200. As shown in the figure, the projection display device 200 includes electro-optical devices 100R, 100G, and 100B.

[0089] A lamp unit 2102 consisting of a white light source such as a halogen lamp or an LED is provided inside the projection display device 200. Light emitted from the lamp unit 2102 is separated into three primary colors, red (R), green (G), and blue (B), by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. Of these, the R light enters the electro-optical device 100R, the G light enters the electro-optical device 100G, and the B light enters the electro-optical device 100B. Since the optical path of B is longer than the optical paths of R and G, it is necessary to prevent loss in the optical path of B. For this reason, a relay lens system 2121 consisting of an input lens 2122, a relay lens 2123, and an output lens 2124 is provided in the optical path of B.

[0090] The electro-optical devices 100R, 100G, and 100B are common to the electro-optical device 100 according to the embodiment, but because the colors of the incident light are different, they are distinguished by symbols for convenience. The liquid crystal elements of the electro-optical device 100R are driven based on a data signal corresponding to R supplied from a higher-level circuit, and have a transmittance that corresponds to the voltage of the data signal. Therefore, in the electro-optical device 100R, an R transmission image is generated by individually controlling the transmittance of the liquid crystal elements. Similarly, in the electro-optical device 100G, a G transmission image is generated based on a data signal corresponding to G, and in the electro-optical device 100B, a B transmission image is generated based on a data signal corresponding to B.

[0091] The transmitted images of each color generated by the electro-optical devices 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light are refracted at 90 degrees, while the G light travels straight. Therefore, the dichroic prism 2112 combines the images of each color. The combined image formed by the dichroic prism 2112 is incident on the projection lens 2114. The projection lens 2114 enlarges and projects the combined image onto the screen Scr.

[0092] The transmission images of the electro-optical devices 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmission image of the electro-optical device 100G is projected in a straight line. Therefore, the transmission images of the electro-optical devices 100R and 100B are left-right inverted relative to the transmission image of the electro-optical device 100G.

[0093] Furthermore, although a projection display device 200 has been used as an example of an electronic device here, the present invention is not limited to this and can also be applied to, for example, the display panel of a head-mounted display, an electronic viewfinder in a video camera or a digital camera with interchangeable lenses, a personal digital assistant, a display part of a wristwatch, and the like.

[0094] From the above-described exemplary embodiments, the following aspects can be understood, for example.

[0095] In order to solve the above problem, an electro-optical device according to one aspect of the present disclosure includes a plurality of data lines including k (k is an integer of 2 or more) data lines that are grouped together, data signal lines that output data signals corresponding to the k data lines according to gradations of pixels, k selection signal lines to which selection signals are respectively supplied, k inverted selection signal lines that form pairs with the k selection signal lines and to which inverted signals of the selection signals are respectively supplied, and switching elements provided in one-to-one correspondence with the plurality of data lines, wherein the k selection signal lines and the k inverted selection signal lines are provided along a first direction, the data signal lines and the data signal lines are arranged along a second direction intersecting the first direction, the switching element has an input terminal connected to the data signal line and an output terminal connected to one of the k data lines, the conduction state between the input terminal and the output terminal is determined based on the selection signal and the inverted selection signal line, and a first coupling capacitance between the data signal line and one of the k selection signal lines and a second coupling capacitance between the data signal line and one of the k inverted selection signal lines that forms a pair with the one selection signal line have approximately the same relationship.

[0096] According to the electro-optical device of aspect 1, the noise superimposed on the data signal line due to the potential fluctuation of the selection signal line is offset by the noise due to the potential fluctuation of the inverted selection signal line, thereby avoiding adverse effects on display quality. In this description, the term "the first coupling capacitance and the second coupling capacitance are in approximately the same relationship" refers to a relationship in which the noise superimposed on the data signal line when the potential of the selection signal supplied to one selection signal line changes is canceled out by the noise superimposed on the data signal line when the potential of the inverted selection signal supplied to one inverted selection signal line changes. The phrase "one noise is cancelled out by another noise" means that a noise of the opposite direction occurs in the opposite direction to the one noise, thereby canceling out the one noise.

[0097] Specifically, the first coupling capacitance is generated when the data signal line and the selection signal line overlap with each other in a planar view via an insulating layer, and the second coupling capacitance is generated when the data signal line and the inverted selection signal line overlap with each other in a planar view via an insulating layer. In this configuration, the capacitance value of the first coupling capacitance is determined by the area where the data signal line and the selection signal line overlap with each other in a planar view via the insulating layer, the thickness of the insulating layer, and the dielectric constant of the insulating layer. Similarly, the capacitance value of the second coupling capacitance is determined by the area where the data signal line and the inverted selection signal line overlap with each other in a planar view via the insulating layer, the thickness of the insulating layer, and the dielectric constant of the insulating layer. Therefore, for example, the capacitance values ​​of the first coupling capacitor and the second coupling capacitor will be substantially the same if the overlapping area, the thickness of the insulating layer, and the dielectric constant of the insulating layer are the same. Furthermore, even if the area defining the first coupling capacitor is larger than the area defining the second coupling capacitor, the capacitance values ​​of the first coupling capacitor and the second coupling capacitor will be substantially the same if the thickness of the insulating layer defining the first coupling capacitor is larger than the thickness of the insulating layer defining the second coupling capacitor. In other words, the overlapping area, the thickness of the insulating layer, and the dielectric constant of the insulating layer may be different between the first coupling capacitor and the second coupling capacitor. It is assumed that the first coupling capacitance occurs when the data signal line and the selection signal line are arranged in parallel with a distance in a planar view, and that the second coupling capacitance occurs when the data signal line and the inverted selection signal line are arranged in parallel with a distance in a planar view.

[0098] In an electro-optical device according to a specific aspect 2 of aspect 1, in a planar view, the data signal line and the one selection signal line intersect with each other via a first insulating layer, and the data signal line and the one inverted selection signal line intersect with each other via a second insulating layer.

[0099] In the electro-optical device according to a third specific aspect of the first aspect, the switching element is a P-channel transistor or an N-channel transistor.

[0100] In an electro-optical device according to a fourth specific aspect of the first aspect, the switching element is a transmission gate that combines a P-channel transistor and an N-channel transistor.

[0101] In an electro-optical device according to a specific aspect 5 of aspect 1, there is provided a NOT circuit provided in one-to-one correspondence with the plurality of data lines, and the NOT circuit inverts the logical level of a selection signal supplied to one of the k selection signal lines and supplies the inverted selection signal line that is paired with the one selection signal line.

[0102] In an electro-optical device according to a specific embodiment 6 of embodiment 1, a first insulating layer, a first wiring layer, a second insulating layer, a second wiring layer, a third insulating layer, and a third wiring layer are stacked in this order, and the one selection signal line is made of the same material as the first wiring layer, the data signal line is made of the same material as the second wiring layer, and the one inverted selection signal line is made of the same material as the third wiring layer.

[0103] In an electro-optical device according to a specific aspect 7 of aspect 6, a first wiring branching off from one of the selection signal lines and extending along the second direction to the switching element, the data signal line, and a second wiring branching off from one of the inverted selection signal lines and extending along the second direction to the switching element overlap in a planar view.

[0104] An electronic device according to an eighth aspect includes the electro-optical device according to any one of the first to seventh aspects. [Explanation of symbols]

[0105] 1...projection display device, 30...display control circuit, 100...electro-optical device, 110...pixel circuit, 118...pixel electrode, 120...liquid crystal element, 180...selection signal line, 181...inverted selection signal line, N1, P1...transistor, Trs...transmission gate, Iv1, Iv2, Iv11...NOT circuit, Sc1a, Sc1b...capacitor, Mw11, Mw31...wiring.

Claims

1. a plurality of data lines including grouped k (k is an integer of 2 or more) data lines; data signal lines for outputting data signals corresponding to the k data lines in accordance with the gradation of the pixel; k selection signal lines each supplied with a selection signal; k inverted selection signal lines that are paired with the k selection signal lines and that are supplied with inverted signals of the selection signals; switching elements provided in one-to-one correspondence with the plurality of data lines; Including, the k selection signal lines and the k inverted selection signal lines are provided along a first direction; the plurality of data lines and the data signal lines are provided along a second direction intersecting the first direction, The switching element is an input terminal connected to the data signal line, and an output terminal connected to any one of the k data lines; a conduction state between the input terminal and the output terminal is defined based on the selection signal and the inverted selection signal line; a first coupling capacitance between the data signal line and one of the k selection signal lines; a second coupling capacitance between the data signal line and one of the k inverted selection signal lines that forms a pair with the one selection signal line; are in almost the same relationship Electro-optical device.

2. In plan view, the data signal line and the one selection signal line intersect with each other via a first insulating layer; the data signal line and the one inverted select signal line intersect with each other via a second insulating layer; The electro-optical device according to claim 1 .

3. The switching element is It is a P-channel transistor or an N-channel transistor. The electro-optical device according to claim 1 .

4. The switching element is It is a transmission gate that combines P-channel transistors and N-channel transistors. The electro-optical device according to claim 1 .

5. a NOT circuit provided in one-to-one correspondence with the plurality of data lines; The NOT circuit is A logic level of a selection signal supplied to one of the k selection signal lines is inverted and supplied to an inverted selection signal line that forms a pair with the one selection signal line. The electro-optical device according to claim 1 .

6. a first insulating layer, a first wiring layer, a second insulating layer, a second wiring layer, a third insulating layer, and a third wiring layer are laminated in this order; the one selection signal line is made of the same material as the first wiring layer, the data signal line is made of the same material as the second wiring layer, The one inverted selection signal line is made of the same material as the third wiring layer. The electro-optical device according to claim 1 .

7. a first wiring branching from the one selection signal line and extending along the second direction to the switching element; the data signal line, and a second wiring branching from the one inverted selection signal line and extending to the switching element along the second direction; overlap in plan view 7. The electro-optical device according to claim 6.

8. 8. An electronic device comprising the electro-optical device according to claim 1.

Images