Manufacturing method for semiconductor device and semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device, in which the position of a gate electrode is easily controllable.SOLUTION: A manufacturing method for a semiconductor device includes steps of: forming a mask layer on a substrate; forming a plurality of opening parts in the mask layer; growing crystals of a semiconductor in the openings to form a plurality of columnar parts including a first impurity region, which is one of a source region and a drain region, a second impurity region, which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; forming an insulating layer at a side wall of each of the columnar parts; and forming a gate electrode at a side of the channel formation region through the insulating layer. The first impurity region is formed between the substrate and the channel formation region. The thickness of the mask layer is made larger than a half of the thickness of the first impurity region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Semiconductor nanocolumns are attracting attention as a component of next-generation nanodevices, with potential applications in various semiconductor devices such as transistors and light sources.

[0003] For example, Patent Document 1 describes a semiconductor device including a plurality of pillars each having a source region, a drain region, and a channel formation region, an insulating layer provided between the source regions of adjacent pillars, and a gate electrode provided between the channel formation regions of adjacent pillars. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-146053 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device described above, after forming the multiple pillar-shaped sections, an insulating layer is formed to cover the multiple pillar-shaped sections, and the insulating layer is etched back to form an insulating layer between the source regions of adjacent pillar-shaped sections. The height position of the gate electrode is determined by the amount of etching in the insulating layer during the etch-back. However, it is difficult to control the amount of etching in the insulating layer during the etch-back. [Means for solving the problem]

[0006] One aspect of the method for manufacturing a semiconductor device according to the present invention is to forming a mask layer on a substrate; forming a plurality of openings in the mask layer; growing a semiconductor crystal in the plurality of openings to form a plurality of pillar-shaped portions each having a first impurity region which is one of a source region and a drain region, a second impurity region which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; forming an insulating layer on a side wall of each of the plurality of columnar portions; forming a gate electrode on a side of the channel formation region via the insulating layer; Including, The first impurity region is formed between the substrate and the channel formation region; The thickness of the mask layer is set to be greater than half the thickness of the first impurity region.

[0007] One aspect of the semiconductor device according to the present invention is A substrate; a plurality of pillar-shaped portions made of a semiconductor, each of which has a first impurity region which is one of a source region and a drain region, a second impurity region which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; an insulating layer provided on a side wall of each of the plurality of columnar portions; a gate electrode provided on a side of the channel formation region via the insulating layer; a mask layer provided between the substrate and the gate electrode and having a plurality of openings; Including, the plurality of columnar portions are provided in the plurality of openings, the first impurity region is provided between the substrate and the channel formation region, The thickness of the mask layer is greater than half the thickness of the first impurity region. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention. [Figure 2]3 is a flowchart for explaining a method for manufacturing a semiconductor device according to the present embodiment. [Figure 3] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 11] 10A to 10C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to a reference example. [Figure 12] 10A to 10C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to a reference example. [Figure 13] 10A to 10C are cross-sectional views schematically showing a manufacturing process of a semiconductor device according to a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. Semiconductor Devices First, the semiconductor device according to this embodiment will be described with reference to the drawings. Fig. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to this embodiment.

[0011] As shown in FIG. 1, the semiconductor device 100 includes, for example, a substrate 10, a columnar portion 20, a mask layer 30, an insulating layer 40, a gate electrode 50, an inter-columnar insulating layer 60, a first electrode 70, and a second electrode 72.

[0012] The substrate 10 supports the columnar section 20 and the mask layer 30. The substrate 10 is, for example, an n-type GaN substrate doped with Si.

[0013] The columnar portion 20 is provided on the substrate 10. The columnar portion 20 is provided between the substrate 10 and the second electrode 72. The columnar portion 20 has a columnar shape that protrudes upward from the substrate 10. The columnar portion 20 is also called, for example, a nanocolumn, a nanowire, a nanorod, or a nanopillar. The planar shape of the columnar portion 20 is, for example, a polygon such as a hexagon, or a circle.

[0014] The diameter of the columnar portion 20 is, for example, 50 nm or more and 800 nm or less, and preferably 400 nm or more and 600 nm or less. By making the diameter of the columnar portion 20 800 nm or less, it is possible to obtain a columnar portion 20 of high quality crystal.

[0015] For example, a plurality of columnar sections 20 are provided. By providing a plurality of columnar sections 20, the semiconductor device 100 can achieve a large current and is suitably used as a power device. The plurality of columnar sections 20 are spaced apart from one another. The interval between adjacent columnar sections 20 is, for example, 10 nm or more and 1 μm or less, preferably 100 nm or more and 800 nm or less. The thickness is more preferably 400 nm or more and 600 nm or less. The plurality of columnar sections 20 are arranged, for example, in a predetermined direction at a predetermined pitch in a planar view. The plurality of columnar sections 20 are arranged, for example, in a regular triangular lattice pattern or a square lattice pattern in a planar view.

[0016] The pillar-shaped portion 20 is made of a semiconductor. The pillar-shaped portion 20 is, for example, a group III nitride semiconductor and has a wurtzite crystal structure. The pillar-shaped portion 20 has, for example, a first impurity region 22, a channel formation region 24, a drift region 26, and a second impurity region 28.

[0017] The first impurity region 22 is provided on the substrate 10. The first impurity region 22 is provided between the substrate 10 and the channel formation region 24. In the illustrated example, the first impurity region 22 is in contact with the substrate 10 and the channel formation region 24. The first impurity region 22 is one of a source region and a drain region. The first impurity region 22 is, for example, a source region. The material of the first impurity region 22 is, for example, n-type GaN doped with Si. The impurity concentration of the first impurity region 22 may be the same as the impurity concentration of the substrate 10. The impurity concentration is measured, for example, by an atom probe method.

[0018] The channel formation region 24 is provided on the first impurity region 22. The channel formation region 24 is provided between the first impurity region 22 and the second impurity region 28. In the illustrated example, the channel formation region 24 is provided between the first impurity region 22 and the drift region 26. The material of the channel formation region 24 is, for example, n-type GaN doped with Si. The impurity concentration of the channel formation region 24 is lower than the impurity concentrations of the substrate 10 and the impurity regions 22 and 28. The impurity concentration of the channel formation region 24 may be lower than the impurity concentration of the drift region 26. A channel is formed in the channel formation region 24 by applying a predetermined voltage to the gate electrode 50. For example, an N-channel is formed in the channel formation region 24.

[0019] The material of the channel formation region 24 may be p-type GaN doped with Mg, or may be a UID (unitentionally doped) type semiconductor that is not intentionally doped with impurities.

[0020] The drift region 26 is provided on the channel formation region 24. The drift region 26 is provided between the channel formation region 24 and the second impurity region 28. In the example shown, the drift region 26 is in contact with the channel formation region 24 and the second impurity region 28. The thickness of the drift region 26 is, for example, greater than the thicknesses of the channel formation region 24 and the impurity regions 22 and 28. The material of the drift region 26 is, for example, n-type GaN doped with Si. The impurity concentration of the drift region 26 is lower than the impurity concentrations of the impurity regions 22 and 28.

[0021] The second impurity region 28 is provided on the drift region 26. The second impurity region 28 is provided between the drift region 26 and the second electrode 72. The second impurity region 28 is the other of the source region and the drain region. The second impurity region 28 is, for example, the drain region. The material of the second impurity region 28 is, for example, n-type GaN doped with Si. The impurity concentration of the second impurity region 28 may be the same as the impurity concentration of the first impurity region 22.

[0022] The mask layer 30 is provided on the substrate 10. The mask layer 30 is provided between the substrate 10 and the gate electrode 50. In the illustrated example, the mask layer 30 is provided between the substrate 10 and the insulating layer 40. The mask layer 30 is in contact with the substrate 10 and the insulating layer 40. The mask layer 30 is provided between the first impurity regions 22 of the adjacent columnar sections 20. Mask The layer 30 surrounds the first impurity region 22 in a plan view.

[0023] The thickness T1 of the mask layer 30 is greater than half the thickness T2 of the first impurity region 22. In the illustrated example, the thickness T1 is smaller than the thickness T2. The thickness T1 is the size of the mask layer 30 in the height direction of the columnar section 20. The thickness T2 is the size of the first impurity region 22 in the height direction of the columnar section 20. The thicknesses are measured, for example, by a scanning electron microscope (SEM). The mask layer 30 is, for example, a titanium (Ti) layer, a molybdenum (Mo) layer, a silicon oxide (SiO2) layer, or the like.

[0024] A plurality of openings 32 are formed in the mask layer 30. A plurality of openings 32 are formed corresponding to a plurality of columnar sections 20. The columnar sections 20 are provided in the openings 32. The plurality of columnar sections 20 are provided in the plurality of openings 32. The openings 32 expose the substrate 10. The mask layer 30 functions as a mask for growing the columnar sections 20.

[0025] The insulating layer 40 is provided on the sidewall 21 of the columnar section 20. The insulating layer 40 is further provided on the mask layer 30. The insulating layer 40 has a first layer 42 provided on the sidewall 21 and a second layer 44 provided on the mask layer 30.

[0026] The first layer 42 of the insulating layer 40 is provided between the columnar section 20 and the gate electrode 50. Furthermore, the first layer 42 is provided between the columnar section 20 and the inter-columnar insulating layer 60. In the illustrated example, the first layer 42 is in contact with the first impurity region 22, the channel formation region 24, the drift region 26, and the second impurity region 28. The first layer 42 functions as a gate insulating layer.

[0027] The second layer 44 of the insulating layer 40 is provided between the mask layer 30 and the gate electrode 50. In the illustrated example, the second layer 44 is in contact with the mask layer 30 and the gate electrode 50. The second layer 44 is connected to the first layer 42. The second layer 44 is provided integrally with the first layer 42. In the illustrated example, the sum of the thickness T1 of the mask layer 30 and the thickness T3 of the second layer 44 is the same as the thickness T2 of the first impurity region 22. In other words, the upper surface of the mask layer 30 is located lower than the upper surface of the first impurity region 22 by the thickness T3 of the second layer 44.

[0028] The insulating layer 40 is, for example, a silicon oxide (SiO2) layer, a hafnium oxide (HfO2) layer, a tantalum oxide (Ta2O5) layer, an yttrium oxide (Y2O3) layer, a zirconium oxide (ZrO2) layer, or a lanthanum oxide (La2O3) layer.

[0029] The gate electrode 50 is provided on the second layer 44 of the insulating layer 40. The gate electrode 50 is provided between the second layer 44 and the inter-columnar insulating layer 60. The gate electrode 50 is provided between the channel formation regions 24 of adjacent columnar sections 20. The gate electrode 50 is provided on the side of the channel formation region 24, with the first layer 42 of the insulating layer 40 interposed therebetween. For example, the gate electrode 50 surrounds the channel formation region 24 in a plan view. That is, the semiconductor device 100 is, for example, a field effect transistor (FET) with a gate all around (GAA) structure. This allows the channel formation region 24 to be completely depleted, improving current controllability. Note that the semiconductor device 100 may be a FinFET in which the gate electrode 50 is provided to surround the channel formation region 24.

[0030] The distance D1 between the gate electrode 50 and the substrate 10 is, for example, the same as the distance D2 between the channel formation region 24 and the substrate 10. The distances D1 and D2 are measured, for example, by SEM. In the height direction of the columnar section 20, for example, the position of the boundary between the second layer 44 and the gate electrode 50 is the same as the position of the boundary between the first impurity region 22 and the channel formation region 24. In the illustrated example, the thickness of the gate electrode 50 is the same as the thickness of the channel formation region 24. The gate electrode 50 is made of, for example, polysilicon or metal doped with impurities such as phosphorus or boron.

[0031] The inter-columnar insulating layer 60 is provided on the gate electrode 50. The inter-columnar insulating layer 60 is provided between the gate electrode 50 and the second electrode 72. The inter-columnar insulating layer 60 is provided between the drift regions 26 of adjacent columnar portions 20 and between the second impurity regions 28 of adjacent columnar portions 20. The inter-columnar insulating layer 60 surrounds the drift regions 26 and the second impurity regions 28 in a plan view. In the height direction of the columnar portion 20, for example, the position of the boundary between the gate electrode 50 and the inter-columnar insulating layer 60 is the same as the position of the boundary between the channel formation region 24 and the drift region 26. The inter-columnar insulating layer 60 is, for example, a silicon oxide, polyimide, or SOG (spin on glass) layer.

[0032] The first electrode 70 is provided below the substrate 10. The first electrode 70 is provided on the opposite side of the substrate 10 from the multiple columnar sections 20. The first electrode 70 is electrically connected to the first impurity region 22 via the substrate 10. The substrate 10 may be in ohmic contact with the first electrode 70. The material of the first electrode 70 is, for example, polysilicon or metal doped with impurities such as phosphorus or boron.

[0033] The second electrode 72 is provided on the multiple columnar sections 20 and on the inter-columnar insulating layer 60. The second electrode 72 is provided on the multiple columnar sections 20 on the side opposite the substrate 10, and on the inter-columnar insulating layer 60 on the side opposite the substrate 10. The second electrode 72 is electrically connected to the second impurity region 28. The second impurity region 28 may be in ohmic contact with the second electrode 72. The material of the second electrode 72 is, for example, polysilicon or metal doped with impurities such as phosphorus or boron.

[0034] In the above, an example has been described in which the materials of the substrate 10, the impurity regions 22, 28, and the drift region 26 are n-type semiconductors and an N-channel is formed in the channel formation region 24. However, the materials of the substrate 10, the impurity regions 22, 28, and the drift region 26 may be p-type semiconductors and a P-channel may be formed in the channel formation region 24.

[0035] Although the above description has been given of an example in which the material of the columnar section 20 is GaN, a Group III nitride semiconductor, the material of the columnar section 20 may be a Group III nitride semiconductor other than GaN, a compound semiconductor other than a Group III nitride semiconductor including a Group II semiconductor, or silicon. However, when the semiconductor device 100 is used as a high-frequency device, the material of the columnar section 20 is preferably a Group III nitride semiconductor.

[0036] The semiconductor device 100 is used, for example, as a power device, and is applied to inverters, chargers, step-up converters, step-down converters, DC (Direct Current) / DC converters, electric airplanes, electric vehicles, etc. The semiconductor device 100 may also be used as a logic device, a high-frequency device, etc., instead of a power device.

[0037] 2. Manufacturing method of semiconductor device Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described with reference to the drawings. Fig. 2 is a flowchart for explaining the method for manufacturing the semiconductor device 100 according to this embodiment. Figs. 3 to 10 are cross-sectional views schematically showing the manufacturing process of the semiconductor device 100 according to this embodiment.

[0038] As shown in FIGS. 2 and 3, a mask layer 30 is formed on a substrate 10 (step S1). The mask layer 30 is formed by, for example, a CVD (Chemical Vapor Deposition) method, an electron beam evaporation method, or a sputtering method. In this step, the thickness of the mask layer 30 is determined so as to be equal to or larger than the thickness of the first impurity region. The mask layer 30 is formed so that the thickness thereof is greater than half the thickness of the first impurity region 22. In other words, the thickness of the mask layer 30 is made greater than half the thickness of the first impurity region 22.

[0039] 4, the mask layer 30 is patterned to form a plurality of openings 32 in the mask layer 30 (step S2). The patterning is performed by, for example, electron beam lithography and dry etching, or photolithography and dry etching.

[0040] 5, using the mask layer 30 as a mask, a semiconductor is grown in the plurality of openings 32 on the substrate 10 to form a plurality of columnar sections 20 (step S3). Specifically, a first impurity region 22, a channel formation region 24, a drift region 26, and a second impurity region 28 are formed in this order from the substrate 10 side. The crystal growth of the columnar sections 20 is performed by epitaxial growth using, for example, MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy). The crystal growth of the columnar sections 20 is performed while doping with impurities.

[0041] 6, an insulating layer 40 is formed on the sidewall 21 of the columnar section 20 (step S4). In the illustrated example, the insulating layer 40 is formed on the sidewall 21 and upper surface of the columnar section 20 and the upper surface of the mask layer 30 so as to cover the columnar section 20 and the mask layer 30. The insulating layer 40 is formed by, for example, a CVD method, an ALD (Atomic Layer Deposition) method, or a thermal oxidation method.

[0042] 7, a conductive layer 50a that will become the gate electrode 50 is formed so as to cover the insulating layer 40 (step S5). Specifically, the conductive layer 50a is formed so as to cover the insulating layer 40 and fill the spaces between adjacent columnar sections 20. The conductive layer 50a is formed by, for example, a CVD method, a sputtering method, or a vacuum deposition method. In this step, for example, the distance between the conductive layer 50a that will become the gate electrode 50 and the substrate 10 is set to be the same as the distance between the channel formation region 24 and the substrate 10.

[0043] 8, the conductive layer 50a is etched back to form the gate electrode 50 on the side of the channel formation region 24 via the insulating layer 40 (step S6). The etch back is performed by, for example, dry etching.

[0044] 9, the inter-columnar insulating layer 60 is formed so as to cover the insulating layer 40 and the gate electrode 50 (step S7). Specifically, the inter-columnar insulating layer 60 is formed so as to cover the insulating layer 40 and the gate electrode 50 and fill the spaces between adjacent columnar portions 20. The inter-columnar insulating layer 60 is formed by, for example, a CVD method, an ALD method, or a spin coating method.

[0045] 10, the inter-columnar insulating layer 60 is etched back to expose the multiple columnar sections 20 (step S8). Specifically, the upper surfaces of the second impurity regions 28 are exposed. The etchback is performed by, for example, dry etching.

[0046] 1, a second electrode 72 electrically connected to the second impurity region 28 is formed on the plurality of columnar sections 20 and on the inter-columnar insulating layer 60 (step S9). Next, a first electrode 70 electrically connected to the first impurity region 22 via the substrate 10 is formed on the side of the substrate 10 opposite the plurality of columnar sections 20 (step S10). The first electrode 70 and the second electrode 72 are formed by, for example, a CVD method, a sputtering method, or a vacuum deposition method. The order in which the first electrode 70 and the second electrode 72 are formed is not particularly limited.

[0047] Through the above steps, the semiconductor device 100 can be manufactured.

[0048] The method for manufacturing the semiconductor device 100 has, for example, the following features.

[0049] The method for manufacturing the semiconductor device 100 includes the steps of forming a mask layer 30 on a substrate 10, forming a plurality of openings 32 in the mask layer 30, growing a semiconductor crystal in the plurality of openings 32 to form a plurality of columnar sections 20, forming an insulating layer 40 on the sidewall 21 of each of the plurality of columnar sections 20, and forming a gate electrode 50 on the side of the channel formation region 24 via the insulating layer 40. A first impurity region 22 is formed between the substrate 10 and the channel formation region 24, and a thickness T1 of the mask layer 30 is set to be greater than half a thickness T2 of the first impurity region 22.

[0050] Therefore, in the manufacturing method of the semiconductor device 100, the height position of the gate electrode 50 can be determined by the thickness T1 of the mask layer 30. Therefore, the position of the gate electrode 50 can be easily controlled. As a result, the variation in the position of the gate electrode 50 can be reduced, and the variation in electrical characteristics can be reduced. Furthermore, the gate electrode 50 can be positioned at a desired position.

[0051] For example, as shown in FIG. 11 , when the thickness of the mask layer 1030 is less than half the thickness of the first impurity region 1022, an insulating layer 1080 is formed on the entire surface, and then the insulating layer 1080 is etched back as shown in FIG. 12 . Next, a gate electrode 1050 is formed on the insulating layer 1080 as shown in FIG. 13 . It is difficult to control the amount of etching during the etch-back of the insulating layer 1080, and the thickness of the etched-back insulating layer 1080 may vary or may not be the desired value. As a result, the position of the gate electrode 1050 may vary, or the gate electrode 1050 may not be positioned at the desired position. For example, if the amount of etching of the insulating layer 1080 is too great, the insulating layer 1040 may be removed, and the columnar portion 1020 may also be etched.

[0052] As described above, in the method for manufacturing the semiconductor device 100, the position of the gate electrode 50 is not determined by etching back an insulating layer, making it easy to control the position of the gate electrode 50. Furthermore, since the steps of forming an insulating layer corresponding to the insulating layer 1080 and etching back the insulating layer are unnecessary, the manufacturing process can be shortened, thereby reducing costs.

[0053] 11 to 13 are cross-sectional views schematically showing manufacturing steps of a semiconductor device according to a reference example. The semiconductor device according to the reference example includes a substrate 1010, a columnar section 1020, a mask layer 1030, an insulating layer 1040, a gate electrode 1050, and an insulating layer 1080. The columnar section 1020 has a first impurity region 1022, a channel formation region 1024, a drift region 1026, and a second impurity region 1028.

[0054] In the method for manufacturing the semiconductor device 100, the drift region 26 is formed between the channel formation region 24 and the drain region in the step of forming the multiple pillars 20. Therefore, in the method for manufacturing the semiconductor device 100, the breakdown voltage can be improved.

[0055] The method for manufacturing the semiconductor device 100 includes a step of forming a first electrode 70 electrically connected to the first impurity region 22 via the substrate 10 on the side of the substrate 10 opposite the plurality of columnar sections 20. Therefore, the method for manufacturing the semiconductor device 100 can reduce the area in a plan view and achieve miniaturization, for example, compared to when the first electrode is formed on a substrate.

[0056] The method for manufacturing the semiconductor device 100 includes, after the step of forming the gate electrode 50, the steps of forming an inter-columnar insulating layer 60 between the second impurity regions 28 of adjacent columnar sections 20 among the plurality of columnar sections 20, and forming a second electrode 72 electrically connected to the second impurity regions 28 on the plurality of columnar sections 20 and on the inter-columnar insulating layer 60. Therefore, the method for manufacturing the semiconductor device 100 has a reduced cost compared to, for example, when the inter-columnar insulating layer is not formed. 2, and the possibility of the second electrode 72 being broken can be reduced.

[0057] In the method for manufacturing the semiconductor device 100, the distance D1 between the gate electrode 50 and the substrate 10 is set to be the same as the distance D2 between the channel formation region 24 and the substrate 10. Therefore, in the method for manufacturing the semiconductor device 100, the influence of the voltage applied to the gate electrode 50 on the first impurity region 22 can be reduced.

[0058] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0059] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0060] The following can be derived from the above-described embodiment and modifications.

[0061] One aspect of the method for manufacturing a semiconductor device includes: forming a mask layer on the substrate; forming a plurality of openings in the mask layer; growing a semiconductor crystal in the plurality of openings to form a plurality of pillar-shaped portions each having a first impurity region which is one of a source region and a drain region, a second impurity region which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; forming an insulating layer on a side wall of each of the plurality of columnar portions; forming a gate electrode on a side of the channel formation region via the insulating layer; Including, The first impurity region is formed between the substrate and the channel formation region; The thickness of the mask layer is set to be larger than half the thickness of the first impurity region.

[0062] According to such a method for manufacturing a semiconductor device, the position of the gate electrode can be easily controlled.

[0063] In one aspect of the manufacturing method of the semiconductor device, In the step of forming the plurality of pillar-shaped portions, a drift region may be formed between the channel formation region and the drain region.

[0064] According to such a method for manufacturing a semiconductor device, the breakdown voltage can be improved.

[0065] In one aspect of the manufacturing method of the semiconductor device, The method may include forming a first electrode electrically connected to the first impurity region via the substrate on the opposite side of the substrate from the plurality of columnar portions.

[0066] According to such a method for manufacturing a semiconductor device, miniaturization can be achieved.

[0067] In one aspect of the manufacturing method of the semiconductor device, forming an inter-columnar portion insulating layer between the second impurity regions of adjacent columnar portions of the plurality of columnar portions after the step of forming the gate electrode; forming a second electrode electrically connected to the second impurity region on the plurality of columnar portions and on the inter-columnar insulating layer; may include:

[0068] According to this method for manufacturing a semiconductor device, the possibility of the second electrode being broken can be reduced.

[0069] In one aspect of the manufacturing method of the semiconductor device, The distance between the gate electrode and the substrate may be the same as the distance between the channel formation region and the substrate.

[0070] According to this method for manufacturing a semiconductor device, it is possible to reduce the influence of the voltage applied to the gate electrode on the first impurity region.

[0071] One aspect of the semiconductor device is A substrate; a plurality of pillar-shaped portions made of a semiconductor, each of which has a first impurity region which is one of a source region and a drain region, a second impurity region which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; an insulating layer provided on a side wall of each of the plurality of columnar portions; a gate electrode provided on a side of the channel formation region via the insulating layer; a mask layer provided between the substrate and the gate electrode, the mask layer having a plurality of openings formed therein; the plurality of columnar portions are provided in the plurality of openings, the first impurity region is provided between the substrate and the channel formation region, The thickness of the mask layer is greater than half the thickness of the first impurity region.

[0072] According to such a semiconductor device, the position of the gate electrode can be easily controlled.

[0073] In one aspect of the semiconductor device, Each of the plurality of pillar portions may have a drift region provided between the channel formation region and the drain region.

[0074] Such a semiconductor device can improve the breakdown voltage.

[0075] In one aspect of the semiconductor device, The semiconductor device may further include a first electrode provided on the substrate on the opposite side to the plurality of columnar portions and electrically connected to the first impurity region via the substrate.

[0076] Such a semiconductor device can be made smaller.

[0077] In one aspect of the semiconductor device, an inter-columnar portion insulating layer provided between the second impurity regions of adjacent columnar portions among the plurality of columnar portions; a second electrode provided on the plurality of columnar portions and on the inter-columnar insulating layer, the second electrode being electrically connected to the second impurity region; may include:

[0078] According to such a semiconductor device, the possibility of the second electrode being broken can be reduced. .

[0079] In one aspect of the semiconductor device, The distance between the gate electrode and the substrate may be the same as the distance between the channel formation region and the substrate.

[0080] According to such a semiconductor device, it is possible to reduce the influence of the voltage applied to the gate electrode on the first impurity region. [Explanation of symbols]

[0081] 10...substrate, 20...columnar portion, 21...sidewall, 22...first impurity region, 24...channel formation region, 26...drift region, 28...second impurity region, 30...mask layer, 32...opening, 40...insulating layer, 42...first layer, 44...second layer, 50...gate electrode, 50a...conductive layer, 60...inter-columnar portion insulating layer, 70...first electrode, 72...second electrode, 100...semiconductor device, 1010...substrate, 1020...columnar portion, 1022...first impurity region, 1024...channel formation region, 1026...drift region, 1028...second impurity region, 1030...mask layer, 1040...insulating layer, 1050...gate electrode, 1080...insulating layer

Claims

1. forming a mask layer on a substrate; forming a plurality of openings in the mask layer; growing a semiconductor crystal in the plurality of openings to form a plurality of pillar-shaped portions each having a first impurity region which is one of a source region and a drain region, a second impurity region which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; forming an insulating layer on a side wall of each of the plurality of columnar portions; forming a gate electrode on a side of the channel formation region via the insulating layer; Including, The first impurity region is formed between the substrate and the channel formation region; A method for manufacturing a semiconductor device, wherein the thickness of the mask layer is set to be greater than half the thickness of the first impurity region.

2. In claim 1, In the step of forming the plurality of pillar portions, a drift region is formed between the channel formation region and the drain region.

3. In claim 1, A method for manufacturing a semiconductor device, comprising: forming a first electrode electrically connected to the first impurity region via the substrate on a side of the substrate opposite to the plurality of columnar portions.

4. In claim 3, forming an inter-columnar portion insulating layer between the second impurity regions of adjacent columnar portions of the plurality of columnar portions after the step of forming the gate electrode; forming a second electrode electrically connected to the second impurity region on the plurality of columnar portions and on the inter-columnar insulating layer; A method for manufacturing a semiconductor device, comprising:

5. In claim 1, A method for manufacturing a semiconductor device, wherein the distance between the gate electrode and the substrate is made the same as the distance between the channel formation region and the substrate.

6. A substrate; a plurality of pillar-shaped portions made of a semiconductor, each of which has a first impurity region which is one of a source region and a drain region, a second impurity region which is the other of the source region and the drain region, and a channel formation region provided between the first impurity region and the second impurity region; an insulating layer provided on a side wall of each of the plurality of columnar portions; a gate electrode provided on a side of the channel formation region via the insulating layer; a mask layer provided between the substrate and the gate electrode, the mask layer having a plurality of openings formed therein; the plurality of columnar portions are provided in the plurality of openings, the first impurity region is provided between the substrate and the channel formation region, The thickness of the mask layer is greater than half the thickness of the first impurity region.

7. In claim 6, Each of the plurality of pillar portions has a drift region provided between the channel formation region and the drain region.

8. In claim 6, a first electrode provided on the substrate on the opposite side to the plurality of columnar portions, the first electrode being electrically connected to the first impurity region via the substrate;

9. In claim 8, an inter-columnar portion insulating layer provided between the second impurity regions of adjacent columnar portions among the plurality of columnar portions; a second electrode provided on the plurality of columnar portions and on the inter-columnar insulating layer, the second electrode being electrically connected to the second impurity region; 10. A semiconductor device comprising:

10. In claim 1, a distance between the gate electrode and the substrate being the same as a distance between the channel formation region and the substrate;

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