Semiconductor device

Abstract

To provide a reference voltage generator that generates a reference voltage based on light irradiation.SOLUTION: A reference voltage generator in the present disclosure generates a reference voltage based on the open-circuit voltage difference between solar cell 100A and solar cell 200A.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and for example, to a technique that is effective when applied to a semiconductor device that includes a reference voltage generating unit that generates a reference voltage. [Background technology]

[0002] Non-Patent Document 1 describes a technique related to a reference voltage generating circuit that generates a reference voltage using a transistor. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Haoyu Zhuang, Xiaoxian Liu, and Hao Wang “Voltage Reference With Linear-Temperature-Dependent Power Consumption” IEEE TRANSACTION ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.28, NO.4 APRIL 2020 Summary of the Invention [Problem to be solved by the invention]

[0004] Typically, circuits generate various voltages required for operation based on a reference voltage. Therefore, for example, a circuit includes a reference voltage generation circuit that generates the reference voltages. A typical reference voltage generation circuit uses transistors. In this regard, there is a demand for a versatile reference voltage generation circuit that can be used in standalone devices such as sensor nodes and Internet of Things (IoT) devices, which are expected to develop in the future. [Means for solving the problem]

[0005] A semiconductor device in one embodiment includes a reference voltage generating unit that generates a reference voltage based on an open-circuit voltage difference between a first solar cell and a second solar cell. [Effects of the Invention]

[0006] According to one embodiment, the reference voltage can be generated based on illumination with light. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a diagram illustrating a circuit configuration of a reference voltage generating unit. [Figure 2] FIG. 2 is a diagram showing the configuration of a first solar cell. [Figure 3] FIG. 4 is a diagram showing the configuration of a second solar cell. [Figure 4] FIG. 10 is a plan view showing the configuration of a semiconductor device according to Modification 1. [Figure 5] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 1. [Figure 6] 10A and 10B are cross-sectional views showing an example of irradiating a semiconductor device with light. [Figure 7] 10 is a graph showing the relationship between temperature and open-circuit voltage difference in the present first modification. [Figure 8] 10 is a graph showing the temperature dependence of a reference voltage generated by adding an open circuit voltage difference and the open circuit voltage itself multiplied by a correction factor. [Figure 9] FIG. 1 is a diagram showing an example of a circuit configuration of a reference voltage generating unit 1A incorporating temperature correction. [Figure 10] FIG. 10 is a diagram showing a configuration of a semiconductor device according to a second modification. [Figure 11] 10 is a graph showing the relationship between the carrier lifetime and the open-circuit voltage difference in a bulk substrate. DETAILED DESCRIPTION OF THE INVENTION

[0008] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0009] <Basic Concept of the Embodiment> The basic idea of ​​this embodiment is to realize a reference voltage generation unit that generates a reference voltage based on, for example, the open-circuit voltage difference between a first solar cell and a second solar cell. That is, the basic idea is based on a new design concept of generating a reference voltage by utilizing the open-circuit voltage difference between multiple solar cell structures. In this way, the basic idea is novel in that solar cells are used as components of the reference voltage generation unit, rather than transistors. In other words, the reference voltage generation unit in the basic idea does not include transistors. On the other hand, the reference voltage generation unit in the basic idea includes two solar cell structures with different open-circuit voltages. As a result, the basic idea provides the following advantages.

[0010] (1) It is possible to provide a reference voltage generating unit that does not require transistors. In other words, by using solar cells, it is possible to generate a reference voltage with a simple configuration that does not include transistors.

[0011] (2) According to the basic concept, the reference voltage generation unit can be operated by irradiating the solar cell with light. As a result, the basic concept eliminates the need to supply power to the reference voltage generation unit. For example, a typical reference voltage generation unit that uses a transistor requires an external power supply unit to operate. In contrast, the basic concept allows the reference voltage generation unit to be operated by irradiating the solar cell itself with light. Therefore, according to the basic concept, a reference voltage generation unit that can be easily applied to standalone devices such as sensor nodes and IoT devices can be provided. In other words, according to the basic concept, a highly versatile reference voltage generation unit that does not require an external power supply unit can be realized. Therefore, the basic concept is an extremely excellent technical concept in that it can provide a reference voltage generation unit with a wide range of applications that does not require an external power supply unit.

[0012] (3) For example, a typical reference voltage generator that uses a transistor requires a separate power supply unit to operate the reference voltage generator. This increases the size of the typical reference voltage generator, as it also requires a power supply unit. In contrast, a reference voltage generator that uses a solar cell does not require a separate power supply unit. This allows the size of a reference voltage generator that uses a solar cell to be reduced. This means that the basic concept is useful from the perspective of miniaturizing standalone devices such as sensor nodes and IoT devices. Therefore, the basic concept has extremely important technical significance from the perspective of reducing the size of the reference voltage generator.

[0013] The following describes embodiments that embody the basic concept described above.

[0014] <Realization mode> <<Circuit configuration of the reference voltage generation section>> FIG. 1 is a diagram showing a circuit configuration of a reference voltage generating unit 1 in an embodiment.

[0015] As shown in FIG. 1, the reference voltage generating unit 1 has a solar cell 100, a solar cell 200, and a high resistance element 300. The solar cell 100 has an anode and a cathode. The anode of the solar cell 100 is electrically connected to one end of the high resistance element 300. Meanwhile, the cathode of the solar cell 100 is electrically connected to ground. Similarly, the solar cell 200 also has an anode and a cathode. The anode of the solar cell 200 is electrically connected to the other end of the high resistance element 300. Meanwhile, the cathode of the solar cell 200 is electrically connected to ground.

[0016] Open circuit voltage V of solar cell 100 OCH is the open circuit voltage V of the solar cell 200 OCL As a result, an open circuit voltage V OCH and open circuit voltage V OCLAs a result, the reference voltage generating unit 1 applies the difference between the open circuit voltage V OCH and open circuit voltage V OCL A reference voltage is generated which is the difference between

[0017] Structural differences are provided between solar cell 100 and solar cell 200 to differentiate the open circuit voltages. Below, the configurations of solar cell 100 and solar cell 200, which have structural differences, will be described.

[0018] <<Configuration of solar cell 100>> FIG. 2 is a diagram showing the configuration of the solar cell 100. As shown in FIG.

[0019] In FIG. 2, solar cell 100 has p-type semiconductor substrate 10, n-type well 11A, p-type semiconductor region 12, p-type semiconductor region 13, n-type semiconductor region 14, insulating film 15, contact 16A, contact 17A and contact 18A.

[0020] The p-type semiconductor substrate 10 is made of, for example, a silicon substrate doped with boron, which is a p-type impurity (acceptor). The n-type well 11A is formed in the p-type semiconductor substrate 10. The n-type well 11A is doped with, for example, arsenic or phosphorus, which is an n-type impurity (donor). The p-type semiconductor region 12 and the p-type semiconductor region 13 are each formed in the p-type semiconductor substrate 10. The p-type semiconductor region 12 and the p-type semiconductor region 13 are each doped with, for example, boron, which is a p-type impurity. The impurity concentration of the p-type semiconductor region 12 is higher than the impurity concentration of the p-type semiconductor substrate 10. Similarly, the impurity concentration of the p-type semiconductor region 13 is also higher than the impurity concentration of the p-type semiconductor substrate 10.

[0021] An insulating film 15 is formed on the p-type semiconductor substrate 10. The insulating film 15 is made of, for example, a silicon oxide film. The contact 16A penetrates the insulating film 15 and is electrically connected to the p-type semiconductor region 12. That is, the contact 16A is arranged on the p-type semiconductor region 12. The contact 17A penetrates the insulating film 15 and is electrically connected to the p-type semiconductor region 13. That is, the contact 17A is arranged on the p-type semiconductor region 13. The contact 18A penetrates the insulating film 15 and is electrically connected to the n-type semiconductor region 14. That is, the contact 18A is arranged on the n-type semiconductor region 14. In this manner, the solar cell 100 is constructed.

[0022] <<Configuration of solar cell 200>> FIG. 3 is a diagram showing the configuration of the solar cell 200. As shown in FIG.

[0023] In FIG. 3, solar cell 200 has p-type semiconductor substrate 10, n-type well 11B, insulating film 15, contact 16B, contact 17B, and contact 18B.

[0024] The p-type semiconductor substrate 10 is made of, for example, a silicon substrate doped with boron, which is a p-type impurity (acceptor). The n-type well 11B is formed in the p-type semiconductor substrate 10. The n-type well 11B is doped with, for example, arsenic or phosphorus, which is an n-type impurity (donor). An insulating film 15 is formed on the p-type semiconductor substrate 10. The insulating film 15 is made of, for example, a silicon oxide film. The contact 16B penetrates the insulating film 15 and is electrically connected to the p-type semiconductor substrate 10. That is, the contact 16B is arranged on the p-type semiconductor substrate 10. The contact 17B penetrates the insulating film 15 and is electrically connected to the p-type semiconductor substrate 10. That is, the contact 17B is arranged on the p-type semiconductor substrate 10. The contact 18B penetrates the insulating film 15 and is electrically connected to the n-type well 11B. That is, the contact 18B is arranged on the n-type well 11B. In this manner, the solar cell 200 is configured.

[0025] <<Structural differences>> The structural differences between solar cell 100 and solar cell 200 will be described below. As is clear from FIGS. 2 and 3, the differences are as follows. Specifically, in solar cell 100 shown in FIG. 2, p-type semiconductor region 12, p-type semiconductor region 13, and n-type semiconductor region 14, each having a high impurity concentration, are formed. In contrast, in solar cell 200 shown in FIG. 3, these semiconductor regions are not formed. As a result, the open-circuit voltage of solar cell 100 differs from that of solar cell 200. In other words, the open-circuit voltage of solar cell 100 is higher than that of solar cell 200.

[0026] The reason for this will be explained below.

[0027] For example, in solar cell 100, p-type semiconductor region 12, p-type semiconductor region 13, and n-type semiconductor region 14 are formed with high impurity concentrations. This creates bandgap barriers in the peripheral regions of contacts 16A, 17A, and 18A, respectively. As a result, carriers approaching contacts 16A, 17A, and 18A are repelled. This suppresses the recombination rate in the peripheral regions of contacts 16A, 17A, and 18A, respectively, resulting in an increase in open-circuit voltage. In contrast, in solar cell 200, p-type semiconductor region 12, p-type semiconductor region 13, and n-type semiconductor region 14 are not formed with high impurity concentrations. As a result, the recombination rate is not suppressed in the peripheral regions of contacts 16B, 17B, and 18B, resulting in a decrease in open-circuit voltage. In other words, in solar cell 200, the open-circuit voltage is reduced by intentionally not forming p-type semiconductor region 12, p-type semiconductor region 13, and n-type semiconductor region 14 with high impurity concentrations.

[0028] From the above, the open circuit voltage of solar cell 100 is higher than that of solar cell 200 due to the formation of p-type semiconductor region 12, p-type semiconductor region 13 and n-type semiconductor region 14 having high impurity concentrations.

[0029] <<Features in Realization Mode>> Next, the features of the embodiment will be described.

[0030] A feature of the embodiment is that the configuration of solar cell 100 is different from that of solar cell 200, as shown in Figures 2 and 3, for example. Specifically, the feature is that high-concentration semiconductor regions (p-type semiconductor region 12, p-type semiconductor region 13, and n-type semiconductor region 14) are formed in solar cell 100, while high-concentration semiconductor regions are not formed in solar cell 200. This makes it possible to make the open-circuit voltage of solar cell 100 higher than the open-circuit voltage of solar cell 200. In other words, it is possible to generate an open-circuit voltage difference between solar cell 100 and solar cell 200. As a result, according to the embodiment, it is possible to realize a reference voltage generation unit that generates a reference voltage based on the open-circuit voltage difference.

[0031] For example, the reference voltage generator in the embodiment operates by irradiating the solar cell itself with light, and therefore the reference voltage generator in the embodiment is effective when applied to stand-alone devices such as sensor nodes and IoT devices.

[0032] Here, it is desirable that the open-circuit voltage difference does not depend on the illuminance of light irradiating the solar cell. This is because, for example, if the open-circuit voltage difference depends on the illuminance of light, the reference voltage generated from the open-circuit voltage difference will fluctuate depending on the external environment in which the standalone device is used. In other words, it is desirable that the reference voltage is a constant voltage that is not affected by the external environment. In this regard, in the embodied embodiment, the open-circuit voltage difference is almost independent of the illuminance of light. Therefore, according to the embodied embodiment, a constant reference voltage can be generated regardless of the external environment (illuminance environment) in which the standalone device is used. In this way, the reference voltage generator in the embodied embodiment is suitable for use in standalone devices placed in various external environments, in that it can generate a constant reference voltage without being affected by the illuminance environment.

[0033] <Variation 1> <<Improvements for improved performance>> FIG. 4 is a plan view showing the configuration of the semiconductor device according to the first modification.

[0034] 4, a solar cell 100A and a solar cell 200A are formed on a p-type semiconductor substrate 10. As shown in Fig. 4, for example, the solar cell 100A and the solar cell 200A are arranged side by side in the X direction.

[0035] The solar cell 100A has an n-type well 20A, a p-type well 30A, a p-type semiconductor region 12, a p-type semiconductor region 13, an n-type semiconductor region 14, a contact 16A, a contact 17A, and a contact 18A.

[0036] The n-type well 20A surrounds the p-type well 30A. An n-type semiconductor region 14 is formed in the p-type well 30A. A p-type semiconductor region 12 and a p-type semiconductor region 13 are formed outside the n-type semiconductor region 14. That is, the n-type semiconductor region 14 is formed between the p-type semiconductor region 12 and the p-type semiconductor region 13.

[0037] A contact 16A is disposed directly on the p-type semiconductor region 12. A contact 17A is disposed directly on the p-type semiconductor region 13. Meanwhile, a contact 18A is disposed on a portion of the n-type semiconductor region 14.

[0038] The solar cell 200A has an n-type well 20B, a p-type well 30B, an n-type semiconductor region 14, a contact 16B, a contact 17B, and a contact 18B.

[0039] The n-type well 20B surrounds the p-type well 30B. An n-type semiconductor region 14 is formed in the p-type well 30B. On the other hand, in the solar cell 200A, the p-type semiconductor region 12 and the p-type semiconductor region 13 are not formed in the p-type well 30B. A contact 16B and a contact 17B are arranged in the p-type well 30B. A contact 18B is arranged on a portion of the n-type semiconductor region 14.

[0040] FIG. 5 is a cross-sectional view showing the configuration of a semiconductor device according to the first modification.

[0041] The semiconductor device includes a solar cell 100A and a solar cell 200A.

[0042] Solar cell 100A has p-type semiconductor substrate 10, n-type well 20A, p-type well 30A, p-type semiconductor region 12, p-type semiconductor region 13, n-type semiconductor region 14, insulating film 15, contact 16A, contact 17A, and contact 18A.

[0043] The impurity concentrations of the p-type semiconductor region 12 and the p-type semiconductor region 13 are higher than the impurity concentration of the p-type semiconductor substrate and the p-type semiconductor region 12 and the p-type semiconductor region 13 are higher than the impurity concentration of the p-type well 30A.

[0044] Therefore, the solar cell 100A has high-concentration p-type semiconductor regions 12 and 13. Therefore, the open-circuit voltage of the solar cell 100A is high.

[0045] Solar cell 200A has p-type semiconductor substrate 10, n-type well 20B, p-type well 30B, n-type semiconductor region 14, insulating film 15, contact 16B, contact 17B, and contact 18B. Solar cell 200A configured in this manner does not have p-type semiconductor region 12 and p-type semiconductor region 13 present in solar cell 100A. Therefore, the open-circuit voltage of solar cell 200A is lower than the open-circuit voltage of solar cell 100A. In other words, solar cell 100A and solar cell 200A constitute solar cells with different open-circuit voltages. This allows the semiconductor device of Modification 1 to constitute a reference voltage generation unit that generates a reference voltage based on the difference in open-circuit voltage between solar cell 100A and solar cell 200A.

[0046] FIG. 6 is a cross-sectional view showing an example of irradiating a semiconductor device with light.

[0047] 6, a light-shielding member 40 is disposed above a p-type semiconductor substrate 10. The light-shielding member 40 has an opening OP1 and an opening OP2 formed therein.

[0048] Light is incident from above the light-shielding member 40. In this case, part of the light passes through the opening OP1 and enters the solar cell 100A. Also, part of the light passes through the opening OP2 and enters the solar cell 200A. This allows each of the solar cell 100A and the solar cell 200A to operate.

[0049] The semiconductor device of the first modification configured in this way can improve its performance, as will be described below.

[0050] In this first modification, the solar cell 100A has a p-type semiconductor substrate 10, an n-type well 20A, and a p-type well 30A. The n-type well 20A is formed in the p-type semiconductor substrate 10. The p-type well 30A is formed in the n-type well 20A. Therefore, the solar cell 100A has a so-called "triple well structure." In the "triple well structure," the p-type semiconductor substrate 10 and the p-type well 30A are electrically isolated by the n-type well 20A. Therefore, the p-type semiconductor region 12, the p-type semiconductor region 13, and the n-type semiconductor region 14 formed in the p-type well 30A are electrically isolated from the p-type semiconductor substrate 10.

[0051] The solar cell 200A has a p-type semiconductor substrate 10, an n-type well 20B, and a p-type well 30B. The n-type well 20B is formed in the n-type well 20B. Therefore, the solar cell 200A also has a "triple well structure." In the "triple well structure," the p-type semiconductor substrate 10 and the p-type well 30B are electrically isolated by the n-type well 20B. Therefore, the n-type semiconductor region 14 formed in the p-type well 30B is electrically isolated from the p-type semiconductor substrate 10.

[0052] As described above, in Modification 1, each of solar cell 100A and solar cell 200A has a "triple well structure." Therefore, in Modification 1, even if solar cell 100A and solar cell 200A are formed using a single p-type semiconductor substrate 10, as shown in FIG. 5, for example, solar cell 100A and solar cell 200A can be electrically isolated from each other. As a result, mutual interference between solar cell 100A and solar cell 200A can be suppressed. For example, it is possible to suppress the influence of recombination loss (large recombination loss) occurring in solar cell 200A having a low open circuit voltage on solar cell 100A having a high open circuit voltage (small recombination loss).

[0053] Therefore, according to Modification 1, it is possible to suppress fluctuations in the open-circuit voltage difference caused by mutual interference between solar cell 100A and solar cell 200A. Therefore, according to Modification 1, it is possible to improve the stability of the reference voltage generated based on the open-circuit voltage difference. In other words, according to Modification 1, it is possible to improve the performance of a semiconductor device including a reference voltage generation unit.

[0054] Thus, the technical significance of the "triple well structure" is that it can electrically isolate solar cell 100A from solar cell 200A. Therefore, according to Modification 1, by adopting the "triple well structure", it is possible to realize a reference voltage generation unit including solar cell 100A and solar cell 200A on one p-type semiconductor substrate 10 (one chip) without causing a decrease in performance of the semiconductor device including the reference voltage generation unit.

[0055] Hereinafter, it will be explained that, according to the semiconductor device of the present modification 1, the relationship between the temperature and the open-circuit voltage difference does not depend on the illuminance within a predetermined temperature range.

[0056] FIG. 7 is a graph showing the relationship between temperature and open-circuit voltage difference in the present first modification.

[0057] Figure 7 shows graphs (1), (2), (3), and (4). Graph (1) shows the relationship between temperature and open-circuit voltage difference when the illuminance is 100,000 lux. Graph (2) shows the relationship between temperature and open-circuit voltage difference when the illuminance is 10,000 lux. Graph (3) shows the relationship between temperature and open-circuit voltage difference when the illuminance is 1,000 lux. Graph (4) shows the relationship between temperature and open-circuit voltage difference when the illuminance is 100 lux.

[0058] As shown in Figure 7, for example, in the temperature range of -50°C to 75°C, graphs (1), (2), (3), and (4) are consistent. This means that in this temperature range, the relationship between temperature and open-circuit voltage difference is independent of illuminance.

[0059] Therefore, according to Modification 1, it can be seen that the relationship between temperature and open-circuit voltage difference does not depend on illuminance within a predetermined temperature range. Therefore, the semiconductor device in Modification 1 can obtain a stable relationship between temperature and open-circuit voltage difference that does not depend on illuminance.

[0060] Next, the temperature dependency of the open circuit voltage difference will be described.

[0061] As shown in FIG. 7, in the temperature range from 0°C to 125°C, the open-circuit voltage difference is proportional to the temperature. That is, the temperature dependency of the open-circuit voltage difference is linear. As a result, according to this modification 1, it is easy to perform temperature correction to keep the reference voltage generated based on the open-circuit voltage difference constant. For example, the open-circuit voltage difference is temperature dependent. Therefore, if the temperature changes, the reference voltage generated based on the open-circuit voltage difference changes. Therefore, in order to generate a constant reference voltage even when the temperature changes, temperature correction is required.

[0062] In this regard, in this modification, as shown in FIG. 7, the open-circuit voltage difference and temperature are proportional to each other within a predetermined temperature range. Therefore, to generate a constant reference voltage even when the temperature changes, temperature correction can be performed based on this proportional relationship. In other words, the semiconductor device in this modification 1 has the characteristic that the open-circuit voltage difference and temperature are proportional to each other within a predetermined temperature range. As a result, temperature correction can be easily performed to maintain a constant open-circuit voltage difference.

[0063] From the above, Modification 1 has the following excellent characteristics: (1) it obtains a relationship between temperature and open-circuit voltage difference that is independent of illuminance, and (2) the temperature dependency of the open-circuit voltage difference is linear. As a result, Modification 1 can provide a high-performance reference voltage generation unit that is highly versatile and has excellent reference voltage stability, even for application to standalone devices. Therefore, Modification 1 has great technical significance in practical use.

[0064] <<An example of temperature compensation>> As described above, the temperature dependency of the open-circuit voltage difference is linear. Below, an example configuration of a reference voltage generation unit that utilizes this linear relationship to generate a reference voltage that is nearly constant even when the temperature changes will be described. Specifically, the reference voltage generation unit is configured to generate a reference voltage based on the open-circuit voltage difference between solar cell 100A and solar cell 200A and either the open-circuit voltage of solar cell 100A (first open-circuit voltage) or the open-circuit voltage of solar cell 200A (second open-circuit voltage). With this configuration of the reference voltage unit, a nearly constant reference voltage can be obtained even when temperature changes occur. This is because the open-circuit voltage difference has a positive temperature dependency, while the temperature dependency of the open-circuit voltage itself has a negative dependency.

[0065] That is, the temperature dependency of the open-circuit voltage difference and the temperature dependency of the open-circuit voltage itself have opposite dependencies. Therefore, for example, the temperature dependency of a reference voltage generated by adding the open-circuit voltage itself (first open-circuit voltage or second open-circuit voltage) multiplied by a certain correction coefficient and the open-circuit voltage difference becomes small because the temperature change of the open-circuit voltage difference and the temperature change of the open-circuit voltage itself cancel each other out. As a result, the reference voltage generated by adding the open-circuit voltage itself multiplied by a proportional coefficient and the open-circuit voltage difference remains nearly constant even when the temperature changes. In other words, the open-circuit voltage difference has a positive temperature dependency, while the temperature dependency of the open-circuit voltage itself has a negative dependency. Therefore, a stable reference voltage with little temperature dependency can be generated by adding the open-circuit voltage itself multiplied by a certain magnification (correction coefficient) and the open-circuit voltage difference together.

[0066] For example, the reference voltage generation unit generates the reference voltage as follows: ΔVoc is the open-circuit voltage difference, Voc is either the first open-circuit voltage of the first solar cell 100A or the second open-circuit voltage of the second solar cell 200A, and α is the proportionality constant. In this case, the reference voltage is generated by Reference Voltage = ΔVoc + α × Voc. This generates the reference voltage by adding the open-circuit voltage itself multiplied by the correction coefficient to the open-circuit voltage difference. As a result, according to this first modification, a stable reference voltage with little temperature dependency can be generated.

[0067] The following describes how the temperature dependency of the reference voltage generated by adding the open-circuit voltage itself multiplied by the correction coefficient and the open-circuit voltage difference is reduced.

[0068] FIG. 8 is a graph showing the temperature dependence of a reference voltage generated by adding the open circuit voltage difference and the open circuit voltage itself multiplied by a correction factor (0.16).

[0069] Figure 8 shows graphs (1), (2), (3), and (4). Graph (1) shows the relationship between temperature and reference voltage when the illuminance is 100,000 lux. Graph (2) shows the relationship between temperature and reference voltage when the illuminance is 10,000 lux. Graph (3) shows the relationship between temperature and reference voltage when the illuminance is 1,000 lux. Graph (4) shows the relationship between temperature and reference voltage when the illuminance is 100 lux.

[0070] As shown in Figure 8, in all of graphs (1), (2), (3), and (4), the reference voltage generated by adding the open-circuit voltage difference and the open-circuit voltage itself multiplied by the correction coefficient can reduce the influence of temperature changes. In other words, it is confirmed that the reference voltage generated by adding the open-circuit voltage difference and the open-circuit voltage itself multiplied by the correction coefficient has small temperature dependency.

[0071] In this way, the reference voltage generated by adding the open-circuit voltage and the open-circuit voltage itself multiplied by the correction coefficient is effective in that it can reduce temperature dependency. In particular, in semiconductor devices used in external environments with large temperature changes, it is very effective to incorporate a reference voltage generation unit that can generate the above-mentioned reference voltage with small temperature dependency.

[0072] <<Example of a reference voltage generator incorporating temperature compensation>> Next, a specific example of a reference voltage generating unit incorporating temperature compensation will be described.

[0073] FIG. 9 is a diagram showing an example of the circuit configuration of a reference voltage generating unit 1A incorporating temperature correction.

[0074] In FIG. 9, the reference voltage generating unit 1A has a solar cell 100A, a resistive element 110, a resistive element 111, a resistive element 112, a capacitive element 120, a capacitive element 130, a solar cell 150 and a solar cell 200A.

[0075] Open circuit voltage V of a 100A solar cell OCH is the open circuit voltage V of the solar cell 200A OCL Specifically, the open circuit voltage V of the solar cell 100A is different from OCH is the open circuit voltage V of the solar cell 200A OCL Moreover, the solar cell 150 has the same configuration as either the solar cell 100A or the solar cell 200A. Therefore, the open-circuit voltage Voc of the solar cell 150 is greater than the open-circuit voltage V OCH or open circuit voltage V OCL is equal to.

[0076] The resistor element 110 and the capacitor element 120 are each connected to the open circuit voltage V OCH and the open circuit voltage V of the solar cell 200A OCL The difference between the open circuit voltage difference ΔVoc (=V OCH -V OCL ) is applied to the resistor 111. The ratio of the resistance value R1 of the resistor 111 to the resistance value R2 of the resistor 112 is set to 1-α:α. In this case, a voltage (α×Voc) obtained by multiplying the open circuit voltage Voc of the solar cell 150 by α is applied to each of the resistor 112 and the capacitor 130. At this time, the output voltage Vout is the sum of the voltage applied to the capacitor 120 and the voltage applied to the capacitor 130. Therefore, the output voltage Vout is Vout=ΔVoc+α×Voc. This output voltage Vout is a reference voltage output from the reference voltage generating unit 1A. Therefore, the reference voltage generating unit 1A having the circuit configuration shown in FIG. 9 can generate a reference voltage expressed as ΔVoc+α×Voc.

[0077] 9, the reason for providing solar cell 150 is to connect it to GND. In other words, solar cell 100A and solar cell 200A that generate the open-circuit voltage difference ΔVoc are not connected to GND. For this reason, solar cell 150 is provided to connect reference voltage generating unit 1A to GND.

[0078] <Modification 2: Combined mounting of solar cells and complementary field-effect transistors> <<Basic Concept of Modification 2>> The basic idea of ​​this Modification 2 is to manufacture solar cells by a CMOS process by forming complementary field effect transistors (sometimes referred to as CMOSFETs in this specification) that constitute an integrated circuit and solar cells that constitute a reference voltage generating unit on the same semiconductor substrate. In other words, the basic idea is to realize a device structure of a solar cell that can be mounted on a semiconductor substrate on which CMOSFETs are formed so that solar cells can be manufactured by a CMOS process.

[0079] According to this basic concept, the CMOSFET and the solar cell can be manufactured using a CMOS process, which reduces manufacturing costs compared to manufacturing an integrated circuit and a solar cell using separate manufacturing processes. In other words, according to this basic concept, the manufacturing efficiency of a semiconductor device including a CMOSFET and a solar cell can be improved.

[0080] Furthermore, according to the basic concept, solar cells can be manufactured using a CMOS process with high processing accuracy, and integrated circuits including CMOSFETs and solar cells can be formed on the same semiconductor chip. Therefore, according to the basic concept, systems including integrated circuits and solar cells can be miniaturized. In particular, the basic concept is very useful in that it can realize the miniaturization of standalone devices by applying it to standalone devices, which are in high demand for miniaturization. Thus, the basic concept is a useful technical concept in that it can not only reduce the manufacturing cost of systems including integrated circuits and solar cells, but also enable the miniaturization of the systems.

[0081] The following describes how the basic concept is embodied.

[0082] <<Configuration of semiconductor device>> FIG. 10 is a diagram showing the configuration of a semiconductor device according to the second modification.

[0083] 10, for example, a p-type semiconductor substrate 10 has a CMOSFET formation region R1 and a solar cell formation region R2. In the CMOSFET formation region R1, a p-channel MOSFET Q1 and an n-channel MOSFET Q2 that constitute a CMOSFET (complementary field effect transistor) are formed.

[0084] On the other hand, in the solar cell formation region R2, the solar cell 100A and the solar cell 200A are formed. That is, the semiconductor device in the present modification 2 includes a CMOSFET formed on a p-type semiconductor substrate 10, and the solar cell 100A and the solar cell 200A formed on this p-type semiconductor substrate 10.

[0085] P-type semiconductor substrate 10 has a front surface and a back surface, and CMOSFET, solar cell 100A, and solar cell 200A are formed on the front surface. If the thickness direction of p-type semiconductor substrate 10 from the back surface to the front surface is defined as a first direction and the direction perpendicular to this first direction is defined as a second direction, CMOSFET, solar cell 100A, and solar cell 200A are arranged to line up in the second direction. In other words, CMOSFET, solar cell 100A1, and solar cell 200A are arranged to line up in the left-right direction in FIG. 1.

[0086] First, the configuration of the CMOSFET will be explained. Specifically, since the CMOSFET is composed of a p-channel MOSFET Q1 and an n-channel MOSFET Q2, the device structures of the p-channel MOSFET Q1 and the n-channel MOSFET Q2 will be explained below with reference to FIG.

[0087] An n-type well NWL1 and an n-type well NWL2 are formed in a p-type semiconductor substrate 10. A p-type well PWL is formed in the n-type well NWL2.

[0088] The p-channel MOSFET Q1 is formed in an n-type well NWL1 formed in a p-type semiconductor substrate 10. Specifically, the p-channel MOSFET Q1 has a gate insulating film GOX1 formed on the surface of the n-type well NWL1 and a gate electrode GE1 formed on the gate insulating film GOX1. The p-channel MOSFET Q1 also has a source region SR1 and a drain region DR1 provided separately from each other inside the n-type well NWL1. The source region SR1 and the drain region DR1 are each made of a p-type semiconductor region, and a channel formation region is formed between the source region SR1 and the drain region DR1. The gate electrode GE1 is formed on this channel formation region via the above-mentioned gate insulating film GOX1. The p-channel MOSFET Q1 also has an n-type semiconductor region NR1 inside the n-type well NWL1 that is electrically connected to the n-type well NWL1. The p-channel MOSFET Q1 is configured as described above.

[0089] Next, the n-channel MOSFET Q2 has a gate insulating film GOX2 formed on the surface of the p-type semiconductor substrate 10 and a gate electrode GE2 formed on the gate insulating film GOX2. Furthermore, the n-channel MOSFET Q2 has a source region SR2 and a drain region DR2 provided separately from each other inside the p-type well PWL. The source region SR2 and the drain region DR2 are each made of an n-type semiconductor region, and a channel formation region is formed between the source region SR2 and the drain region DR2. The gate electrode GE2 is formed on this channel formation region via the aforementioned gate insulating film GOX2. Furthermore, the n-channel MOSFET Q2 has a p-type semiconductor region PR1 inside the p-type well PWL that is electrically connected to the p-type well PWL. Furthermore, an n-type semiconductor region NR2 is formed on the surface of the n-type well NWL2. The n-channel MOSFET Q2 is configured as described above.

[0090] An interlayer insulating film IL is formed so as to cover the CMOSFET configured in this manner, and plugs PLG are formed in this interlayer insulating film IL. Wiring WL electrically connected to the plugs PLG is then formed on the interlayer insulating film IL with the plugs PLG formed on it. As a result, the CMOSFETs are electrically connected by the wiring WL via the plugs PLG. As a result, an integrated circuit made up of CMOSFETs electrically connected by the wiring WL is formed on the p-type semiconductor substrate 10.

[0091] Next, the configurations of the solar cell 100A and the solar cell 200A will be described.

[0092] The solar cell 100A has a configuration similar to that of Modification 1 shown in FIG. 5, for example. That is, it has a p-type semiconductor substrate 10, an n-type well 20A, a p-type well 30A, a p-type semiconductor region 12, a p-type semiconductor region 13, and an n-type semiconductor region 14. The solar cell 200A also has a configuration similar to that of Modification 1 shown in FIG. 5, for example. That is, the solar cell 200A has a p-type semiconductor substrate 10, an n-type well 20B, a p-type well 30B, and an n-type semiconductor region 14. Therefore, the p-type semiconductor region 12 and the p-type semiconductor region 13 are formed in the solar cell 100A. In contrast, the p-type semiconductor region 12 and the p-type semiconductor region 13 are not formed in the solar cell 200A. As a result, the open-circuit voltage of the solar cell 100A is higher than that of the solar cell 200A. That is, an open-circuit voltage difference occurs between the solar cell 100A and the solar cell 200A. A reference voltage generation unit that generates a reference voltage based on this open-circuit voltage difference is realized.

[0093] The semiconductor device according to the second modification is configured as described above.

[0094] <<Semiconductor Device Manufacturing Method>> Next, a method for manufacturing the semiconductor device according to the second modification will be described.

[0095] For example, a CMOSFET is manufactured by a CMOS process. Specifically, for example, in FIG. 10, an n-type well NWL1, an n-type well NWL2, and a p-type well PWL are formed in a p-type semiconductor substrate 10 by using an ion implantation method. Then, a gate insulating film GOX1 (GOX2) is formed on the surface of the p-type semiconductor substrate 10 by using, for example, a thermal oxidation method, and then a gate electrode GE1 (GE2) is formed on the gate insulating film GOX1 (GOX2) by using, for example, a patterning technique.

[0096] Thereafter, for example, by using ion implantation, a source region SR1 (p-type semiconductor region) and a drain region DR1 (p-type semiconductor region) that match the gate electrode GE1 are formed in the n-type well NWL1. Meanwhile, a source region SR2 (n-type semiconductor region) and a drain region DR2 (n-type semiconductor region) that match the gate electrode GE2 are formed in the p-type well PWL. In this manner, a p-channel MOSFET Q1 and an n-channel MOSFET Q2 that constitute the CMOSFET can be manufactured.

[0097] Next, for example, an interlayer insulating film IL is formed so as to cover the CMOSFET, and then contact holes are formed in the interlayer insulating film IL using photolithography and etching techniques. Subsequently, a conductive film is embedded in the contact holes to form plugs PLG, and then wiring WL is formed in the interlayer insulating film IL with the plugs PLG formed therein using, for example, patterning techniques. In this manner, a semiconductor device including a CMOSFET can be manufactured using the CMOS process.

[0098] In the semiconductor device according to the second modification shown in FIG. 10, the solar cell 100A and the solar cell 200A can be manufactured using the above-mentioned CMOS process.

[0099] Specifically, the n-type well 20A and the n-type well 20B can be formed in the same process as the process of forming the n-type well NWL2, and the p-type well 30A and the p-type well 30B can be formed in the same process as the process of forming the p-type well PWL.

[0100] On the other hand, p-type semiconductor region 12 and p-type semiconductor region 13 of solar cell 100A can be formed in the same process as the process for forming source region SR1 and drain region DR1 of p-channel MOSFET Q1. Also, n-type semiconductor region 14 of solar cell 100A and n-type semiconductor region 14 of solar cell 200A can be formed in the same process as the process for forming source region SR2 and drain region DR2 of n-channel MOSFET Q2.

[0101] In this way, according to Modification 2, it is possible to manufacture by a CMOS process the CMOSFET, solar cell 100A, and solar cell 200A mounted on one p-type semiconductor substrate 10. Therefore, according to Modification 2, it is possible to manufacture by a CMOS process the CMOSFET, solar cell 100A, and solar cell 200A, and therefore it is possible to reduce manufacturing costs compared to manufacturing an integrated circuit and solar cell 100A and solar cell 200A in separate manufacturing processes.

[0102] Furthermore, according to Modification 2, solar cell 100A and solar cell 200A can be manufactured using a CMOS process with high processing accuracy, and an integrated circuit including a CMOSFET and solar cell 100A and solar cell 200A can be formed on a single semiconductor chip. Therefore, according to Modification 2, it is possible to miniaturize a system that includes an integrated circuit and solar cell 100A and solar cell 200A. In other words, according to Modification 2, not only can the manufacturing cost of a system that includes an integrated circuit and solar cell 100A and solar cell 200A be reduced, but the system can also be miniaturized.

[0103] Hereinafter, the p-type semiconductor substrate 10 on which the solar cell and CMOSFET are mounted together will be referred to as a bulk substrate. FIG. 11 is a graph showing the relationship between the carrier lifetime and the open-circuit voltage difference in a bulk substrate. As shown in FIG. 11, when the lifetime is 100 μs or more, the open-circuit voltage difference remains constant at approximately 70 mV, regardless of the illuminance. This means that when the carrier lifetime in the bulk substrate is 100 μs or more, a stable open-circuit voltage difference can be obtained that is independent of the illuminance. Therefore, from the perspective of obtaining a stable reference voltage, it is desirable to use a bulk substrate with a carrier lifetime of 100 μs or more as the bulk substrate on which the solar cell and CMOSFET are mounted together.

[0104] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0105] 1 Reference voltage generation section 1A Reference Voltage Generator 10 p-type semiconductor substrate 11A n-type well 11B n-type well 12 p-type semiconductor region 13 p-type semiconductor region 14 n-type semiconductor region 15 insulating film 16A Contact 16B Contact 17A Contact 17B Contact 18A Contact 18B Contact 20A n-type well 20B n-type well 30A p-type well 30B p-type well 40 Light blocking member 100 solar cells 100A solar cell 110 Resistor element 111 Resistor element 112 Resistor element 120 Capacitor 130 Capacitive element 150 solar cells 200 solar cells 200A solar cell 300 High resistance element DR1 drain region DR2 drain region GE1 gate electrode GE1 gate electrode GOX1 gate insulating film GOX2 gate insulating film IL Interlayer insulating film NR1 n-type semiconductor region NR2 n-type semiconductor region NWL1 n-type well NWL2 n-type well OP1 opening OP2 opening PLG plug PR1 p-type semiconductor region PWL p-type well Q1 p-channel MOSFET Q2 n-channel MOSFET SR1 Source Region SR2 Source Region Vout Output voltage WL wiring

Claims

1. A semiconductor device comprising: a reference voltage generating unit that generates a reference voltage based on an open-circuit voltage difference between a first solar cell and a second solar cell.

2. 2. The semiconductor device according to claim 1, The first solar cell is a semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in the semiconductor substrate; a first semiconductor region of the first conductivity type formed in the semiconductor substrate and having an impurity concentration higher than an impurity concentration of the semiconductor substrate; a second semiconductor region of the second conductivity type formed in the first well and having an impurity concentration higher than an impurity concentration of the first well; a first contact connected to the first semiconductor region; a second contact connected to the second semiconductor region; and The second solar cell is the semiconductor substrate; a second well of the second conductivity type formed in the semiconductor substrate; a third contact connected to the semiconductor substrate; a fourth contact connected to the second well; The semiconductor device has:

3. 2. The semiconductor device according to claim 1, The semiconductor device has a circuit portion including complementary field effect transistors.

4. 3. The semiconductor device according to claim 2, The semiconductor device, wherein the open circuit voltage of the first solar cell is higher than the open circuit voltage of the second solar cell.

5. 3. The semiconductor device according to claim 2, the first conductivity type is p-type, The second conductivity type is n-type.

6. 2. The semiconductor device according to claim 1, The first solar cell is a semiconductor substrate of a first conductivity type; a first well of a second conductivity type formed in the semiconductor substrate; a second well of the first conductivity type formed within the first well; a first semiconductor region of the first conductivity type formed in the second well and having an impurity concentration higher than an impurity concentration of the second well; a second semiconductor region of the second conductivity type formed in the second well and having an impurity concentration higher than an impurity concentration of the first well; a first contact connected to the first semiconductor region; a second contact connected to the second semiconductor region; and The second solar cell is the semiconductor substrate; a third well of a second conductivity type formed in the semiconductor substrate; a fourth well of the first conductivity type formed in the third well; a third semiconductor region of the second conductivity type formed in the fourth well and having an impurity concentration higher than an impurity concentration of the third well; a third contact connected to the fourth well; a fourth contact connected to the third semiconductor region; The semiconductor device has:

7. 7. The semiconductor device according to claim 6, The semiconductor device, wherein the open circuit voltage of the first solar cell is higher than the open circuit voltage of the second solar cell.

8. 7. The semiconductor device according to claim 6, the first conductivity type is p-type, The second conductivity type is n-type.

9. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the reference voltage generating unit does not include a transistor.

10. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the reference voltage generating unit operates when irradiated with light.

11. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the reference voltage generation unit is configured to generate the reference voltage based on the open-circuit voltage difference and a first open-circuit voltage of the first solar cell or a second open-circuit voltage of the second solar cell.

12. 12. The semiconductor device according to claim 11, The open circuit voltage difference is ΔVoc, the first open circuit voltage or the second open circuit voltage is Voc, If the proportionality constant is α, The semiconductor device is configured such that the reference voltage is generated by the formula: Reference Voltage=ΔVoc+α×Voc.

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